diff --git a/src/ram/include/ram/ram.h b/src/ram/include/ram/ram.h index 17d83c38914..c4281020b7d 100644 --- a/src/ram/include/ram/ram.h +++ b/src/ram/include/ram/ram.h @@ -90,6 +90,7 @@ class RamGen void generate(int mask_size, int word_size, int num_words, + int column_mux_ratio, int read_ports, odb::dbMaster* storage_cell, odb::dbMaster* tristate_cell, @@ -139,22 +140,32 @@ class RamGen void makeSlice(int slice_idx, int mask_size, int row_idx, + int word_idx, int read_ports, + int column_mux_ratio, odb::dbNet* clock, odb::dbNet* write_enable, + odb::dbNet* word_select, const std::vector& selects, + const std::vector& shared_select_b_nets, + bool create_select_inv, const std::vector& data_input, - const std::vector>& data_output); + const std::vector>& data_output); void makeWord(int slices_per_word, int mask_size, int row_idx, + int word_idx, int read_ports, + int column_mux_ratio, odb::dbNet* clock, + odb::dbNet* word_select, std::vector& write_enable, const std::vector& selects, + const std::vector& shared_select_b_nets, + bool create_select_inv, const std::vector& data_input, - const std::vector>& data_output); + const std::vector>& data_output); odb::dbBTerm* makeBTerm(const std::string& name, odb::dbIoType io_type); @@ -185,6 +196,7 @@ class RamGen odb::dbMaster* and2_cell_{nullptr}; odb::dbMaster* clock_gate_cell_{nullptr}; odb::dbMaster* buffer_cell_{nullptr}; + odb::dbMaster* aoi22_cell_{nullptr}; odb::dbMaster* tapcell_{nullptr}; std::map storage_ports_; @@ -198,6 +210,8 @@ class RamGen std::vector data_inputs_; std::vector> q_outputs_; std::string behavioral_verilog_filename_; + std::string aoi22_in_a1_, aoi22_in_a2_, aoi22_in_b1_, aoi22_in_b2_, + aoi22_out_; Grid ram_grid_; }; diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 43b4d441f46..951d05ea3b7 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -29,6 +30,7 @@ #include "sta/FuncExpr.hh" #include "sta/Liberty.hh" #include "sta/PortDirection.hh" +#include "sta/Sequential.hh" #include "utl/Logger.h" namespace ram { @@ -140,21 +142,39 @@ std::unique_ptr RamGen::makeBit(const std::string& prefix, return bit_cell; } +// Note: For column_mux_ratio > 1, a single shared select_b net and select_inv +// gate are reused across all words in the same physical row (passed via +// shared_select_b_nets). This avoids creating redundant nets and gates per +// word that would cause horizontal routing congestion. Word selection on the +// read path is handled by the AOI mux in the buffer row, so all tristates in +// a row can share the same row-select enable signal. + void RamGen::makeSlice(const int slice_idx, const int mask_size, const int row_idx, + const int word_idx, const int read_ports, + const int column_mux_ratio, dbNet* clock, dbNet* write_enable, + dbNet* word_select, const vector& selects, + const vector& shared_select_b_nets, + const bool create_select_inv, const vector& data_input, - const vector>& data_output) + const vector>& data_output) { const int start_bit_idx = slice_idx * mask_size; - std::string prefix = fmt::format("storage_{}_{}", row_idx, start_bit_idx); + std::string prefix + = fmt::format("storage_{}_{}_{}", row_idx, word_idx, start_bit_idx); + vector select_b_nets(selects.size()); - for (int i = 0; i < selects.size(); ++i) { - select_b_nets[i] = makeNet(prefix, fmt::format("select{}_b", i)); + if (column_mux_ratio == 1) { + for (int i = 0; i < selects.size(); ++i) { + select_b_nets[i] = makeNet(prefix, fmt::format("select{}_b", i)); + } + } else { + select_b_nets = shared_select_b_nets; } auto gclock_net = makeNet(prefix, "gclock"); @@ -164,18 +184,22 @@ void RamGen::makeSlice(const int slice_idx, auto name = fmt::format("{}.bit{}", prefix, start_bit_idx + local_bit); vector outs(read_ports); for (int read_port = 0; read_port < read_ports; ++read_port) { - outs[read_port] = data_output[read_port][local_bit]->getNet(); + outs[read_port] = data_output[read_port][local_bit]; } + + int bit_col = slice_idx * (mask_size * column_mux_ratio + column_mux_ratio) + + local_bit * column_mux_ratio + word_idx; ram_grid_.addCell(makeBit(name, read_ports, gclock_net, select_b_nets, data_input[local_bit], outs), - start_bit_idx + local_bit + slice_idx); + bit_col); } auto sel_cell = std::make_unique(); + // Make clock gate makeInst(sel_cell.get(), prefix, @@ -185,6 +209,21 @@ void RamGen::makeSlice(const int slice_idx, {clock_gate_ports_[{PortRoleType::DataIn, 0}], we0_net}, {clock_gate_ports_[{PortRoleType::DataOut, 0}], gclock_net}}); + // Write path: this net is row_select AND with word_select so clock gate only + // fires for the addressed word within the row. Read path handled by AOI mux. + // word_select is nullptr when column_mux_ratio=1 (no mux needed). + dbNet* write_sel = selects[0]; + if (word_select) { + write_sel = makeNet(prefix, "write_sel"); + makeInst(sel_cell.get(), + prefix, + "word_and", + and2_cell_, + {{and2_ports_[{PortRoleType::DataIn, 0}], selects[0]}, + {and2_ports_[{PortRoleType::DataIn, 1}], word_select}, + {and2_ports_[{PortRoleType::DataOut, 0}], write_sel}}); + } + // Make clock and // this AND gate needs to be fed a net created by a decoder // adding any net will automatically connect with any port @@ -192,39 +231,55 @@ void RamGen::makeSlice(const int slice_idx, prefix, "gcand", and2_cell_, - {{and2_ports_[{PortRoleType::DataIn, 0}], selects[0]}, + {{and2_ports_[{PortRoleType::DataIn, 0}], write_sel}, {and2_ports_[{PortRoleType::DataIn, 1}], write_enable}, {and2_ports_[{PortRoleType::DataOut, 0}], we0_net}}); // Make select inverters - for (int i = 0; i < selects.size(); ++i) { - makeInst(sel_cell.get(), - prefix, - fmt::format("select_inv_{}", i), - inv_cell_, - {{inv_ports_[{PortRoleType::DataIn, 0}], selects[i]}, - {inv_ports_[{PortRoleType::DataOut, 0}], select_b_nets[i]}}); + if (create_select_inv) { + for (int i = 0; i < selects.size(); ++i) { + makeInst(sel_cell.get(), + prefix, + fmt::format("select_inv_{}", i), + inv_cell_, + {{inv_ports_[{PortRoleType::DataIn, 0}], selects[i]}, + {inv_ports_[{PortRoleType::DataOut, 0}], select_b_nets[i]}}); + } } - ram_grid_.addCell(std::move(sel_cell), start_bit_idx + mask_size + slice_idx); + int sel_col = slice_idx * (mask_size * column_mux_ratio + column_mux_ratio) + + mask_size * column_mux_ratio + word_idx; + ram_grid_.addCell(std::move(sel_cell), sel_col); } +// Note: For column_mux_ratio > 1, creates one shared select_b net per row and +// passes it to all makeSlice calls for words in the same row. Only the first +// word_idx creates the select_inv gate and subsequent words reuse the net +// This reduces horizontal routing congestion where +// col_mux_ratio=2: 1 shared net per row instead of 2 +// col_mux ratio=4: 1 shared net per row instead of 4 + void RamGen::makeWord(const int slices_per_word, const int mask_size, const int row_idx, + const int word_idx, const int read_ports, + const int column_mux_ratio, dbNet* clock, + dbNet* word_select, vector& write_enable, const vector& selects, + const vector& shared_select_b_nets, + const bool create_select_inv, const vector& data_input, - const vector>& data_output) + const vector>& data_output) { for (int slice = 0; slice < slices_per_word; ++slice) { int start_idx = slice * mask_size; vector slice_inputs(data_input.begin() + start_idx, data_input.begin() + start_idx + mask_size); - std::vector> slice_outputs; + std::vector> slice_outputs; slice_outputs.reserve(read_ports); for (int port = 0; port < read_ports; ++port) { const auto& port_outputs = data_output[port]; @@ -235,10 +290,15 @@ void RamGen::makeWord(const int slices_per_word, makeSlice(slice, mask_size, row_idx, + word_idx, read_ports, + column_mux_ratio, clock, write_enable[slice]->getNet(), + word_select, selects, + shared_select_b_nets, + create_select_inv, slice_inputs, slice_outputs); } @@ -441,7 +501,32 @@ std::map RamGen::buildPortMap(dbMaster* master) tri_enable_name = tri_expr->left()->port()->name(); } } else if (dir->isAnyOutput()) { // catches isOutput() - pin_map[{PortRoleType::DataOut, 0}] = lib_port->name(); + auto lib_cell = lib_port->libertyCell(); + auto func = lib_port->function(); + bool is_seq_output = false; + bool is_seq_inverted = false; + + if (func && func->op() == sta::FuncExpr::Op::port) { + auto internal_port = lib_cell->findLibertyPort(func->port()->name()); + if (internal_port) { + auto seq = lib_cell->outputPortSequential(internal_port); + if (seq) { + is_seq_output = true; + // outputInv() is the negative state variable (IQN) + is_seq_inverted = (seq->outputInv() == internal_port); + } + } + } + + if (is_seq_output) { + // only assign if this is the non-inverted output (Q and not Qn) + if (!is_seq_inverted) { + pin_map[{PortRoleType::DataOut, 0}] = lib_port->name(); + } + } else { + // non-sequential cell (AND2, INV etc) assign as DataOut + pin_map[{PortRoleType::DataOut, 0}] = lib_port->name(); + } } else if (dir->isInput()) { pin_map[{PortRoleType::DataIn, in_idx++}] = lib_port->name(); } @@ -485,6 +570,12 @@ std::map RamGen::buildPortMap(dbMaster* master) master->getName(), ground_count); } + + logger_->info(RAM, + 30, + "buildPortMap DataOut for {}: {}", + master->getName(), + pin_map[{PortRoleType::DataOut, 0}]); return pin_map; } @@ -569,6 +660,141 @@ void RamGen::findMasters() "buffer"); } buffer_ports_ = buildPortMap(buffer_cell_); + + // aoi cells used for column mux functionality when column_mux_ratio > 1 + // uses truth table simulation to identify AOI22 and discover port names + // to work for all PDKs, avoiding hardcoding PDK-specific expression parsing + if (!aoi22_cell_) { + // AOI22 truth table: Y = !(A1&A2 | B1&B2) + // for 4 inputs ordered (A1,A2,B1,B2) mapped to bits (0,1,2,3), + // bit k of the table = output when inputs = k in binary. + // kAoi22Table holds the expected output values column for aoi22 truth table + static const uint16_t kAoi22Table = 0x0777; + + // recursively evaluate a liberty function expression given input port + // values + std::function&, + const std::vector&)> + evalFunc; + + evalFunc = [&evalFunc](const sta::FuncExpr* expr, + const std::vector& ports, + const std::vector& vals) -> bool { + if (!expr) { + return false; + } + switch (expr->op()) { + case sta::FuncExpr::Op::port: { + // look up this port's value in the input vector + auto p = expr->port(); + for (int i = 0; i < (int) ports.size(); ++i) { + if (ports[i] == p) { + return vals[i]; + } + } + return false; + } + case sta::FuncExpr::Op::not_: + return !evalFunc(expr->left(), ports, vals); + case sta::FuncExpr::Op::and_: + return evalFunc(expr->left(), ports, vals) + && evalFunc(expr->right(), ports, vals); + case sta::FuncExpr::Op::or_: + return evalFunc(expr->left(), ports, vals) + || evalFunc(expr->right(), ports, vals); + case sta::FuncExpr::Op::xor_: + return evalFunc(expr->left(), ports, vals) + != evalFunc(expr->right(), ports, vals); + case sta::FuncExpr::Op::one: + return true; + case sta::FuncExpr::Op::zero: + return false; + default: + return false; + } + }; + + // compute 16-entry truth table for a function given 4 ordered input ports. + // each bit k of the result = output when inputs = k in binary. (i.e. k= 2 = + // 10) + auto computeTable = + [&evalFunc](const sta::FuncExpr* func, + const std::vector& inputs) -> uint16_t { + uint16_t table = 0; + for (int k = 0; k < 16; ++k) { + std::vector vals(4); + for (int i = 0; i < 4; ++i) { + vals[i] = (k >> i) & 1; + } + if (evalFunc(func, inputs, vals)) { + table |= (1 << k); + } + } + return table; + }; + + // there are exactly 3 unique ways to split 4 ports into 2 pairs for AOI22, + // each pairing assigns (inputs[0],inputs[1]) to group A and + // (inputs[2],inputs[3]) to group B. Try all 3 and check which pattern + // pairing produces the correct AOI22 truth table, which is the correct port + // mapping + static const int kPairings[3][4] = { + {0, 1, 2, 3}, // group A=(p0,p1), group B=(p2,p3) + {0, 2, 1, 3}, // group A=(p0,p2), group B=(p1,p3) + {0, 3, 1, 2}, // group A=(p0,p3), group B=(p1,p2) + }; + + aoi22_cell_ = findMaster( + [&](sta::LibertyPort* out_port) -> bool { + if (!out_port->direction()->isOutput()) { + return false; + } + auto func = out_port->function(); + if (!func) { + return false; + } + auto cell = out_port->libertyCell(); + + // collect all input ports for this cell + std::vector inputs; + std::unique_ptr port_iter( + cell->portIterator()); + while (port_iter->hasNext()) { + auto p = static_cast(port_iter->next()); + if (p->direction()->isInput()) { + inputs.push_back(p->libertyPort()); + } + } + + // aoi22 must have exactly 4 inputs + if (inputs.size() != 4) { + return false; + } + + // try each pairing, if truth table matches, record port names + for (auto& pairing : kPairings) { + std::vector ordered = {inputs[pairing[0]], + inputs[pairing[1]], + inputs[pairing[2]], + inputs[pairing[3]]}; + if (computeTable(func, ordered) == kAoi22Table) { + // found matching pairing so this is the correct port mapping, + // store port names for later use + // ordered[0] = A1, ordered[1] = A2, ordered[2] = B1, ordered[3] = + // B2 + aoi22_in_a1_ = ordered[0]->name(); + aoi22_in_a2_ = ordered[1]->name(); + aoi22_in_b1_ = ordered[2]->name(); + aoi22_in_b2_ = ordered[3]->name(); + aoi22_out_ = out_port->name(); + return true; + } + } + return false; + }, + "aoi22"); + } } void RamGen::ramPdngen(const char* power_pin, @@ -585,6 +811,15 @@ void RamGen::ramPdngen(const char* power_pin, const odb::Rect& die = block_->getDieArea(); const double dbu_per_um = block_->getDb()->getDbuPerMicron(); + // check that vertical strap pitch is at least 4 bits wide for column side + if (ver_pitch < 4 * ram_grid_.getWidth()) { + logger_->warn(RAM, + 35, + "Vertical strap pitch ({:.2f} um) is less than 4 bit-columns " + "wide. try increasing -ver_layer pitch.", + ver_pitch / dbu_per_um); + } + if (die.dy() < hor_pitch) { logger_->error(RAM, 31, @@ -594,6 +829,7 @@ void RamGen::ramPdngen(const char* power_pin, die.dy() / dbu_per_um, hor_pitch / dbu_per_um); } + if (die.dx() < ver_pitch) { logger_->error( RAM, @@ -606,6 +842,7 @@ void RamGen::ramPdngen(const char* power_pin, // need parameters for power and ground nets auto power_net = dbNet::create(block_, "VDD"); + // need parameters for power and ground nets auto ground_net = dbNet::create(block_, "VSS"); power_net->setSpecial(); @@ -703,14 +940,34 @@ void RamGen::ramPdngen(const char* power_pin, void RamGen::ramPinplacer(const char* ver_name, const char* hor_name) { const odb::Rect& die_bounds = block_->getDieArea(); + + // Q output and D input pins on top odb::Rect top_constraint = block_->findConstraintRegion( odb::Direction2D::North, die_bounds.xMin(), die_bounds.xMax()); block_->addBTermConstraintByDirection(dbIoType::OUTPUT, top_constraint); - block_->addBTermsToConstraint(data_inputs_, top_constraint); + + // clk, we, addr_rw pins on the right + odb::Rect right_constraint = block_->findConstraintRegion( + odb::Direction2D::East, die_bounds.yMin(), die_bounds.yMax()); + + vector clk_pins, we_pins; + for (auto bterm : block_->getBTerms()) { + std::string name = bterm->getName(); + if (name == "clk") { + clk_pins.push_back(bterm); + } else if (name.starts_with("we[")) { + we_pins.push_back(bterm); + } + } + block_->addBTermsToConstraint(clk_pins, right_constraint); + block_->addBTermsToConstraint(we_pins, right_constraint); + block_->addBTermsToConstraint(addr_inputs_, right_constraint); + auto pin_tech = block_->getDb()->getTech(); io_placer_->addHorLayer(pin_tech->findLayer(hor_name)); io_placer_->addVerLayer(pin_tech->findLayer(ver_name)); + io_placer_->getParameters()->setCornerAvoidance(0); io_placer_->runHungarianMatching(); } @@ -747,6 +1004,7 @@ void RamGen::ramRouting(int thread_count) void RamGen::generate(const int mask_size, const int word_size, const int num_words, + const int column_mux_ratio, const int read_ports, dbMaster* storage_cell, dbMaster* tristate_cell, @@ -765,6 +1023,44 @@ void RamGen::generate(const int mask_size, return; } + // error checking for column_mux_ratio + if (column_mux_ratio != 1 && column_mux_ratio != 2 && column_mux_ratio != 4) { + logger_->error(RAM, + 33, + "The ram generator currently only supports column_mux_ratio " + "values of 1, 2, or 4."); + } + + // TODO: add support for col/mux ratio when read_ports > 1 + // error checking, current col/mux only supports read_ports = 1 + if (column_mux_ratio > 1 && read_ports != 1) { + logger_->error(RAM, + 36, + "The ram generator currently only supports column_mux_ratio " + "> 1 when read_ports = 1."); + } + + // TODO: add support for non-divisble word counts, for these cases the last + // row will have empty spaces/filler cells instead of errorring out + if (num_words % column_mux_ratio != 0) { + logger_->error(RAM, + 34, + "num_words ({}) must be divisible by column_mux_ratio ({}).", + num_words, + column_mux_ratio); + } + + int num_inputs = std::ceil(std::log2(num_words)); + // compute information to support col/mux ratio feature + int num_rows = num_words / column_mux_ratio; + // if column mux ratio > 1, then the lower log2(column_mux_ratio) bits are + // used to select the word within a row + int num_word_bits = (column_mux_ratio > 1) + ? static_cast(std::log2(column_mux_ratio)) + : 0; + // the remaining upper bits are used to select the row + int num_row_bits = num_inputs - num_word_bits; + logger_->info(RAM, 3, "Generating {}", ram_name); storage_cell_ = storage_cell; @@ -774,6 +1070,7 @@ void RamGen::generate(const int mask_size, and2_cell_ = nullptr; clock_gate_cell_ = nullptr; buffer_cell_ = nullptr; + aoi22_cell_ = nullptr; findMasters(); auto chip = db_->getChip(); @@ -787,9 +1084,13 @@ void RamGen::generate(const int mask_size, block_ = odb::dbBlock::create(chip, ram_name.c_str()); } - // One column per bit plus one select/control column per slice, - // plus one extra decoder column. - int col_cell_count = slices_per_word * (mask_size + 1); + // With column_mux_ratio = 1: One column per bit plus one select/control + // column per slice, plus one extra decoder column With column_mux_ratio > 1: + // Each slice has (mask_size * column_mux_ratio) columns (one per bit per word + // in the row), plus one select/control column per slice (one per word), plus + // one extra decoder column at far right shared across all row + int col_cell_count + = slices_per_word * (mask_size * column_mux_ratio + column_mux_ratio); ram_grid_.setNumLayouts(col_cell_count + 1); auto clock = makeBTerm("clk", dbIoType::INPUT); @@ -801,67 +1102,145 @@ void RamGen::generate(const int mask_size, } // input bterms - int num_inputs = std::ceil(std::log2(num_words)); for (int i = 0; i < num_inputs; ++i) { addr_inputs_.push_back( - makeBTerm(fmt::format("addr[{}]", i), dbIoType::INPUT)); + makeBTerm(fmt::format("addr_rw[{}]", i), dbIoType::INPUT)); } // vector of nets storing inverter nets vector inv_addr(num_inputs); for (int i = 0; i < num_inputs; ++i) { - inv_addr[i] = makeNet("inv", fmt::format("addr[{}]", i)); + inv_addr[i] = makeNet("inv", fmt::format("addr{}", i)); } + // When column_mux_ratio > 1: word_sel_nets[word_idx] is high/active when + // word_idx is the addressed word within a physical row. Derived from the + // lower num_word_bits address bits. Used only on the write path to gate the + // clock per word in makeSlice. Read path word selection uses addr[0]/addr[1] + // directly in the AOI mux. + + // When column_mux_ratio = 1: set to nullptr for all entries because only one + // word per row + vector word_sel_nets(column_mux_ratio, nullptr); + // decoder_layer nets - vector> decoder_input_nets(num_words, - vector(num_inputs)); - for (int word = 0; word < num_words; ++word) { - int word_num = word; + // for column muxing, deocder input nets uses only the upper address bits + // (num_row_bits) to determine row + vector> decoder_input_nets(num_rows, + vector(num_row_bits)); + for (int row = 0; row < num_rows; ++row) { + int row_num = row; // start at right most bit - for (int input = 0; input < num_inputs; ++input) { - if (word_num % 2 == 0) { + for (int input = 0; input < num_row_bits; ++input) { + if (row_num % 2 == 0) { // places inverted address for each input - decoder_input_nets[word][input] = inv_addr[input]; + decoder_input_nets[row][input] = inv_addr[num_word_bits + input]; } else { // puts original input in invert nets - decoder_input_nets[word][input] = addr_inputs_[input]->getNet(); + decoder_input_nets[row][input] + = addr_inputs_[num_word_bits + input]->getNet(); } - word_num /= 2; + row_num /= 2; } } // word decoder signals to have one deccoder per word, shared between all // slices of a word - vector> word_decoder_nets(num_words); + vector> word_decoder_nets(num_rows); - for (int row = 0; row < num_words; ++row) { + for (int row = 0; row < num_rows; ++row) { auto decoder_name = fmt::format("decoder_{}", row); - if (num_words == 2) { - dbNet* addr_net = (row == 0 ? inv_addr[0] : addr_inputs_[0]->getNet()); + if (num_rows == 2) { + dbNet* addr_net = (row == 0 ? inv_addr[num_word_bits] + : addr_inputs_[num_word_bits]->getNet()); for (int i = 0; i < read_ports; ++i) { word_decoder_nets[row].push_back(addr_net); } } else { word_decoder_nets[row] = selectNets(decoder_name, read_ports); - auto decoder_and_cell = makeDecoder(decoder_name, - num_words, + num_rows, read_ports, word_decoder_nets[row], decoder_input_nets[row]); - ram_grid_.addCell(std::move(decoder_and_cell), col_cell_count); } } + std::unique_ptr inv_sel_cell; + std::unique_ptr word_sel_cell; + + if (column_mux_ratio == 2) { + word_sel_nets[0] = inv_addr[0]; + word_sel_nets[1] = addr_inputs_[0]->getNet(); + // place inv_addr[0] inverter in sel column + inv_sel_cell = std::make_unique(); + makeInst( + inv_sel_cell.get(), + "word_sel", + "inv_addr_0", + inv_cell_, + {{inv_ports_[{PortRoleType::DataIn, 0}], addr_inputs_[0]->getNet()}, + {inv_ports_[{PortRoleType::DataOut, 0}], inv_addr[0]}}); + } else if (column_mux_ratio == 4) { + word_sel_cell = std::make_unique(); + for (int c = 0; c < 4; ++c) { + word_sel_nets[c] = makeNet("word_sel", fmt::format("{}", c)); + } + makeInst(word_sel_cell.get(), + "word_sel", + "and_0", + and2_cell_, + {{and2_ports_[{PortRoleType::DataIn, 0}], inv_addr[1]}, + {and2_ports_[{PortRoleType::DataIn, 1}], inv_addr[0]}, + {and2_ports_[{PortRoleType::DataOut, 0}], word_sel_nets[0]}}); + makeInst( + word_sel_cell.get(), + "word_sel", + "and_1", + and2_cell_, + {{and2_ports_[{PortRoleType::DataIn, 0}], inv_addr[1]}, + {and2_ports_[{PortRoleType::DataIn, 1}], addr_inputs_[0]->getNet()}, + {and2_ports_[{PortRoleType::DataOut, 0}], word_sel_nets[1]}}); + makeInst( + word_sel_cell.get(), + "word_sel", + "and_2", + and2_cell_, + {{and2_ports_[{PortRoleType::DataIn, 0}], addr_inputs_[1]->getNet()}, + {and2_ports_[{PortRoleType::DataIn, 1}], inv_addr[0]}, + {and2_ports_[{PortRoleType::DataOut, 0}], word_sel_nets[2]}}); + makeInst( + word_sel_cell.get(), + "word_sel", + "and_3", + and2_cell_, + {{and2_ports_[{PortRoleType::DataIn, 0}], addr_inputs_[1]->getNet()}, + {and2_ports_[{PortRoleType::DataIn, 1}], addr_inputs_[0]->getNet()}, + {and2_ports_[{PortRoleType::DataOut, 0}], word_sel_nets[3]}}); + makeInst( + word_sel_cell.get(), + "word_sel", + "inv_addr_0", + inv_cell_, + {{inv_ports_[{PortRoleType::DataIn, 0}], addr_inputs_[0]->getNet()}, + {inv_ports_[{PortRoleType::DataOut, 0}], inv_addr[0]}}); + makeInst( + word_sel_cell.get(), + "word_sel", + "inv_addr_1", + inv_cell_, + {{inv_ports_[{PortRoleType::DataIn, 0}], addr_inputs_[1]->getNet()}, + {inv_ports_[{PortRoleType::DataOut, 0}], inv_addr[1]}}); + } + // start of input/output net creation q_outputs_.resize(read_ports); vector D_nets(word_size); for (int bit = 0; bit < word_size; ++bit) { data_inputs_.push_back( makeBTerm(fmt::format("D[{}]", bit), dbIoType::INPUT)); - D_nets[bit] = makeNet(fmt::format("D_nets[{}]", bit), "net"); + D_nets[bit] = makeNet("D_nets", fmt::format("b{}", bit)); // if readports == 1, only have Q outputs if (read_ports == 1) { @@ -875,16 +1254,159 @@ void RamGen::generate(const int mask_size, } } - for (int row = 0; row < num_words; ++row) { - makeWord(slices_per_word, - mask_size, - row, - read_ports, - clock->getNet(), - write_enable, - word_decoder_nets[row], - D_nets, - q_outputs_); + // Intermediate nets between tristate outputs and Q BTerms + // When column_mux_ratio = 1: tristate drives Q directly, so reuse Q BTerm + // nets When column_mux_ratio > 1: tristate drives intermediate net, AOI mux + // selects correct net based on lower address bits (word_select net) + // word_q_nets[word_idx][bit] = intermed. net for that word and bit pair + vector> word_q_nets(column_mux_ratio, + vector(word_size)); + if (column_mux_ratio == 1) { + for (int bit = 0; bit < word_size; ++bit) { + word_q_nets[0][bit] = q_outputs_[0][bit]->getNet(); + } + } else { + for (int w = 0; w < column_mux_ratio; ++w) { + for (int bit = 0; bit < word_size; ++bit) { + word_q_nets[w][bit] = makeNet("word_q", fmt::format("w{}_b{}", w, bit)); + } + } + } + + // For column_mux_ratio > 1, create one shared select_b net per row before + // iterating over word_idx. All words in the same row share this net as the + // tristate TE_B enable signal. Only word_idx=0 instantiates the select_inv + // gate — all other word_idx reuse the existing net, reducing cell count + // and horizontal routing congestion in storage rows. + + for (int row = 0; row < num_rows; ++row) { + // one select_b_net per row for column_mux_ratio > 1 + vector shared_select_b_nets(read_ports); + if (column_mux_ratio > 1) { + for (int i = 0; i < read_ports; ++i) { + shared_select_b_nets[i] + = makeNet(fmt::format("row{}", row), fmt::format("select{}_b", i)); + } + } + + for (int word_idx = 0; word_idx < column_mux_ratio; ++word_idx) { + vector> word_output_nets(read_ports); + for (int port = 0; port < read_ports; ++port) { + for (int bit = 0; bit < word_size; ++bit) { + word_output_nets[port].push_back(word_q_nets[word_idx][bit]); + } + } + + makeWord(slices_per_word, + mask_size, + row, + word_idx, + read_ports, + column_mux_ratio, + clock->getNet(), + word_sel_nets[word_idx], + write_enable, + word_decoder_nets[row], + shared_select_b_nets, + (word_idx == 0 || column_mux_ratio == 1), + D_nets, + word_output_nets); + } + } + + // cell placement for mux made of AOI22 (and inverter if needed) for column + // muxing + if (column_mux_ratio > 1) { + for (int slice = 0; slice < slices_per_word; ++slice) { + for (int bit = 0; bit < mask_size; ++bit) { + const int global_bit = slice * mask_size + bit; + const int base_col + = slice * (mask_size * column_mux_ratio + column_mux_ratio) + + bit * column_mux_ratio; + const std::string prefix = fmt::format("mux_slice{}_bit{}", slice, bit); + + // collect this bit's net from each word + vector bit_word_q_nets(column_mux_ratio); + for (int word_idx = 0; word_idx < column_mux_ratio; ++word_idx) { + bit_word_q_nets[word_idx] = word_q_nets[word_idx][global_bit]; + } + + if (column_mux_ratio == 2) { + // mux placement + // col base_col+0: buffer + // col base_col+1: AOI22 + inverter side by side in same cell/column + auto aoi_out = makeNet(prefix, "aoi_out"); + auto mux_cell = std::make_unique(); + makeInst(mux_cell.get(), + prefix, + "aoi", + aoi22_cell_, + {{aoi22_in_a1_, inv_addr[0]}, + {aoi22_in_a2_, bit_word_q_nets[0]}, + {aoi22_in_b1_, addr_inputs_[0]->getNet()}, + {aoi22_in_b2_, bit_word_q_nets[1]}, + {aoi22_out_, aoi_out}}); + makeInst(mux_cell.get(), + prefix, + "inv", + inv_cell_, + {{inv_ports_[{PortRoleType::DataIn, 0}], aoi_out}, + {inv_ports_[{PortRoleType::DataOut, 0}], + q_outputs_[0][global_bit]->getNet()}}); + ram_grid_.addCell(std::move(mux_cell), base_col + 1); + + } else if (column_mux_ratio == 4) { + // mux placement: + // col base_col+0: buffer + // col base_col+1: s1_AOI_0 (w0+w1) + // col base_col+2: s2_AOI final (even stages so no inverter needed) + // col base_col+3: s1_AOI_1 (w2+w3) + auto s1_out_0 = makeNet(prefix, "s1_out_0"); + auto s1_out_1 = makeNet(prefix, "s1_out_1"); + + // col base_col+1: stage1 AOI for word0+word1 + auto s1_cell_0 = std::make_unique(); + makeInst(s1_cell_0.get(), + prefix, + "s1_aoi_0", + aoi22_cell_, + {{aoi22_in_a1_, inv_addr[0]}, + {aoi22_in_a2_, bit_word_q_nets[0]}, + {aoi22_in_b1_, addr_inputs_[0]->getNet()}, + {aoi22_in_b2_, bit_word_q_nets[1]}, + {aoi22_out_, s1_out_0}}); + ram_grid_.addCell(std::move(s1_cell_0), base_col + 1); + + // col base_col+3: stage1 AOI for word2 + word3 + // NOTE: must be placed before s2 so s1_out_1 net exists for s2 input + auto s1_cell_1 = std::make_unique(); + makeInst(s1_cell_1.get(), + prefix, + "s1_aoi_1", + aoi22_cell_, + {{aoi22_in_a1_, inv_addr[0]}, + {aoi22_in_a2_, bit_word_q_nets[2]}, + {aoi22_in_b1_, addr_inputs_[0]->getNet()}, + {aoi22_in_b2_, bit_word_q_nets[3]}, + {aoi22_out_, s1_out_1}}); + ram_grid_.addCell(std::move(s1_cell_1), base_col + 3); + + // col base_col+2: stage2 AOI combining stage 1 outputs and drives Q + // directly + auto s2_cell = std::make_unique(); + makeInst(s2_cell.get(), + prefix, + "s2_aoi", + aoi22_cell_, + {{aoi22_in_a1_, inv_addr[1]}, + {aoi22_in_a2_, s1_out_0}, + {aoi22_in_b1_, addr_inputs_[1]->getNet()}, + {aoi22_in_b2_, s1_out_1}, + {aoi22_out_, q_outputs_[0][global_bit]->getNet()}}); + ram_grid_.addCell(std::move(s2_cell), base_col + 2); + } + } + } } for (int slice = 0; slice < slices_per_word; ++slice) { @@ -898,14 +1420,23 @@ void RamGen::generate(const int mask_size, {{buffer_ports_[{PortRoleType::DataIn, 0}], data_inputs_[bit_idx]->getNet()}, {buffer_ports_[{PortRoleType::DataOut, 0}], D_nets[bit_idx]}}); - ram_grid_.addCell(std::move(buffer_grid_cell), bit_idx + slice); + int buf_col = slice * (mask_size * column_mux_ratio + column_mux_ratio) + + bit * column_mux_ratio; + ram_grid_.addCell(std::move(buffer_grid_cell), buf_col); } } + if (column_mux_ratio == 2) { + ram_grid_.addCell(std::move(inv_sel_cell), col_cell_count - 1); + } else if (column_mux_ratio == 4) { + ram_grid_.addCell(std::move(word_sel_cell), col_cell_count - 1); + } + auto cell_inv_layout = std::make_unique(odb::vertical); // check for AND gate, specific case for 2 words - if (num_inputs > 1) { - for (int i = num_inputs - 1; i >= 0; --i) { + int inv_col_cells = 0; + if (num_row_bits > 1) { + for (int i = num_inputs - 1; i >= num_word_bits; --i) { auto inv_grid_cell = std::make_unique(); makeInst( inv_grid_cell.get(), @@ -915,9 +1446,11 @@ void RamGen::generate(const int mask_size, {{inv_ports_[{PortRoleType::DataIn, 0}], addr_inputs_[i]->getNet()}, {inv_ports_[{PortRoleType::DataOut, 0}], inv_addr[i]}}); cell_inv_layout->addCell(std::move(inv_grid_cell)); - for (int filler_count = 0; filler_count < num_inputs - 1; + ++inv_col_cells; + for (int filler_count = 0; filler_count < num_row_bits - 1; ++filler_count) { cell_inv_layout->addCell(nullptr); + ++inv_col_cells; } } } else { @@ -925,13 +1458,25 @@ void RamGen::generate(const int mask_size, makeInst( inv_grid_cell.get(), "decoder", - fmt::format("inv_{}", 0), + fmt::format("inv_{}", num_word_bits), inv_cell_, - {{inv_ports_[{PortRoleType::DataIn, 0}], addr_inputs_[0]->getNet()}, - {inv_ports_[{PortRoleType::DataOut, 0}], inv_addr[0]}}); + {{inv_ports_[{PortRoleType::DataIn, 0}], + addr_inputs_[num_word_bits]->getNet()}, + {inv_ports_[{PortRoleType::DataOut, 0}], inv_addr[num_word_bits]}}); + cell_inv_layout->addCell(std::move(inv_grid_cell)); + ++inv_col_cells; + for (int filler_count = 0; filler_count < num_row_bits - 1; + ++filler_count) { + cell_inv_layout->addCell(nullptr); + ++inv_col_cells; + } + } + // Pad remaining slots so this column matches the grid height (num_rows + 1) + while (inv_col_cells < num_rows + 1) { + cell_inv_layout->addCell(nullptr); + ++inv_col_cells; } - ram_grid_.addLayout(std::move(cell_inv_layout)); auto ram_origin(odb::Point(0, 0)); @@ -942,7 +1487,7 @@ void RamGen::generate(const int mask_size, if (tapcell_) { // max tap distance specified is greater than the length of ram if (ram_grid_.getRowWidth() <= max_tap_dist) { - auto tapcell_layout = generateTapColumn(num_words, 0); + auto tapcell_layout = generateTapColumn(num_rows, 0); ram_grid_.insertLayout(std::move(tapcell_layout), 0); } else { // needed this calculation so first cells have right distance @@ -953,7 +1498,7 @@ void RamGen::generate(const int mask_size, for (int col = 0; col < ram_grid_.numLayouts(); ++col) { if (nearest_tap + ram_grid_.getLayoutWidth(col) >= max_tap_dist) { // if the nearest_tap is too far, generate tap column - auto tapcell_layout = generateTapColumn(num_words, tapcell_count); + auto tapcell_layout = generateTapColumn(num_rows, tapcell_count); ram_grid_.insertLayout(std::move(tapcell_layout), col); ++col; // col adjustment after insertion nearest_tap = 0; @@ -963,7 +1508,7 @@ void RamGen::generate(const int mask_size, } // check for last column in the grid if (nearest_tap >= max_tap_dist) { - auto tapcell_layout = generateTapColumn(num_words, tapcell_count); + auto tapcell_layout = generateTapColumn(num_rows, tapcell_count); ram_grid_.addLayout(std::move(tapcell_layout)); } } @@ -978,8 +1523,8 @@ void RamGen::generate(const int mask_size, int num_sites = ram_grid_.getRowWidth() / db_sites->getWidth(); // One extra row at the top for placing input buffers - const int num_rows = num_words + 1; - for (int i = 0; i < num_rows; ++i) { + const int num_rows_grid = num_rows + 1; + for (int i = 0; i < num_rows_grid; ++i) { auto row_name = fmt::format("RAM_ROW{}", i); auto y_coord = i * ram_grid_.getHeight(); auto row_orient = odb::dbOrientType::R0; @@ -999,7 +1544,7 @@ void RamGen::generate(const int mask_size, ram_grid_.placeGrid(); - int max_y_coord = ram_grid_.getHeight() * (num_rows); + int max_y_coord = ram_grid_.getHeight() * (num_rows_grid); int max_x_coord = ram_grid_.getRowWidth(); block_->setDieArea(odb::Rect(0, 0, max_x_coord, max_y_coord)); diff --git a/src/ram/src/ram.i b/src/ram/src/ram.i index 37e475e1c42..638ec9312b3 100644 --- a/src/ram/src/ram.i +++ b/src/ram/src/ram.i @@ -32,6 +32,7 @@ void generate_ram_netlist_cmd(int mask_size, int word_size, int num_words, + int column_mux_ratio, const char* storage_cell_name, const char* tristate_cell_name, const char* inv_cell_name, @@ -87,7 +88,7 @@ generate_ram_netlist_cmd(int mask_size, } } - ram_gen->generate(mask_size, word_size, num_words, read_ports, + ram_gen->generate(mask_size, word_size, num_words, column_mux_ratio, read_ports, storage_cell, tristate_cell, inv_cell, tapcell, max_tap_dist); } @@ -96,7 +97,6 @@ void ram_pdngen(const char* power_pin, const char* ground_pin, const char* route_name, int route_width, const char* ver_name, int ver_width, int ver_pitch, const char* hor_name, int hor_width, int hor_pitch) - { RamGen* ram_gen = ord::getRamGen(); ram_gen->ramPdngen(power_pin, ground_pin, @@ -132,5 +132,4 @@ void set_behavioral_verilog_filename(const char* filename) } //namespace_ram -%} // inline - +%} // inline \ No newline at end of file diff --git a/src/ram/src/ram.tcl b/src/ram/src/ram.tcl index 86c08b8bf63..0868000fe04 100644 --- a/src/ram/src/ram.tcl +++ b/src/ram/src/ram.tcl @@ -4,6 +4,7 @@ sta::define_cmd_args "generate_ram_netlist" {-mask_size bits -word_size bits -num_words words + [-column_mux_ratio ratio] [-storage_cell name] [-tristate_cell name] [-inv_cell name] @@ -13,8 +14,13 @@ sta::define_cmd_args "generate_ram_netlist" {-mask_size bits proc generate_ram_netlist { args } { sta::parse_key_args "generate_ram_netlist" args \ - keys { -mask_size -word_size -num_words -storage_cell -tristate_cell -inv_cell - -read_ports -tapcell -max_tap_dist } flags {} + keys { -mask_size -word_size -num_words -column_mux_ratio -storage_cell -tristate_cell -inv_cell + -read_ports -tapcell -max_tap_dist -write_behavioral_verilog } flags {} + + set column_mux_ratio 1 + if { [info exists keys(-column_mux_ratio)] } { + set column_mux_ratio $keys(-column_mux_ratio) + } if { [info exists keys(-mask_size)] } { set mask_size $keys(-mask_size) @@ -73,13 +79,18 @@ proc generate_ram_netlist { args } { The generated layout may not pass Design Rule Checks." } - ram::generate_ram_netlist_cmd $mask_size $word_size $num_words $storage_cell \ + if { [info exists keys(-write_behavioral_verilog)] } { + ram::set_behavioral_verilog_filename $keys(-write_behavioral_verilog) + } + + ram::generate_ram_netlist_cmd $mask_size $word_size $num_words $column_mux_ratio $storage_cell \ $tristate_cell $inv_cell $read_ports $tapcell $max_tap_dist } sta::define_cmd_args "generate_ram" {-mask_size bits -word_size bits -num_words words + [-column_mux_ratio ratio] [-read_ports count] [-storage_cell name] [-tristate_cell name] @@ -98,7 +109,8 @@ sta::define_cmd_args "generate_ram" {-mask_size bits # user arguments for generate ram arguments proc generate_ram { args } { sta::parse_key_args "generate_ram" args \ - keys { -mask_size -word_size -num_words -storage_cell -tristate_cell -inv_cell -read_ports + keys { -mask_size -word_size -num_words -column_mux_ratio + -storage_cell -tristate_cell -inv_cell -read_ports -power_pin -ground_pin -routing_layer -ver_layer -hor_layer -filler_cells -tapcell -max_tap_dist -write_behavioral_verilog } flags {} @@ -138,6 +150,10 @@ proc generate_ram { args } { lappend ram_netlist_args -max_tap_dist $keys(-max_tap_dist) } + if { [info exists keys(-column_mux_ratio)] } { + lappend ram_netlist_args -column_mux_ratio $keys(-column_mux_ratio) + } + if { [info exists keys(-write_behavioral_verilog)] } { set behavioral_verilog_file $keys(-write_behavioral_verilog) ram::set_behavioral_verilog_filename $behavioral_verilog_file diff --git a/src/ram/test/make_7x7_nangate45.defok b/src/ram/test/make_7x7_nangate45.defok index f539370c5d5..d0600a3556e 100644 --- a/src/ram/test/make_7x7_nangate45.defok +++ b/src/ram/test/make_7x7_nangate45.defok @@ -99,125 +99,125 @@ COMPONENTS 218 ; - decoder_5.buf_port0 BUF_X1 + PLACED ( 3838 700 ) FS ; - decoder_6.and_layer0 AND2_X1 + PLACED ( 3762 840 ) N ; - decoder_6.buf_port0 BUF_X1 + PLACED ( 3838 840 ) N ; - - storage_0_0.bit0.bit DFF_X1 + PLACED ( 19 0 ) N ; - - storage_0_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 0 ) N ; - - storage_0_0.bit1.bit DFF_X1 + PLACED ( 494 0 ) N ; - - storage_0_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 0 ) N ; - - storage_0_0.bit2.bit DFF_X1 + PLACED ( 988 0 ) N ; - - storage_0_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 0 ) N ; - - storage_0_0.bit3.bit DFF_X1 + PLACED ( 1463 0 ) N ; - - storage_0_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 0 ) N ; - - storage_0_0.bit4.bit DFF_X1 + PLACED ( 1957 0 ) N ; - - storage_0_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 0 ) N ; - - storage_0_0.bit5.bit DFF_X1 + PLACED ( 2432 0 ) N ; - - storage_0_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 0 ) N ; - - storage_0_0.bit6.bit DFF_X1 + PLACED ( 2926 0 ) N ; - - storage_0_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 0 ) N ; - - storage_0_0.cg CLKGATE_X1 + PLACED ( 3401 0 ) N ; - - storage_0_0.gcand AND2_X1 + PLACED ( 3648 0 ) N ; - - storage_0_0.select_inv_0 INV_X1 + PLACED ( 3724 0 ) N ; - - storage_1_0.bit0.bit DFF_X1 + PLACED ( 19 140 ) FS ; - - storage_1_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 140 ) FS ; - - storage_1_0.bit1.bit DFF_X1 + PLACED ( 494 140 ) FS ; - - storage_1_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 140 ) FS ; - - storage_1_0.bit2.bit DFF_X1 + PLACED ( 988 140 ) FS ; - - storage_1_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 140 ) FS ; - - storage_1_0.bit3.bit DFF_X1 + PLACED ( 1463 140 ) FS ; - - storage_1_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 140 ) FS ; - - storage_1_0.bit4.bit DFF_X1 + PLACED ( 1957 140 ) FS ; - - storage_1_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 140 ) FS ; - - storage_1_0.bit5.bit DFF_X1 + PLACED ( 2432 140 ) FS ; - - storage_1_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 140 ) FS ; - - storage_1_0.bit6.bit DFF_X1 + PLACED ( 2926 140 ) FS ; - - storage_1_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 140 ) FS ; - - storage_1_0.cg CLKGATE_X1 + PLACED ( 3401 140 ) FS ; - - storage_1_0.gcand AND2_X1 + PLACED ( 3648 140 ) FS ; - - storage_1_0.select_inv_0 INV_X1 + PLACED ( 3724 140 ) FS ; - - storage_2_0.bit0.bit DFF_X1 + PLACED ( 19 280 ) N ; - - storage_2_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 280 ) N ; - - storage_2_0.bit1.bit DFF_X1 + PLACED ( 494 280 ) N ; - - storage_2_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 280 ) N ; - - storage_2_0.bit2.bit DFF_X1 + PLACED ( 988 280 ) N ; - - storage_2_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 280 ) N ; - - storage_2_0.bit3.bit DFF_X1 + PLACED ( 1463 280 ) N ; - - storage_2_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 280 ) N ; - - storage_2_0.bit4.bit DFF_X1 + PLACED ( 1957 280 ) N ; - - storage_2_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 280 ) N ; - - storage_2_0.bit5.bit DFF_X1 + PLACED ( 2432 280 ) N ; - - storage_2_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 280 ) N ; - - storage_2_0.bit6.bit DFF_X1 + PLACED ( 2926 280 ) N ; - - storage_2_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 280 ) N ; - - storage_2_0.cg CLKGATE_X1 + PLACED ( 3401 280 ) N ; - - storage_2_0.gcand AND2_X1 + PLACED ( 3648 280 ) N ; - - storage_2_0.select_inv_0 INV_X1 + PLACED ( 3724 280 ) N ; - - storage_3_0.bit0.bit DFF_X1 + PLACED ( 19 420 ) FS ; - - storage_3_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 420 ) FS ; - - storage_3_0.bit1.bit DFF_X1 + PLACED ( 494 420 ) FS ; - - storage_3_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 420 ) FS ; - - storage_3_0.bit2.bit DFF_X1 + PLACED ( 988 420 ) FS ; - - storage_3_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 420 ) FS ; - - storage_3_0.bit3.bit DFF_X1 + PLACED ( 1463 420 ) FS ; - - storage_3_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 420 ) FS ; - - storage_3_0.bit4.bit DFF_X1 + PLACED ( 1957 420 ) FS ; - - storage_3_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 420 ) FS ; - - storage_3_0.bit5.bit DFF_X1 + PLACED ( 2432 420 ) FS ; - - storage_3_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 420 ) FS ; - - storage_3_0.bit6.bit DFF_X1 + PLACED ( 2926 420 ) FS ; - - storage_3_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 420 ) FS ; - - storage_3_0.cg CLKGATE_X1 + PLACED ( 3401 420 ) FS ; - - storage_3_0.gcand AND2_X1 + PLACED ( 3648 420 ) FS ; - - storage_3_0.select_inv_0 INV_X1 + PLACED ( 3724 420 ) FS ; - - storage_4_0.bit0.bit DFF_X1 + PLACED ( 19 560 ) N ; - - storage_4_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 560 ) N ; - - storage_4_0.bit1.bit DFF_X1 + PLACED ( 494 560 ) N ; - - storage_4_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 560 ) N ; - - storage_4_0.bit2.bit DFF_X1 + PLACED ( 988 560 ) N ; - - storage_4_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 560 ) N ; - - storage_4_0.bit3.bit DFF_X1 + PLACED ( 1463 560 ) N ; - - storage_4_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 560 ) N ; - - storage_4_0.bit4.bit DFF_X1 + PLACED ( 1957 560 ) N ; - - storage_4_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 560 ) N ; - - storage_4_0.bit5.bit DFF_X1 + PLACED ( 2432 560 ) N ; - - storage_4_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 560 ) N ; - - storage_4_0.bit6.bit DFF_X1 + PLACED ( 2926 560 ) N ; - - storage_4_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 560 ) N ; - - storage_4_0.cg CLKGATE_X1 + PLACED ( 3401 560 ) N ; - - storage_4_0.gcand AND2_X1 + PLACED ( 3648 560 ) N ; - - storage_4_0.select_inv_0 INV_X1 + PLACED ( 3724 560 ) N ; - - storage_5_0.bit0.bit DFF_X1 + PLACED ( 19 700 ) FS ; - - storage_5_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 700 ) FS ; - - storage_5_0.bit1.bit DFF_X1 + PLACED ( 494 700 ) FS ; - - storage_5_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 700 ) FS ; - - storage_5_0.bit2.bit DFF_X1 + PLACED ( 988 700 ) FS ; - - storage_5_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 700 ) FS ; - - storage_5_0.bit3.bit DFF_X1 + PLACED ( 1463 700 ) FS ; - - storage_5_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 700 ) FS ; - - storage_5_0.bit4.bit DFF_X1 + PLACED ( 1957 700 ) FS ; - - storage_5_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 700 ) FS ; - - storage_5_0.bit5.bit DFF_X1 + PLACED ( 2432 700 ) FS ; - - storage_5_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 700 ) FS ; - - storage_5_0.bit6.bit DFF_X1 + PLACED ( 2926 700 ) FS ; - - storage_5_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 700 ) FS ; - - storage_5_0.cg CLKGATE_X1 + PLACED ( 3401 700 ) FS ; - - storage_5_0.gcand AND2_X1 + PLACED ( 3648 700 ) FS ; - - storage_5_0.select_inv_0 INV_X1 + PLACED ( 3724 700 ) FS ; - - storage_6_0.bit0.bit DFF_X1 + PLACED ( 19 840 ) N ; - - storage_6_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 840 ) N ; - - storage_6_0.bit1.bit DFF_X1 + PLACED ( 494 840 ) N ; - - storage_6_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 840 ) N ; - - storage_6_0.bit2.bit DFF_X1 + PLACED ( 988 840 ) N ; - - storage_6_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 840 ) N ; - - storage_6_0.bit3.bit DFF_X1 + PLACED ( 1463 840 ) N ; - - storage_6_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 840 ) N ; - - storage_6_0.bit4.bit DFF_X1 + PLACED ( 1957 840 ) N ; - - storage_6_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 840 ) N ; - - storage_6_0.bit5.bit DFF_X1 + PLACED ( 2432 840 ) N ; - - storage_6_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 840 ) N ; - - storage_6_0.bit6.bit DFF_X1 + PLACED ( 2926 840 ) N ; - - storage_6_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 840 ) N ; - - storage_6_0.cg CLKGATE_X1 + PLACED ( 3401 840 ) N ; - - storage_6_0.gcand AND2_X1 + PLACED ( 3648 840 ) N ; - - storage_6_0.select_inv_0 INV_X1 + PLACED ( 3724 840 ) N ; + - storage_0_0_0.bit0.bit DFF_X1 + PLACED ( 19 0 ) N ; + - storage_0_0_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 0 ) N ; + - storage_0_0_0.bit1.bit DFF_X1 + PLACED ( 494 0 ) N ; + - storage_0_0_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 0 ) N ; + - storage_0_0_0.bit2.bit DFF_X1 + PLACED ( 988 0 ) N ; + - storage_0_0_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 0 ) N ; + - storage_0_0_0.bit3.bit DFF_X1 + PLACED ( 1463 0 ) N ; + - storage_0_0_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 0 ) N ; + - storage_0_0_0.bit4.bit DFF_X1 + PLACED ( 1957 0 ) N ; + - storage_0_0_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 0 ) N ; + - storage_0_0_0.bit5.bit DFF_X1 + PLACED ( 2432 0 ) N ; + - storage_0_0_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 0 ) N ; + - storage_0_0_0.bit6.bit DFF_X1 + PLACED ( 2926 0 ) N ; + - storage_0_0_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 0 ) N ; + - storage_0_0_0.cg CLKGATE_X1 + PLACED ( 3401 0 ) N ; + - storage_0_0_0.gcand AND2_X1 + PLACED ( 3648 0 ) N ; + - storage_0_0_0.select_inv_0 INV_X1 + PLACED ( 3724 0 ) N ; + - storage_1_0_0.bit0.bit DFF_X1 + PLACED ( 19 140 ) FS ; + - storage_1_0_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 140 ) FS ; + - storage_1_0_0.bit1.bit DFF_X1 + PLACED ( 494 140 ) FS ; + - storage_1_0_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 140 ) FS ; + - storage_1_0_0.bit2.bit DFF_X1 + PLACED ( 988 140 ) FS ; + - storage_1_0_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 140 ) FS ; + - storage_1_0_0.bit3.bit DFF_X1 + PLACED ( 1463 140 ) FS ; + - storage_1_0_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 140 ) FS ; + - storage_1_0_0.bit4.bit DFF_X1 + PLACED ( 1957 140 ) FS ; + - storage_1_0_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 140 ) FS ; + - storage_1_0_0.bit5.bit DFF_X1 + PLACED ( 2432 140 ) FS ; + - storage_1_0_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 140 ) FS ; + - storage_1_0_0.bit6.bit DFF_X1 + PLACED ( 2926 140 ) FS ; + - storage_1_0_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 140 ) FS ; + - storage_1_0_0.cg CLKGATE_X1 + PLACED ( 3401 140 ) FS ; + - storage_1_0_0.gcand AND2_X1 + PLACED ( 3648 140 ) FS ; + - storage_1_0_0.select_inv_0 INV_X1 + PLACED ( 3724 140 ) FS ; + - storage_2_0_0.bit0.bit DFF_X1 + PLACED ( 19 280 ) N ; + - storage_2_0_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 280 ) N ; + - storage_2_0_0.bit1.bit DFF_X1 + PLACED ( 494 280 ) N ; + - storage_2_0_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 280 ) N ; + - storage_2_0_0.bit2.bit DFF_X1 + PLACED ( 988 280 ) N ; + - storage_2_0_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 280 ) N ; + - storage_2_0_0.bit3.bit DFF_X1 + PLACED ( 1463 280 ) N ; + - storage_2_0_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 280 ) N ; + - storage_2_0_0.bit4.bit DFF_X1 + PLACED ( 1957 280 ) N ; + - storage_2_0_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 280 ) N ; + - storage_2_0_0.bit5.bit DFF_X1 + PLACED ( 2432 280 ) N ; + - storage_2_0_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 280 ) N ; + - storage_2_0_0.bit6.bit DFF_X1 + PLACED ( 2926 280 ) N ; + - storage_2_0_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 280 ) N ; + - storage_2_0_0.cg CLKGATE_X1 + PLACED ( 3401 280 ) N ; + - storage_2_0_0.gcand AND2_X1 + PLACED ( 3648 280 ) N ; + - storage_2_0_0.select_inv_0 INV_X1 + PLACED ( 3724 280 ) N ; + - storage_3_0_0.bit0.bit DFF_X1 + PLACED ( 19 420 ) FS ; + - storage_3_0_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 420 ) FS ; + - storage_3_0_0.bit1.bit DFF_X1 + PLACED ( 494 420 ) FS ; + - storage_3_0_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 420 ) FS ; + - storage_3_0_0.bit2.bit DFF_X1 + PLACED ( 988 420 ) FS ; + - storage_3_0_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 420 ) FS ; + - storage_3_0_0.bit3.bit DFF_X1 + PLACED ( 1463 420 ) FS ; + - storage_3_0_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 420 ) FS ; + - storage_3_0_0.bit4.bit DFF_X1 + PLACED ( 1957 420 ) FS ; + - storage_3_0_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 420 ) FS ; + - storage_3_0_0.bit5.bit DFF_X1 + PLACED ( 2432 420 ) FS ; + - storage_3_0_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 420 ) FS ; + - storage_3_0_0.bit6.bit DFF_X1 + PLACED ( 2926 420 ) FS ; + - storage_3_0_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 420 ) FS ; + - storage_3_0_0.cg CLKGATE_X1 + PLACED ( 3401 420 ) FS ; + - storage_3_0_0.gcand AND2_X1 + PLACED ( 3648 420 ) FS ; + - storage_3_0_0.select_inv_0 INV_X1 + PLACED ( 3724 420 ) FS ; + - storage_4_0_0.bit0.bit DFF_X1 + PLACED ( 19 560 ) N ; + - storage_4_0_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 560 ) N ; + - storage_4_0_0.bit1.bit DFF_X1 + PLACED ( 494 560 ) N ; + - storage_4_0_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 560 ) N ; + - storage_4_0_0.bit2.bit DFF_X1 + PLACED ( 988 560 ) N ; + - storage_4_0_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 560 ) N ; + - storage_4_0_0.bit3.bit DFF_X1 + PLACED ( 1463 560 ) N ; + - storage_4_0_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 560 ) N ; + - storage_4_0_0.bit4.bit DFF_X1 + PLACED ( 1957 560 ) N ; + - storage_4_0_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 560 ) N ; + - storage_4_0_0.bit5.bit DFF_X1 + PLACED ( 2432 560 ) N ; + - storage_4_0_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 560 ) N ; + - storage_4_0_0.bit6.bit DFF_X1 + PLACED ( 2926 560 ) N ; + - storage_4_0_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 560 ) N ; + - storage_4_0_0.cg CLKGATE_X1 + PLACED ( 3401 560 ) N ; + - storage_4_0_0.gcand AND2_X1 + PLACED ( 3648 560 ) N ; + - storage_4_0_0.select_inv_0 INV_X1 + PLACED ( 3724 560 ) N ; + - storage_5_0_0.bit0.bit DFF_X1 + PLACED ( 19 700 ) FS ; + - storage_5_0_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 700 ) FS ; + - storage_5_0_0.bit1.bit DFF_X1 + PLACED ( 494 700 ) FS ; + - storage_5_0_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 700 ) FS ; + - storage_5_0_0.bit2.bit DFF_X1 + PLACED ( 988 700 ) FS ; + - storage_5_0_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 700 ) FS ; + - storage_5_0_0.bit3.bit DFF_X1 + PLACED ( 1463 700 ) FS ; + - storage_5_0_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 700 ) FS ; + - storage_5_0_0.bit4.bit DFF_X1 + PLACED ( 1957 700 ) FS ; + - storage_5_0_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 700 ) FS ; + - storage_5_0_0.bit5.bit DFF_X1 + PLACED ( 2432 700 ) FS ; + - storage_5_0_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 700 ) FS ; + - storage_5_0_0.bit6.bit DFF_X1 + PLACED ( 2926 700 ) FS ; + - storage_5_0_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 700 ) FS ; + - storage_5_0_0.cg CLKGATE_X1 + PLACED ( 3401 700 ) FS ; + - storage_5_0_0.gcand AND2_X1 + PLACED ( 3648 700 ) FS ; + - storage_5_0_0.select_inv_0 INV_X1 + PLACED ( 3724 700 ) FS ; + - storage_6_0_0.bit0.bit DFF_X1 + PLACED ( 19 840 ) N ; + - storage_6_0_0.bit0.obuf0 TBUF_X1 + PLACED ( 342 840 ) N ; + - storage_6_0_0.bit1.bit DFF_X1 + PLACED ( 494 840 ) N ; + - storage_6_0_0.bit1.obuf0 TBUF_X1 + PLACED ( 817 840 ) N ; + - storage_6_0_0.bit2.bit DFF_X1 + PLACED ( 988 840 ) N ; + - storage_6_0_0.bit2.obuf0 TBUF_X1 + PLACED ( 1311 840 ) N ; + - storage_6_0_0.bit3.bit DFF_X1 + PLACED ( 1463 840 ) N ; + - storage_6_0_0.bit3.obuf0 TBUF_X1 + PLACED ( 1786 840 ) N ; + - storage_6_0_0.bit4.bit DFF_X1 + PLACED ( 1957 840 ) N ; + - storage_6_0_0.bit4.obuf0 TBUF_X1 + PLACED ( 2280 840 ) N ; + - storage_6_0_0.bit5.bit DFF_X1 + PLACED ( 2432 840 ) N ; + - storage_6_0_0.bit5.obuf0 TBUF_X1 + PLACED ( 2755 840 ) N ; + - storage_6_0_0.bit6.bit DFF_X1 + PLACED ( 2926 840 ) N ; + - storage_6_0_0.bit6.obuf0 TBUF_X1 + PLACED ( 3249 840 ) N ; + - storage_6_0_0.cg CLKGATE_X1 + PLACED ( 3401 840 ) N ; + - storage_6_0_0.gcand AND2_X1 + PLACED ( 3648 840 ) N ; + - storage_6_0_0.select_inv_0 INV_X1 + PLACED ( 3724 840 ) N ; - tapcell.cell0_0 TAPCELL_X1 + PLACED ( 0 0 ) N ; - tapcell.cell0_1 TAPCELL_X1 + PLACED ( 0 140 ) FS ; - tapcell.cell0_2 TAPCELL_X1 + PLACED ( 0 280 ) N ; @@ -263,7 +263,7 @@ PINS 21 ; - D[0] + NET D[0] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER metal4 ( -7 -7 ) ( 7 7 ) - + PLACED ( 121 1113 ) N ; + + PLACED ( 9 1113 ) N ; - D[1] + NET D[1] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER metal4 ( -7 -7 ) ( 7 7 ) @@ -356,26 +356,26 @@ PINS 21 ; + LAYER metal1 ( 345 -1117 ) ( 352 -1109 ) + LAYER metal1 ( -3600 -1117 ) ( -3593 -1109 ) + FIXED ( 3600 1113 ) N ; - - addr[0] + NET addr[0] + DIRECTION INPUT + USE SIGNAL + - addr_rw[0] + NET addr_rw[0] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER metal3 ( -3 -3 ) ( 4 4 ) + PLACED ( 3948 230 ) N ; - - addr[1] + NET addr[1] + DIRECTION INPUT + USE SIGNAL + - addr_rw[1] + NET addr_rw[1] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER metal3 ( -3 -3 ) ( 4 4 ) + PLACED ( 3948 342 ) N ; - - addr[2] + NET addr[2] + DIRECTION INPUT + USE SIGNAL + - addr_rw[2] + NET addr_rw[2] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER metal3 ( -3 -3 ) ( 4 4 ) - + PLACED ( 3948 118 ) N ; + + PLACED ( 3948 62 ) N ; - clk + NET clk + DIRECTION INPUT + USE SIGNAL + PORT + LAYER metal3 ( -3 -3 ) ( 4 4 ) - + PLACED ( 3948 146 ) N ; + + PLACED ( 3948 90 ) N ; - we[0] + NET we[0] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER metal3 ( -3 -3 ) ( 4 4 ) - + PLACED ( 3948 174 ) N ; + + PLACED ( 3948 118 ) N ; END PINS SPECIALNETS 2 ; - VDD ( PIN VDD ) ( tapcell.cell4_7 VDD ) ( tapcell.cell4_6 VDD ) ( tapcell.cell4_5 VDD ) ( tapcell.cell4_4 VDD ) ( tapcell.cell4_3 VDD ) ( tapcell.cell4_2 VDD ) @@ -384,22 +384,22 @@ SPECIALNETS 2 ; ( tapcell.cell2_1 VDD ) ( tapcell.cell2_0 VDD ) ( tapcell.cell1_7 VDD ) ( tapcell.cell1_6 VDD ) ( tapcell.cell1_5 VDD ) ( tapcell.cell1_4 VDD ) ( tapcell.cell1_3 VDD ) ( tapcell.cell1_2 VDD ) ( tapcell.cell1_1 VDD ) ( tapcell.cell1_0 VDD ) ( tapcell.cell0_7 VDD ) ( tapcell.cell0_6 VDD ) ( tapcell.cell0_5 VDD ) ( tapcell.cell0_4 VDD ) ( tapcell.cell0_3 VDD ) ( tapcell.cell0_2 VDD ) ( tapcell.cell0_1 VDD ) ( tapcell.cell0_0 VDD ) ( decoder.inv_0 VDD ) ( decoder.inv_1 VDD ) ( decoder.inv_2 VDD ) ( buffer.in[6] VDD ) ( buffer.in[5] VDD ) ( buffer.in[4] VDD ) - ( buffer.in[3] VDD ) ( buffer.in[2] VDD ) ( buffer.in[1] VDD ) ( buffer.in[0] VDD ) ( storage_6_0.select_inv_0 VDD ) ( storage_6_0.gcand VDD ) ( storage_6_0.cg VDD ) ( storage_6_0.bit6.obuf0 VDD ) - ( storage_6_0.bit6.bit VDD ) ( storage_6_0.bit5.obuf0 VDD ) ( storage_6_0.bit5.bit VDD ) ( storage_6_0.bit4.obuf0 VDD ) ( storage_6_0.bit4.bit VDD ) ( storage_6_0.bit3.obuf0 VDD ) ( storage_6_0.bit3.bit VDD ) ( storage_6_0.bit2.obuf0 VDD ) - ( storage_6_0.bit2.bit VDD ) ( storage_6_0.bit1.obuf0 VDD ) ( storage_6_0.bit1.bit VDD ) ( storage_6_0.bit0.obuf0 VDD ) ( storage_6_0.bit0.bit VDD ) ( storage_5_0.select_inv_0 VDD ) ( storage_5_0.gcand VDD ) ( storage_5_0.cg VDD ) - ( storage_5_0.bit6.obuf0 VDD ) ( storage_5_0.bit6.bit VDD ) ( storage_5_0.bit5.obuf0 VDD ) ( storage_5_0.bit5.bit VDD ) ( storage_5_0.bit4.obuf0 VDD ) ( storage_5_0.bit4.bit VDD ) ( storage_5_0.bit3.obuf0 VDD ) ( storage_5_0.bit3.bit VDD ) - ( storage_5_0.bit2.obuf0 VDD ) ( storage_5_0.bit2.bit VDD ) ( storage_5_0.bit1.obuf0 VDD ) ( storage_5_0.bit1.bit VDD ) ( storage_5_0.bit0.obuf0 VDD ) ( storage_5_0.bit0.bit VDD ) ( storage_4_0.select_inv_0 VDD ) ( storage_4_0.gcand VDD ) - ( storage_4_0.cg VDD ) ( storage_4_0.bit6.obuf0 VDD ) ( storage_4_0.bit6.bit VDD ) ( storage_4_0.bit5.obuf0 VDD ) ( storage_4_0.bit5.bit VDD ) ( storage_4_0.bit4.obuf0 VDD ) ( storage_4_0.bit4.bit VDD ) ( storage_4_0.bit3.obuf0 VDD ) - ( storage_4_0.bit3.bit VDD ) ( storage_4_0.bit2.obuf0 VDD ) ( storage_4_0.bit2.bit VDD ) ( storage_4_0.bit1.obuf0 VDD ) ( storage_4_0.bit1.bit VDD ) ( storage_4_0.bit0.obuf0 VDD ) ( storage_4_0.bit0.bit VDD ) ( storage_3_0.select_inv_0 VDD ) - ( storage_3_0.gcand VDD ) ( storage_3_0.cg VDD ) ( storage_3_0.bit6.obuf0 VDD ) ( storage_3_0.bit6.bit VDD ) ( storage_3_0.bit5.obuf0 VDD ) ( storage_3_0.bit5.bit VDD ) ( storage_3_0.bit4.obuf0 VDD ) ( storage_3_0.bit4.bit VDD ) - ( storage_3_0.bit3.obuf0 VDD ) ( storage_3_0.bit3.bit VDD ) ( storage_3_0.bit2.obuf0 VDD ) ( storage_3_0.bit2.bit VDD ) ( storage_3_0.bit1.obuf0 VDD ) ( storage_3_0.bit1.bit VDD ) ( storage_3_0.bit0.obuf0 VDD ) ( storage_3_0.bit0.bit VDD ) - ( storage_2_0.select_inv_0 VDD ) ( storage_2_0.gcand VDD ) ( storage_2_0.cg VDD ) ( storage_2_0.bit6.obuf0 VDD ) ( storage_2_0.bit6.bit VDD ) ( storage_2_0.bit5.obuf0 VDD ) ( storage_2_0.bit5.bit VDD ) ( storage_2_0.bit4.obuf0 VDD ) - ( storage_2_0.bit4.bit VDD ) ( storage_2_0.bit3.obuf0 VDD ) ( storage_2_0.bit3.bit VDD ) ( storage_2_0.bit2.obuf0 VDD ) ( storage_2_0.bit2.bit VDD ) ( storage_2_0.bit1.obuf0 VDD ) ( storage_2_0.bit1.bit VDD ) ( storage_2_0.bit0.obuf0 VDD ) - ( storage_2_0.bit0.bit VDD ) ( storage_1_0.select_inv_0 VDD ) ( storage_1_0.gcand VDD ) ( storage_1_0.cg VDD ) ( storage_1_0.bit6.obuf0 VDD ) ( storage_1_0.bit6.bit VDD ) ( storage_1_0.bit5.obuf0 VDD ) ( storage_1_0.bit5.bit VDD ) - ( storage_1_0.bit4.obuf0 VDD ) ( storage_1_0.bit4.bit VDD ) ( storage_1_0.bit3.obuf0 VDD ) ( storage_1_0.bit3.bit VDD ) ( storage_1_0.bit2.obuf0 VDD ) ( storage_1_0.bit2.bit VDD ) ( storage_1_0.bit1.obuf0 VDD ) ( storage_1_0.bit1.bit VDD ) - ( storage_1_0.bit0.obuf0 VDD ) ( storage_1_0.bit0.bit VDD ) ( storage_0_0.select_inv_0 VDD ) ( storage_0_0.gcand VDD ) ( storage_0_0.cg VDD ) ( storage_0_0.bit6.obuf0 VDD ) ( storage_0_0.bit6.bit VDD ) ( storage_0_0.bit5.obuf0 VDD ) - ( storage_0_0.bit5.bit VDD ) ( storage_0_0.bit4.obuf0 VDD ) ( storage_0_0.bit4.bit VDD ) ( storage_0_0.bit3.obuf0 VDD ) ( storage_0_0.bit3.bit VDD ) ( storage_0_0.bit2.obuf0 VDD ) ( storage_0_0.bit2.bit VDD ) ( storage_0_0.bit1.obuf0 VDD ) - ( storage_0_0.bit1.bit VDD ) ( storage_0_0.bit0.obuf0 VDD ) ( storage_0_0.bit0.bit VDD ) ( decoder_6.buf_port0 VDD ) ( decoder_6.and_layer0 VDD ) ( decoder_5.buf_port0 VDD ) ( decoder_5.and_layer0 VDD ) ( decoder_4.buf_port0 VDD ) + ( buffer.in[3] VDD ) ( buffer.in[2] VDD ) ( buffer.in[1] VDD ) ( buffer.in[0] VDD ) ( storage_6_0_0.select_inv_0 VDD ) ( storage_6_0_0.gcand VDD ) ( storage_6_0_0.cg VDD ) ( storage_6_0_0.bit6.obuf0 VDD ) + ( storage_6_0_0.bit6.bit VDD ) ( storage_6_0_0.bit5.obuf0 VDD ) ( storage_6_0_0.bit5.bit VDD ) ( storage_6_0_0.bit4.obuf0 VDD ) ( storage_6_0_0.bit4.bit VDD ) ( storage_6_0_0.bit3.obuf0 VDD ) ( storage_6_0_0.bit3.bit VDD ) ( storage_6_0_0.bit2.obuf0 VDD ) + ( storage_6_0_0.bit2.bit VDD ) ( storage_6_0_0.bit1.obuf0 VDD ) ( storage_6_0_0.bit1.bit VDD ) ( storage_6_0_0.bit0.obuf0 VDD ) ( storage_6_0_0.bit0.bit VDD ) ( storage_5_0_0.select_inv_0 VDD ) ( storage_5_0_0.gcand VDD ) ( storage_5_0_0.cg VDD ) + ( storage_5_0_0.bit6.obuf0 VDD ) ( storage_5_0_0.bit6.bit VDD ) ( storage_5_0_0.bit5.obuf0 VDD ) ( storage_5_0_0.bit5.bit VDD ) ( storage_5_0_0.bit4.obuf0 VDD ) ( storage_5_0_0.bit4.bit VDD ) ( storage_5_0_0.bit3.obuf0 VDD ) ( storage_5_0_0.bit3.bit VDD ) + ( storage_5_0_0.bit2.obuf0 VDD ) ( storage_5_0_0.bit2.bit VDD ) ( storage_5_0_0.bit1.obuf0 VDD ) ( storage_5_0_0.bit1.bit VDD ) ( storage_5_0_0.bit0.obuf0 VDD ) ( storage_5_0_0.bit0.bit VDD ) ( storage_4_0_0.select_inv_0 VDD ) ( storage_4_0_0.gcand VDD ) + ( storage_4_0_0.cg VDD ) ( storage_4_0_0.bit6.obuf0 VDD ) ( storage_4_0_0.bit6.bit VDD ) ( storage_4_0_0.bit5.obuf0 VDD ) ( storage_4_0_0.bit5.bit VDD ) ( storage_4_0_0.bit4.obuf0 VDD ) ( storage_4_0_0.bit4.bit VDD ) ( storage_4_0_0.bit3.obuf0 VDD ) + ( storage_4_0_0.bit3.bit VDD ) ( storage_4_0_0.bit2.obuf0 VDD ) ( storage_4_0_0.bit2.bit VDD ) ( storage_4_0_0.bit1.obuf0 VDD ) ( storage_4_0_0.bit1.bit VDD ) ( storage_4_0_0.bit0.obuf0 VDD ) ( storage_4_0_0.bit0.bit VDD ) ( storage_3_0_0.select_inv_0 VDD ) + ( storage_3_0_0.gcand VDD ) ( storage_3_0_0.cg VDD ) ( storage_3_0_0.bit6.obuf0 VDD ) ( storage_3_0_0.bit6.bit VDD ) ( storage_3_0_0.bit5.obuf0 VDD ) ( storage_3_0_0.bit5.bit VDD ) ( storage_3_0_0.bit4.obuf0 VDD ) ( storage_3_0_0.bit4.bit VDD ) + ( storage_3_0_0.bit3.obuf0 VDD ) ( storage_3_0_0.bit3.bit VDD ) ( storage_3_0_0.bit2.obuf0 VDD ) ( storage_3_0_0.bit2.bit VDD ) ( storage_3_0_0.bit1.obuf0 VDD ) ( storage_3_0_0.bit1.bit VDD ) ( storage_3_0_0.bit0.obuf0 VDD ) ( storage_3_0_0.bit0.bit VDD ) + ( storage_2_0_0.select_inv_0 VDD ) ( storage_2_0_0.gcand VDD ) ( storage_2_0_0.cg VDD ) ( storage_2_0_0.bit6.obuf0 VDD ) ( storage_2_0_0.bit6.bit VDD ) ( storage_2_0_0.bit5.obuf0 VDD ) ( storage_2_0_0.bit5.bit VDD ) ( storage_2_0_0.bit4.obuf0 VDD ) + ( storage_2_0_0.bit4.bit VDD ) ( storage_2_0_0.bit3.obuf0 VDD ) ( storage_2_0_0.bit3.bit VDD ) ( storage_2_0_0.bit2.obuf0 VDD ) ( storage_2_0_0.bit2.bit VDD ) ( storage_2_0_0.bit1.obuf0 VDD ) ( storage_2_0_0.bit1.bit VDD ) ( storage_2_0_0.bit0.obuf0 VDD ) + ( storage_2_0_0.bit0.bit VDD ) ( storage_1_0_0.select_inv_0 VDD ) ( storage_1_0_0.gcand VDD ) ( storage_1_0_0.cg VDD ) ( storage_1_0_0.bit6.obuf0 VDD ) ( storage_1_0_0.bit6.bit VDD ) ( storage_1_0_0.bit5.obuf0 VDD ) ( storage_1_0_0.bit5.bit VDD ) + ( storage_1_0_0.bit4.obuf0 VDD ) ( storage_1_0_0.bit4.bit VDD ) ( storage_1_0_0.bit3.obuf0 VDD ) ( storage_1_0_0.bit3.bit VDD ) ( storage_1_0_0.bit2.obuf0 VDD ) ( storage_1_0_0.bit2.bit VDD ) ( storage_1_0_0.bit1.obuf0 VDD ) ( storage_1_0_0.bit1.bit VDD ) + ( storage_1_0_0.bit0.obuf0 VDD ) ( storage_1_0_0.bit0.bit VDD ) ( storage_0_0_0.select_inv_0 VDD ) ( storage_0_0_0.gcand VDD ) ( storage_0_0_0.cg VDD ) ( storage_0_0_0.bit6.obuf0 VDD ) ( storage_0_0_0.bit6.bit VDD ) ( storage_0_0_0.bit5.obuf0 VDD ) + ( storage_0_0_0.bit5.bit VDD ) ( storage_0_0_0.bit4.obuf0 VDD ) ( storage_0_0_0.bit4.bit VDD ) ( storage_0_0_0.bit3.obuf0 VDD ) ( storage_0_0_0.bit3.bit VDD ) ( storage_0_0_0.bit2.obuf0 VDD ) ( storage_0_0_0.bit2.bit VDD ) ( storage_0_0_0.bit1.obuf0 VDD ) + ( storage_0_0_0.bit1.bit VDD ) ( storage_0_0_0.bit0.obuf0 VDD ) ( storage_0_0_0.bit0.bit VDD ) ( decoder_6.buf_port0 VDD ) ( decoder_6.and_layer0 VDD ) ( decoder_5.buf_port0 VDD ) ( decoder_5.and_layer0 VDD ) ( decoder_4.buf_port0 VDD ) ( decoder_4.and_layer0 VDD ) ( decoder_3.buf_port0 VDD ) ( decoder_3.and_layer0 VDD ) ( decoder_2.buf_port0 VDD ) ( decoder_2.and_layer0 VDD ) ( decoder_1.buf_port0 VDD ) ( decoder_1.and_layer0 VDD ) ( decoder_0.buf_port0 VDD ) ( decoder_0.and_layer0 VDD ) + USE POWER + ROUTED metal4 14 + SHAPE STRIPE ( 3150 0 ) ( 3150 1120 ) @@ -464,22 +464,22 @@ SPECIALNETS 2 ; ( tapcell.cell2_1 VSS ) ( tapcell.cell2_0 VSS ) ( tapcell.cell1_7 VSS ) ( tapcell.cell1_6 VSS ) ( tapcell.cell1_5 VSS ) ( tapcell.cell1_4 VSS ) ( tapcell.cell1_3 VSS ) ( tapcell.cell1_2 VSS ) ( tapcell.cell1_1 VSS ) ( tapcell.cell1_0 VSS ) ( tapcell.cell0_7 VSS ) ( tapcell.cell0_6 VSS ) ( tapcell.cell0_5 VSS ) ( tapcell.cell0_4 VSS ) ( tapcell.cell0_3 VSS ) ( tapcell.cell0_2 VSS ) ( tapcell.cell0_1 VSS ) ( tapcell.cell0_0 VSS ) ( decoder.inv_0 VSS ) ( decoder.inv_1 VSS ) ( decoder.inv_2 VSS ) ( buffer.in[6] VSS ) ( buffer.in[5] VSS ) ( buffer.in[4] VSS ) - ( buffer.in[3] VSS ) ( buffer.in[2] VSS ) ( buffer.in[1] VSS ) ( buffer.in[0] VSS ) ( storage_6_0.select_inv_0 VSS ) ( storage_6_0.gcand VSS ) ( storage_6_0.cg VSS ) ( storage_6_0.bit6.obuf0 VSS ) - ( storage_6_0.bit6.bit VSS ) ( storage_6_0.bit5.obuf0 VSS ) ( storage_6_0.bit5.bit VSS ) ( storage_6_0.bit4.obuf0 VSS ) ( storage_6_0.bit4.bit VSS ) ( storage_6_0.bit3.obuf0 VSS ) ( storage_6_0.bit3.bit VSS ) ( storage_6_0.bit2.obuf0 VSS ) - ( storage_6_0.bit2.bit VSS ) ( storage_6_0.bit1.obuf0 VSS ) ( storage_6_0.bit1.bit VSS ) ( storage_6_0.bit0.obuf0 VSS ) ( storage_6_0.bit0.bit VSS ) ( storage_5_0.select_inv_0 VSS ) ( storage_5_0.gcand VSS ) ( storage_5_0.cg VSS ) - ( storage_5_0.bit6.obuf0 VSS ) ( storage_5_0.bit6.bit VSS ) ( storage_5_0.bit5.obuf0 VSS ) ( storage_5_0.bit5.bit VSS ) ( storage_5_0.bit4.obuf0 VSS ) ( storage_5_0.bit4.bit VSS ) ( storage_5_0.bit3.obuf0 VSS ) ( storage_5_0.bit3.bit VSS ) - ( storage_5_0.bit2.obuf0 VSS ) ( storage_5_0.bit2.bit VSS ) ( storage_5_0.bit1.obuf0 VSS ) ( storage_5_0.bit1.bit VSS ) ( storage_5_0.bit0.obuf0 VSS ) ( storage_5_0.bit0.bit VSS ) ( storage_4_0.select_inv_0 VSS ) ( storage_4_0.gcand VSS ) - ( storage_4_0.cg VSS ) ( storage_4_0.bit6.obuf0 VSS ) ( storage_4_0.bit6.bit VSS ) ( storage_4_0.bit5.obuf0 VSS ) ( storage_4_0.bit5.bit VSS ) ( storage_4_0.bit4.obuf0 VSS ) ( storage_4_0.bit4.bit VSS ) ( storage_4_0.bit3.obuf0 VSS ) - ( storage_4_0.bit3.bit VSS ) ( storage_4_0.bit2.obuf0 VSS ) ( storage_4_0.bit2.bit VSS ) ( storage_4_0.bit1.obuf0 VSS ) ( storage_4_0.bit1.bit VSS ) ( storage_4_0.bit0.obuf0 VSS ) ( storage_4_0.bit0.bit VSS ) ( storage_3_0.select_inv_0 VSS ) - ( storage_3_0.gcand VSS ) ( storage_3_0.cg VSS ) ( storage_3_0.bit6.obuf0 VSS ) ( storage_3_0.bit6.bit VSS ) ( storage_3_0.bit5.obuf0 VSS ) ( storage_3_0.bit5.bit VSS ) ( storage_3_0.bit4.obuf0 VSS ) ( storage_3_0.bit4.bit VSS ) - ( storage_3_0.bit3.obuf0 VSS ) ( storage_3_0.bit3.bit VSS ) ( storage_3_0.bit2.obuf0 VSS ) ( storage_3_0.bit2.bit VSS ) ( storage_3_0.bit1.obuf0 VSS ) ( storage_3_0.bit1.bit VSS ) ( storage_3_0.bit0.obuf0 VSS ) ( storage_3_0.bit0.bit VSS ) - ( storage_2_0.select_inv_0 VSS ) ( storage_2_0.gcand VSS ) ( storage_2_0.cg VSS ) ( storage_2_0.bit6.obuf0 VSS ) ( storage_2_0.bit6.bit VSS ) ( storage_2_0.bit5.obuf0 VSS ) ( storage_2_0.bit5.bit VSS ) ( storage_2_0.bit4.obuf0 VSS ) - ( storage_2_0.bit4.bit VSS ) ( storage_2_0.bit3.obuf0 VSS ) ( storage_2_0.bit3.bit VSS ) ( storage_2_0.bit2.obuf0 VSS ) ( storage_2_0.bit2.bit VSS ) ( storage_2_0.bit1.obuf0 VSS ) ( storage_2_0.bit1.bit VSS ) ( storage_2_0.bit0.obuf0 VSS ) - ( storage_2_0.bit0.bit VSS ) ( storage_1_0.select_inv_0 VSS ) ( storage_1_0.gcand VSS ) ( storage_1_0.cg VSS ) ( storage_1_0.bit6.obuf0 VSS ) ( storage_1_0.bit6.bit VSS ) ( storage_1_0.bit5.obuf0 VSS ) ( storage_1_0.bit5.bit VSS ) - ( storage_1_0.bit4.obuf0 VSS ) ( storage_1_0.bit4.bit VSS ) ( storage_1_0.bit3.obuf0 VSS ) ( storage_1_0.bit3.bit VSS ) ( storage_1_0.bit2.obuf0 VSS ) ( storage_1_0.bit2.bit VSS ) ( storage_1_0.bit1.obuf0 VSS ) ( storage_1_0.bit1.bit VSS ) - ( storage_1_0.bit0.obuf0 VSS ) ( storage_1_0.bit0.bit VSS ) ( storage_0_0.select_inv_0 VSS ) ( storage_0_0.gcand VSS ) ( storage_0_0.cg VSS ) ( storage_0_0.bit6.obuf0 VSS ) ( storage_0_0.bit6.bit VSS ) ( storage_0_0.bit5.obuf0 VSS ) - ( storage_0_0.bit5.bit VSS ) ( storage_0_0.bit4.obuf0 VSS ) ( storage_0_0.bit4.bit VSS ) ( storage_0_0.bit3.obuf0 VSS ) ( storage_0_0.bit3.bit VSS ) ( storage_0_0.bit2.obuf0 VSS ) ( storage_0_0.bit2.bit VSS ) ( storage_0_0.bit1.obuf0 VSS ) - ( storage_0_0.bit1.bit VSS ) ( storage_0_0.bit0.obuf0 VSS ) ( storage_0_0.bit0.bit VSS ) ( decoder_6.buf_port0 VSS ) ( decoder_6.and_layer0 VSS ) ( decoder_5.buf_port0 VSS ) ( decoder_5.and_layer0 VSS ) ( decoder_4.buf_port0 VSS ) + ( buffer.in[3] VSS ) ( buffer.in[2] VSS ) ( buffer.in[1] VSS ) ( buffer.in[0] VSS ) ( storage_6_0_0.select_inv_0 VSS ) ( storage_6_0_0.gcand VSS ) ( storage_6_0_0.cg VSS ) ( storage_6_0_0.bit6.obuf0 VSS ) + ( storage_6_0_0.bit6.bit VSS ) ( storage_6_0_0.bit5.obuf0 VSS ) ( storage_6_0_0.bit5.bit VSS ) ( storage_6_0_0.bit4.obuf0 VSS ) ( storage_6_0_0.bit4.bit VSS ) ( storage_6_0_0.bit3.obuf0 VSS ) ( storage_6_0_0.bit3.bit VSS ) ( storage_6_0_0.bit2.obuf0 VSS ) + ( storage_6_0_0.bit2.bit VSS ) ( storage_6_0_0.bit1.obuf0 VSS ) ( storage_6_0_0.bit1.bit VSS ) ( storage_6_0_0.bit0.obuf0 VSS ) ( storage_6_0_0.bit0.bit VSS ) ( storage_5_0_0.select_inv_0 VSS ) ( storage_5_0_0.gcand VSS ) ( storage_5_0_0.cg VSS ) + ( storage_5_0_0.bit6.obuf0 VSS ) ( storage_5_0_0.bit6.bit VSS ) ( storage_5_0_0.bit5.obuf0 VSS ) ( storage_5_0_0.bit5.bit VSS ) ( storage_5_0_0.bit4.obuf0 VSS ) ( storage_5_0_0.bit4.bit VSS ) ( storage_5_0_0.bit3.obuf0 VSS ) ( storage_5_0_0.bit3.bit VSS ) + ( storage_5_0_0.bit2.obuf0 VSS ) ( storage_5_0_0.bit2.bit VSS ) ( storage_5_0_0.bit1.obuf0 VSS ) ( storage_5_0_0.bit1.bit VSS ) ( storage_5_0_0.bit0.obuf0 VSS ) ( storage_5_0_0.bit0.bit VSS ) ( storage_4_0_0.select_inv_0 VSS ) ( storage_4_0_0.gcand VSS ) + ( storage_4_0_0.cg VSS ) ( storage_4_0_0.bit6.obuf0 VSS ) ( storage_4_0_0.bit6.bit VSS ) ( storage_4_0_0.bit5.obuf0 VSS ) ( storage_4_0_0.bit5.bit VSS ) ( storage_4_0_0.bit4.obuf0 VSS ) ( storage_4_0_0.bit4.bit VSS ) ( storage_4_0_0.bit3.obuf0 VSS ) + ( storage_4_0_0.bit3.bit VSS ) ( storage_4_0_0.bit2.obuf0 VSS ) ( storage_4_0_0.bit2.bit VSS ) ( storage_4_0_0.bit1.obuf0 VSS ) ( storage_4_0_0.bit1.bit VSS ) ( storage_4_0_0.bit0.obuf0 VSS ) ( storage_4_0_0.bit0.bit VSS ) ( storage_3_0_0.select_inv_0 VSS ) + ( storage_3_0_0.gcand VSS ) ( storage_3_0_0.cg VSS ) ( storage_3_0_0.bit6.obuf0 VSS ) ( storage_3_0_0.bit6.bit VSS ) ( storage_3_0_0.bit5.obuf0 VSS ) ( storage_3_0_0.bit5.bit VSS ) ( storage_3_0_0.bit4.obuf0 VSS ) ( storage_3_0_0.bit4.bit VSS ) + ( storage_3_0_0.bit3.obuf0 VSS ) ( storage_3_0_0.bit3.bit VSS ) ( storage_3_0_0.bit2.obuf0 VSS ) ( storage_3_0_0.bit2.bit VSS ) ( storage_3_0_0.bit1.obuf0 VSS ) ( storage_3_0_0.bit1.bit VSS ) ( storage_3_0_0.bit0.obuf0 VSS ) ( storage_3_0_0.bit0.bit VSS ) + ( storage_2_0_0.select_inv_0 VSS ) ( storage_2_0_0.gcand VSS ) ( storage_2_0_0.cg VSS ) ( storage_2_0_0.bit6.obuf0 VSS ) ( storage_2_0_0.bit6.bit VSS ) ( storage_2_0_0.bit5.obuf0 VSS ) ( storage_2_0_0.bit5.bit VSS ) ( storage_2_0_0.bit4.obuf0 VSS ) + ( storage_2_0_0.bit4.bit VSS ) ( storage_2_0_0.bit3.obuf0 VSS ) ( storage_2_0_0.bit3.bit VSS ) ( storage_2_0_0.bit2.obuf0 VSS ) ( storage_2_0_0.bit2.bit VSS ) ( storage_2_0_0.bit1.obuf0 VSS ) ( storage_2_0_0.bit1.bit VSS ) ( storage_2_0_0.bit0.obuf0 VSS ) + ( storage_2_0_0.bit0.bit VSS ) ( storage_1_0_0.select_inv_0 VSS ) ( storage_1_0_0.gcand VSS ) ( storage_1_0_0.cg VSS ) ( storage_1_0_0.bit6.obuf0 VSS ) ( storage_1_0_0.bit6.bit VSS ) ( storage_1_0_0.bit5.obuf0 VSS ) ( storage_1_0_0.bit5.bit VSS ) + ( storage_1_0_0.bit4.obuf0 VSS ) ( storage_1_0_0.bit4.bit VSS ) ( storage_1_0_0.bit3.obuf0 VSS ) ( storage_1_0_0.bit3.bit VSS ) ( storage_1_0_0.bit2.obuf0 VSS ) ( storage_1_0_0.bit2.bit VSS ) ( storage_1_0_0.bit1.obuf0 VSS ) ( storage_1_0_0.bit1.bit VSS ) + ( storage_1_0_0.bit0.obuf0 VSS ) ( storage_1_0_0.bit0.bit VSS ) ( storage_0_0_0.select_inv_0 VSS ) ( storage_0_0_0.gcand VSS ) ( storage_0_0_0.cg VSS ) ( storage_0_0_0.bit6.obuf0 VSS ) ( storage_0_0_0.bit6.bit VSS ) ( storage_0_0_0.bit5.obuf0 VSS ) + ( storage_0_0_0.bit5.bit VSS ) ( storage_0_0_0.bit4.obuf0 VSS ) ( storage_0_0_0.bit4.bit VSS ) ( storage_0_0_0.bit3.obuf0 VSS ) ( storage_0_0_0.bit3.bit VSS ) ( storage_0_0_0.bit2.obuf0 VSS ) ( storage_0_0_0.bit2.bit VSS ) ( storage_0_0_0.bit1.obuf0 VSS ) + ( storage_0_0_0.bit1.bit VSS ) ( storage_0_0_0.bit0.obuf0 VSS ) ( storage_0_0_0.bit0.bit VSS ) ( decoder_6.buf_port0 VSS ) ( decoder_6.and_layer0 VSS ) ( decoder_5.buf_port0 VSS ) ( decoder_5.and_layer0 VSS ) ( decoder_4.buf_port0 VSS ) ( decoder_4.and_layer0 VSS ) ( decoder_3.buf_port0 VSS ) ( decoder_3.and_layer0 VSS ) ( decoder_2.buf_port0 VSS ) ( decoder_2.and_layer0 VSS ) ( decoder_1.buf_port0 VSS ) ( decoder_1.and_layer0 VSS ) ( decoder_0.buf_port0 VSS ) ( decoder_0.and_layer0 VSS ) + USE GROUND + ROUTED metal4 14 + SHAPE STRIPE ( 3600 -7 ) ( 3600 1127 ) @@ -554,9 +554,9 @@ SPECIALNETS 2 ; END SPECIALNETS NETS 120 ; - D[0] ( PIN D[0] ) ( buffer.in[0] A ) + USE SIGNAL - + ROUTED metal4 ( 121 1057 ) ( * 1113 0 ) - NEW metal3 ( 28 1057 ) ( 121 * ) - NEW metal3 ( 121 1057 ) via3_2 + + ROUTED metal4 ( 9 1057 ) ( * 1113 0 ) + NEW metal3 ( 9 1057 ) ( 28 * ) + NEW metal3 ( 9 1057 ) via3_2 NEW metal1 ( 28 1057 ) via1_4 NEW metal2 ( 28 1057 ) via2_5 ; - D[1] ( PIN D[1] ) ( buffer.in[1] A ) + USE SIGNAL @@ -595,8 +595,8 @@ NETS 120 ; NEW metal3 ( 2921 1057 ) via3_2 NEW metal1 ( 2935 1057 ) via1_4 NEW metal2 ( 2935 1057 ) via2_5 ; - - D_nets[0].net ( buffer.in[0] Z ) ( storage_6_0.bit0.bit D ) ( storage_5_0.bit0.bit D ) ( storage_4_0.bit0.bit D ) ( storage_3_0.bit0.bit D ) ( storage_2_0.bit0.bit D ) ( storage_1_0.bit0.bit D ) - ( storage_0_0.bit0.bit D ) + USE SIGNAL + - D_nets.b0 ( buffer.in[0] Z ) ( storage_6_0_0.bit0.bit D ) ( storage_5_0_0.bit0.bit D ) ( storage_4_0_0.bit0.bit D ) ( storage_3_0_0.bit0.bit D ) ( storage_2_0_0.bit0.bit D ) ( storage_1_0_0.bit0.bit D ) + ( storage_0_0_0.bit0.bit D ) + USE SIGNAL + ROUTED metal2 ( 104 903 ) ( * 1001 ) NEW metal2 ( 66 1001 ) ( 104 * ) NEW metal2 ( 104 777 ) ( * 903 ) @@ -613,8 +613,8 @@ NETS 120 ; NEW metal1 ( 104 343 ) via1_4 NEW metal1 ( 104 217 ) via1_4 NEW metal1 ( 104 63 ) via1_4 ; - - D_nets[1].net ( buffer.in[1] Z ) ( storage_6_0.bit1.bit D ) ( storage_5_0.bit1.bit D ) ( storage_4_0.bit1.bit D ) ( storage_3_0.bit1.bit D ) ( storage_2_0.bit1.bit D ) ( storage_1_0.bit1.bit D ) - ( storage_0_0.bit1.bit D ) + USE SIGNAL + - D_nets.b1 ( buffer.in[1] Z ) ( storage_6_0_0.bit1.bit D ) ( storage_5_0_0.bit1.bit D ) ( storage_4_0_0.bit1.bit D ) ( storage_3_0_0.bit1.bit D ) ( storage_2_0_0.bit1.bit D ) ( storage_1_0_0.bit1.bit D ) + ( storage_0_0_0.bit1.bit D ) + USE SIGNAL + ROUTED metal2 ( 579 903 ) ( * 1001 ) NEW metal2 ( 541 1001 ) ( 579 * ) NEW metal2 ( 579 777 ) ( * 903 ) @@ -631,8 +631,8 @@ NETS 120 ; NEW metal1 ( 579 343 ) via1_4 NEW metal1 ( 579 217 ) via1_4 NEW metal1 ( 579 63 ) via1_4 ; - - D_nets[2].net ( buffer.in[2] Z ) ( storage_6_0.bit2.bit D ) ( storage_5_0.bit2.bit D ) ( storage_4_0.bit2.bit D ) ( storage_3_0.bit2.bit D ) ( storage_2_0.bit2.bit D ) ( storage_1_0.bit2.bit D ) - ( storage_0_0.bit2.bit D ) + USE SIGNAL + - D_nets.b2 ( buffer.in[2] Z ) ( storage_6_0_0.bit2.bit D ) ( storage_5_0_0.bit2.bit D ) ( storage_4_0_0.bit2.bit D ) ( storage_3_0_0.bit2.bit D ) ( storage_2_0_0.bit2.bit D ) ( storage_1_0_0.bit2.bit D ) + ( storage_0_0_0.bit2.bit D ) + USE SIGNAL + ROUTED metal2 ( 1073 903 ) ( * 1001 ) NEW metal2 ( 1035 1001 ) ( 1073 * ) NEW metal2 ( 1073 777 ) ( * 903 ) @@ -649,8 +649,8 @@ NETS 120 ; NEW metal1 ( 1073 343 ) via1_4 NEW metal1 ( 1073 217 ) via1_4 NEW metal1 ( 1073 63 ) via1_4 ; - - D_nets[3].net ( buffer.in[3] Z ) ( storage_6_0.bit3.bit D ) ( storage_5_0.bit3.bit D ) ( storage_4_0.bit3.bit D ) ( storage_3_0.bit3.bit D ) ( storage_2_0.bit3.bit D ) ( storage_1_0.bit3.bit D ) - ( storage_0_0.bit3.bit D ) + USE SIGNAL + - D_nets.b3 ( buffer.in[3] Z ) ( storage_6_0_0.bit3.bit D ) ( storage_5_0_0.bit3.bit D ) ( storage_4_0_0.bit3.bit D ) ( storage_3_0_0.bit3.bit D ) ( storage_2_0_0.bit3.bit D ) ( storage_1_0_0.bit3.bit D ) + ( storage_0_0_0.bit3.bit D ) + USE SIGNAL + ROUTED metal2 ( 1548 903 ) ( * 1001 ) NEW metal2 ( 1510 1001 ) ( 1548 * ) NEW metal2 ( 1548 777 ) ( * 903 ) @@ -667,8 +667,8 @@ NETS 120 ; NEW metal1 ( 1548 343 ) via1_4 NEW metal1 ( 1548 217 ) via1_4 NEW metal1 ( 1548 63 ) via1_4 ; - - D_nets[4].net ( buffer.in[4] Z ) ( storage_6_0.bit4.bit D ) ( storage_5_0.bit4.bit D ) ( storage_4_0.bit4.bit D ) ( storage_3_0.bit4.bit D ) ( storage_2_0.bit4.bit D ) ( storage_1_0.bit4.bit D ) - ( storage_0_0.bit4.bit D ) + USE SIGNAL + - D_nets.b4 ( buffer.in[4] Z ) ( storage_6_0_0.bit4.bit D ) ( storage_5_0_0.bit4.bit D ) ( storage_4_0_0.bit4.bit D ) ( storage_3_0_0.bit4.bit D ) ( storage_2_0_0.bit4.bit D ) ( storage_1_0_0.bit4.bit D ) + ( storage_0_0_0.bit4.bit D ) + USE SIGNAL + ROUTED metal2 ( 2042 903 ) ( * 1001 ) NEW metal2 ( 2004 1001 ) ( 2042 * ) NEW metal2 ( 2042 777 ) ( * 903 ) @@ -685,8 +685,8 @@ NETS 120 ; NEW metal1 ( 2042 343 ) via1_4 NEW metal1 ( 2042 217 ) via1_4 NEW metal1 ( 2042 63 ) via1_4 ; - - D_nets[5].net ( buffer.in[5] Z ) ( storage_6_0.bit5.bit D ) ( storage_5_0.bit5.bit D ) ( storage_4_0.bit5.bit D ) ( storage_3_0.bit5.bit D ) ( storage_2_0.bit5.bit D ) ( storage_1_0.bit5.bit D ) - ( storage_0_0.bit5.bit D ) + USE SIGNAL + - D_nets.b5 ( buffer.in[5] Z ) ( storage_6_0_0.bit5.bit D ) ( storage_5_0_0.bit5.bit D ) ( storage_4_0_0.bit5.bit D ) ( storage_3_0_0.bit5.bit D ) ( storage_2_0_0.bit5.bit D ) ( storage_1_0_0.bit5.bit D ) + ( storage_0_0_0.bit5.bit D ) + USE SIGNAL + ROUTED metal2 ( 2517 903 ) ( * 1001 ) NEW metal2 ( 2479 1001 ) ( 2517 * ) NEW metal2 ( 2517 777 ) ( * 903 ) @@ -703,8 +703,8 @@ NETS 120 ; NEW metal1 ( 2517 343 ) via1_4 NEW metal1 ( 2517 217 ) via1_4 NEW metal1 ( 2517 63 ) via1_4 ; - - D_nets[6].net ( buffer.in[6] Z ) ( storage_6_0.bit6.bit D ) ( storage_5_0.bit6.bit D ) ( storage_4_0.bit6.bit D ) ( storage_3_0.bit6.bit D ) ( storage_2_0.bit6.bit D ) ( storage_1_0.bit6.bit D ) - ( storage_0_0.bit6.bit D ) + USE SIGNAL + - D_nets.b6 ( buffer.in[6] Z ) ( storage_6_0_0.bit6.bit D ) ( storage_5_0_0.bit6.bit D ) ( storage_4_0_0.bit6.bit D ) ( storage_3_0_0.bit6.bit D ) ( storage_2_0_0.bit6.bit D ) ( storage_1_0_0.bit6.bit D ) + ( storage_0_0_0.bit6.bit D ) + USE SIGNAL + ROUTED metal2 ( 3011 903 ) ( * 1001 ) NEW metal2 ( 2973 1001 ) ( 3011 * ) NEW metal2 ( 3011 777 ) ( * 903 ) @@ -721,8 +721,8 @@ NETS 120 ; NEW metal1 ( 3011 343 ) via1_4 NEW metal1 ( 3011 217 ) via1_4 NEW metal1 ( 3011 63 ) via1_4 ; - - Q[0] ( PIN Q[0] ) ( storage_6_0.bit0.obuf0 Z ) ( storage_5_0.bit0.obuf0 Z ) ( storage_4_0.bit0.obuf0 Z ) ( storage_3_0.bit0.obuf0 Z ) ( storage_2_0.bit0.obuf0 Z ) ( storage_1_0.bit0.obuf0 Z ) - ( storage_0_0.bit0.obuf0 Z ) + USE SIGNAL + - Q[0] ( PIN Q[0] ) ( storage_6_0_0.bit0.obuf0 Z ) ( storage_5_0_0.bit0.obuf0 Z ) ( storage_4_0_0.bit0.obuf0 Z ) ( storage_3_0_0.bit0.obuf0 Z ) ( storage_2_0_0.bit0.obuf0 Z ) ( storage_1_0_0.bit0.obuf0 Z ) + ( storage_0_0_0.bit0.obuf0 Z ) + USE SIGNAL + ROUTED metal3 ( 345 945 ) ( 351 * ) NEW metal4 ( 345 945 ) ( * 1113 0 ) NEW metal2 ( 351 805 ) ( * 875 ) @@ -746,8 +746,8 @@ NETS 120 ; NEW metal1 ( 351 315 ) via1_4 NEW metal1 ( 351 105 ) via1_4 NEW metal1 ( 351 175 ) via1_4 ; - - Q[1] ( PIN Q[1] ) ( storage_6_0.bit1.obuf0 Z ) ( storage_5_0.bit1.obuf0 Z ) ( storage_4_0.bit1.obuf0 Z ) ( storage_3_0.bit1.obuf0 Z ) ( storage_2_0.bit1.obuf0 Z ) ( storage_1_0.bit1.obuf0 Z ) - ( storage_0_0.bit1.obuf0 Z ) + USE SIGNAL + - Q[1] ( PIN Q[1] ) ( storage_6_0_0.bit1.obuf0 Z ) ( storage_5_0_0.bit1.obuf0 Z ) ( storage_4_0_0.bit1.obuf0 Z ) ( storage_3_0_0.bit1.obuf0 Z ) ( storage_2_0_0.bit1.obuf0 Z ) ( storage_1_0_0.bit1.obuf0 Z ) + ( storage_0_0_0.bit1.obuf0 Z ) + USE SIGNAL + ROUTED metal3 ( 826 945 ) ( 849 * ) NEW metal4 ( 849 945 ) ( * 1113 0 ) NEW metal2 ( 826 805 ) ( * 945 ) @@ -765,8 +765,8 @@ NETS 120 ; NEW metal1 ( 826 385 ) via1_4 NEW metal1 ( 826 245 ) via1_4 NEW metal1 ( 826 105 ) via1_4 ; - - Q[2] ( PIN Q[2] ) ( storage_6_0.bit2.obuf0 Z ) ( storage_5_0.bit2.obuf0 Z ) ( storage_4_0.bit2.obuf0 Z ) ( storage_3_0.bit2.obuf0 Z ) ( storage_2_0.bit2.obuf0 Z ) ( storage_1_0.bit2.obuf0 Z ) - ( storage_0_0.bit2.obuf0 Z ) + USE SIGNAL + - Q[2] ( PIN Q[2] ) ( storage_6_0_0.bit2.obuf0 Z ) ( storage_5_0_0.bit2.obuf0 Z ) ( storage_4_0_0.bit2.obuf0 Z ) ( storage_3_0_0.bit2.obuf0 Z ) ( storage_2_0_0.bit2.obuf0 Z ) ( storage_1_0_0.bit2.obuf0 Z ) + ( storage_0_0_0.bit2.obuf0 Z ) + USE SIGNAL + ROUTED metal3 ( 1297 945 ) ( 1320 * ) NEW metal4 ( 1297 945 ) ( * 1113 0 ) NEW metal2 ( 1320 805 ) ( * 875 ) @@ -790,8 +790,8 @@ NETS 120 ; NEW metal1 ( 1320 315 ) via1_4 NEW metal1 ( 1320 105 ) via1_4 NEW metal1 ( 1320 175 ) via1_4 ; - - Q[3] ( PIN Q[3] ) ( storage_6_0.bit3.obuf0 Z ) ( storage_5_0.bit3.obuf0 Z ) ( storage_4_0.bit3.obuf0 Z ) ( storage_3_0.bit3.obuf0 Z ) ( storage_2_0.bit3.obuf0 Z ) ( storage_1_0.bit3.obuf0 Z ) - ( storage_0_0.bit3.obuf0 Z ) + USE SIGNAL + - Q[3] ( PIN Q[3] ) ( storage_6_0_0.bit3.obuf0 Z ) ( storage_5_0_0.bit3.obuf0 Z ) ( storage_4_0_0.bit3.obuf0 Z ) ( storage_3_0_0.bit3.obuf0 Z ) ( storage_2_0_0.bit3.obuf0 Z ) ( storage_1_0_0.bit3.obuf0 Z ) + ( storage_0_0_0.bit3.obuf0 Z ) + USE SIGNAL + ROUTED metal3 ( 1745 945 ) ( 1795 * ) NEW metal4 ( 1745 945 ) ( * 1113 0 ) NEW metal2 ( 1776 805 ) ( 1795 * ) @@ -821,8 +821,8 @@ NETS 120 ; NEW metal1 ( 1795 315 ) via1_4 NEW metal1 ( 1795 105 ) via1_4 NEW metal1 ( 1795 175 ) via1_4 ; - - Q[4] ( PIN Q[4] ) ( storage_6_0.bit4.obuf0 Z ) ( storage_5_0.bit4.obuf0 Z ) ( storage_4_0.bit4.obuf0 Z ) ( storage_3_0.bit4.obuf0 Z ) ( storage_2_0.bit4.obuf0 Z ) ( storage_1_0.bit4.obuf0 Z ) - ( storage_0_0.bit4.obuf0 Z ) + USE SIGNAL + - Q[4] ( PIN Q[4] ) ( storage_6_0_0.bit4.obuf0 Z ) ( storage_5_0_0.bit4.obuf0 Z ) ( storage_4_0_0.bit4.obuf0 Z ) ( storage_3_0_0.bit4.obuf0 Z ) ( storage_2_0_0.bit4.obuf0 Z ) ( storage_1_0_0.bit4.obuf0 Z ) + ( storage_0_0_0.bit4.obuf0 Z ) + USE SIGNAL + ROUTED metal3 ( 2289 945 ) ( 2305 * ) NEW metal4 ( 2305 945 ) ( * 1113 0 ) NEW metal2 ( 2289 805 ) ( * 945 ) @@ -840,8 +840,8 @@ NETS 120 ; NEW metal1 ( 2289 385 ) via1_4 NEW metal1 ( 2289 245 ) via1_4 NEW metal1 ( 2289 105 ) via1_4 ; - - Q[5] ( PIN Q[5] ) ( storage_6_0.bit5.obuf0 Z ) ( storage_5_0.bit5.obuf0 Z ) ( storage_4_0.bit5.obuf0 Z ) ( storage_3_0.bit5.obuf0 Z ) ( storage_2_0.bit5.obuf0 Z ) ( storage_1_0.bit5.obuf0 Z ) - ( storage_0_0.bit5.obuf0 Z ) + USE SIGNAL + - Q[5] ( PIN Q[5] ) ( storage_6_0_0.bit5.obuf0 Z ) ( storage_5_0_0.bit5.obuf0 Z ) ( storage_4_0_0.bit5.obuf0 Z ) ( storage_3_0_0.bit5.obuf0 Z ) ( storage_2_0_0.bit5.obuf0 Z ) ( storage_1_0_0.bit5.obuf0 Z ) + ( storage_0_0_0.bit5.obuf0 Z ) + USE SIGNAL + ROUTED metal3 ( 2753 945 ) ( 2764 * ) NEW metal4 ( 2753 945 ) ( * 1113 0 ) NEW metal2 ( 2764 805 ) ( * 875 ) @@ -865,8 +865,8 @@ NETS 120 ; NEW metal1 ( 2764 315 ) via1_4 NEW metal1 ( 2764 105 ) via1_4 NEW metal1 ( 2764 175 ) via1_4 ; - - Q[6] ( PIN Q[6] ) ( storage_6_0.bit6.obuf0 Z ) ( storage_5_0.bit6.obuf0 Z ) ( storage_4_0.bit6.obuf0 Z ) ( storage_3_0.bit6.obuf0 Z ) ( storage_2_0.bit6.obuf0 Z ) ( storage_1_0.bit6.obuf0 Z ) - ( storage_0_0.bit6.obuf0 Z ) + USE SIGNAL + - Q[6] ( PIN Q[6] ) ( storage_6_0_0.bit6.obuf0 Z ) ( storage_5_0_0.bit6.obuf0 Z ) ( storage_4_0_0.bit6.obuf0 Z ) ( storage_3_0_0.bit6.obuf0 Z ) ( storage_2_0_0.bit6.obuf0 Z ) ( storage_1_0_0.bit6.obuf0 Z ) + ( storage_0_0_0.bit6.obuf0 Z ) + USE SIGNAL + ROUTED metal3 ( 3257 945 ) ( 3258 * ) NEW metal4 ( 3257 945 ) ( * 1113 0 ) NEW metal2 ( 3258 805 ) ( * 875 ) @@ -890,7 +890,7 @@ NETS 120 ; NEW metal1 ( 3258 315 ) via1_4 NEW metal1 ( 3258 105 ) via1_4 NEW metal1 ( 3258 175 ) via1_4 ; - - addr[0] ( PIN addr[0] ) ( decoder.inv_0 A ) ( decoder_5.and_layer0 A1 ) ( decoder_3.and_layer0 A1 ) ( decoder_1.and_layer0 A1 ) + USE SIGNAL + - addr_rw[0] ( PIN addr_rw[0] ) ( decoder.inv_0 A ) ( decoder_5.and_layer0 A1 ) ( decoder_3.and_layer0 A1 ) ( decoder_1.and_layer0 A1 ) + USE SIGNAL + ROUTED metal2 ( 3771 217 ) ( * 231 ) NEW metal3 ( 3771 231 ) ( 3948 * 0 ) NEW metal2 ( 3771 441 ) ( * 497 ) @@ -911,7 +911,7 @@ NETS 120 ; NEW metal2 ( 3695 735 ) via2_5 NEW metal1 ( 3923 903 ) via1_4 NEW metal2 ( 3923 735 ) via2_5 ; - - addr[1] ( PIN addr[1] ) ( decoder.inv_1 A ) ( decoder_6.and_layer0 A2 ) ( decoder_3.and_layer0 A2 ) ( decoder_2.and_layer0 A2 ) + USE SIGNAL + - addr_rw[1] ( PIN addr_rw[1] ) ( decoder.inv_1 A ) ( decoder_6.and_layer0 A2 ) ( decoder_3.and_layer0 A2 ) ( decoder_2.and_layer0 A2 ) + USE SIGNAL + ROUTED metal2 ( 3790 497 ) ( * 553 ) NEW metal2 ( 3790 553 ) ( 3809 * ) NEW metal2 ( 3809 553 ) ( * 791 ) @@ -935,46 +935,42 @@ NETS 120 ; NEW metal2 ( 3790 483 ) via2_5 NEW metal1 ( 3790 343 ) via1_4 NEW metal2 ( 3790 343 ) via2_5 ; - - addr[2] ( PIN addr[2] ) ( decoder.inv_2 A ) + USE SIGNAL - + ROUTED metal3 ( 3923 119 ) ( 3948 * 0 ) - NEW metal2 ( 3923 63 ) ( * 119 ) - NEW metal2 ( 3923 119 ) via2_5 - NEW metal1 ( 3923 63 ) via1_4 ; - - clk ( PIN clk ) ( storage_6_0.cg CK ) ( storage_5_0.cg CK ) ( storage_4_0.cg CK ) ( storage_3_0.cg CK ) ( storage_2_0.cg CK ) ( storage_1_0.cg CK ) - ( storage_0_0.cg CK ) + USE SIGNAL - + ROUTED metal2 ( 3581 147 ) ( * 231 ) - NEW metal3 ( 3581 147 ) ( 3948 * 0 ) - NEW metal2 ( 3581 49 ) ( * 147 ) + - addr_rw[2] ( PIN addr_rw[2] ) ( decoder.inv_2 A ) + USE SIGNAL + + ROUTED metal3 ( 3923 63 ) ( 3948 * 0 ) + NEW metal1 ( 3923 63 ) via1_4 + NEW metal2 ( 3923 63 ) via2_5 ; + - clk ( PIN clk ) ( storage_6_0_0.cg CK ) ( storage_5_0_0.cg CK ) ( storage_4_0_0.cg CK ) ( storage_3_0_0.cg CK ) ( storage_2_0_0.cg CK ) ( storage_1_0_0.cg CK ) + ( storage_0_0_0.cg CK ) + USE SIGNAL + + ROUTED metal2 ( 3581 49 ) ( * 91 ) + NEW metal3 ( 3581 91 ) ( 3948 * 0 ) + NEW metal2 ( 3581 91 ) ( * 231 ) NEW metal2 ( 3581 231 ) ( * 329 ) NEW metal2 ( 3581 329 ) ( * 511 ) NEW metal2 ( 3581 511 ) ( * 609 ) NEW metal2 ( 3581 609 ) ( * 791 ) NEW metal2 ( 3581 791 ) ( * 889 ) - NEW metal1 ( 3581 231 ) via1_7 - NEW metal2 ( 3581 147 ) via2_5 NEW metal1 ( 3581 49 ) via1_7 + NEW metal2 ( 3581 91 ) via2_5 + NEW metal1 ( 3581 231 ) via1_7 NEW metal1 ( 3581 329 ) via1_7 NEW metal1 ( 3581 511 ) via1_7 NEW metal1 ( 3581 609 ) via1_7 NEW metal1 ( 3581 791 ) via1_7 NEW metal1 ( 3581 889 ) via1_7 ; - - decoder_0.decoder0 ( storage_0_0.select_inv_0 A ) ( storage_0_0.gcand A1 ) ( decoder_0.buf_port0 Z ) + USE SIGNAL - + ROUTED metal2 ( 3733 49 ) ( * 63 ) - NEW metal3 ( 3733 49 ) ( 3885 * ) - NEW metal2 ( 3657 35 ) ( * 63 ) - NEW metal2 ( 3657 35 ) ( 3733 * ) - NEW metal2 ( 3733 35 ) ( * 49 ) + - decoder_0.decoder0 ( storage_0_0_0.select_inv_0 A ) ( storage_0_0_0.gcand A1 ) ( decoder_0.buf_port0 Z ) + USE SIGNAL + + ROUTED metal2 ( 3733 21 ) ( * 63 ) + NEW metal2 ( 3733 21 ) ( 3885 * ) + NEW metal2 ( 3657 21 ) ( * 63 ) + NEW metal2 ( 3657 21 ) ( 3733 * ) NEW metal1 ( 3733 63 ) via1_4 - NEW metal2 ( 3733 49 ) via2_5 - NEW metal1 ( 3885 49 ) via1_4 - NEW metal2 ( 3885 49 ) via2_5 + NEW metal1 ( 3885 21 ) via1_7 NEW metal1 ( 3657 63 ) via1_4 ; - decoder_0.decoder_out ( decoder_0.buf_port0 A ) ( decoder_0.and_layer0 ZN ) + USE SIGNAL + ROUTED metal2 ( 3828 63 ) ( 3847 * ) NEW metal1 ( 3847 63 ) via1_4 NEW metal1 ( 3828 63 ) via1_4 ; - decoder_0.layer_in0 + USE SIGNAL ; - - decoder_1.decoder0 ( storage_1_0.select_inv_0 A ) ( storage_1_0.gcand A1 ) ( decoder_1.buf_port0 Z ) + USE SIGNAL + - decoder_1.decoder0 ( storage_1_0_0.select_inv_0 A ) ( storage_1_0_0.gcand A1 ) ( decoder_1.buf_port0 Z ) + USE SIGNAL + ROUTED metal2 ( 3733 203 ) ( * 217 ) NEW metal3 ( 3733 203 ) ( 3885 * ) NEW metal2 ( 3657 203 ) ( * 217 ) @@ -990,7 +986,7 @@ NETS 120 ; NEW metal1 ( 3847 217 ) via1_4 NEW metal1 ( 3828 217 ) via1_4 ; - decoder_1.layer_in0 + USE SIGNAL ; - - decoder_2.decoder0 ( storage_2_0.select_inv_0 A ) ( storage_2_0.gcand A1 ) ( decoder_2.buf_port0 Z ) + USE SIGNAL + - decoder_2.decoder0 ( storage_2_0_0.select_inv_0 A ) ( storage_2_0_0.gcand A1 ) ( decoder_2.buf_port0 Z ) + USE SIGNAL + ROUTED metal2 ( 3733 329 ) ( * 343 ) NEW metal3 ( 3733 329 ) ( 3885 * ) NEW metal2 ( 3657 315 ) ( * 343 ) @@ -1007,7 +1003,7 @@ NETS 120 ; NEW metal1 ( 3847 343 ) via1_4 NEW metal1 ( 3828 343 ) via1_4 ; - decoder_2.layer_in0 + USE SIGNAL ; - - decoder_3.decoder0 ( storage_3_0.select_inv_0 A ) ( storage_3_0.gcand A1 ) ( decoder_3.buf_port0 Z ) + USE SIGNAL + - decoder_3.decoder0 ( storage_3_0_0.select_inv_0 A ) ( storage_3_0_0.gcand A1 ) ( decoder_3.buf_port0 Z ) + USE SIGNAL + ROUTED metal2 ( 3733 497 ) ( 3752 * ) NEW metal3 ( 3752 497 ) ( 3885 * ) NEW metal2 ( 3657 483 ) ( * 497 ) @@ -1025,7 +1021,7 @@ NETS 120 ; NEW metal1 ( 3847 497 ) via1_4 NEW metal1 ( 3828 497 ) via1_4 ; - decoder_3.layer_in0 + USE SIGNAL ; - - decoder_4.decoder0 ( storage_4_0.select_inv_0 A ) ( storage_4_0.gcand A1 ) ( decoder_4.buf_port0 Z ) + USE SIGNAL + - decoder_4.decoder0 ( storage_4_0_0.select_inv_0 A ) ( storage_4_0_0.gcand A1 ) ( decoder_4.buf_port0 Z ) + USE SIGNAL + ROUTED metal2 ( 3733 609 ) ( * 623 ) NEW metal3 ( 3733 609 ) ( 3885 * ) NEW metal2 ( 3657 595 ) ( * 623 ) @@ -1042,7 +1038,7 @@ NETS 120 ; NEW metal1 ( 3847 623 ) via1_4 NEW metal1 ( 3828 623 ) via1_4 ; - decoder_4.layer_in0 + USE SIGNAL ; - - decoder_5.decoder0 ( storage_5_0.select_inv_0 A ) ( storage_5_0.gcand A1 ) ( decoder_5.buf_port0 Z ) + USE SIGNAL + - decoder_5.decoder0 ( storage_5_0_0.select_inv_0 A ) ( storage_5_0_0.gcand A1 ) ( decoder_5.buf_port0 Z ) + USE SIGNAL + ROUTED metal2 ( 3733 777 ) ( * 791 ) NEW metal3 ( 3733 791 ) ( 3885 * ) NEW metal2 ( 3657 777 ) ( * 805 ) @@ -1060,7 +1056,7 @@ NETS 120 ; NEW metal1 ( 3847 777 ) via1_4 NEW metal1 ( 3828 777 ) via1_4 ; - decoder_5.layer_in0 + USE SIGNAL ; - - decoder_6.decoder0 ( storage_6_0.select_inv_0 A ) ( storage_6_0.gcand A1 ) ( decoder_6.buf_port0 Z ) + USE SIGNAL + - decoder_6.decoder0 ( storage_6_0_0.select_inv_0 A ) ( storage_6_0_0.gcand A1 ) ( decoder_6.buf_port0 Z ) + USE SIGNAL + ROUTED metal2 ( 3733 903 ) ( * 931 ) NEW metal2 ( 3733 931 ) ( 3885 * ) NEW metal2 ( 3657 903 ) ( * 931 ) @@ -1073,7 +1069,7 @@ NETS 120 ; NEW metal1 ( 3847 903 ) via1_4 NEW metal1 ( 3828 903 ) via1_4 ; - decoder_6.layer_in0 + USE SIGNAL ; - - inv.addr[0] ( decoder.inv_0 ZN ) ( decoder_6.and_layer0 A1 ) ( decoder_4.and_layer0 A1 ) ( decoder_2.and_layer0 A1 ) ( decoder_0.and_layer0 A1 ) + USE SIGNAL + - inv.addr0 ( decoder.inv_0 ZN ) ( decoder_6.and_layer0 A1 ) ( decoder_4.and_layer0 A1 ) ( decoder_2.and_layer0 A1 ) ( decoder_0.and_layer0 A1 ) + USE SIGNAL + ROUTED metal2 ( 3771 889 ) ( * 903 ) NEW metal3 ( 3771 889 ) ( 3942 * ) NEW metal2 ( 3771 623 ) ( * 637 ) @@ -1097,7 +1093,7 @@ NETS 120 ; NEW metal1 ( 3771 63 ) via1_4 NEW metal2 ( 3771 105 ) via2_5 NEW metal2 ( 3809 105 ) via2_5 ; - - inv.addr[1] ( decoder.inv_1 ZN ) ( decoder_5.and_layer0 A2 ) ( decoder_4.and_layer0 A2 ) ( decoder_1.and_layer0 A2 ) ( decoder_0.and_layer0 A2 ) + USE SIGNAL + - inv.addr1 ( decoder.inv_1 ZN ) ( decoder_5.and_layer0 A2 ) ( decoder_4.and_layer0 A2 ) ( decoder_1.and_layer0 A2 ) ( decoder_0.and_layer0 A2 ) + USE SIGNAL + ROUTED metal2 ( 3790 63 ) ( * 217 ) NEW metal2 ( 3942 217 ) ( * 441 ) NEW metal3 ( 3790 217 ) ( 3942 * ) @@ -1114,46 +1110,46 @@ NETS 120 ; NEW metal2 ( 3942 623 ) via2_5 NEW metal1 ( 3942 539 ) via1_7 NEW metal1 ( 3790 770 ) via1_4 ; - - inv.addr[2] ( decoder.inv_2 ZN ) + USE SIGNAL ; - - storage_0_0.bit0.storage ( storage_0_0.bit0.obuf0 A ) ( storage_0_0.bit0.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 294 63 ) ( 427 * ) - NEW metal1 ( 294 63 ) via1_4 - NEW metal1 ( 427 63 ) via1_4 ; - - storage_0_0.bit1.storage ( storage_0_0.bit1.obuf0 A ) ( storage_0_0.bit1.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 769 63 ) ( 902 * ) - NEW metal1 ( 769 63 ) via1_4 - NEW metal2 ( 769 63 ) via2_5 + - inv.addr2 ( decoder.inv_2 ZN ) + USE SIGNAL ; + - storage_0_0_0.bit0.storage ( storage_0_0_0.bit0.obuf0 A ) ( storage_0_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 332 63 ) ( 427 * ) + NEW metal1 ( 427 63 ) via1_4 + NEW metal1 ( 332 63 ) via1_4 ; + - storage_0_0_0.bit1.storage ( storage_0_0_0.bit1.obuf0 A ) ( storage_0_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 807 63 ) ( 902 * ) NEW metal1 ( 902 63 ) via1_4 - NEW metal2 ( 902 63 ) via2_5 ; - - storage_0_0.bit2.storage ( storage_0_0.bit2.obuf0 A ) ( storage_0_0.bit2.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1263 63 ) ( 1396 * ) - NEW metal1 ( 1263 63 ) via1_4 - NEW metal1 ( 1396 63 ) via1_4 ; - - storage_0_0.bit3.storage ( storage_0_0.bit3.obuf0 A ) ( storage_0_0.bit3.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1738 63 ) ( 1871 * ) - NEW metal1 ( 1738 63 ) via1_4 - NEW metal1 ( 1871 63 ) via1_4 ; - - storage_0_0.bit4.storage ( storage_0_0.bit4.obuf0 A ) ( storage_0_0.bit4.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 2232 63 ) ( 2365 * ) - NEW metal1 ( 2232 63 ) via1_4 - NEW metal2 ( 2232 63 ) via2_5 + NEW metal2 ( 902 63 ) via2_5 + NEW metal1 ( 807 63 ) via1_4 + NEW metal2 ( 807 63 ) via2_5 ; + - storage_0_0_0.bit2.storage ( storage_0_0_0.bit2.obuf0 A ) ( storage_0_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1301 63 ) ( 1396 * ) + NEW metal1 ( 1396 63 ) via1_4 + NEW metal1 ( 1301 63 ) via1_4 ; + - storage_0_0_0.bit3.storage ( storage_0_0_0.bit3.obuf0 A ) ( storage_0_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1776 63 ) ( 1871 * ) + NEW metal1 ( 1871 63 ) via1_4 + NEW metal1 ( 1776 63 ) via1_4 ; + - storage_0_0_0.bit4.storage ( storage_0_0_0.bit4.obuf0 A ) ( storage_0_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 2270 63 ) ( 2365 * ) NEW metal1 ( 2365 63 ) via1_4 - NEW metal2 ( 2365 63 ) via2_5 ; - - storage_0_0.bit5.storage ( storage_0_0.bit5.obuf0 A ) ( storage_0_0.bit5.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 2707 63 ) ( 2840 * ) - NEW metal1 ( 2707 63 ) via1_4 - NEW metal1 ( 2840 63 ) via1_4 ; - - storage_0_0.bit6.storage ( storage_0_0.bit6.obuf0 A ) ( storage_0_0.bit6.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 3201 63 ) ( 3334 * ) - NEW metal1 ( 3201 63 ) via1_4 - NEW metal1 ( 3334 63 ) via1_4 ; - - storage_0_0.gclock ( storage_0_0.cg GCK ) ( storage_0_0.bit6.bit CK ) ( storage_0_0.bit5.bit CK ) ( storage_0_0.bit4.bit CK ) ( storage_0_0.bit3.bit CK ) ( storage_0_0.bit2.bit CK ) ( storage_0_0.bit1.bit CK ) - ( storage_0_0.bit0.bit CK ) + USE SIGNAL + NEW metal2 ( 2365 63 ) via2_5 + NEW metal1 ( 2270 63 ) via1_4 + NEW metal2 ( 2270 63 ) via2_5 ; + - storage_0_0_0.bit5.storage ( storage_0_0_0.bit5.obuf0 A ) ( storage_0_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 2745 63 ) ( 2840 * ) + NEW metal1 ( 2840 63 ) via1_4 + NEW metal1 ( 2745 63 ) via1_4 ; + - storage_0_0_0.bit6.storage ( storage_0_0_0.bit6.obuf0 A ) ( storage_0_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 3239 63 ) ( 3334 * ) + NEW metal1 ( 3334 63 ) via1_4 + NEW metal1 ( 3239 63 ) via1_4 ; + - storage_0_0_0.gclock ( storage_0_0_0.cg GCK ) ( storage_0_0_0.bit6.bit CK ) ( storage_0_0_0.bit5.bit CK ) ( storage_0_0_0.bit4.bit CK ) ( storage_0_0_0.bit3.bit CK ) ( storage_0_0_0.bit2.bit CK ) ( storage_0_0_0.bit1.bit CK ) + ( storage_0_0_0.bit0.bit CK ) + USE SIGNAL + ROUTED metal3 ( 180 63 ) ( 655 * ) NEW metal2 ( 1149 49 ) ( * 63 ) - NEW metal3 ( 737 49 ) ( 1149 * ) - NEW metal3 ( 737 49 ) ( * 63 ) - NEW metal3 ( 655 63 ) ( 737 * ) + NEW metal3 ( 765 49 ) ( 1149 * ) + NEW metal3 ( 765 49 ) ( * 63 ) + NEW metal3 ( 655 63 ) ( 765 * ) NEW metal2 ( 3087 49 ) ( * 63 ) NEW metal2 ( 2593 49 ) ( * 63 ) NEW metal3 ( 2593 49 ) ( 3087 * ) @@ -1179,8 +1175,8 @@ NETS 120 ; NEW metal2 ( 2118 49 ) via2_5 NEW metal1 ( 1624 63 ) via1_4 NEW metal2 ( 1624 49 ) via2_5 ; - - storage_0_0.select0_b ( storage_0_0.select_inv_0 ZN ) ( storage_0_0.bit6.obuf0 EN ) ( storage_0_0.bit5.obuf0 EN ) ( storage_0_0.bit4.obuf0 EN ) ( storage_0_0.bit3.obuf0 EN ) ( storage_0_0.bit2.obuf0 EN ) ( storage_0_0.bit1.obuf0 EN ) - ( storage_0_0.bit0.obuf0 EN ) + USE SIGNAL + - storage_0_0_0.select0_b ( storage_0_0_0.select_inv_0 ZN ) ( storage_0_0_0.bit6.obuf0 EN ) ( storage_0_0_0.bit5.obuf0 EN ) ( storage_0_0_0.bit4.obuf0 EN ) ( storage_0_0_0.bit3.obuf0 EN ) ( storage_0_0_0.bit2.obuf0 EN ) ( storage_0_0_0.bit1.obuf0 EN ) + ( storage_0_0_0.bit0.obuf0 EN ) + USE SIGNAL + ROUTED metal3 ( 465 77 ) ( 940 * ) NEW metal3 ( 3733 63 ) ( * 77 ) NEW metal3 ( 3733 63 ) ( 3752 * ) @@ -1206,51 +1202,51 @@ NETS 120 ; NEW metal2 ( 1909 77 ) via2_5 NEW metal1 ( 1434 77 ) via1_4 NEW metal2 ( 1434 77 ) via2_5 ; - - storage_0_0.we0 ( storage_0_0.gcand ZN ) ( storage_0_0.cg E ) + USE SIGNAL + - storage_0_0_0.we0 ( storage_0_0_0.gcand ZN ) ( storage_0_0_0.cg E ) + USE SIGNAL + ROUTED metal3 ( 3505 63 ) ( 3714 * ) NEW metal1 ( 3505 63 ) via1_4 NEW metal2 ( 3505 63 ) via2_5 NEW metal1 ( 3714 63 ) via1_4 NEW metal2 ( 3714 63 ) via2_5 ; - - storage_1_0.bit0.storage ( storage_1_0.bit0.obuf0 A ) ( storage_1_0.bit0.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 294 217 ) ( 427 * ) + - storage_1_0_0.bit0.storage ( storage_1_0_0.bit0.obuf0 A ) ( storage_1_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 332 217 ) ( 427 * ) NEW metal1 ( 427 217 ) via1_4 - NEW metal1 ( 294 217 ) via1_4 ; - - storage_1_0.bit1.storage ( storage_1_0.bit1.obuf0 A ) ( storage_1_0.bit1.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 769 217 ) ( 902 * ) + NEW metal1 ( 332 217 ) via1_4 ; + - storage_1_0_0.bit1.storage ( storage_1_0_0.bit1.obuf0 A ) ( storage_1_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 807 217 ) ( 902 * ) NEW metal1 ( 902 217 ) via1_4 NEW metal2 ( 902 217 ) via2_5 - NEW metal1 ( 769 217 ) via1_4 - NEW metal2 ( 769 217 ) via2_5 ; - - storage_1_0.bit2.storage ( storage_1_0.bit2.obuf0 A ) ( storage_1_0.bit2.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1263 217 ) ( 1396 * ) + NEW metal1 ( 807 217 ) via1_4 + NEW metal2 ( 807 217 ) via2_5 ; + - storage_1_0_0.bit2.storage ( storage_1_0_0.bit2.obuf0 A ) ( storage_1_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1301 217 ) ( 1396 * ) NEW metal1 ( 1396 217 ) via1_4 - NEW metal1 ( 1263 217 ) via1_4 ; - - storage_1_0.bit3.storage ( storage_1_0.bit3.obuf0 A ) ( storage_1_0.bit3.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1738 217 ) ( 1871 * ) + NEW metal1 ( 1301 217 ) via1_4 ; + - storage_1_0_0.bit3.storage ( storage_1_0_0.bit3.obuf0 A ) ( storage_1_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1776 217 ) ( 1871 * ) NEW metal1 ( 1871 217 ) via1_4 - NEW metal1 ( 1738 217 ) via1_4 ; - - storage_1_0.bit4.storage ( storage_1_0.bit4.obuf0 A ) ( storage_1_0.bit4.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 2232 217 ) ( 2365 * ) + NEW metal1 ( 1776 217 ) via1_4 ; + - storage_1_0_0.bit4.storage ( storage_1_0_0.bit4.obuf0 A ) ( storage_1_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 2270 217 ) ( 2365 * ) NEW metal1 ( 2365 217 ) via1_4 NEW metal2 ( 2365 217 ) via2_5 - NEW metal1 ( 2232 217 ) via1_4 - NEW metal2 ( 2232 217 ) via2_5 ; - - storage_1_0.bit5.storage ( storage_1_0.bit5.obuf0 A ) ( storage_1_0.bit5.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 2707 217 ) ( 2840 * ) + NEW metal1 ( 2270 217 ) via1_4 + NEW metal2 ( 2270 217 ) via2_5 ; + - storage_1_0_0.bit5.storage ( storage_1_0_0.bit5.obuf0 A ) ( storage_1_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 2745 217 ) ( 2840 * ) NEW metal1 ( 2840 217 ) via1_4 - NEW metal1 ( 2707 217 ) via1_4 ; - - storage_1_0.bit6.storage ( storage_1_0.bit6.obuf0 A ) ( storage_1_0.bit6.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 3201 217 ) ( 3334 * ) + NEW metal1 ( 2745 217 ) via1_4 ; + - storage_1_0_0.bit6.storage ( storage_1_0_0.bit6.obuf0 A ) ( storage_1_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 3239 217 ) ( 3334 * ) NEW metal1 ( 3334 217 ) via1_4 - NEW metal1 ( 3201 217 ) via1_4 ; - - storage_1_0.gclock ( storage_1_0.cg GCK ) ( storage_1_0.bit6.bit CK ) ( storage_1_0.bit5.bit CK ) ( storage_1_0.bit4.bit CK ) ( storage_1_0.bit3.bit CK ) ( storage_1_0.bit2.bit CK ) ( storage_1_0.bit1.bit CK ) - ( storage_1_0.bit0.bit CK ) + USE SIGNAL + NEW metal1 ( 3239 217 ) via1_4 ; + - storage_1_0_0.gclock ( storage_1_0_0.cg GCK ) ( storage_1_0_0.bit6.bit CK ) ( storage_1_0_0.bit5.bit CK ) ( storage_1_0_0.bit4.bit CK ) ( storage_1_0_0.bit3.bit CK ) ( storage_1_0_0.bit2.bit CK ) ( storage_1_0_0.bit1.bit CK ) + ( storage_1_0_0.bit0.bit CK ) + USE SIGNAL + ROUTED metal3 ( 180 217 ) ( 655 * ) NEW metal2 ( 1149 217 ) ( * 231 ) - NEW metal3 ( 737 231 ) ( 1149 * ) - NEW metal3 ( 737 217 ) ( * 231 ) - NEW metal3 ( 655 217 ) ( 737 * ) + NEW metal3 ( 765 231 ) ( 1149 * ) + NEW metal3 ( 765 217 ) ( * 231 ) + NEW metal3 ( 655 217 ) ( 765 * ) NEW metal2 ( 3087 217 ) ( * 231 ) NEW metal2 ( 2593 217 ) ( * 231 ) NEW metal3 ( 2593 231 ) ( 3087 * ) @@ -1276,8 +1272,8 @@ NETS 120 ; NEW metal2 ( 2118 231 ) via2_5 NEW metal1 ( 1624 217 ) via1_4 NEW metal2 ( 1624 231 ) via2_5 ; - - storage_1_0.select0_b ( storage_1_0.select_inv_0 ZN ) ( storage_1_0.bit6.obuf0 EN ) ( storage_1_0.bit5.obuf0 EN ) ( storage_1_0.bit4.obuf0 EN ) ( storage_1_0.bit3.obuf0 EN ) ( storage_1_0.bit2.obuf0 EN ) ( storage_1_0.bit1.obuf0 EN ) - ( storage_1_0.bit0.obuf0 EN ) + USE SIGNAL + - storage_1_0_0.select0_b ( storage_1_0_0.select_inv_0 ZN ) ( storage_1_0_0.bit6.obuf0 EN ) ( storage_1_0_0.bit5.obuf0 EN ) ( storage_1_0_0.bit4.obuf0 EN ) ( storage_1_0_0.bit3.obuf0 EN ) ( storage_1_0_0.bit2.obuf0 EN ) ( storage_1_0_0.bit1.obuf0 EN ) + ( storage_1_0_0.bit0.obuf0 EN ) + USE SIGNAL + ROUTED metal3 ( 465 189 ) ( 940 * ) NEW metal3 ( 2878 189 ) ( 3372 * ) NEW metal3 ( 2403 189 ) ( 2878 * ) @@ -1301,51 +1297,51 @@ NETS 120 ; NEW metal2 ( 1909 189 ) via2_5 NEW metal1 ( 1434 189 ) via1_4 NEW metal2 ( 1434 189 ) via2_5 ; - - storage_1_0.we0 ( storage_1_0.gcand ZN ) ( storage_1_0.cg E ) + USE SIGNAL + - storage_1_0_0.we0 ( storage_1_0_0.gcand ZN ) ( storage_1_0_0.cg E ) + USE SIGNAL + ROUTED metal3 ( 3505 217 ) ( 3714 * ) NEW metal1 ( 3505 217 ) via1_4 NEW metal2 ( 3505 217 ) via2_5 NEW metal1 ( 3714 217 ) via1_4 NEW metal2 ( 3714 217 ) via2_5 ; - - storage_2_0.bit0.storage ( storage_2_0.bit0.obuf0 A ) ( storage_2_0.bit0.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 294 343 ) ( 427 * ) - NEW metal1 ( 294 343 ) via1_4 - NEW metal1 ( 427 343 ) via1_4 ; - - storage_2_0.bit1.storage ( storage_2_0.bit1.obuf0 A ) ( storage_2_0.bit1.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 769 343 ) ( 902 * ) - NEW metal1 ( 769 343 ) via1_4 - NEW metal2 ( 769 343 ) via2_5 + - storage_2_0_0.bit0.storage ( storage_2_0_0.bit0.obuf0 A ) ( storage_2_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 332 343 ) ( 427 * ) + NEW metal1 ( 427 343 ) via1_4 + NEW metal1 ( 332 343 ) via1_4 ; + - storage_2_0_0.bit1.storage ( storage_2_0_0.bit1.obuf0 A ) ( storage_2_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 807 343 ) ( 902 * ) NEW metal1 ( 902 343 ) via1_4 - NEW metal2 ( 902 343 ) via2_5 ; - - storage_2_0.bit2.storage ( storage_2_0.bit2.obuf0 A ) ( storage_2_0.bit2.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1263 343 ) ( 1396 * ) - NEW metal1 ( 1263 343 ) via1_4 - NEW metal1 ( 1396 343 ) via1_4 ; - - storage_2_0.bit3.storage ( storage_2_0.bit3.obuf0 A ) ( storage_2_0.bit3.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1738 343 ) ( 1871 * ) - NEW metal1 ( 1738 343 ) via1_4 - NEW metal1 ( 1871 343 ) via1_4 ; - - storage_2_0.bit4.storage ( storage_2_0.bit4.obuf0 A ) ( storage_2_0.bit4.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 2232 343 ) ( 2365 * ) - NEW metal1 ( 2232 343 ) via1_4 - NEW metal2 ( 2232 343 ) via2_5 + NEW metal2 ( 902 343 ) via2_5 + NEW metal1 ( 807 343 ) via1_4 + NEW metal2 ( 807 343 ) via2_5 ; + - storage_2_0_0.bit2.storage ( storage_2_0_0.bit2.obuf0 A ) ( storage_2_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1301 343 ) ( 1396 * ) + NEW metal1 ( 1396 343 ) via1_4 + NEW metal1 ( 1301 343 ) via1_4 ; + - storage_2_0_0.bit3.storage ( storage_2_0_0.bit3.obuf0 A ) ( storage_2_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1776 343 ) ( 1871 * ) + NEW metal1 ( 1871 343 ) via1_4 + NEW metal1 ( 1776 343 ) via1_4 ; + - storage_2_0_0.bit4.storage ( storage_2_0_0.bit4.obuf0 A ) ( storage_2_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 2270 343 ) ( 2365 * ) NEW metal1 ( 2365 343 ) via1_4 - NEW metal2 ( 2365 343 ) via2_5 ; - - storage_2_0.bit5.storage ( storage_2_0.bit5.obuf0 A ) ( storage_2_0.bit5.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 2707 343 ) ( 2840 * ) - NEW metal1 ( 2707 343 ) via1_4 - NEW metal1 ( 2840 343 ) via1_4 ; - - storage_2_0.bit6.storage ( storage_2_0.bit6.obuf0 A ) ( storage_2_0.bit6.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 3201 343 ) ( 3334 * ) - NEW metal1 ( 3201 343 ) via1_4 - NEW metal1 ( 3334 343 ) via1_4 ; - - storage_2_0.gclock ( storage_2_0.cg GCK ) ( storage_2_0.bit6.bit CK ) ( storage_2_0.bit5.bit CK ) ( storage_2_0.bit4.bit CK ) ( storage_2_0.bit3.bit CK ) ( storage_2_0.bit2.bit CK ) ( storage_2_0.bit1.bit CK ) - ( storage_2_0.bit0.bit CK ) + USE SIGNAL + NEW metal2 ( 2365 343 ) via2_5 + NEW metal1 ( 2270 343 ) via1_4 + NEW metal2 ( 2270 343 ) via2_5 ; + - storage_2_0_0.bit5.storage ( storage_2_0_0.bit5.obuf0 A ) ( storage_2_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 2745 343 ) ( 2840 * ) + NEW metal1 ( 2840 343 ) via1_4 + NEW metal1 ( 2745 343 ) via1_4 ; + - storage_2_0_0.bit6.storage ( storage_2_0_0.bit6.obuf0 A ) ( storage_2_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 3239 343 ) ( 3334 * ) + NEW metal1 ( 3334 343 ) via1_4 + NEW metal1 ( 3239 343 ) via1_4 ; + - storage_2_0_0.gclock ( storage_2_0_0.cg GCK ) ( storage_2_0_0.bit6.bit CK ) ( storage_2_0_0.bit5.bit CK ) ( storage_2_0_0.bit4.bit CK ) ( storage_2_0_0.bit3.bit CK ) ( storage_2_0_0.bit2.bit CK ) ( storage_2_0_0.bit1.bit CK ) + ( storage_2_0_0.bit0.bit CK ) + USE SIGNAL + ROUTED metal3 ( 180 343 ) ( 655 * ) NEW metal2 ( 1149 329 ) ( * 343 ) - NEW metal3 ( 737 329 ) ( 1149 * ) - NEW metal3 ( 737 329 ) ( * 343 ) - NEW metal3 ( 655 343 ) ( 737 * ) + NEW metal3 ( 765 329 ) ( 1149 * ) + NEW metal3 ( 765 329 ) ( * 343 ) + NEW metal3 ( 655 343 ) ( 765 * ) NEW metal2 ( 3087 329 ) ( * 343 ) NEW metal2 ( 2593 329 ) ( * 343 ) NEW metal3 ( 2593 329 ) ( 3087 * ) @@ -1371,8 +1367,8 @@ NETS 120 ; NEW metal2 ( 2118 329 ) via2_5 NEW metal1 ( 1624 343 ) via1_4 NEW metal2 ( 1624 329 ) via2_5 ; - - storage_2_0.select0_b ( storage_2_0.select_inv_0 ZN ) ( storage_2_0.bit6.obuf0 EN ) ( storage_2_0.bit5.obuf0 EN ) ( storage_2_0.bit4.obuf0 EN ) ( storage_2_0.bit3.obuf0 EN ) ( storage_2_0.bit2.obuf0 EN ) ( storage_2_0.bit1.obuf0 EN ) - ( storage_2_0.bit0.obuf0 EN ) + USE SIGNAL + - storage_2_0_0.select0_b ( storage_2_0_0.select_inv_0 ZN ) ( storage_2_0_0.bit6.obuf0 EN ) ( storage_2_0_0.bit5.obuf0 EN ) ( storage_2_0_0.bit4.obuf0 EN ) ( storage_2_0_0.bit3.obuf0 EN ) ( storage_2_0_0.bit2.obuf0 EN ) ( storage_2_0_0.bit1.obuf0 EN ) + ( storage_2_0_0.bit0.obuf0 EN ) + USE SIGNAL + ROUTED metal3 ( 465 357 ) ( 940 * ) NEW metal3 ( 3733 343 ) ( * 357 ) NEW metal3 ( 3733 343 ) ( 3752 * ) @@ -1398,51 +1394,51 @@ NETS 120 ; NEW metal2 ( 1909 357 ) via2_5 NEW metal1 ( 1434 357 ) via1_4 NEW metal2 ( 1434 357 ) via2_5 ; - - storage_2_0.we0 ( storage_2_0.gcand ZN ) ( storage_2_0.cg E ) + USE SIGNAL + - storage_2_0_0.we0 ( storage_2_0_0.gcand ZN ) ( storage_2_0_0.cg E ) + USE SIGNAL + ROUTED metal3 ( 3505 343 ) ( 3714 * ) NEW metal1 ( 3505 343 ) via1_4 NEW metal2 ( 3505 343 ) via2_5 NEW metal1 ( 3714 343 ) via1_4 NEW metal2 ( 3714 343 ) via2_5 ; - - storage_3_0.bit0.storage ( storage_3_0.bit0.obuf0 A ) ( storage_3_0.bit0.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 294 497 ) ( 427 * ) + - storage_3_0_0.bit0.storage ( storage_3_0_0.bit0.obuf0 A ) ( storage_3_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 332 497 ) ( 427 * ) NEW metal1 ( 427 497 ) via1_4 - NEW metal1 ( 294 497 ) via1_4 ; - - storage_3_0.bit1.storage ( storage_3_0.bit1.obuf0 A ) ( storage_3_0.bit1.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 769 497 ) ( 902 * ) + NEW metal1 ( 332 497 ) via1_4 ; + - storage_3_0_0.bit1.storage ( storage_3_0_0.bit1.obuf0 A ) ( storage_3_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 807 497 ) ( 902 * ) NEW metal1 ( 902 497 ) via1_4 NEW metal2 ( 902 497 ) via2_5 - NEW metal1 ( 769 497 ) via1_4 - NEW metal2 ( 769 497 ) via2_5 ; - - storage_3_0.bit2.storage ( storage_3_0.bit2.obuf0 A ) ( storage_3_0.bit2.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1263 497 ) ( 1396 * ) + NEW metal1 ( 807 497 ) via1_4 + NEW metal2 ( 807 497 ) via2_5 ; + - storage_3_0_0.bit2.storage ( storage_3_0_0.bit2.obuf0 A ) ( storage_3_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1301 497 ) ( 1396 * ) NEW metal1 ( 1396 497 ) via1_4 - NEW metal1 ( 1263 497 ) via1_4 ; - - storage_3_0.bit3.storage ( storage_3_0.bit3.obuf0 A ) ( storage_3_0.bit3.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1738 497 ) ( 1871 * ) + NEW metal1 ( 1301 497 ) via1_4 ; + - storage_3_0_0.bit3.storage ( storage_3_0_0.bit3.obuf0 A ) ( storage_3_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1776 497 ) ( 1871 * ) NEW metal1 ( 1871 497 ) via1_4 - NEW metal1 ( 1738 497 ) via1_4 ; - - storage_3_0.bit4.storage ( storage_3_0.bit4.obuf0 A ) ( storage_3_0.bit4.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 2232 497 ) ( 2365 * ) + NEW metal1 ( 1776 497 ) via1_4 ; + - storage_3_0_0.bit4.storage ( storage_3_0_0.bit4.obuf0 A ) ( storage_3_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 2270 497 ) ( 2365 * ) NEW metal1 ( 2365 497 ) via1_4 NEW metal2 ( 2365 497 ) via2_5 - NEW metal1 ( 2232 497 ) via1_4 - NEW metal2 ( 2232 497 ) via2_5 ; - - storage_3_0.bit5.storage ( storage_3_0.bit5.obuf0 A ) ( storage_3_0.bit5.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 2707 497 ) ( 2840 * ) + NEW metal1 ( 2270 497 ) via1_4 + NEW metal2 ( 2270 497 ) via2_5 ; + - storage_3_0_0.bit5.storage ( storage_3_0_0.bit5.obuf0 A ) ( storage_3_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 2745 497 ) ( 2840 * ) NEW metal1 ( 2840 497 ) via1_4 - NEW metal1 ( 2707 497 ) via1_4 ; - - storage_3_0.bit6.storage ( storage_3_0.bit6.obuf0 A ) ( storage_3_0.bit6.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 3201 497 ) ( 3334 * ) + NEW metal1 ( 2745 497 ) via1_4 ; + - storage_3_0_0.bit6.storage ( storage_3_0_0.bit6.obuf0 A ) ( storage_3_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 3239 497 ) ( 3334 * ) NEW metal1 ( 3334 497 ) via1_4 - NEW metal1 ( 3201 497 ) via1_4 ; - - storage_3_0.gclock ( storage_3_0.cg GCK ) ( storage_3_0.bit6.bit CK ) ( storage_3_0.bit5.bit CK ) ( storage_3_0.bit4.bit CK ) ( storage_3_0.bit3.bit CK ) ( storage_3_0.bit2.bit CK ) ( storage_3_0.bit1.bit CK ) - ( storage_3_0.bit0.bit CK ) + USE SIGNAL + NEW metal1 ( 3239 497 ) via1_4 ; + - storage_3_0_0.gclock ( storage_3_0_0.cg GCK ) ( storage_3_0_0.bit6.bit CK ) ( storage_3_0_0.bit5.bit CK ) ( storage_3_0_0.bit4.bit CK ) ( storage_3_0_0.bit3.bit CK ) ( storage_3_0_0.bit2.bit CK ) ( storage_3_0_0.bit1.bit CK ) + ( storage_3_0_0.bit0.bit CK ) + USE SIGNAL + ROUTED metal3 ( 180 497 ) ( 655 * ) NEW metal2 ( 1149 497 ) ( * 511 ) - NEW metal3 ( 737 511 ) ( 1149 * ) - NEW metal3 ( 737 497 ) ( * 511 ) - NEW metal3 ( 655 497 ) ( 737 * ) + NEW metal3 ( 765 511 ) ( 1149 * ) + NEW metal3 ( 765 497 ) ( * 511 ) + NEW metal3 ( 655 497 ) ( 765 * ) NEW metal2 ( 3087 497 ) ( * 511 ) NEW metal2 ( 2593 497 ) ( * 511 ) NEW metal3 ( 2593 511 ) ( 3087 * ) @@ -1468,8 +1464,8 @@ NETS 120 ; NEW metal2 ( 2118 511 ) via2_5 NEW metal1 ( 1624 497 ) via1_4 NEW metal2 ( 1624 511 ) via2_5 ; - - storage_3_0.select0_b ( storage_3_0.select_inv_0 ZN ) ( storage_3_0.bit6.obuf0 EN ) ( storage_3_0.bit5.obuf0 EN ) ( storage_3_0.bit4.obuf0 EN ) ( storage_3_0.bit3.obuf0 EN ) ( storage_3_0.bit2.obuf0 EN ) ( storage_3_0.bit1.obuf0 EN ) - ( storage_3_0.bit0.obuf0 EN ) + USE SIGNAL + - storage_3_0_0.select0_b ( storage_3_0_0.select_inv_0 ZN ) ( storage_3_0_0.bit6.obuf0 EN ) ( storage_3_0_0.bit5.obuf0 EN ) ( storage_3_0_0.bit4.obuf0 EN ) ( storage_3_0_0.bit3.obuf0 EN ) ( storage_3_0_0.bit2.obuf0 EN ) ( storage_3_0_0.bit1.obuf0 EN ) + ( storage_3_0_0.bit0.obuf0 EN ) + USE SIGNAL + ROUTED metal3 ( 465 469 ) ( 940 * ) NEW metal3 ( 2878 469 ) ( 3372 * ) NEW metal3 ( 2403 469 ) ( 2878 * ) @@ -1493,51 +1489,51 @@ NETS 120 ; NEW metal2 ( 1909 469 ) via2_5 NEW metal1 ( 1434 469 ) via1_4 NEW metal2 ( 1434 469 ) via2_5 ; - - storage_3_0.we0 ( storage_3_0.gcand ZN ) ( storage_3_0.cg E ) + USE SIGNAL + - storage_3_0_0.we0 ( storage_3_0_0.gcand ZN ) ( storage_3_0_0.cg E ) + USE SIGNAL + ROUTED metal3 ( 3505 497 ) ( 3714 * ) NEW metal1 ( 3505 497 ) via1_4 NEW metal2 ( 3505 497 ) via2_5 NEW metal1 ( 3714 497 ) via1_4 NEW metal2 ( 3714 497 ) via2_5 ; - - storage_4_0.bit0.storage ( storage_4_0.bit0.obuf0 A ) ( storage_4_0.bit0.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 294 623 ) ( 427 * ) - NEW metal1 ( 294 623 ) via1_4 - NEW metal1 ( 427 623 ) via1_4 ; - - storage_4_0.bit1.storage ( storage_4_0.bit1.obuf0 A ) ( storage_4_0.bit1.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 769 623 ) ( 902 * ) - NEW metal1 ( 769 623 ) via1_4 - NEW metal2 ( 769 623 ) via2_5 + - storage_4_0_0.bit0.storage ( storage_4_0_0.bit0.obuf0 A ) ( storage_4_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 332 623 ) ( 427 * ) + NEW metal1 ( 427 623 ) via1_4 + NEW metal1 ( 332 623 ) via1_4 ; + - storage_4_0_0.bit1.storage ( storage_4_0_0.bit1.obuf0 A ) ( storage_4_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 807 623 ) ( 902 * ) NEW metal1 ( 902 623 ) via1_4 - NEW metal2 ( 902 623 ) via2_5 ; - - storage_4_0.bit2.storage ( storage_4_0.bit2.obuf0 A ) ( storage_4_0.bit2.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1263 623 ) ( 1396 * ) - NEW metal1 ( 1263 623 ) via1_4 - NEW metal1 ( 1396 623 ) via1_4 ; - - storage_4_0.bit3.storage ( storage_4_0.bit3.obuf0 A ) ( storage_4_0.bit3.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1738 623 ) ( 1871 * ) - NEW metal1 ( 1738 623 ) via1_4 - NEW metal1 ( 1871 623 ) via1_4 ; - - storage_4_0.bit4.storage ( storage_4_0.bit4.obuf0 A ) ( storage_4_0.bit4.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 2232 623 ) ( 2365 * ) - NEW metal1 ( 2232 623 ) via1_4 - NEW metal2 ( 2232 623 ) via2_5 + NEW metal2 ( 902 623 ) via2_5 + NEW metal1 ( 807 623 ) via1_4 + NEW metal2 ( 807 623 ) via2_5 ; + - storage_4_0_0.bit2.storage ( storage_4_0_0.bit2.obuf0 A ) ( storage_4_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1301 623 ) ( 1396 * ) + NEW metal1 ( 1396 623 ) via1_4 + NEW metal1 ( 1301 623 ) via1_4 ; + - storage_4_0_0.bit3.storage ( storage_4_0_0.bit3.obuf0 A ) ( storage_4_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1776 623 ) ( 1871 * ) + NEW metal1 ( 1871 623 ) via1_4 + NEW metal1 ( 1776 623 ) via1_4 ; + - storage_4_0_0.bit4.storage ( storage_4_0_0.bit4.obuf0 A ) ( storage_4_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 2270 623 ) ( 2365 * ) NEW metal1 ( 2365 623 ) via1_4 - NEW metal2 ( 2365 623 ) via2_5 ; - - storage_4_0.bit5.storage ( storage_4_0.bit5.obuf0 A ) ( storage_4_0.bit5.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 2707 623 ) ( 2840 * ) - NEW metal1 ( 2707 623 ) via1_4 - NEW metal1 ( 2840 623 ) via1_4 ; - - storage_4_0.bit6.storage ( storage_4_0.bit6.obuf0 A ) ( storage_4_0.bit6.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 3201 623 ) ( 3334 * ) - NEW metal1 ( 3201 623 ) via1_4 - NEW metal1 ( 3334 623 ) via1_4 ; - - storage_4_0.gclock ( storage_4_0.cg GCK ) ( storage_4_0.bit6.bit CK ) ( storage_4_0.bit5.bit CK ) ( storage_4_0.bit4.bit CK ) ( storage_4_0.bit3.bit CK ) ( storage_4_0.bit2.bit CK ) ( storage_4_0.bit1.bit CK ) - ( storage_4_0.bit0.bit CK ) + USE SIGNAL + NEW metal2 ( 2365 623 ) via2_5 + NEW metal1 ( 2270 623 ) via1_4 + NEW metal2 ( 2270 623 ) via2_5 ; + - storage_4_0_0.bit5.storage ( storage_4_0_0.bit5.obuf0 A ) ( storage_4_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 2745 623 ) ( 2840 * ) + NEW metal1 ( 2840 623 ) via1_4 + NEW metal1 ( 2745 623 ) via1_4 ; + - storage_4_0_0.bit6.storage ( storage_4_0_0.bit6.obuf0 A ) ( storage_4_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 3239 623 ) ( 3334 * ) + NEW metal1 ( 3334 623 ) via1_4 + NEW metal1 ( 3239 623 ) via1_4 ; + - storage_4_0_0.gclock ( storage_4_0_0.cg GCK ) ( storage_4_0_0.bit6.bit CK ) ( storage_4_0_0.bit5.bit CK ) ( storage_4_0_0.bit4.bit CK ) ( storage_4_0_0.bit3.bit CK ) ( storage_4_0_0.bit2.bit CK ) ( storage_4_0_0.bit1.bit CK ) + ( storage_4_0_0.bit0.bit CK ) + USE SIGNAL + ROUTED metal3 ( 180 623 ) ( 655 * ) NEW metal2 ( 1149 609 ) ( * 623 ) - NEW metal3 ( 737 609 ) ( 1149 * ) - NEW metal3 ( 737 609 ) ( * 623 ) - NEW metal3 ( 655 623 ) ( 737 * ) + NEW metal3 ( 765 609 ) ( 1149 * ) + NEW metal3 ( 765 609 ) ( * 623 ) + NEW metal3 ( 655 623 ) ( 765 * ) NEW metal2 ( 3087 609 ) ( * 623 ) NEW metal2 ( 2593 609 ) ( * 623 ) NEW metal3 ( 2593 609 ) ( 3087 * ) @@ -1563,8 +1559,8 @@ NETS 120 ; NEW metal2 ( 2118 609 ) via2_5 NEW metal1 ( 1624 623 ) via1_4 NEW metal2 ( 1624 609 ) via2_5 ; - - storage_4_0.select0_b ( storage_4_0.select_inv_0 ZN ) ( storage_4_0.bit6.obuf0 EN ) ( storage_4_0.bit5.obuf0 EN ) ( storage_4_0.bit4.obuf0 EN ) ( storage_4_0.bit3.obuf0 EN ) ( storage_4_0.bit2.obuf0 EN ) ( storage_4_0.bit1.obuf0 EN ) - ( storage_4_0.bit0.obuf0 EN ) + USE SIGNAL + - storage_4_0_0.select0_b ( storage_4_0_0.select_inv_0 ZN ) ( storage_4_0_0.bit6.obuf0 EN ) ( storage_4_0_0.bit5.obuf0 EN ) ( storage_4_0_0.bit4.obuf0 EN ) ( storage_4_0_0.bit3.obuf0 EN ) ( storage_4_0_0.bit2.obuf0 EN ) ( storage_4_0_0.bit1.obuf0 EN ) + ( storage_4_0_0.bit0.obuf0 EN ) + USE SIGNAL + ROUTED metal3 ( 465 637 ) ( 940 * ) NEW metal3 ( 3733 623 ) ( * 637 ) NEW metal3 ( 3733 623 ) ( 3752 * ) @@ -1590,51 +1586,51 @@ NETS 120 ; NEW metal2 ( 1909 637 ) via2_5 NEW metal1 ( 1434 637 ) via1_4 NEW metal2 ( 1434 637 ) via2_5 ; - - storage_4_0.we0 ( storage_4_0.gcand ZN ) ( storage_4_0.cg E ) + USE SIGNAL + - storage_4_0_0.we0 ( storage_4_0_0.gcand ZN ) ( storage_4_0_0.cg E ) + USE SIGNAL + ROUTED metal3 ( 3505 623 ) ( 3714 * ) NEW metal1 ( 3505 623 ) via1_4 NEW metal2 ( 3505 623 ) via2_5 NEW metal1 ( 3714 623 ) via1_4 NEW metal2 ( 3714 623 ) via2_5 ; - - storage_5_0.bit0.storage ( storage_5_0.bit0.obuf0 A ) ( storage_5_0.bit0.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 294 777 ) ( 427 * ) + - storage_5_0_0.bit0.storage ( storage_5_0_0.bit0.obuf0 A ) ( storage_5_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 332 777 ) ( 427 * ) NEW metal1 ( 427 777 ) via1_4 - NEW metal1 ( 294 777 ) via1_4 ; - - storage_5_0.bit1.storage ( storage_5_0.bit1.obuf0 A ) ( storage_5_0.bit1.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 769 777 ) ( 902 * ) + NEW metal1 ( 332 777 ) via1_4 ; + - storage_5_0_0.bit1.storage ( storage_5_0_0.bit1.obuf0 A ) ( storage_5_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 807 777 ) ( 902 * ) NEW metal1 ( 902 777 ) via1_4 NEW metal2 ( 902 777 ) via2_5 - NEW metal1 ( 769 777 ) via1_4 - NEW metal2 ( 769 777 ) via2_5 ; - - storage_5_0.bit2.storage ( storage_5_0.bit2.obuf0 A ) ( storage_5_0.bit2.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1263 777 ) ( 1396 * ) + NEW metal1 ( 807 777 ) via1_4 + NEW metal2 ( 807 777 ) via2_5 ; + - storage_5_0_0.bit2.storage ( storage_5_0_0.bit2.obuf0 A ) ( storage_5_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1301 777 ) ( 1396 * ) NEW metal1 ( 1396 777 ) via1_4 - NEW metal1 ( 1263 777 ) via1_4 ; - - storage_5_0.bit3.storage ( storage_5_0.bit3.obuf0 A ) ( storage_5_0.bit3.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1738 777 ) ( 1871 * ) + NEW metal1 ( 1301 777 ) via1_4 ; + - storage_5_0_0.bit3.storage ( storage_5_0_0.bit3.obuf0 A ) ( storage_5_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1776 777 ) ( 1871 * ) NEW metal1 ( 1871 777 ) via1_4 - NEW metal1 ( 1738 777 ) via1_4 ; - - storage_5_0.bit4.storage ( storage_5_0.bit4.obuf0 A ) ( storage_5_0.bit4.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 2232 777 ) ( 2365 * ) + NEW metal1 ( 1776 777 ) via1_4 ; + - storage_5_0_0.bit4.storage ( storage_5_0_0.bit4.obuf0 A ) ( storage_5_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 2270 777 ) ( 2365 * ) NEW metal1 ( 2365 777 ) via1_4 NEW metal2 ( 2365 777 ) via2_5 - NEW metal1 ( 2232 777 ) via1_4 - NEW metal2 ( 2232 777 ) via2_5 ; - - storage_5_0.bit5.storage ( storage_5_0.bit5.obuf0 A ) ( storage_5_0.bit5.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 2707 777 ) ( 2840 * ) + NEW metal1 ( 2270 777 ) via1_4 + NEW metal2 ( 2270 777 ) via2_5 ; + - storage_5_0_0.bit5.storage ( storage_5_0_0.bit5.obuf0 A ) ( storage_5_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 2745 777 ) ( 2840 * ) NEW metal1 ( 2840 777 ) via1_4 - NEW metal1 ( 2707 777 ) via1_4 ; - - storage_5_0.bit6.storage ( storage_5_0.bit6.obuf0 A ) ( storage_5_0.bit6.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 3201 777 ) ( 3334 * ) + NEW metal1 ( 2745 777 ) via1_4 ; + - storage_5_0_0.bit6.storage ( storage_5_0_0.bit6.obuf0 A ) ( storage_5_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 3239 777 ) ( 3334 * ) NEW metal1 ( 3334 777 ) via1_4 - NEW metal1 ( 3201 777 ) via1_4 ; - - storage_5_0.gclock ( storage_5_0.cg GCK ) ( storage_5_0.bit6.bit CK ) ( storage_5_0.bit5.bit CK ) ( storage_5_0.bit4.bit CK ) ( storage_5_0.bit3.bit CK ) ( storage_5_0.bit2.bit CK ) ( storage_5_0.bit1.bit CK ) - ( storage_5_0.bit0.bit CK ) + USE SIGNAL + NEW metal1 ( 3239 777 ) via1_4 ; + - storage_5_0_0.gclock ( storage_5_0_0.cg GCK ) ( storage_5_0_0.bit6.bit CK ) ( storage_5_0_0.bit5.bit CK ) ( storage_5_0_0.bit4.bit CK ) ( storage_5_0_0.bit3.bit CK ) ( storage_5_0_0.bit2.bit CK ) ( storage_5_0_0.bit1.bit CK ) + ( storage_5_0_0.bit0.bit CK ) + USE SIGNAL + ROUTED metal3 ( 180 777 ) ( 655 * ) NEW metal2 ( 1149 777 ) ( * 791 ) - NEW metal3 ( 737 791 ) ( 1149 * ) - NEW metal3 ( 737 777 ) ( * 791 ) - NEW metal3 ( 655 777 ) ( 737 * ) + NEW metal3 ( 765 791 ) ( 1149 * ) + NEW metal3 ( 765 777 ) ( * 791 ) + NEW metal3 ( 655 777 ) ( 765 * ) NEW metal2 ( 3087 777 ) ( * 791 ) NEW metal2 ( 2593 777 ) ( * 791 ) NEW metal3 ( 2593 791 ) ( 3087 * ) @@ -1660,8 +1656,8 @@ NETS 120 ; NEW metal2 ( 2118 791 ) via2_5 NEW metal1 ( 1624 777 ) via1_4 NEW metal2 ( 1624 791 ) via2_5 ; - - storage_5_0.select0_b ( storage_5_0.select_inv_0 ZN ) ( storage_5_0.bit6.obuf0 EN ) ( storage_5_0.bit5.obuf0 EN ) ( storage_5_0.bit4.obuf0 EN ) ( storage_5_0.bit3.obuf0 EN ) ( storage_5_0.bit2.obuf0 EN ) ( storage_5_0.bit1.obuf0 EN ) - ( storage_5_0.bit0.obuf0 EN ) + USE SIGNAL + - storage_5_0_0.select0_b ( storage_5_0_0.select_inv_0 ZN ) ( storage_5_0_0.bit6.obuf0 EN ) ( storage_5_0_0.bit5.obuf0 EN ) ( storage_5_0_0.bit4.obuf0 EN ) ( storage_5_0_0.bit3.obuf0 EN ) ( storage_5_0_0.bit2.obuf0 EN ) ( storage_5_0_0.bit1.obuf0 EN ) + ( storage_5_0_0.bit0.obuf0 EN ) + USE SIGNAL + ROUTED metal3 ( 465 749 ) ( 940 * ) NEW metal2 ( 3733 735 ) ( * 749 ) NEW metal2 ( 3733 735 ) ( 3752 * ) @@ -1687,51 +1683,51 @@ NETS 120 ; NEW metal2 ( 1909 749 ) via2_5 NEW metal1 ( 1434 749 ) via1_4 NEW metal2 ( 1434 749 ) via2_5 ; - - storage_5_0.we0 ( storage_5_0.gcand ZN ) ( storage_5_0.cg E ) + USE SIGNAL + - storage_5_0_0.we0 ( storage_5_0_0.gcand ZN ) ( storage_5_0_0.cg E ) + USE SIGNAL + ROUTED metal3 ( 3505 777 ) ( 3714 * ) NEW metal1 ( 3505 777 ) via1_4 NEW metal2 ( 3505 777 ) via2_5 NEW metal1 ( 3714 777 ) via1_4 NEW metal2 ( 3714 777 ) via2_5 ; - - storage_6_0.bit0.storage ( storage_6_0.bit0.obuf0 A ) ( storage_6_0.bit0.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 294 903 ) ( 427 * ) - NEW metal1 ( 294 903 ) via1_4 - NEW metal1 ( 427 903 ) via1_4 ; - - storage_6_0.bit1.storage ( storage_6_0.bit1.obuf0 A ) ( storage_6_0.bit1.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 769 903 ) ( 902 * ) - NEW metal1 ( 769 903 ) via1_4 - NEW metal2 ( 769 903 ) via2_5 + - storage_6_0_0.bit0.storage ( storage_6_0_0.bit0.obuf0 A ) ( storage_6_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 332 903 ) ( 427 * ) + NEW metal1 ( 427 903 ) via1_4 + NEW metal1 ( 332 903 ) via1_4 ; + - storage_6_0_0.bit1.storage ( storage_6_0_0.bit1.obuf0 A ) ( storage_6_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 807 903 ) ( 902 * ) NEW metal1 ( 902 903 ) via1_4 - NEW metal2 ( 902 903 ) via2_5 ; - - storage_6_0.bit2.storage ( storage_6_0.bit2.obuf0 A ) ( storage_6_0.bit2.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1263 903 ) ( 1396 * ) - NEW metal1 ( 1263 903 ) via1_4 - NEW metal1 ( 1396 903 ) via1_4 ; - - storage_6_0.bit3.storage ( storage_6_0.bit3.obuf0 A ) ( storage_6_0.bit3.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 1738 903 ) ( 1871 * ) - NEW metal1 ( 1738 903 ) via1_4 - NEW metal1 ( 1871 903 ) via1_4 ; - - storage_6_0.bit4.storage ( storage_6_0.bit4.obuf0 A ) ( storage_6_0.bit4.bit QN ) + USE SIGNAL - + ROUTED metal3 ( 2232 903 ) ( 2365 * ) - NEW metal1 ( 2232 903 ) via1_4 - NEW metal2 ( 2232 903 ) via2_5 + NEW metal2 ( 902 903 ) via2_5 + NEW metal1 ( 807 903 ) via1_4 + NEW metal2 ( 807 903 ) via2_5 ; + - storage_6_0_0.bit2.storage ( storage_6_0_0.bit2.obuf0 A ) ( storage_6_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1301 903 ) ( 1396 * ) + NEW metal1 ( 1396 903 ) via1_4 + NEW metal1 ( 1301 903 ) via1_4 ; + - storage_6_0_0.bit3.storage ( storage_6_0_0.bit3.obuf0 A ) ( storage_6_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 1776 903 ) ( 1871 * ) + NEW metal1 ( 1871 903 ) via1_4 + NEW metal1 ( 1776 903 ) via1_4 ; + - storage_6_0_0.bit4.storage ( storage_6_0_0.bit4.obuf0 A ) ( storage_6_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED metal3 ( 2270 903 ) ( 2365 * ) NEW metal1 ( 2365 903 ) via1_4 - NEW metal2 ( 2365 903 ) via2_5 ; - - storage_6_0.bit5.storage ( storage_6_0.bit5.obuf0 A ) ( storage_6_0.bit5.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 2707 903 ) ( 2840 * ) - NEW metal1 ( 2707 903 ) via1_4 - NEW metal1 ( 2840 903 ) via1_4 ; - - storage_6_0.bit6.storage ( storage_6_0.bit6.obuf0 A ) ( storage_6_0.bit6.bit QN ) + USE SIGNAL - + ROUTED metal2 ( 3201 903 ) ( 3334 * ) - NEW metal1 ( 3201 903 ) via1_4 - NEW metal1 ( 3334 903 ) via1_4 ; - - storage_6_0.gclock ( storage_6_0.cg GCK ) ( storage_6_0.bit6.bit CK ) ( storage_6_0.bit5.bit CK ) ( storage_6_0.bit4.bit CK ) ( storage_6_0.bit3.bit CK ) ( storage_6_0.bit2.bit CK ) ( storage_6_0.bit1.bit CK ) - ( storage_6_0.bit0.bit CK ) + USE SIGNAL + NEW metal2 ( 2365 903 ) via2_5 + NEW metal1 ( 2270 903 ) via1_4 + NEW metal2 ( 2270 903 ) via2_5 ; + - storage_6_0_0.bit5.storage ( storage_6_0_0.bit5.obuf0 A ) ( storage_6_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 2745 903 ) ( 2840 * ) + NEW metal1 ( 2840 903 ) via1_4 + NEW metal1 ( 2745 903 ) via1_4 ; + - storage_6_0_0.bit6.storage ( storage_6_0_0.bit6.obuf0 A ) ( storage_6_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED metal2 ( 3239 903 ) ( 3334 * ) + NEW metal1 ( 3334 903 ) via1_4 + NEW metal1 ( 3239 903 ) via1_4 ; + - storage_6_0_0.gclock ( storage_6_0_0.cg GCK ) ( storage_6_0_0.bit6.bit CK ) ( storage_6_0_0.bit5.bit CK ) ( storage_6_0_0.bit4.bit CK ) ( storage_6_0_0.bit3.bit CK ) ( storage_6_0_0.bit2.bit CK ) ( storage_6_0_0.bit1.bit CK ) + ( storage_6_0_0.bit0.bit CK ) + USE SIGNAL + ROUTED metal3 ( 180 903 ) ( 655 * ) NEW metal2 ( 1149 889 ) ( * 903 ) - NEW metal3 ( 737 889 ) ( 1149 * ) - NEW metal3 ( 737 889 ) ( * 903 ) - NEW metal3 ( 655 903 ) ( 737 * ) + NEW metal3 ( 765 889 ) ( 1149 * ) + NEW metal3 ( 765 889 ) ( * 903 ) + NEW metal3 ( 655 903 ) ( 765 * ) NEW metal2 ( 3087 889 ) ( * 903 ) NEW metal2 ( 2593 889 ) ( * 903 ) NEW metal3 ( 2593 889 ) ( 3087 * ) @@ -1757,8 +1753,8 @@ NETS 120 ; NEW metal2 ( 2118 889 ) via2_5 NEW metal1 ( 1624 903 ) via1_4 NEW metal2 ( 1624 889 ) via2_5 ; - - storage_6_0.select0_b ( storage_6_0.select_inv_0 ZN ) ( storage_6_0.bit6.obuf0 EN ) ( storage_6_0.bit5.obuf0 EN ) ( storage_6_0.bit4.obuf0 EN ) ( storage_6_0.bit3.obuf0 EN ) ( storage_6_0.bit2.obuf0 EN ) ( storage_6_0.bit1.obuf0 EN ) - ( storage_6_0.bit0.obuf0 EN ) + USE SIGNAL + - storage_6_0_0.select0_b ( storage_6_0_0.select_inv_0 ZN ) ( storage_6_0_0.bit6.obuf0 EN ) ( storage_6_0_0.bit5.obuf0 EN ) ( storage_6_0_0.bit4.obuf0 EN ) ( storage_6_0_0.bit3.obuf0 EN ) ( storage_6_0_0.bit2.obuf0 EN ) ( storage_6_0_0.bit1.obuf0 EN ) + ( storage_6_0_0.bit0.obuf0 EN ) + USE SIGNAL + ROUTED metal3 ( 465 917 ) ( 940 * ) NEW metal3 ( 3733 903 ) ( * 917 ) NEW metal3 ( 3733 903 ) ( 3752 * ) @@ -1784,25 +1780,29 @@ NETS 120 ; NEW metal2 ( 1909 917 ) via2_5 NEW metal1 ( 1434 917 ) via1_4 NEW metal2 ( 1434 917 ) via2_5 ; - - storage_6_0.we0 ( storage_6_0.gcand ZN ) ( storage_6_0.cg E ) + USE SIGNAL + - storage_6_0_0.we0 ( storage_6_0_0.gcand ZN ) ( storage_6_0_0.cg E ) + USE SIGNAL + ROUTED metal3 ( 3505 903 ) ( 3714 * ) NEW metal1 ( 3505 903 ) via1_4 NEW metal2 ( 3505 903 ) via2_5 NEW metal1 ( 3714 903 ) via1_4 NEW metal2 ( 3714 903 ) via2_5 ; - - we[0] ( PIN we[0] ) ( storage_6_0.gcand A2 ) ( storage_5_0.gcand A2 ) ( storage_4_0.gcand A2 ) ( storage_3_0.gcand A2 ) ( storage_2_0.gcand A2 ) ( storage_1_0.gcand A2 ) - ( storage_0_0.gcand A2 ) + USE SIGNAL - + ROUTED metal2 ( 3676 175 ) ( * 217 ) - NEW metal3 ( 3676 175 ) ( 3948 * 0 ) - NEW metal2 ( 3676 63 ) ( * 175 ) + - we[0] ( PIN we[0] ) ( storage_6_0_0.gcand A2 ) ( storage_5_0_0.gcand A2 ) ( storage_4_0_0.gcand A2 ) ( storage_3_0_0.gcand A2 ) ( storage_2_0_0.gcand A2 ) ( storage_1_0_0.gcand A2 ) + ( storage_0_0_0.gcand A2 ) + USE SIGNAL + + ROUTED metal2 ( 3676 49 ) ( * 63 ) + NEW metal3 ( 3676 49 ) ( 3904 * ) + NEW metal2 ( 3904 49 ) ( * 119 ) + NEW metal3 ( 3904 119 ) ( 3948 * 0 ) + NEW metal2 ( 3676 63 ) ( * 217 ) NEW metal2 ( 3676 217 ) ( * 343 ) NEW metal2 ( 3676 343 ) ( * 497 ) NEW metal2 ( 3676 497 ) ( * 623 ) NEW metal2 ( 3676 623 ) ( * 777 ) NEW metal2 ( 3676 777 ) ( * 903 ) - NEW metal1 ( 3676 217 ) via1_4 - NEW metal2 ( 3676 175 ) via2_5 NEW metal1 ( 3676 63 ) via1_4 + NEW metal2 ( 3676 49 ) via2_5 + NEW metal2 ( 3904 49 ) via2_5 + NEW metal2 ( 3904 119 ) via2_5 + NEW metal1 ( 3676 217 ) via1_4 NEW metal1 ( 3676 343 ) via1_4 NEW metal1 ( 3676 497 ) via1_4 NEW metal1 ( 3676 623 ) via1_4 diff --git a/src/ram/test/make_7x7_nangate45.lefok b/src/ram/test/make_7x7_nangate45.lefok index 7fb088640e8..9d9d1b1bd91 100644 --- a/src/ram/test/make_7x7_nangate45.lefok +++ b/src/ram/test/make_7x7_nangate45.lefok @@ -14,7 +14,7 @@ MACRO RAM7x7 USE SIGNAL ; PORT LAYER metal3 ; - RECT 39.45 1.435 39.52 1.505 ; + RECT 39.45 0.875 39.52 0.945 ; END END clk PIN we[0] @@ -22,39 +22,39 @@ MACRO RAM7x7 USE SIGNAL ; PORT LAYER metal3 ; - RECT 39.45 1.715 39.52 1.785 ; + RECT 39.45 1.155 39.52 1.225 ; END END we[0] - PIN addr[0] + PIN addr_rw[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER metal3 ; RECT 39.45 2.275 39.52 2.345 ; END - END addr[0] - PIN addr[1] + END addr_rw[0] + PIN addr_rw[1] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER metal3 ; RECT 39.45 3.395 39.52 3.465 ; END - END addr[1] - PIN addr[2] + END addr_rw[1] + PIN addr_rw[2] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER metal3 ; - RECT 39.45 1.155 39.52 1.225 ; + RECT 39.45 0.595 39.52 0.665 ; END - END addr[2] + END addr_rw[2] PIN D[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER metal4 ; - RECT 1.145 11.06 1.285 11.2 ; + RECT 0.025 11.06 0.165 11.2 ; END END D[0] PIN Q[0] @@ -216,15 +216,15 @@ MACRO RAM7x7 RECT 0 -0.085 39.33 11.285 ; RECT 39.33 -0.085 39.52 11.24 ; LAYER metal2 ; - RECT 35.93 -0.07 36.07 0.315 ; + RECT 35.93 -0.07 36.07 0.14 ; RECT 8.93 -0.07 9.07 0.42 ; RECT 17.93 -0.07 18.07 0.42 ; RECT 26.93 -0.07 27.07 0.42 ; - RECT 35.93 0.315 37.37 0.42 ; + RECT 35.93 0.14 38.89 0.42 ; RECT 8.93 0.42 11.53 0.56 ; RECT 16.21 0.42 21.22 0.56 ; RECT 25.9 0.42 30.91 0.56 ; - RECT 35.78 0.42 38.89 0.56 ; + RECT 35.78 0.42 39.08 0.56 ; RECT 1.01 0.56 39.27 2.1 ; RECT 1.01 2.1 39.46 8.96 ; RECT 1.01 8.96 39.27 9.1 ; @@ -250,12 +250,13 @@ MACRO RAM7x7 RECT 26.93 10.64 27.07 11.27 ; RECT 35.93 9.52 36.07 11.27 ; LAYER metal3 ; - RECT 0.215 10.535 1.285 10.605 ; - RECT 1.735 0.595 4.43 9.485 ; + RECT 0.025 10.535 0.355 10.605 ; + RECT 1.735 0.595 3.385 9.065 ; + RECT 3.385 0.595 4.43 9.485 ; RECT 4.43 0.595 4.965 9.87 ; RECT 4.965 0.595 5.205 10.605 ; - RECT 5.205 0.595 7.34 9.205 ; - RECT 7.34 0.455 8.195 9.205 ; + RECT 5.205 0.595 7.62 9.205 ; + RECT 7.62 0.455 8.195 9.205 ; RECT 8.195 0.455 8.93 9.485 ; RECT 8.93 -0.07 9.07 11.27 ; RECT 9.07 0.455 10.245 10.605 ; @@ -275,8 +276,8 @@ MACRO RAM7x7 RECT 35.93 -0.07 36.07 11.27 ; RECT 36.07 0.455 37.37 9.205 ; RECT 37.37 0.455 37.595 9.065 ; - RECT 37.595 0.455 38.925 8.925 ; - RECT 38.925 1.155 39.485 8.925 ; + RECT 37.595 0.455 39.115 8.925 ; + RECT 39.115 0.595 39.485 8.925 ; RECT 39.485 2.135 39.495 2.205 ; RECT 39.485 6.195 39.495 8.925 ; LAYER metal4 ; @@ -286,7 +287,7 @@ MACRO RAM7x7 RECT 35.93 -0.07 36.07 0 ; RECT 4.43 0 36.07 9.38 ; RECT 3.385 9.38 36.07 10.5 ; - RECT 1.145 10.5 36.07 11.13 ; + RECT 0.025 10.5 36.07 11.13 ; RECT 4.43 11.13 36.07 11.2 ; RECT 8.93 11.2 9.07 11.27 ; RECT 17.93 11.2 18.07 11.27 ; diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok index 46f3bad74d2..f6b4cb39811 100644 --- a/src/ram/test/make_7x7_nangate45.ok +++ b/src/ram/test/make_7x7_nangate45.ok @@ -22,10 +22,17 @@ [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 135 library cells [INFO RAM-0003] Generating RAM7x7 [INFO RAM-0016] Selected inverter cell INV_X1 +[INFO RAM-0030] buildPortMap DataOut for INV_X1: ZN [INFO RAM-0016] Selected tristate cell TBUF_X1 +[INFO RAM-0030] buildPortMap DataOut for TBUF_X1: Z [INFO RAM-0016] Selected and2 cell AND2_X1 +[INFO RAM-0030] buildPortMap DataOut for AND2_X1: ZN +[INFO RAM-0030] buildPortMap DataOut for DFF_X1: Q [INFO RAM-0016] Selected clock gate cell CLKGATE_X1 +[INFO RAM-0030] buildPortMap DataOut for CLKGATE_X1: GCK [INFO RAM-0016] Selected buffer cell BUF_X1 +[INFO RAM-0030] buildPortMap DataOut for BUF_X1: Z +[INFO RAM-0016] Selected aoi22 cell AOI22_X1 [INFO RAM-0024] Behavioral Verilog written for RAM7x7 [INFO PDN-0001] Inserting grid: ram_grid [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (4.5000 um, 4.0000 um) for VDD @@ -37,13 +44,14 @@ [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (31.5000 um, 4.0000 um) for VDD [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (36.0000 um, 8.0000 um) for VSS [INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-39.52u at the TOP edge. -[INFO PPL-0001] Number of available slots 184 +[INFO PPL-0067] Restrict pins [ clk we[0] addr_rw[0] addr_rw[1] addr_rw[2] ... ] to region 0.00u-11.20u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 208 [INFO PPL-0002] Number of I/O 19 [INFO PPL-0003] Number of I/O w/sink 19 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 120.70 um. +[INFO PPL-0012] I/O nets HPWL: 119.46 um. [INFO DPL-0001] Placed 35 filler instances. [INFO DRT-0167] List of default vias: Layer via2 diff --git a/src/ram/test/make_8x8.defok b/src/ram/test/make_8x8.defok new file mode 100644 index 00000000000..db5c5e5456b --- /dev/null +++ b/src/ram/test/make_8x8.defok @@ -0,0 +1,2515 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN RAM8x8 ; +UNITS DISTANCE MICRONS 100 ; +DIEAREA ( 0 0 ) ( 11040 2448 ) ; +ROW RAM_ROW0 unithd 0 0 N DO 240 BY 1 STEP 46 0 ; +ROW RAM_ROW1 unithd 0 272 FS DO 240 BY 1 STEP 46 0 ; +ROW RAM_ROW2 unithd 0 544 N DO 240 BY 1 STEP 46 0 ; +ROW RAM_ROW3 unithd 0 816 FS DO 240 BY 1 STEP 46 0 ; +ROW RAM_ROW4 unithd 0 1088 N DO 240 BY 1 STEP 46 0 ; +ROW RAM_ROW5 unithd 0 1360 FS DO 240 BY 1 STEP 46 0 ; +ROW RAM_ROW6 unithd 0 1632 N DO 240 BY 1 STEP 46 0 ; +ROW RAM_ROW7 unithd 0 1904 FS DO 240 BY 1 STEP 46 0 ; +ROW RAM_ROW8 unithd 0 2176 N DO 240 BY 1 STEP 46 0 ; +TRACKS X 23 DO 240 STEP 46 LAYER li1 ; +TRACKS Y 17 DO 72 STEP 34 LAYER li1 ; +TRACKS X 17 DO 325 STEP 34 LAYER met1 ; +TRACKS Y 17 DO 72 STEP 34 LAYER met1 ; +TRACKS X 23 DO 240 STEP 46 LAYER met2 ; +TRACKS Y 23 DO 53 STEP 46 LAYER met2 ; +TRACKS X 34 DO 162 STEP 68 LAYER met3 ; +TRACKS Y 34 DO 36 STEP 68 LAYER met3 ; +TRACKS X 46 DO 120 STEP 92 LAYER met4 ; +TRACKS Y 46 DO 26 STEP 92 LAYER met4 ; +TRACKS X 170 DO 32 STEP 340 LAYER met5 ; +TRACKS Y 170 DO 7 STEP 340 LAYER met5 ; +GCELLGRID X 0 DO 16 STEP 690 ; +GCELLGRID Y 0 DO 3 STEP 690 ; +VIAS 2 ; + - via2_3_480_480_1_1_320_320 + VIARULE M1M2_PR + CUTSIZE 15 15 + LAYERS met1 via met2 + CUTSPACING 17 17 + ENCLOSURE 8 16 16 8 ; + - via3_4_480_480_1_1_400_400 + VIARULE M2M3_PR + CUTSIZE 20 20 + LAYERS met2 via2 met3 + CUTSPACING 20 20 + ENCLOSURE 14 8 6 14 ; +END VIAS +COMPONENTS 325 ; + - FILLER_1_237 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 10902 272 ) FS ; + - FILLER_1_239 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 10994 272 ) FS ; + - FILLER_2_237 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 10902 544 ) N ; + - FILLER_2_239 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 10994 544 ) N ; + - FILLER_4_237 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 10902 1088 ) N ; + - FILLER_4_239 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 10994 1088 ) N ; + - FILLER_5_237 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 10902 1360 ) FS ; + - FILLER_5_239 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 10994 1360 ) FS ; + - FILLER_7_237 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 10902 1904 ) FS ; + - FILLER_7_239 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 10994 1904 ) FS ; + - FILLER_8_104 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4784 2176 ) N ; + - FILLER_8_112 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5152 2176 ) N ; + - FILLER_8_12 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 552 2176 ) N ; + - FILLER_8_120 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 5520 2176 ) N ; + - FILLER_8_124 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5704 2176 ) N ; + - FILLER_8_129 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5934 2176 ) N ; + - FILLER_8_137 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6302 2176 ) N ; + - FILLER_8_145 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 6670 2176 ) N ; + - FILLER_8_149 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 6854 2176 ) N ; + - FILLER_8_154 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7084 2176 ) N ; + - FILLER_8_162 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7452 2176 ) N ; + - FILLER_8_170 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 7820 2176 ) N ; + - FILLER_8_174 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 8004 2176 ) N ; + - FILLER_8_179 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8234 2176 ) N ; + - FILLER_8_187 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8602 2176 ) N ; + - FILLER_8_195 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8970 2176 ) N ; + - FILLER_8_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 2176 ) N ; + - FILLER_8_20 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 920 2176 ) N ; + - FILLER_8_201 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 9246 2176 ) N ; + - FILLER_8_209 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 9614 2176 ) N ; + - FILLER_8_217 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 9982 2176 ) N ; + - FILLER_8_221 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 10166 2176 ) N ; + - FILLER_8_224 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 10304 2176 ) N ; + - FILLER_8_232 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 10672 2176 ) N ; + - FILLER_8_24 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 1104 2176 ) N ; + - FILLER_8_29 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1334 2176 ) N ; + - FILLER_8_37 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1702 2176 ) N ; + - FILLER_8_4 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 184 2176 ) N ; + - FILLER_8_45 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 2070 2176 ) N ; + - FILLER_8_49 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 2254 2176 ) N ; + - FILLER_8_54 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2484 2176 ) N ; + - FILLER_8_62 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2852 2176 ) N ; + - FILLER_8_70 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 3220 2176 ) N ; + - FILLER_8_74 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 3404 2176 ) N ; + - FILLER_8_79 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3634 2176 ) N ; + - FILLER_8_87 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4002 2176 ) N ; + - FILLER_8_95 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 4370 2176 ) N ; + - FILLER_8_99 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 4554 2176 ) N ; + - buffer.in[0] sky130_fd_sc_hd__buf_1 + PLACED ( 46 2176 ) N ; + - buffer.in[1] sky130_fd_sc_hd__buf_1 + PLACED ( 1196 2176 ) N ; + - buffer.in[2] sky130_fd_sc_hd__buf_1 + PLACED ( 2346 2176 ) N ; + - buffer.in[3] sky130_fd_sc_hd__buf_1 + PLACED ( 3496 2176 ) N ; + - buffer.in[4] sky130_fd_sc_hd__buf_1 + PLACED ( 4646 2176 ) N ; + - buffer.in[5] sky130_fd_sc_hd__buf_1 + PLACED ( 5796 2176 ) N ; + - buffer.in[6] sky130_fd_sc_hd__buf_1 + PLACED ( 6946 2176 ) N ; + - buffer.in[7] sky130_fd_sc_hd__buf_1 + PLACED ( 8096 2176 ) N ; + - decoder.inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10902 1632 ) N ; + - decoder.inv_1 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10902 816 ) FS ; + - decoder.inv_2 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10902 0 ) N ; + - decoder_0.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 10304 0 ) N ; + - decoder_0.and_layer1 sky130_fd_sc_hd__and2_0 + PLACED ( 10534 0 ) N ; + - decoder_0.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 10764 0 ) N ; + - decoder_1.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 10304 272 ) FS ; + - decoder_1.and_layer1 sky130_fd_sc_hd__and2_0 + PLACED ( 10534 272 ) FS ; + - decoder_1.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 10764 272 ) FS ; + - decoder_2.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 10304 544 ) N ; + - decoder_2.and_layer1 sky130_fd_sc_hd__and2_0 + PLACED ( 10534 544 ) N ; + - decoder_2.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 10764 544 ) N ; + - decoder_3.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 10304 816 ) FS ; + - decoder_3.and_layer1 sky130_fd_sc_hd__and2_0 + PLACED ( 10534 816 ) FS ; + - decoder_3.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 10764 816 ) FS ; + - decoder_4.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 10304 1088 ) N ; + - decoder_4.and_layer1 sky130_fd_sc_hd__and2_0 + PLACED ( 10534 1088 ) N ; + - decoder_4.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 10764 1088 ) N ; + - decoder_5.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 10304 1360 ) FS ; + - decoder_5.and_layer1 sky130_fd_sc_hd__and2_0 + PLACED ( 10534 1360 ) FS ; + - decoder_5.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 10764 1360 ) FS ; + - decoder_6.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 10304 1632 ) N ; + - decoder_6.and_layer1 sky130_fd_sc_hd__and2_0 + PLACED ( 10534 1632 ) N ; + - decoder_6.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 10764 1632 ) N ; + - decoder_7.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 10304 1904 ) FS ; + - decoder_7.and_layer1 sky130_fd_sc_hd__and2_0 + PLACED ( 10534 1904 ) FS ; + - decoder_7.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 10764 1904 ) FS ; + - storage_0_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 0 ) N ; + - storage_0_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 0 ) N ; + - storage_0_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 0 ) N ; + - storage_0_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 0 ) N ; + - storage_0_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 0 ) N ; + - storage_0_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 0 ) N ; + - storage_0_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 0 ) N ; + - storage_0_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 0 ) N ; + - storage_0_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 0 ) N ; + - storage_0_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 0 ) N ; + - storage_0_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 0 ) N ; + - storage_0_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 0 ) N ; + - storage_0_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 0 ) N ; + - storage_0_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 0 ) N ; + - storage_0_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 0 ) N ; + - storage_0_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 0 ) N ; + - storage_0_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 0 ) N ; + - storage_0_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 0 ) N ; + - storage_0_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 0 ) N ; + - storage_1_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 272 ) FS ; + - storage_1_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 272 ) FS ; + - storage_1_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 272 ) FS ; + - storage_1_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 272 ) FS ; + - storage_1_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 272 ) FS ; + - storage_1_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 272 ) FS ; + - storage_1_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 272 ) FS ; + - storage_1_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 272 ) FS ; + - storage_1_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 272 ) FS ; + - storage_1_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 272 ) FS ; + - storage_1_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 272 ) FS ; + - storage_1_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 272 ) FS ; + - storage_1_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 272 ) FS ; + - storage_1_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 272 ) FS ; + - storage_1_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 272 ) FS ; + - storage_1_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 272 ) FS ; + - storage_1_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 272 ) FS ; + - storage_1_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 272 ) FS ; + - storage_1_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 272 ) FS ; + - storage_2_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 544 ) N ; + - storage_2_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 544 ) N ; + - storage_2_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 544 ) N ; + - storage_2_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 544 ) N ; + - storage_2_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 544 ) N ; + - storage_2_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 544 ) N ; + - storage_2_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 544 ) N ; + - storage_2_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 544 ) N ; + - storage_2_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 544 ) N ; + - storage_2_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 544 ) N ; + - storage_2_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 544 ) N ; + - storage_2_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 544 ) N ; + - storage_2_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 544 ) N ; + - storage_2_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 544 ) N ; + - storage_2_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 544 ) N ; + - storage_2_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 544 ) N ; + - storage_2_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 544 ) N ; + - storage_2_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 544 ) N ; + - storage_2_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 544 ) N ; + - storage_3_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 816 ) FS ; + - storage_3_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 816 ) FS ; + - storage_3_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 816 ) FS ; + - storage_3_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 816 ) FS ; + - storage_3_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 816 ) FS ; + - storage_3_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 816 ) FS ; + - storage_3_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 816 ) FS ; + - storage_3_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 816 ) FS ; + - storage_3_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 816 ) FS ; + - storage_3_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 816 ) FS ; + - storage_3_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 816 ) FS ; + - storage_3_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 816 ) FS ; + - storage_3_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 816 ) FS ; + - storage_3_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 816 ) FS ; + - storage_3_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 816 ) FS ; + - storage_3_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 816 ) FS ; + - storage_3_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 816 ) FS ; + - storage_3_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 816 ) FS ; + - storage_3_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 816 ) FS ; + - storage_4_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1088 ) N ; + - storage_4_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1088 ) N ; + - storage_4_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1088 ) N ; + - storage_4_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1088 ) N ; + - storage_4_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1088 ) N ; + - storage_4_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1088 ) N ; + - storage_4_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1088 ) N ; + - storage_4_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1088 ) N ; + - storage_4_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1088 ) N ; + - storage_4_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1088 ) N ; + - storage_4_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1088 ) N ; + - storage_4_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1088 ) N ; + - storage_4_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1088 ) N ; + - storage_4_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1088 ) N ; + - storage_4_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1088 ) N ; + - storage_4_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1088 ) N ; + - storage_4_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1088 ) N ; + - storage_4_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1088 ) N ; + - storage_4_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1088 ) N ; + - storage_5_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1360 ) FS ; + - storage_5_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1360 ) FS ; + - storage_5_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1360 ) FS ; + - storage_5_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1360 ) FS ; + - storage_5_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1360 ) FS ; + - storage_5_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1360 ) FS ; + - storage_5_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1360 ) FS ; + - storage_5_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1360 ) FS ; + - storage_5_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1360 ) FS ; + - storage_5_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1360 ) FS ; + - storage_5_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1360 ) FS ; + - storage_5_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1360 ) FS ; + - storage_5_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1360 ) FS ; + - storage_5_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1360 ) FS ; + - storage_5_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1360 ) FS ; + - storage_5_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1360 ) FS ; + - storage_5_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1360 ) FS ; + - storage_5_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1360 ) FS ; + - storage_5_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1360 ) FS ; + - storage_6_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1632 ) N ; + - storage_6_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1632 ) N ; + - storage_6_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1632 ) N ; + - storage_6_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1632 ) N ; + - storage_6_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1632 ) N ; + - storage_6_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1632 ) N ; + - storage_6_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1632 ) N ; + - storage_6_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1632 ) N ; + - storage_6_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1632 ) N ; + - storage_6_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1632 ) N ; + - storage_6_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1632 ) N ; + - storage_6_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1632 ) N ; + - storage_6_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1632 ) N ; + - storage_6_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1632 ) N ; + - storage_6_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1632 ) N ; + - storage_6_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1632 ) N ; + - storage_6_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1632 ) N ; + - storage_6_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1632 ) N ; + - storage_6_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1632 ) N ; + - storage_7_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1904 ) FS ; + - storage_7_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1904 ) FS ; + - storage_7_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1904 ) FS ; + - storage_7_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1904 ) FS ; + - storage_7_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1904 ) FS ; + - storage_7_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1904 ) FS ; + - storage_7_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1904 ) FS ; + - storage_7_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1904 ) FS ; + - storage_7_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1904 ) FS ; + - storage_7_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1904 ) FS ; + - storage_7_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1904 ) FS ; + - storage_7_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1904 ) FS ; + - storage_7_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1904 ) FS ; + - storage_7_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1904 ) FS ; + - storage_7_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1904 ) FS ; + - storage_7_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1904 ) FS ; + - storage_7_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1904 ) FS ; + - storage_7_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1904 ) FS ; + - storage_7_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1904 ) FS ; + - tapcell.cell0_0 sky130_fd_sc_hd__tap_1 + PLACED ( 0 0 ) N ; + - tapcell.cell0_1 sky130_fd_sc_hd__tap_1 + PLACED ( 0 272 ) FS ; + - tapcell.cell0_2 sky130_fd_sc_hd__tap_1 + PLACED ( 0 544 ) N ; + - tapcell.cell0_3 sky130_fd_sc_hd__tap_1 + PLACED ( 0 816 ) FS ; + - tapcell.cell0_4 sky130_fd_sc_hd__tap_1 + PLACED ( 0 1088 ) N ; + - tapcell.cell0_5 sky130_fd_sc_hd__tap_1 + PLACED ( 0 1360 ) FS ; + - tapcell.cell0_6 sky130_fd_sc_hd__tap_1 + PLACED ( 0 1632 ) N ; + - tapcell.cell0_7 sky130_fd_sc_hd__tap_1 + PLACED ( 0 1904 ) FS ; + - tapcell.cell0_8 sky130_fd_sc_hd__tap_1 + PLACED ( 0 2176 ) N ; + - tapcell.cell1_0 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 0 ) N ; + - tapcell.cell1_1 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 272 ) FS ; + - tapcell.cell1_2 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 544 ) N ; + - tapcell.cell1_3 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 816 ) FS ; + - tapcell.cell1_4 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 1088 ) N ; + - tapcell.cell1_5 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 1360 ) FS ; + - tapcell.cell1_6 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 1632 ) N ; + - tapcell.cell1_7 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 1904 ) FS ; + - tapcell.cell1_8 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 2176 ) N ; + - tapcell.cell2_0 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 0 ) N ; + - tapcell.cell2_1 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 272 ) FS ; + - tapcell.cell2_2 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 544 ) N ; + - tapcell.cell2_3 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 816 ) FS ; + - tapcell.cell2_4 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 1088 ) N ; + - tapcell.cell2_5 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 1360 ) FS ; + - tapcell.cell2_6 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 1632 ) N ; + - tapcell.cell2_7 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 1904 ) FS ; + - tapcell.cell2_8 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 2176 ) N ; + - tapcell.cell3_0 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 0 ) N ; + - tapcell.cell3_1 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 272 ) FS ; + - tapcell.cell3_2 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 544 ) N ; + - tapcell.cell3_3 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 816 ) FS ; + - tapcell.cell3_4 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 1088 ) N ; + - tapcell.cell3_5 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 1360 ) FS ; + - tapcell.cell3_6 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 1632 ) N ; + - tapcell.cell3_7 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 1904 ) FS ; + - tapcell.cell3_8 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 2176 ) N ; + - tapcell.cell4_0 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 0 ) N ; + - tapcell.cell4_1 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 272 ) FS ; + - tapcell.cell4_2 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 544 ) N ; + - tapcell.cell4_3 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 816 ) FS ; + - tapcell.cell4_4 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1088 ) N ; + - tapcell.cell4_5 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1360 ) FS ; + - tapcell.cell4_6 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1632 ) N ; + - tapcell.cell4_7 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1904 ) FS ; + - tapcell.cell4_8 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 2176 ) N ; + - tapcell.cell5_0 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 0 ) N ; + - tapcell.cell5_1 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 272 ) FS ; + - tapcell.cell5_2 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 544 ) N ; + - tapcell.cell5_3 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 816 ) FS ; + - tapcell.cell5_4 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 1088 ) N ; + - tapcell.cell5_5 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 1360 ) FS ; + - tapcell.cell5_6 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 1632 ) N ; + - tapcell.cell5_7 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 1904 ) FS ; + - tapcell.cell5_8 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 2176 ) N ; + - tapcell.cell6_0 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 0 ) N ; + - tapcell.cell6_1 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 272 ) FS ; + - tapcell.cell6_2 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 544 ) N ; + - tapcell.cell6_3 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 816 ) FS ; + - tapcell.cell6_4 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 1088 ) N ; + - tapcell.cell6_5 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 1360 ) FS ; + - tapcell.cell6_6 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 1632 ) N ; + - tapcell.cell6_7 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 1904 ) FS ; + - tapcell.cell6_8 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 2176 ) N ; + - tapcell.cell7_0 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 0 ) N ; + - tapcell.cell7_1 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 272 ) FS ; + - tapcell.cell7_2 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 544 ) N ; + - tapcell.cell7_3 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 816 ) FS ; + - tapcell.cell7_4 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 1088 ) N ; + - tapcell.cell7_5 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 1360 ) FS ; + - tapcell.cell7_6 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 1632 ) N ; + - tapcell.cell7_7 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 1904 ) FS ; + - tapcell.cell7_8 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 2176 ) N ; + - tapcell.cell8_0 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 0 ) N ; + - tapcell.cell8_1 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 272 ) FS ; + - tapcell.cell8_2 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 544 ) N ; + - tapcell.cell8_3 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 816 ) FS ; + - tapcell.cell8_4 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 1088 ) N ; + - tapcell.cell8_5 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 1360 ) FS ; + - tapcell.cell8_6 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 1632 ) N ; + - tapcell.cell8_7 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 1904 ) FS ; + - tapcell.cell8_8 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 2176 ) N ; + - tapcell.cell9_0 sky130_fd_sc_hd__tap_1 + PLACED ( 10258 0 ) N ; + - tapcell.cell9_1 sky130_fd_sc_hd__tap_1 + PLACED ( 10258 272 ) FS ; + - tapcell.cell9_2 sky130_fd_sc_hd__tap_1 + PLACED ( 10258 544 ) N ; + - tapcell.cell9_3 sky130_fd_sc_hd__tap_1 + PLACED ( 10258 816 ) FS ; + - tapcell.cell9_4 sky130_fd_sc_hd__tap_1 + PLACED ( 10258 1088 ) N ; + - tapcell.cell9_5 sky130_fd_sc_hd__tap_1 + PLACED ( 10258 1360 ) FS ; + - tapcell.cell9_6 sky130_fd_sc_hd__tap_1 + PLACED ( 10258 1632 ) N ; + - tapcell.cell9_7 sky130_fd_sc_hd__tap_1 + PLACED ( 10258 1904 ) FS ; + - tapcell.cell9_8 sky130_fd_sc_hd__tap_1 + PLACED ( 10258 2176 ) N ; +END COMPONENTS +PINS 23 ; + - D[0] + NET D[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 115 2423 ) N ; + - D[1] + NET D[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 1219 2423 ) N ; + - D[2] + NET D[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 2415 2423 ) N ; + - D[3] + NET D[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 3519 2423 ) N ; + - D[4] + NET D[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 4715 2423 ) N ; + - D[5] + NET D[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 5819 2423 ) N ; + - D[6] + NET D[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 7015 2423 ) N ; + - D[7] + NET D[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 8119 2423 ) N ; + - Q[0] + NET Q[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 1127 2423 ) N ; + - Q[1] + NET Q[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 2231 2423 ) N ; + - Q[2] + NET Q[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 3427 2423 ) N ; + - Q[3] + NET Q[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 4531 2423 ) N ; + - Q[4] + NET Q[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 5727 2423 ) N ; + - Q[5] + NET Q[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 6831 2423 ) N ; + - Q[6] + NET Q[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 8027 2423 ) N ; + - Q[7] + NET Q[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 9131 2423 ) N ; + - VDD + NET VDD + SPECIAL + DIRECTION INOUT + USE POWER + + PORT + + LAYER met3 ( -15 -24 ) ( 15 24 ) + + LAYER met3 ( -11025 -24 ) ( -10995 24 ) + + LAYER met2 ( -1049 1434 ) ( -1001 1448 ) + + LAYER met2 ( -1049 -1000 ) ( -1001 -986 ) + + LAYER met2 ( -5049 1434 ) ( -5001 1448 ) + + LAYER met2 ( -5049 -1000 ) ( -5001 -986 ) + + LAYER met2 ( -9049 1434 ) ( -9001 1448 ) + + LAYER met2 ( -9049 -1000 ) ( -9001 -986 ) + + LAYER met1 ( 1 1424 ) ( 15 1472 ) + + LAYER met1 ( -11025 1424 ) ( -11011 1472 ) + + LAYER met1 ( 1 880 ) ( 15 928 ) + + LAYER met1 ( -11025 880 ) ( -11011 928 ) + + LAYER met1 ( 1 336 ) ( 15 384 ) + + LAYER met1 ( -11025 336 ) ( -11011 384 ) + + LAYER met1 ( 1 -208 ) ( 15 -160 ) + + LAYER met1 ( -11025 -208 ) ( -11011 -160 ) + + LAYER met1 ( 1 -752 ) ( 15 -704 ) + + LAYER met1 ( -11025 -752 ) ( -11011 -704 ) + + FIXED ( 11025 1000 ) N ; + - VSS + NET VSS + SPECIAL + DIRECTION INOUT + USE GROUND + + PORT + + LAYER met3 ( -15 -24 ) ( 15 24 ) + + LAYER met3 ( -11025 -24 ) ( -10995 24 ) + + LAYER met2 ( -3049 434 ) ( -3001 448 ) + + LAYER met2 ( -3049 -2000 ) ( -3001 -1986 ) + + LAYER met2 ( -7049 434 ) ( -7001 448 ) + + LAYER met2 ( -7049 -2000 ) ( -7001 -1986 ) + + LAYER met1 ( 1 152 ) ( 15 200 ) + + LAYER met1 ( -11025 152 ) ( -11011 200 ) + + LAYER met1 ( 1 -392 ) ( 15 -344 ) + + LAYER met1 ( -11025 -392 ) ( -11011 -344 ) + + LAYER met1 ( 1 -936 ) ( 15 -888 ) + + LAYER met1 ( -11025 -936 ) ( -11011 -888 ) + + LAYER met1 ( 1 -1480 ) ( 15 -1432 ) + + LAYER met1 ( -11025 -1480 ) ( -11011 -1432 ) + + LAYER met1 ( 1 -2024 ) ( 15 -1976 ) + + LAYER met1 ( -11025 -2024 ) ( -11011 -1976 ) + + FIXED ( 11025 2000 ) N ; + - addr_rw[0] + NET addr_rw[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 11000 442 ) N ; + - addr_rw[1] + NET addr_rw[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 11000 714 ) N ; + - addr_rw[2] + NET addr_rw[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 11000 578 ) N ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 11000 170 ) N ; + - we[0] + NET we[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 11000 306 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD ( PIN VDD ) ( tapcell.cell9_8 VPWR ) ( tapcell.cell9_7 VPWR ) ( tapcell.cell9_6 VPWR ) ( tapcell.cell9_5 VPWR ) ( tapcell.cell9_4 VPWR ) ( tapcell.cell9_3 VPWR ) + ( tapcell.cell9_2 VPWR ) ( tapcell.cell9_1 VPWR ) ( tapcell.cell9_0 VPWR ) ( tapcell.cell8_8 VPWR ) ( tapcell.cell8_7 VPWR ) ( tapcell.cell8_6 VPWR ) ( tapcell.cell8_5 VPWR ) ( tapcell.cell8_4 VPWR ) + ( tapcell.cell8_3 VPWR ) ( tapcell.cell8_2 VPWR ) ( tapcell.cell8_1 VPWR ) ( tapcell.cell8_0 VPWR ) ( tapcell.cell7_8 VPWR ) ( tapcell.cell7_7 VPWR ) ( tapcell.cell7_6 VPWR ) ( tapcell.cell7_5 VPWR ) + ( tapcell.cell7_4 VPWR ) ( tapcell.cell7_3 VPWR ) ( tapcell.cell7_2 VPWR ) ( tapcell.cell7_1 VPWR ) ( tapcell.cell7_0 VPWR ) ( tapcell.cell6_8 VPWR ) ( tapcell.cell6_7 VPWR ) ( tapcell.cell6_6 VPWR ) + ( tapcell.cell6_5 VPWR ) ( tapcell.cell6_4 VPWR ) ( tapcell.cell6_3 VPWR ) ( tapcell.cell6_2 VPWR ) ( tapcell.cell6_1 VPWR ) ( tapcell.cell6_0 VPWR ) ( tapcell.cell5_8 VPWR ) ( tapcell.cell5_7 VPWR ) + ( tapcell.cell5_6 VPWR ) ( tapcell.cell5_5 VPWR ) ( tapcell.cell5_4 VPWR ) ( tapcell.cell5_3 VPWR ) ( tapcell.cell5_2 VPWR ) ( tapcell.cell5_1 VPWR ) ( tapcell.cell5_0 VPWR ) ( tapcell.cell4_8 VPWR ) + ( tapcell.cell4_7 VPWR ) ( tapcell.cell4_6 VPWR ) ( tapcell.cell4_5 VPWR ) ( tapcell.cell4_4 VPWR ) ( tapcell.cell4_3 VPWR ) ( tapcell.cell4_2 VPWR ) ( tapcell.cell4_1 VPWR ) ( tapcell.cell4_0 VPWR ) + ( tapcell.cell3_8 VPWR ) ( tapcell.cell3_7 VPWR ) ( tapcell.cell3_6 VPWR ) ( tapcell.cell3_5 VPWR ) ( tapcell.cell3_4 VPWR ) ( tapcell.cell3_3 VPWR ) ( tapcell.cell3_2 VPWR ) ( tapcell.cell3_1 VPWR ) + ( tapcell.cell3_0 VPWR ) ( tapcell.cell2_8 VPWR ) ( tapcell.cell2_7 VPWR ) ( tapcell.cell2_6 VPWR ) ( tapcell.cell2_5 VPWR ) ( tapcell.cell2_4 VPWR ) ( tapcell.cell2_3 VPWR ) ( tapcell.cell2_2 VPWR ) + ( tapcell.cell2_1 VPWR ) ( tapcell.cell2_0 VPWR ) ( tapcell.cell1_8 VPWR ) ( tapcell.cell1_7 VPWR ) ( tapcell.cell1_6 VPWR ) ( tapcell.cell1_5 VPWR ) ( tapcell.cell1_4 VPWR ) ( tapcell.cell1_3 VPWR ) + ( tapcell.cell1_2 VPWR ) ( tapcell.cell1_1 VPWR ) ( tapcell.cell1_0 VPWR ) ( tapcell.cell0_8 VPWR ) ( tapcell.cell0_7 VPWR ) ( tapcell.cell0_6 VPWR ) ( tapcell.cell0_5 VPWR ) ( tapcell.cell0_4 VPWR ) + ( tapcell.cell0_3 VPWR ) ( tapcell.cell0_2 VPWR ) ( tapcell.cell0_1 VPWR ) ( tapcell.cell0_0 VPWR ) ( decoder.inv_0 VPWR ) ( decoder.inv_1 VPWR ) ( decoder.inv_2 VPWR ) ( buffer.in[7] VPWR ) + ( buffer.in[6] VPWR ) ( buffer.in[5] VPWR ) ( buffer.in[4] VPWR ) ( buffer.in[3] VPWR ) ( buffer.in[2] VPWR ) ( buffer.in[1] VPWR ) ( buffer.in[0] VPWR ) ( storage_7_0_0.select_inv_0 VPWR ) + ( storage_7_0_0.gcand VPWR ) ( storage_7_0_0.cg VPWR ) ( storage_7_0_0.bit7.obuf0 VPWR ) ( storage_7_0_0.bit7.bit VPWR ) ( storage_7_0_0.bit6.obuf0 VPWR ) ( storage_7_0_0.bit6.bit VPWR ) ( storage_7_0_0.bit5.obuf0 VPWR ) ( storage_7_0_0.bit5.bit VPWR ) + ( storage_7_0_0.bit4.obuf0 VPWR ) ( storage_7_0_0.bit4.bit VPWR ) ( storage_7_0_0.bit3.obuf0 VPWR ) ( storage_7_0_0.bit3.bit VPWR ) ( storage_7_0_0.bit2.obuf0 VPWR ) ( storage_7_0_0.bit2.bit VPWR ) ( storage_7_0_0.bit1.obuf0 VPWR ) ( storage_7_0_0.bit1.bit VPWR ) + ( storage_7_0_0.bit0.obuf0 VPWR ) ( storage_7_0_0.bit0.bit VPWR ) ( storage_6_0_0.select_inv_0 VPWR ) ( storage_6_0_0.gcand VPWR ) ( storage_6_0_0.cg VPWR ) ( storage_6_0_0.bit7.obuf0 VPWR ) ( storage_6_0_0.bit7.bit VPWR ) ( storage_6_0_0.bit6.obuf0 VPWR ) + ( storage_6_0_0.bit6.bit VPWR ) ( storage_6_0_0.bit5.obuf0 VPWR ) ( storage_6_0_0.bit5.bit VPWR ) ( storage_6_0_0.bit4.obuf0 VPWR ) ( storage_6_0_0.bit4.bit VPWR ) ( storage_6_0_0.bit3.obuf0 VPWR ) ( storage_6_0_0.bit3.bit VPWR ) ( storage_6_0_0.bit2.obuf0 VPWR ) + ( storage_6_0_0.bit2.bit VPWR ) ( storage_6_0_0.bit1.obuf0 VPWR ) ( storage_6_0_0.bit1.bit VPWR ) ( storage_6_0_0.bit0.obuf0 VPWR ) ( storage_6_0_0.bit0.bit VPWR ) ( storage_5_0_0.select_inv_0 VPWR ) ( storage_5_0_0.gcand VPWR ) ( storage_5_0_0.cg VPWR ) + ( storage_5_0_0.bit7.obuf0 VPWR ) ( storage_5_0_0.bit7.bit VPWR ) ( storage_5_0_0.bit6.obuf0 VPWR ) ( storage_5_0_0.bit6.bit VPWR ) ( storage_5_0_0.bit5.obuf0 VPWR ) ( storage_5_0_0.bit5.bit VPWR ) ( storage_5_0_0.bit4.obuf0 VPWR ) ( storage_5_0_0.bit4.bit VPWR ) + ( storage_5_0_0.bit3.obuf0 VPWR ) ( storage_5_0_0.bit3.bit VPWR ) ( storage_5_0_0.bit2.obuf0 VPWR ) ( storage_5_0_0.bit2.bit VPWR ) ( storage_5_0_0.bit1.obuf0 VPWR ) ( storage_5_0_0.bit1.bit VPWR ) ( storage_5_0_0.bit0.obuf0 VPWR ) ( storage_5_0_0.bit0.bit VPWR ) + ( storage_4_0_0.select_inv_0 VPWR ) ( storage_4_0_0.gcand VPWR ) ( storage_4_0_0.cg VPWR ) ( storage_4_0_0.bit7.obuf0 VPWR ) ( storage_4_0_0.bit7.bit VPWR ) ( storage_4_0_0.bit6.obuf0 VPWR ) ( storage_4_0_0.bit6.bit VPWR ) ( storage_4_0_0.bit5.obuf0 VPWR ) + ( storage_4_0_0.bit5.bit VPWR ) ( storage_4_0_0.bit4.obuf0 VPWR ) ( storage_4_0_0.bit4.bit VPWR ) ( storage_4_0_0.bit3.obuf0 VPWR ) ( storage_4_0_0.bit3.bit VPWR ) ( storage_4_0_0.bit2.obuf0 VPWR ) ( storage_4_0_0.bit2.bit VPWR ) ( storage_4_0_0.bit1.obuf0 VPWR ) + ( storage_4_0_0.bit1.bit VPWR ) ( storage_4_0_0.bit0.obuf0 VPWR ) ( storage_4_0_0.bit0.bit VPWR ) ( storage_3_0_0.select_inv_0 VPWR ) ( storage_3_0_0.gcand VPWR ) ( storage_3_0_0.cg VPWR ) ( storage_3_0_0.bit7.obuf0 VPWR ) ( storage_3_0_0.bit7.bit VPWR ) + ( storage_3_0_0.bit6.obuf0 VPWR ) ( storage_3_0_0.bit6.bit VPWR ) ( storage_3_0_0.bit5.obuf0 VPWR ) ( storage_3_0_0.bit5.bit VPWR ) ( storage_3_0_0.bit4.obuf0 VPWR ) ( storage_3_0_0.bit4.bit VPWR ) ( storage_3_0_0.bit3.obuf0 VPWR ) ( storage_3_0_0.bit3.bit VPWR ) + ( storage_3_0_0.bit2.obuf0 VPWR ) ( storage_3_0_0.bit2.bit VPWR ) ( storage_3_0_0.bit1.obuf0 VPWR ) ( storage_3_0_0.bit1.bit VPWR ) ( storage_3_0_0.bit0.obuf0 VPWR ) ( storage_3_0_0.bit0.bit VPWR ) ( storage_2_0_0.select_inv_0 VPWR ) ( storage_2_0_0.gcand VPWR ) + ( storage_2_0_0.cg VPWR ) ( storage_2_0_0.bit7.obuf0 VPWR ) ( storage_2_0_0.bit7.bit VPWR ) ( storage_2_0_0.bit6.obuf0 VPWR ) ( storage_2_0_0.bit6.bit VPWR ) ( storage_2_0_0.bit5.obuf0 VPWR ) ( storage_2_0_0.bit5.bit VPWR ) ( storage_2_0_0.bit4.obuf0 VPWR ) + ( storage_2_0_0.bit4.bit VPWR ) ( storage_2_0_0.bit3.obuf0 VPWR ) ( storage_2_0_0.bit3.bit VPWR ) ( storage_2_0_0.bit2.obuf0 VPWR ) ( storage_2_0_0.bit2.bit VPWR ) ( storage_2_0_0.bit1.obuf0 VPWR ) ( storage_2_0_0.bit1.bit VPWR ) ( storage_2_0_0.bit0.obuf0 VPWR ) + ( storage_2_0_0.bit0.bit VPWR ) ( storage_1_0_0.select_inv_0 VPWR ) ( storage_1_0_0.gcand VPWR ) ( storage_1_0_0.cg VPWR ) ( storage_1_0_0.bit7.obuf0 VPWR ) ( storage_1_0_0.bit7.bit VPWR ) ( storage_1_0_0.bit6.obuf0 VPWR ) ( storage_1_0_0.bit6.bit VPWR ) + ( storage_1_0_0.bit5.obuf0 VPWR ) ( storage_1_0_0.bit5.bit VPWR ) ( storage_1_0_0.bit4.obuf0 VPWR ) ( storage_1_0_0.bit4.bit VPWR ) ( storage_1_0_0.bit3.obuf0 VPWR ) ( storage_1_0_0.bit3.bit VPWR ) ( storage_1_0_0.bit2.obuf0 VPWR ) ( storage_1_0_0.bit2.bit VPWR ) + ( storage_1_0_0.bit1.obuf0 VPWR ) ( storage_1_0_0.bit1.bit VPWR ) ( storage_1_0_0.bit0.obuf0 VPWR ) ( storage_1_0_0.bit0.bit VPWR ) ( storage_0_0_0.select_inv_0 VPWR ) ( storage_0_0_0.gcand VPWR ) ( storage_0_0_0.cg VPWR ) ( storage_0_0_0.bit7.obuf0 VPWR ) + ( storage_0_0_0.bit7.bit VPWR ) ( storage_0_0_0.bit6.obuf0 VPWR ) ( storage_0_0_0.bit6.bit VPWR ) ( storage_0_0_0.bit5.obuf0 VPWR ) ( storage_0_0_0.bit5.bit VPWR ) ( storage_0_0_0.bit4.obuf0 VPWR ) ( storage_0_0_0.bit4.bit VPWR ) ( storage_0_0_0.bit3.obuf0 VPWR ) + ( storage_0_0_0.bit3.bit VPWR ) ( storage_0_0_0.bit2.obuf0 VPWR ) ( storage_0_0_0.bit2.bit VPWR ) ( storage_0_0_0.bit1.obuf0 VPWR ) ( storage_0_0_0.bit1.bit VPWR ) ( storage_0_0_0.bit0.obuf0 VPWR ) ( storage_0_0_0.bit0.bit VPWR ) ( decoder_7.buf_port0 VPWR ) + ( decoder_7.and_layer1 VPWR ) ( decoder_7.and_layer0 VPWR ) ( decoder_6.buf_port0 VPWR ) ( decoder_6.and_layer1 VPWR ) ( decoder_6.and_layer0 VPWR ) ( decoder_5.buf_port0 VPWR ) ( decoder_5.and_layer1 VPWR ) ( decoder_5.and_layer0 VPWR ) + ( decoder_4.buf_port0 VPWR ) ( decoder_4.and_layer1 VPWR ) ( decoder_4.and_layer0 VPWR ) ( decoder_3.buf_port0 VPWR ) ( decoder_3.and_layer1 VPWR ) ( decoder_3.and_layer0 VPWR ) ( decoder_2.buf_port0 VPWR ) ( decoder_2.and_layer1 VPWR ) + ( decoder_2.and_layer0 VPWR ) ( decoder_1.buf_port0 VPWR ) ( decoder_1.and_layer1 VPWR ) ( decoder_1.and_layer0 VPWR ) ( decoder_0.buf_port0 VPWR ) ( decoder_0.and_layer1 VPWR ) ( decoder_0.and_layer0 VPWR ) + USE POWER + + ROUTED met3 48 + SHAPE STRIPE ( 0 1000 ) ( 11040 1000 ) + NEW met2 48 + SHAPE STRIPE ( 10000 0 ) ( 10000 2472 ) + NEW met2 48 + SHAPE STRIPE ( 6000 0 ) ( 6000 2472 ) + NEW met2 48 + SHAPE STRIPE ( 2000 0 ) ( 2000 2472 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 2448 ) ( 11040 2448 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1904 ) ( 11040 1904 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1360 ) ( 11040 1360 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 816 ) ( 11040 816 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 272 ) ( 11040 272 ) + NEW met2 0 + SHAPE STRIPE ( 10000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 6000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 2000 1000 ) via3_4_480_480_1_1_400_400 + NEW met1 0 + SHAPE STRIPE ( 10000 2448 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10000 1904 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 2448 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 1904 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 2448 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 1904 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 272 ) via2_3_480_480_1_1_320_320 ; + - VSS ( PIN VSS ) ( tapcell.cell9_8 VGND ) ( tapcell.cell9_7 VGND ) ( tapcell.cell9_6 VGND ) ( tapcell.cell9_5 VGND ) ( tapcell.cell9_4 VGND ) ( tapcell.cell9_3 VGND ) + ( tapcell.cell9_2 VGND ) ( tapcell.cell9_1 VGND ) ( tapcell.cell9_0 VGND ) ( tapcell.cell8_8 VGND ) ( tapcell.cell8_7 VGND ) ( tapcell.cell8_6 VGND ) ( tapcell.cell8_5 VGND ) ( tapcell.cell8_4 VGND ) + ( tapcell.cell8_3 VGND ) ( tapcell.cell8_2 VGND ) ( tapcell.cell8_1 VGND ) ( tapcell.cell8_0 VGND ) ( tapcell.cell7_8 VGND ) ( tapcell.cell7_7 VGND ) ( tapcell.cell7_6 VGND ) ( tapcell.cell7_5 VGND ) + ( tapcell.cell7_4 VGND ) ( tapcell.cell7_3 VGND ) ( tapcell.cell7_2 VGND ) ( tapcell.cell7_1 VGND ) ( tapcell.cell7_0 VGND ) ( tapcell.cell6_8 VGND ) ( tapcell.cell6_7 VGND ) ( tapcell.cell6_6 VGND ) + ( tapcell.cell6_5 VGND ) ( tapcell.cell6_4 VGND ) ( tapcell.cell6_3 VGND ) ( tapcell.cell6_2 VGND ) ( tapcell.cell6_1 VGND ) ( tapcell.cell6_0 VGND ) ( tapcell.cell5_8 VGND ) ( tapcell.cell5_7 VGND ) + ( tapcell.cell5_6 VGND ) ( tapcell.cell5_5 VGND ) ( tapcell.cell5_4 VGND ) ( tapcell.cell5_3 VGND ) ( tapcell.cell5_2 VGND ) ( tapcell.cell5_1 VGND ) ( tapcell.cell5_0 VGND ) ( tapcell.cell4_8 VGND ) + ( tapcell.cell4_7 VGND ) ( tapcell.cell4_6 VGND ) ( tapcell.cell4_5 VGND ) ( tapcell.cell4_4 VGND ) ( tapcell.cell4_3 VGND ) ( tapcell.cell4_2 VGND ) ( tapcell.cell4_1 VGND ) ( tapcell.cell4_0 VGND ) + ( tapcell.cell3_8 VGND ) ( tapcell.cell3_7 VGND ) ( tapcell.cell3_6 VGND ) ( tapcell.cell3_5 VGND ) ( tapcell.cell3_4 VGND ) ( tapcell.cell3_3 VGND ) ( tapcell.cell3_2 VGND ) ( tapcell.cell3_1 VGND ) + ( tapcell.cell3_0 VGND ) ( tapcell.cell2_8 VGND ) ( tapcell.cell2_7 VGND ) ( tapcell.cell2_6 VGND ) ( tapcell.cell2_5 VGND ) ( tapcell.cell2_4 VGND ) ( tapcell.cell2_3 VGND ) ( tapcell.cell2_2 VGND ) + ( tapcell.cell2_1 VGND ) ( tapcell.cell2_0 VGND ) ( tapcell.cell1_8 VGND ) ( tapcell.cell1_7 VGND ) ( tapcell.cell1_6 VGND ) ( tapcell.cell1_5 VGND ) ( tapcell.cell1_4 VGND ) ( tapcell.cell1_3 VGND ) + ( tapcell.cell1_2 VGND ) ( tapcell.cell1_1 VGND ) ( tapcell.cell1_0 VGND ) ( tapcell.cell0_8 VGND ) ( tapcell.cell0_7 VGND ) ( tapcell.cell0_6 VGND ) ( tapcell.cell0_5 VGND ) ( tapcell.cell0_4 VGND ) + ( tapcell.cell0_3 VGND ) ( tapcell.cell0_2 VGND ) ( tapcell.cell0_1 VGND ) ( tapcell.cell0_0 VGND ) ( decoder.inv_0 VGND ) ( decoder.inv_1 VGND ) ( decoder.inv_2 VGND ) ( buffer.in[7] VGND ) + ( buffer.in[6] VGND ) ( buffer.in[5] VGND ) ( buffer.in[4] VGND ) ( buffer.in[3] VGND ) ( buffer.in[2] VGND ) ( buffer.in[1] VGND ) ( buffer.in[0] VGND ) ( storage_7_0_0.select_inv_0 VGND ) + ( storage_7_0_0.gcand VGND ) ( storage_7_0_0.cg VGND ) ( storage_7_0_0.bit7.obuf0 VGND ) ( storage_7_0_0.bit7.bit VGND ) ( storage_7_0_0.bit6.obuf0 VGND ) ( storage_7_0_0.bit6.bit VGND ) ( storage_7_0_0.bit5.obuf0 VGND ) ( storage_7_0_0.bit5.bit VGND ) + ( storage_7_0_0.bit4.obuf0 VGND ) ( storage_7_0_0.bit4.bit VGND ) ( storage_7_0_0.bit3.obuf0 VGND ) ( storage_7_0_0.bit3.bit VGND ) ( storage_7_0_0.bit2.obuf0 VGND ) ( storage_7_0_0.bit2.bit VGND ) ( storage_7_0_0.bit1.obuf0 VGND ) ( storage_7_0_0.bit1.bit VGND ) + ( storage_7_0_0.bit0.obuf0 VGND ) ( storage_7_0_0.bit0.bit VGND ) ( storage_6_0_0.select_inv_0 VGND ) ( storage_6_0_0.gcand VGND ) ( storage_6_0_0.cg VGND ) ( storage_6_0_0.bit7.obuf0 VGND ) ( storage_6_0_0.bit7.bit VGND ) ( storage_6_0_0.bit6.obuf0 VGND ) + ( storage_6_0_0.bit6.bit VGND ) ( storage_6_0_0.bit5.obuf0 VGND ) ( storage_6_0_0.bit5.bit VGND ) ( storage_6_0_0.bit4.obuf0 VGND ) ( storage_6_0_0.bit4.bit VGND ) ( storage_6_0_0.bit3.obuf0 VGND ) ( storage_6_0_0.bit3.bit VGND ) ( storage_6_0_0.bit2.obuf0 VGND ) + ( storage_6_0_0.bit2.bit VGND ) ( storage_6_0_0.bit1.obuf0 VGND ) ( storage_6_0_0.bit1.bit VGND ) ( storage_6_0_0.bit0.obuf0 VGND ) ( storage_6_0_0.bit0.bit VGND ) ( storage_5_0_0.select_inv_0 VGND ) ( storage_5_0_0.gcand VGND ) ( storage_5_0_0.cg VGND ) + ( storage_5_0_0.bit7.obuf0 VGND ) ( storage_5_0_0.bit7.bit VGND ) ( storage_5_0_0.bit6.obuf0 VGND ) ( storage_5_0_0.bit6.bit VGND ) ( storage_5_0_0.bit5.obuf0 VGND ) ( storage_5_0_0.bit5.bit VGND ) ( storage_5_0_0.bit4.obuf0 VGND ) ( storage_5_0_0.bit4.bit VGND ) + ( storage_5_0_0.bit3.obuf0 VGND ) ( storage_5_0_0.bit3.bit VGND ) ( storage_5_0_0.bit2.obuf0 VGND ) ( storage_5_0_0.bit2.bit VGND ) ( storage_5_0_0.bit1.obuf0 VGND ) ( storage_5_0_0.bit1.bit VGND ) ( storage_5_0_0.bit0.obuf0 VGND ) ( storage_5_0_0.bit0.bit VGND ) + ( storage_4_0_0.select_inv_0 VGND ) ( storage_4_0_0.gcand VGND ) ( storage_4_0_0.cg VGND ) ( storage_4_0_0.bit7.obuf0 VGND ) ( storage_4_0_0.bit7.bit VGND ) ( storage_4_0_0.bit6.obuf0 VGND ) ( storage_4_0_0.bit6.bit VGND ) ( storage_4_0_0.bit5.obuf0 VGND ) + ( storage_4_0_0.bit5.bit VGND ) ( storage_4_0_0.bit4.obuf0 VGND ) ( storage_4_0_0.bit4.bit VGND ) ( storage_4_0_0.bit3.obuf0 VGND ) ( storage_4_0_0.bit3.bit VGND ) ( storage_4_0_0.bit2.obuf0 VGND ) ( storage_4_0_0.bit2.bit VGND ) ( storage_4_0_0.bit1.obuf0 VGND ) + ( storage_4_0_0.bit1.bit VGND ) ( storage_4_0_0.bit0.obuf0 VGND ) ( storage_4_0_0.bit0.bit VGND ) ( storage_3_0_0.select_inv_0 VGND ) ( storage_3_0_0.gcand VGND ) ( storage_3_0_0.cg VGND ) ( storage_3_0_0.bit7.obuf0 VGND ) ( storage_3_0_0.bit7.bit VGND ) + ( storage_3_0_0.bit6.obuf0 VGND ) ( storage_3_0_0.bit6.bit VGND ) ( storage_3_0_0.bit5.obuf0 VGND ) ( storage_3_0_0.bit5.bit VGND ) ( storage_3_0_0.bit4.obuf0 VGND ) ( storage_3_0_0.bit4.bit VGND ) ( storage_3_0_0.bit3.obuf0 VGND ) ( storage_3_0_0.bit3.bit VGND ) + ( storage_3_0_0.bit2.obuf0 VGND ) ( storage_3_0_0.bit2.bit VGND ) ( storage_3_0_0.bit1.obuf0 VGND ) ( storage_3_0_0.bit1.bit VGND ) ( storage_3_0_0.bit0.obuf0 VGND ) ( storage_3_0_0.bit0.bit VGND ) ( storage_2_0_0.select_inv_0 VGND ) ( storage_2_0_0.gcand VGND ) + ( storage_2_0_0.cg VGND ) ( storage_2_0_0.bit7.obuf0 VGND ) ( storage_2_0_0.bit7.bit VGND ) ( storage_2_0_0.bit6.obuf0 VGND ) ( storage_2_0_0.bit6.bit VGND ) ( storage_2_0_0.bit5.obuf0 VGND ) ( storage_2_0_0.bit5.bit VGND ) ( storage_2_0_0.bit4.obuf0 VGND ) + ( storage_2_0_0.bit4.bit VGND ) ( storage_2_0_0.bit3.obuf0 VGND ) ( storage_2_0_0.bit3.bit VGND ) ( storage_2_0_0.bit2.obuf0 VGND ) ( storage_2_0_0.bit2.bit VGND ) ( storage_2_0_0.bit1.obuf0 VGND ) ( storage_2_0_0.bit1.bit VGND ) ( storage_2_0_0.bit0.obuf0 VGND ) + ( storage_2_0_0.bit0.bit VGND ) ( storage_1_0_0.select_inv_0 VGND ) ( storage_1_0_0.gcand VGND ) ( storage_1_0_0.cg VGND ) ( storage_1_0_0.bit7.obuf0 VGND ) ( storage_1_0_0.bit7.bit VGND ) ( storage_1_0_0.bit6.obuf0 VGND ) ( storage_1_0_0.bit6.bit VGND ) + ( storage_1_0_0.bit5.obuf0 VGND ) ( storage_1_0_0.bit5.bit VGND ) ( storage_1_0_0.bit4.obuf0 VGND ) ( storage_1_0_0.bit4.bit VGND ) ( storage_1_0_0.bit3.obuf0 VGND ) ( storage_1_0_0.bit3.bit VGND ) ( storage_1_0_0.bit2.obuf0 VGND ) ( storage_1_0_0.bit2.bit VGND ) + ( storage_1_0_0.bit1.obuf0 VGND ) ( storage_1_0_0.bit1.bit VGND ) ( storage_1_0_0.bit0.obuf0 VGND ) ( storage_1_0_0.bit0.bit VGND ) ( storage_0_0_0.select_inv_0 VGND ) ( storage_0_0_0.gcand VGND ) ( storage_0_0_0.cg VGND ) ( storage_0_0_0.bit7.obuf0 VGND ) + ( storage_0_0_0.bit7.bit VGND ) ( storage_0_0_0.bit6.obuf0 VGND ) ( storage_0_0_0.bit6.bit VGND ) ( storage_0_0_0.bit5.obuf0 VGND ) ( storage_0_0_0.bit5.bit VGND ) ( storage_0_0_0.bit4.obuf0 VGND ) ( storage_0_0_0.bit4.bit VGND ) ( storage_0_0_0.bit3.obuf0 VGND ) + ( storage_0_0_0.bit3.bit VGND ) ( storage_0_0_0.bit2.obuf0 VGND ) ( storage_0_0_0.bit2.bit VGND ) ( storage_0_0_0.bit1.obuf0 VGND ) ( storage_0_0_0.bit1.bit VGND ) ( storage_0_0_0.bit0.obuf0 VGND ) ( storage_0_0_0.bit0.bit VGND ) ( decoder_7.buf_port0 VGND ) + ( decoder_7.and_layer1 VGND ) ( decoder_7.and_layer0 VGND ) ( decoder_6.buf_port0 VGND ) ( decoder_6.and_layer1 VGND ) ( decoder_6.and_layer0 VGND ) ( decoder_5.buf_port0 VGND ) ( decoder_5.and_layer1 VGND ) ( decoder_5.and_layer0 VGND ) + ( decoder_4.buf_port0 VGND ) ( decoder_4.and_layer1 VGND ) ( decoder_4.and_layer0 VGND ) ( decoder_3.buf_port0 VGND ) ( decoder_3.and_layer1 VGND ) ( decoder_3.and_layer0 VGND ) ( decoder_2.buf_port0 VGND ) ( decoder_2.and_layer1 VGND ) + ( decoder_2.and_layer0 VGND ) ( decoder_1.buf_port0 VGND ) ( decoder_1.and_layer1 VGND ) ( decoder_1.and_layer0 VGND ) ( decoder_0.buf_port0 VGND ) ( decoder_0.and_layer1 VGND ) ( decoder_0.and_layer0 VGND ) + USE GROUND + + ROUTED met3 48 + SHAPE STRIPE ( 0 2000 ) ( 11040 2000 ) + NEW met2 48 + SHAPE STRIPE ( 8000 -24 ) ( 8000 2448 ) + NEW met2 48 + SHAPE STRIPE ( 4000 -24 ) ( 4000 2448 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 2176 ) ( 11040 2176 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1632 ) ( 11040 1632 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1088 ) ( 11040 1088 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 544 ) ( 11040 544 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 0 ) ( 11040 0 ) + NEW met2 0 + SHAPE STRIPE ( 8000 2000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 4000 2000 ) via3_4_480_480_1_1_400_400 + NEW met1 0 + SHAPE STRIPE ( 8000 2176 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8000 1632 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 2176 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 1632 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 0 ) via2_3_480_480_1_1_320_320 ; +END SPECIALNETS +NETS 152 ; + - D[0] ( PIN D[0] ) ( buffer.in[0] A ) + USE SIGNAL + + ROUTED met2 ( 115 2295 ) ( * 2414 0 ) + NEW met1 ( 69 2295 ) ( 115 * ) + NEW met1 ( 115 2295 ) M1M2_PR + NEW li1 ( 69 2295 ) L1M1_PR_MR ; + - D[1] ( PIN D[1] ) ( buffer.in[1] A ) + USE SIGNAL + + ROUTED met2 ( 1219 2295 ) ( * 2414 0 ) + NEW li1 ( 1219 2295 ) L1M1_PR_MR + NEW met1 ( 1219 2295 ) M1M2_PR ; + - D[2] ( PIN D[2] ) ( buffer.in[2] A ) + USE SIGNAL + + ROUTED met2 ( 2415 2295 ) ( * 2414 0 ) + NEW met1 ( 2369 2295 ) ( 2415 * ) + NEW met1 ( 2415 2295 ) M1M2_PR + NEW li1 ( 2369 2295 ) L1M1_PR_MR ; + - D[3] ( PIN D[3] ) ( buffer.in[3] A ) + USE SIGNAL + + ROUTED met2 ( 3519 2295 ) ( * 2414 0 ) + NEW li1 ( 3519 2295 ) L1M1_PR_MR + NEW met1 ( 3519 2295 ) M1M2_PR ; + - D[4] ( PIN D[4] ) ( buffer.in[4] A ) + USE SIGNAL + + ROUTED met2 ( 4715 2295 ) ( * 2414 0 ) + NEW met1 ( 4669 2295 ) ( 4715 * ) + NEW met1 ( 4715 2295 ) M1M2_PR + NEW li1 ( 4669 2295 ) L1M1_PR_MR ; + - D[5] ( PIN D[5] ) ( buffer.in[5] A ) + USE SIGNAL + + ROUTED met2 ( 5819 2295 ) ( * 2414 0 ) + NEW li1 ( 5819 2295 ) L1M1_PR_MR + NEW met1 ( 5819 2295 ) M1M2_PR ; + - D[6] ( PIN D[6] ) ( buffer.in[6] A ) + USE SIGNAL + + ROUTED met2 ( 7015 2295 ) ( * 2414 0 ) + NEW met1 ( 6969 2295 ) ( 7015 * ) + NEW met1 ( 7015 2295 ) M1M2_PR + NEW li1 ( 6969 2295 ) L1M1_PR_MR ; + - D[7] ( PIN D[7] ) ( buffer.in[7] A ) + USE SIGNAL + + ROUTED met2 ( 8119 2295 ) ( * 2414 0 ) + NEW li1 ( 8119 2295 ) L1M1_PR_MR + NEW met1 ( 8119 2295 ) M1M2_PR ; + - D_nets.b0 ( buffer.in[0] X ) ( storage_7_0_0.bit0.bit D ) ( storage_6_0_0.bit0.bit D ) ( storage_5_0_0.bit0.bit D ) ( storage_4_0_0.bit0.bit D ) ( storage_3_0_0.bit0.bit D ) ( storage_2_0_0.bit0.bit D ) + ( storage_1_0_0.bit0.bit D ) ( storage_0_0_0.bit0.bit D ) + USE SIGNAL + + ROUTED met1 ( 202 2057 ) ( 207 * ) + NEW met2 ( 207 2057 ) ( * 2227 ) + NEW met1 ( 161 2227 ) ( 207 * ) + NEW met1 ( 202 1751 ) ( 207 * ) + NEW met2 ( 207 1751 ) ( * 2057 ) + NEW met1 ( 202 1547 ) ( 207 * ) + NEW met2 ( 207 1547 ) ( * 1751 ) + NEW met1 ( 202 1207 ) ( 207 * ) + NEW met2 ( 207 1207 ) ( * 1547 ) + NEW met1 ( 202 1003 ) ( 207 * ) + NEW met2 ( 207 1003 ) ( * 1207 ) + NEW met1 ( 202 663 ) ( 207 * ) + NEW met2 ( 207 663 ) ( * 1003 ) + NEW met1 ( 202 459 ) ( 207 * ) + NEW met2 ( 207 459 ) ( * 663 ) + NEW met1 ( 202 119 ) ( 207 * ) + NEW met2 ( 207 119 ) ( * 459 ) + NEW li1 ( 202 2057 ) L1M1_PR_MR + NEW met1 ( 207 2057 ) M1M2_PR + NEW met1 ( 207 2227 ) M1M2_PR + NEW li1 ( 161 2227 ) L1M1_PR_MR + NEW li1 ( 202 1751 ) L1M1_PR_MR + NEW met1 ( 207 1751 ) M1M2_PR + NEW li1 ( 202 1547 ) L1M1_PR_MR + NEW met1 ( 207 1547 ) M1M2_PR + NEW li1 ( 202 1207 ) L1M1_PR_MR + NEW met1 ( 207 1207 ) M1M2_PR + NEW li1 ( 202 1003 ) L1M1_PR_MR + NEW met1 ( 207 1003 ) M1M2_PR + NEW li1 ( 202 663 ) L1M1_PR_MR + NEW met1 ( 207 663 ) M1M2_PR + NEW li1 ( 202 459 ) L1M1_PR_MR + NEW met1 ( 207 459 ) M1M2_PR + NEW li1 ( 202 119 ) L1M1_PR_MR + NEW met1 ( 207 119 ) M1M2_PR + NEW met1 ( 202 2057 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 1751 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 1547 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 1207 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 663 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 459 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 119 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b1 ( buffer.in[1] X ) ( storage_7_0_0.bit1.bit D ) ( storage_6_0_0.bit1.bit D ) ( storage_5_0_0.bit1.bit D ) ( storage_4_0_0.bit1.bit D ) ( storage_3_0_0.bit1.bit D ) ( storage_2_0_0.bit1.bit D ) + ( storage_1_0_0.bit1.bit D ) ( storage_0_0_0.bit1.bit D ) + USE SIGNAL + + ROUTED met1 ( 1352 2057 ) ( 1357 * ) + NEW met2 ( 1357 2057 ) ( * 2227 ) + NEW met1 ( 1311 2227 ) ( 1357 * ) + NEW met1 ( 1352 1717 ) ( 1357 * ) + NEW met2 ( 1357 1717 ) ( * 2057 ) + NEW met1 ( 1352 1547 ) ( 1357 * ) + NEW met2 ( 1357 1547 ) ( * 1717 ) + NEW met1 ( 1352 1207 ) ( 1357 * ) + NEW met2 ( 1357 1207 ) ( * 1547 ) + NEW met1 ( 1352 1003 ) ( 1357 * ) + NEW met2 ( 1357 1003 ) ( * 1207 ) + NEW met1 ( 1352 663 ) ( 1357 * ) + NEW met2 ( 1357 663 ) ( * 1003 ) + NEW met1 ( 1352 459 ) ( 1357 * ) + NEW met2 ( 1357 459 ) ( * 663 ) + NEW met1 ( 1352 119 ) ( 1357 * ) + NEW met2 ( 1357 119 ) ( * 459 ) + NEW li1 ( 1352 2057 ) L1M1_PR_MR + NEW met1 ( 1357 2057 ) M1M2_PR + NEW met1 ( 1357 2227 ) M1M2_PR + NEW li1 ( 1311 2227 ) L1M1_PR_MR + NEW li1 ( 1352 1717 ) L1M1_PR_MR + NEW met1 ( 1357 1717 ) M1M2_PR + NEW li1 ( 1352 1547 ) L1M1_PR_MR + NEW met1 ( 1357 1547 ) M1M2_PR + NEW li1 ( 1352 1207 ) L1M1_PR_MR + NEW met1 ( 1357 1207 ) M1M2_PR + NEW li1 ( 1352 1003 ) L1M1_PR_MR + NEW met1 ( 1357 1003 ) M1M2_PR + NEW li1 ( 1352 663 ) L1M1_PR_MR + NEW met1 ( 1357 663 ) M1M2_PR + NEW li1 ( 1352 459 ) L1M1_PR_MR + NEW met1 ( 1357 459 ) M1M2_PR + NEW li1 ( 1352 119 ) L1M1_PR_MR + NEW met1 ( 1357 119 ) M1M2_PR + NEW met1 ( 1352 2057 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 1717 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 1547 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 1207 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 663 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 459 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 119 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b2 ( buffer.in[2] X ) ( storage_7_0_0.bit2.bit D ) ( storage_6_0_0.bit2.bit D ) ( storage_5_0_0.bit2.bit D ) ( storage_4_0_0.bit2.bit D ) ( storage_3_0_0.bit2.bit D ) ( storage_2_0_0.bit2.bit D ) + ( storage_1_0_0.bit2.bit D ) ( storage_0_0_0.bit2.bit D ) + USE SIGNAL + + ROUTED met1 ( 2502 1207 ) ( 2507 * ) + NEW met1 ( 2502 1003 ) ( 2507 * ) + NEW met2 ( 2507 1003 ) ( * 1207 ) + NEW met1 ( 2502 629 ) ( 2507 * ) + NEW met2 ( 2507 629 ) ( * 1003 ) + NEW met1 ( 2502 459 ) ( 2507 * ) + NEW met2 ( 2507 459 ) ( * 629 ) + NEW met1 ( 2502 119 ) ( 2507 * ) + NEW met2 ( 2507 119 ) ( * 459 ) + NEW met1 ( 2502 2057 ) ( 2507 * ) + NEW met2 ( 2507 2057 ) ( * 2227 ) + NEW met1 ( 2461 2227 ) ( 2507 * ) + NEW met1 ( 2502 1751 ) ( 2507 * ) + NEW met2 ( 2507 1751 ) ( * 2057 ) + NEW met1 ( 2502 1547 ) ( 2507 * ) + NEW met2 ( 2507 1547 ) ( * 1751 ) + NEW met2 ( 2507 1207 ) ( * 1547 ) + NEW li1 ( 2502 1207 ) L1M1_PR_MR + NEW met1 ( 2507 1207 ) M1M2_PR + NEW li1 ( 2502 1003 ) L1M1_PR_MR + NEW met1 ( 2507 1003 ) M1M2_PR + NEW li1 ( 2502 629 ) L1M1_PR_MR + NEW met1 ( 2507 629 ) M1M2_PR + NEW li1 ( 2502 459 ) L1M1_PR_MR + NEW met1 ( 2507 459 ) M1M2_PR + NEW li1 ( 2502 119 ) L1M1_PR_MR + NEW met1 ( 2507 119 ) M1M2_PR + NEW li1 ( 2502 2057 ) L1M1_PR_MR + NEW met1 ( 2507 2057 ) M1M2_PR + NEW met1 ( 2507 2227 ) M1M2_PR + NEW li1 ( 2461 2227 ) L1M1_PR_MR + NEW li1 ( 2502 1751 ) L1M1_PR_MR + NEW met1 ( 2507 1751 ) M1M2_PR + NEW li1 ( 2502 1547 ) L1M1_PR_MR + NEW met1 ( 2507 1547 ) M1M2_PR + NEW met1 ( 2502 1207 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 2502 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 2507 629 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 2502 459 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 2502 119 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 2502 2057 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 2502 1751 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 2502 1547 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b3 ( buffer.in[3] X ) ( storage_7_0_0.bit3.bit D ) ( storage_6_0_0.bit3.bit D ) ( storage_5_0_0.bit3.bit D ) ( storage_4_0_0.bit3.bit D ) ( storage_3_0_0.bit3.bit D ) ( storage_2_0_0.bit3.bit D ) + ( storage_1_0_0.bit3.bit D ) ( storage_0_0_0.bit3.bit D ) + USE SIGNAL + + ROUTED met1 ( 3652 1207 ) ( 3657 * ) + NEW met1 ( 3652 1003 ) ( 3657 * ) + NEW met2 ( 3657 1003 ) ( * 1207 ) + NEW met1 ( 3652 629 ) ( 3657 * ) + NEW met2 ( 3657 629 ) ( * 1003 ) + NEW met1 ( 3652 459 ) ( 3657 * ) + NEW met2 ( 3657 459 ) ( * 629 ) + NEW met1 ( 3652 119 ) ( 3657 * ) + NEW met2 ( 3657 119 ) ( * 459 ) + NEW met1 ( 3652 2057 ) ( 3657 * ) + NEW met2 ( 3657 2057 ) ( * 2227 ) + NEW met1 ( 3611 2227 ) ( 3657 * ) + NEW met1 ( 3652 1751 ) ( 3657 * ) + NEW met2 ( 3657 1751 ) ( * 2057 ) + NEW met1 ( 3652 1547 ) ( 3657 * ) + NEW met2 ( 3657 1547 ) ( * 1751 ) + NEW met2 ( 3657 1207 ) ( * 1547 ) + NEW li1 ( 3652 1207 ) L1M1_PR_MR + NEW met1 ( 3657 1207 ) M1M2_PR + NEW li1 ( 3652 1003 ) L1M1_PR_MR + NEW met1 ( 3657 1003 ) M1M2_PR + NEW li1 ( 3652 629 ) L1M1_PR_MR + NEW met1 ( 3657 629 ) M1M2_PR + NEW li1 ( 3652 459 ) L1M1_PR_MR + NEW met1 ( 3657 459 ) M1M2_PR + NEW li1 ( 3652 119 ) L1M1_PR_MR + NEW met1 ( 3657 119 ) M1M2_PR + NEW li1 ( 3652 2057 ) L1M1_PR_MR + NEW met1 ( 3657 2057 ) M1M2_PR + NEW met1 ( 3657 2227 ) M1M2_PR + NEW li1 ( 3611 2227 ) L1M1_PR_MR + NEW li1 ( 3652 1751 ) L1M1_PR_MR + NEW met1 ( 3657 1751 ) M1M2_PR + NEW li1 ( 3652 1547 ) L1M1_PR_MR + NEW met1 ( 3657 1547 ) M1M2_PR + NEW met1 ( 3652 1207 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 3652 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 3657 629 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 3652 459 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 3652 119 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 3652 2057 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 3652 1751 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 3652 1547 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b4 ( buffer.in[4] X ) ( storage_7_0_0.bit4.bit D ) ( storage_6_0_0.bit4.bit D ) ( storage_5_0_0.bit4.bit D ) ( storage_4_0_0.bit4.bit D ) ( storage_3_0_0.bit4.bit D ) ( storage_2_0_0.bit4.bit D ) + ( storage_1_0_0.bit4.bit D ) ( storage_0_0_0.bit4.bit D ) + USE SIGNAL + + ROUTED met1 ( 4802 1207 ) ( 4807 * ) + NEW met1 ( 4802 1003 ) ( 4807 * ) + NEW met2 ( 4807 1003 ) ( * 1207 ) + NEW met1 ( 4802 629 ) ( 4807 * ) + NEW met2 ( 4807 629 ) ( * 1003 ) + NEW met1 ( 4802 459 ) ( 4807 * ) + NEW met2 ( 4807 459 ) ( * 629 ) + NEW met1 ( 4802 119 ) ( 4807 * ) + NEW met2 ( 4807 119 ) ( * 459 ) + NEW met1 ( 4802 2057 ) ( 4807 * ) + NEW met2 ( 4807 2057 ) ( * 2227 ) + NEW met1 ( 4761 2227 ) ( 4807 * ) + NEW met1 ( 4802 1751 ) ( 4807 * ) + NEW met2 ( 4807 1751 ) ( * 2057 ) + NEW met1 ( 4802 1547 ) ( 4807 * ) + NEW met2 ( 4807 1547 ) ( * 1751 ) + NEW met2 ( 4807 1207 ) ( * 1547 ) + NEW li1 ( 4802 1207 ) L1M1_PR_MR + NEW met1 ( 4807 1207 ) M1M2_PR + NEW li1 ( 4802 1003 ) L1M1_PR_MR + NEW met1 ( 4807 1003 ) M1M2_PR + NEW li1 ( 4802 629 ) L1M1_PR_MR + NEW met1 ( 4807 629 ) M1M2_PR + NEW li1 ( 4802 459 ) L1M1_PR_MR + NEW met1 ( 4807 459 ) M1M2_PR + NEW li1 ( 4802 119 ) L1M1_PR_MR + NEW met1 ( 4807 119 ) M1M2_PR + NEW li1 ( 4802 2057 ) L1M1_PR_MR + NEW met1 ( 4807 2057 ) M1M2_PR + NEW met1 ( 4807 2227 ) M1M2_PR + NEW li1 ( 4761 2227 ) L1M1_PR_MR + NEW li1 ( 4802 1751 ) L1M1_PR_MR + NEW met1 ( 4807 1751 ) M1M2_PR + NEW li1 ( 4802 1547 ) L1M1_PR_MR + NEW met1 ( 4807 1547 ) M1M2_PR + NEW met1 ( 4802 1207 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 4802 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 4807 629 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 4802 459 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 4802 119 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 4802 2057 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 4802 1751 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 4802 1547 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b5 ( buffer.in[5] X ) ( storage_7_0_0.bit5.bit D ) ( storage_6_0_0.bit5.bit D ) ( storage_5_0_0.bit5.bit D ) ( storage_4_0_0.bit5.bit D ) ( storage_3_0_0.bit5.bit D ) ( storage_2_0_0.bit5.bit D ) + ( storage_1_0_0.bit5.bit D ) ( storage_0_0_0.bit5.bit D ) + USE SIGNAL + + ROUTED met1 ( 5865 1207 ) ( 5947 * ) + NEW met1 ( 5865 1003 ) ( 5941 * ) + NEW met2 ( 5865 1003 ) ( * 1207 ) + NEW met1 ( 5865 663 ) ( 5947 * ) + NEW met2 ( 5865 663 ) ( * 1003 ) + NEW met1 ( 5865 459 ) ( 5941 * ) + NEW met2 ( 5865 459 ) ( * 663 ) + NEW met1 ( 5865 119 ) ( 5947 * ) + NEW met2 ( 5865 119 ) ( * 459 ) + NEW met1 ( 5865 1513 ) ( 5947 * ) + NEW met1 ( 5865 1717 ) ( 5941 * ) + NEW met2 ( 5865 1513 ) ( * 1717 ) + NEW met1 ( 5865 2057 ) ( 5947 * ) + NEW met2 ( 5865 1717 ) ( * 2057 ) + NEW met1 ( 5865 2227 ) ( 5911 * ) + NEW met2 ( 5865 2057 ) ( * 2227 ) + NEW met2 ( 5865 1207 ) ( * 1513 ) + NEW li1 ( 5947 1207 ) L1M1_PR_MR + NEW met1 ( 5865 1207 ) M1M2_PR + NEW li1 ( 5941 1003 ) L1M1_PR_MR + NEW met1 ( 5865 1003 ) M1M2_PR + NEW li1 ( 5947 663 ) L1M1_PR_MR + NEW met1 ( 5865 663 ) M1M2_PR + NEW li1 ( 5941 459 ) L1M1_PR_MR + NEW met1 ( 5865 459 ) M1M2_PR + NEW li1 ( 5947 119 ) L1M1_PR_MR + NEW met1 ( 5865 119 ) M1M2_PR + NEW li1 ( 5947 1513 ) L1M1_PR_MR + NEW met1 ( 5865 1513 ) M1M2_PR + NEW li1 ( 5941 1717 ) L1M1_PR_MR + NEW met1 ( 5865 1717 ) M1M2_PR + NEW li1 ( 5947 2057 ) L1M1_PR_MR + NEW met1 ( 5865 2057 ) M1M2_PR + NEW li1 ( 5911 2227 ) L1M1_PR_MR + NEW met1 ( 5865 2227 ) M1M2_PR ; + - D_nets.b6 ( buffer.in[6] X ) ( storage_7_0_0.bit6.bit D ) ( storage_6_0_0.bit6.bit D ) ( storage_5_0_0.bit6.bit D ) ( storage_4_0_0.bit6.bit D ) ( storage_3_0_0.bit6.bit D ) ( storage_2_0_0.bit6.bit D ) + ( storage_1_0_0.bit6.bit D ) ( storage_0_0_0.bit6.bit D ) + USE SIGNAL + + ROUTED met1 ( 7102 1207 ) ( 7107 * ) + NEW met1 ( 7102 1003 ) ( 7107 * ) + NEW met2 ( 7107 1003 ) ( * 1207 ) + NEW met1 ( 7102 663 ) ( 7107 * ) + NEW met2 ( 7107 663 ) ( * 1003 ) + NEW met1 ( 7102 459 ) ( 7107 * ) + NEW met2 ( 7107 459 ) ( * 663 ) + NEW met1 ( 7102 119 ) ( 7107 * ) + NEW met2 ( 7107 119 ) ( * 459 ) + NEW met1 ( 7102 2057 ) ( 7107 * ) + NEW met2 ( 7107 2057 ) ( * 2227 ) + NEW met1 ( 7061 2227 ) ( 7107 * ) + NEW met1 ( 7102 1751 ) ( 7107 * ) + NEW met2 ( 7107 1751 ) ( * 2057 ) + NEW met1 ( 7102 1547 ) ( 7107 * ) + NEW met2 ( 7107 1547 ) ( * 1751 ) + NEW met2 ( 7107 1207 ) ( * 1547 ) + NEW li1 ( 7102 1207 ) L1M1_PR_MR + NEW met1 ( 7107 1207 ) M1M2_PR + NEW li1 ( 7102 1003 ) L1M1_PR_MR + NEW met1 ( 7107 1003 ) M1M2_PR + NEW li1 ( 7102 663 ) L1M1_PR_MR + NEW met1 ( 7107 663 ) M1M2_PR + NEW li1 ( 7102 459 ) L1M1_PR_MR + NEW met1 ( 7107 459 ) M1M2_PR + NEW li1 ( 7102 119 ) L1M1_PR_MR + NEW met1 ( 7107 119 ) M1M2_PR + NEW li1 ( 7102 2057 ) L1M1_PR_MR + NEW met1 ( 7107 2057 ) M1M2_PR + NEW met1 ( 7107 2227 ) M1M2_PR + NEW li1 ( 7061 2227 ) L1M1_PR_MR + NEW li1 ( 7102 1751 ) L1M1_PR_MR + NEW met1 ( 7107 1751 ) M1M2_PR + NEW li1 ( 7102 1547 ) L1M1_PR_MR + NEW met1 ( 7107 1547 ) M1M2_PR + NEW met1 ( 7102 1207 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 663 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 459 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 119 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 2057 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 1751 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 1547 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b7 ( buffer.in[7] X ) ( storage_7_0_0.bit7.bit D ) ( storage_6_0_0.bit7.bit D ) ( storage_5_0_0.bit7.bit D ) ( storage_4_0_0.bit7.bit D ) ( storage_3_0_0.bit7.bit D ) ( storage_2_0_0.bit7.bit D ) + ( storage_1_0_0.bit7.bit D ) ( storage_0_0_0.bit7.bit D ) + USE SIGNAL + + ROUTED met1 ( 8252 2057 ) ( 8257 * ) + NEW met2 ( 8257 2057 ) ( * 2227 ) + NEW met1 ( 8211 2227 ) ( 8257 * ) + NEW met1 ( 8252 1751 ) ( 8257 * ) + NEW met2 ( 8257 1751 ) ( * 2057 ) + NEW met1 ( 8252 1547 ) ( 8257 * ) + NEW met2 ( 8257 1547 ) ( * 1751 ) + NEW met1 ( 8252 1207 ) ( 8257 * ) + NEW met2 ( 8257 1207 ) ( * 1547 ) + NEW met1 ( 8252 1003 ) ( 8257 * ) + NEW met2 ( 8257 1003 ) ( * 1207 ) + NEW met1 ( 8252 663 ) ( 8257 * ) + NEW met2 ( 8257 663 ) ( * 1003 ) + NEW met1 ( 8252 459 ) ( 8257 * ) + NEW met2 ( 8257 459 ) ( * 663 ) + NEW met1 ( 8252 119 ) ( 8257 * ) + NEW met2 ( 8257 119 ) ( * 459 ) + NEW li1 ( 8252 2057 ) L1M1_PR_MR + NEW met1 ( 8257 2057 ) M1M2_PR + NEW met1 ( 8257 2227 ) M1M2_PR + NEW li1 ( 8211 2227 ) L1M1_PR_MR + NEW li1 ( 8252 1751 ) L1M1_PR_MR + NEW met1 ( 8257 1751 ) M1M2_PR + NEW li1 ( 8252 1547 ) L1M1_PR_MR + NEW met1 ( 8257 1547 ) M1M2_PR + NEW li1 ( 8252 1207 ) L1M1_PR_MR + NEW met1 ( 8257 1207 ) M1M2_PR + NEW li1 ( 8252 1003 ) L1M1_PR_MR + NEW met1 ( 8257 1003 ) M1M2_PR + NEW li1 ( 8252 663 ) L1M1_PR_MR + NEW met1 ( 8257 663 ) M1M2_PR + NEW li1 ( 8252 459 ) L1M1_PR_MR + NEW met1 ( 8257 459 ) M1M2_PR + NEW li1 ( 8252 119 ) L1M1_PR_MR + NEW met1 ( 8257 119 ) M1M2_PR + NEW met1 ( 8252 2057 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 8252 1751 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 8252 1547 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 8252 1207 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 8252 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 8252 663 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 8252 459 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 8252 119 ) RECT ( -31 -7 0 7 ) ; + - Q[0] ( PIN Q[0] ) ( storage_7_0_0.bit0.obuf0 Z ) ( storage_6_0_0.bit0.obuf0 Z ) ( storage_5_0_0.bit0.obuf0 Z ) ( storage_4_0_0.bit0.obuf0 Z ) ( storage_3_0_0.bit0.obuf0 Z ) ( storage_2_0_0.bit0.obuf0 Z ) + ( storage_1_0_0.bit0.obuf0 Z ) ( storage_0_0_0.bit0.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 1127 2125 ) ( * 2414 0 ) + NEW met2 ( 1127 1853 ) ( * 2125 ) + NEW met2 ( 1127 1581 ) ( * 1853 ) + NEW met2 ( 1127 1309 ) ( * 1581 ) + NEW met2 ( 1127 1037 ) ( * 1309 ) + NEW met2 ( 1127 765 ) ( * 1037 ) + NEW met2 ( 1127 493 ) ( * 765 ) + NEW met2 ( 1127 221 ) ( * 493 ) + NEW li1 ( 1127 2125 ) L1M1_PR_MR + NEW met1 ( 1127 2125 ) M1M2_PR + NEW li1 ( 1127 1853 ) L1M1_PR_MR + NEW met1 ( 1127 1853 ) M1M2_PR + NEW li1 ( 1127 1581 ) L1M1_PR_MR + NEW met1 ( 1127 1581 ) M1M2_PR + NEW li1 ( 1127 1309 ) L1M1_PR_MR + NEW met1 ( 1127 1309 ) M1M2_PR + NEW li1 ( 1127 1037 ) L1M1_PR_MR + NEW met1 ( 1127 1037 ) M1M2_PR + NEW li1 ( 1127 765 ) L1M1_PR_MR + NEW met1 ( 1127 765 ) M1M2_PR + NEW li1 ( 1127 493 ) L1M1_PR_MR + NEW met1 ( 1127 493 ) M1M2_PR + NEW li1 ( 1127 221 ) L1M1_PR_MR + NEW met1 ( 1127 221 ) M1M2_PR ; + - Q[1] ( PIN Q[1] ) ( storage_7_0_0.bit1.obuf0 Z ) ( storage_6_0_0.bit1.obuf0 Z ) ( storage_5_0_0.bit1.obuf0 Z ) ( storage_4_0_0.bit1.obuf0 Z ) ( storage_3_0_0.bit1.obuf0 Z ) ( storage_2_0_0.bit1.obuf0 Z ) + ( storage_1_0_0.bit1.obuf0 Z ) ( storage_0_0_0.bit1.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 2231 1037 ) ( 2277 * ) + NEW met2 ( 2231 1037 ) ( * 1309 ) + NEW met2 ( 2231 765 ) ( * 1037 ) + NEW met1 ( 2231 493 ) ( 2277 * ) + NEW met2 ( 2231 493 ) ( * 765 ) + NEW met2 ( 2231 221 ) ( * 493 ) + NEW met1 ( 2231 2125 ) ( 2277 * ) + NEW met2 ( 2231 2125 ) ( * 2414 0 ) + NEW met2 ( 2231 1853 ) ( * 2125 ) + NEW met1 ( 2231 1581 ) ( 2277 * ) + NEW met2 ( 2231 1581 ) ( * 1853 ) + NEW met2 ( 2231 1309 ) ( * 1581 ) + NEW li1 ( 2231 1309 ) L1M1_PR_MR + NEW met1 ( 2231 1309 ) M1M2_PR + NEW li1 ( 2277 1037 ) L1M1_PR_MR + NEW met1 ( 2231 1037 ) M1M2_PR + NEW li1 ( 2231 765 ) L1M1_PR_MR + NEW met1 ( 2231 765 ) M1M2_PR + NEW li1 ( 2277 493 ) L1M1_PR_MR + NEW met1 ( 2231 493 ) M1M2_PR + NEW li1 ( 2231 221 ) L1M1_PR_MR + NEW met1 ( 2231 221 ) M1M2_PR + NEW li1 ( 2277 2125 ) L1M1_PR_MR + NEW met1 ( 2231 2125 ) M1M2_PR + NEW li1 ( 2231 1853 ) L1M1_PR_MR + NEW met1 ( 2231 1853 ) M1M2_PR + NEW li1 ( 2277 1581 ) L1M1_PR_MR + NEW met1 ( 2231 1581 ) M1M2_PR ; + - Q[2] ( PIN Q[2] ) ( storage_7_0_0.bit2.obuf0 Z ) ( storage_6_0_0.bit2.obuf0 Z ) ( storage_5_0_0.bit2.obuf0 Z ) ( storage_4_0_0.bit2.obuf0 Z ) ( storage_3_0_0.bit2.obuf0 Z ) ( storage_2_0_0.bit2.obuf0 Z ) + ( storage_1_0_0.bit2.obuf0 Z ) ( storage_0_0_0.bit2.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 3427 1037 ) ( * 1309 ) + NEW met2 ( 3427 765 ) ( * 1037 ) + NEW met2 ( 3427 493 ) ( * 765 ) + NEW met2 ( 3427 221 ) ( * 493 ) + NEW met2 ( 3427 2125 ) ( * 2414 0 ) + NEW met2 ( 3427 1853 ) ( * 2125 ) + NEW met2 ( 3427 1581 ) ( * 1853 ) + NEW met2 ( 3427 1309 ) ( * 1581 ) + NEW li1 ( 3427 1309 ) L1M1_PR_MR + NEW met1 ( 3427 1309 ) M1M2_PR + NEW li1 ( 3427 1037 ) L1M1_PR_MR + NEW met1 ( 3427 1037 ) M1M2_PR + NEW li1 ( 3427 765 ) L1M1_PR_MR + NEW met1 ( 3427 765 ) M1M2_PR + NEW li1 ( 3427 493 ) L1M1_PR_MR + NEW met1 ( 3427 493 ) M1M2_PR + NEW li1 ( 3427 221 ) L1M1_PR_MR + NEW met1 ( 3427 221 ) M1M2_PR + NEW li1 ( 3427 2125 ) L1M1_PR_MR + NEW met1 ( 3427 2125 ) M1M2_PR + NEW li1 ( 3427 1853 ) L1M1_PR_MR + NEW met1 ( 3427 1853 ) M1M2_PR + NEW li1 ( 3427 1581 ) L1M1_PR_MR + NEW met1 ( 3427 1581 ) M1M2_PR ; + - Q[3] ( PIN Q[3] ) ( storage_7_0_0.bit3.obuf0 Z ) ( storage_6_0_0.bit3.obuf0 Z ) ( storage_5_0_0.bit3.obuf0 Z ) ( storage_4_0_0.bit3.obuf0 Z ) ( storage_3_0_0.bit3.obuf0 Z ) ( storage_2_0_0.bit3.obuf0 Z ) + ( storage_1_0_0.bit3.obuf0 Z ) ( storage_0_0_0.bit3.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 4531 1037 ) ( 4577 * ) + NEW met2 ( 4531 1037 ) ( * 1309 ) + NEW met2 ( 4531 765 ) ( * 1037 ) + NEW met1 ( 4531 493 ) ( 4577 * ) + NEW met2 ( 4531 493 ) ( * 765 ) + NEW met2 ( 4531 221 ) ( * 493 ) + NEW met1 ( 4531 2125 ) ( 4577 * ) + NEW met2 ( 4531 2125 ) ( * 2414 0 ) + NEW met2 ( 4531 1853 ) ( * 2125 ) + NEW met1 ( 4531 1581 ) ( 4577 * ) + NEW met2 ( 4531 1581 ) ( * 1853 ) + NEW met2 ( 4531 1309 ) ( * 1581 ) + NEW li1 ( 4531 1309 ) L1M1_PR_MR + NEW met1 ( 4531 1309 ) M1M2_PR + NEW li1 ( 4577 1037 ) L1M1_PR_MR + NEW met1 ( 4531 1037 ) M1M2_PR + NEW li1 ( 4531 765 ) L1M1_PR_MR + NEW met1 ( 4531 765 ) M1M2_PR + NEW li1 ( 4577 493 ) L1M1_PR_MR + NEW met1 ( 4531 493 ) M1M2_PR + NEW li1 ( 4531 221 ) L1M1_PR_MR + NEW met1 ( 4531 221 ) M1M2_PR + NEW li1 ( 4577 2125 ) L1M1_PR_MR + NEW met1 ( 4531 2125 ) M1M2_PR + NEW li1 ( 4531 1853 ) L1M1_PR_MR + NEW met1 ( 4531 1853 ) M1M2_PR + NEW li1 ( 4577 1581 ) L1M1_PR_MR + NEW met1 ( 4531 1581 ) M1M2_PR ; + - Q[4] ( PIN Q[4] ) ( storage_7_0_0.bit4.obuf0 Z ) ( storage_6_0_0.bit4.obuf0 Z ) ( storage_5_0_0.bit4.obuf0 Z ) ( storage_4_0_0.bit4.obuf0 Z ) ( storage_3_0_0.bit4.obuf0 Z ) ( storage_2_0_0.bit4.obuf0 Z ) + ( storage_1_0_0.bit4.obuf0 Z ) ( storage_0_0_0.bit4.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 5727 1037 ) ( * 1309 ) + NEW met2 ( 5727 765 ) ( * 1037 ) + NEW met2 ( 5727 493 ) ( * 765 ) + NEW met2 ( 5727 221 ) ( * 493 ) + NEW met2 ( 5727 2125 ) ( * 2414 0 ) + NEW met2 ( 5727 1853 ) ( * 2125 ) + NEW met2 ( 5727 1581 ) ( * 1853 ) + NEW met2 ( 5727 1309 ) ( * 1581 ) + NEW li1 ( 5727 1309 ) L1M1_PR_MR + NEW met1 ( 5727 1309 ) M1M2_PR + NEW li1 ( 5727 1037 ) L1M1_PR_MR + NEW met1 ( 5727 1037 ) M1M2_PR + NEW li1 ( 5727 765 ) L1M1_PR_MR + NEW met1 ( 5727 765 ) M1M2_PR + NEW li1 ( 5727 493 ) L1M1_PR_MR + NEW met1 ( 5727 493 ) M1M2_PR + NEW li1 ( 5727 221 ) L1M1_PR_MR + NEW met1 ( 5727 221 ) M1M2_PR + NEW li1 ( 5727 2125 ) L1M1_PR_MR + NEW met1 ( 5727 2125 ) M1M2_PR + NEW li1 ( 5727 1853 ) L1M1_PR_MR + NEW met1 ( 5727 1853 ) M1M2_PR + NEW li1 ( 5727 1581 ) L1M1_PR_MR + NEW met1 ( 5727 1581 ) M1M2_PR ; + - Q[5] ( PIN Q[5] ) ( storage_7_0_0.bit5.obuf0 Z ) ( storage_6_0_0.bit5.obuf0 Z ) ( storage_5_0_0.bit5.obuf0 Z ) ( storage_4_0_0.bit5.obuf0 Z ) ( storage_3_0_0.bit5.obuf0 Z ) ( storage_2_0_0.bit5.obuf0 Z ) + ( storage_1_0_0.bit5.obuf0 Z ) ( storage_0_0_0.bit5.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 6831 1037 ) ( 6877 * ) + NEW met2 ( 6831 1037 ) ( * 1309 ) + NEW met2 ( 6831 765 ) ( * 1037 ) + NEW met1 ( 6831 493 ) ( 6877 * ) + NEW met2 ( 6831 493 ) ( * 765 ) + NEW met2 ( 6831 221 ) ( * 493 ) + NEW met1 ( 6831 2125 ) ( 6877 * ) + NEW met2 ( 6831 2125 ) ( * 2414 0 ) + NEW met2 ( 6831 1853 ) ( * 2125 ) + NEW met1 ( 6831 1581 ) ( 6877 * ) + NEW met2 ( 6831 1581 ) ( * 1853 ) + NEW met2 ( 6831 1309 ) ( * 1581 ) + NEW li1 ( 6831 1309 ) L1M1_PR_MR + NEW met1 ( 6831 1309 ) M1M2_PR + NEW li1 ( 6877 1037 ) L1M1_PR_MR + NEW met1 ( 6831 1037 ) M1M2_PR + NEW li1 ( 6831 765 ) L1M1_PR_MR + NEW met1 ( 6831 765 ) M1M2_PR + NEW li1 ( 6877 493 ) L1M1_PR_MR + NEW met1 ( 6831 493 ) M1M2_PR + NEW li1 ( 6831 221 ) L1M1_PR_MR + NEW met1 ( 6831 221 ) M1M2_PR + NEW li1 ( 6877 2125 ) L1M1_PR_MR + NEW met1 ( 6831 2125 ) M1M2_PR + NEW li1 ( 6831 1853 ) L1M1_PR_MR + NEW met1 ( 6831 1853 ) M1M2_PR + NEW li1 ( 6877 1581 ) L1M1_PR_MR + NEW met1 ( 6831 1581 ) M1M2_PR ; + - Q[6] ( PIN Q[6] ) ( storage_7_0_0.bit6.obuf0 Z ) ( storage_6_0_0.bit6.obuf0 Z ) ( storage_5_0_0.bit6.obuf0 Z ) ( storage_4_0_0.bit6.obuf0 Z ) ( storage_3_0_0.bit6.obuf0 Z ) ( storage_2_0_0.bit6.obuf0 Z ) + ( storage_1_0_0.bit6.obuf0 Z ) ( storage_0_0_0.bit6.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 8027 2125 ) ( 8073 * ) + NEW met2 ( 8073 2125 ) ( * 2414 ) + NEW met2 ( 8027 2414 0 ) ( 8073 * ) + NEW met1 ( 8027 1853 ) ( 8073 * ) + NEW met2 ( 8073 1853 ) ( * 2125 ) + NEW met1 ( 8027 1581 ) ( 8073 * ) + NEW met2 ( 8073 1581 ) ( * 1853 ) + NEW met1 ( 8027 1309 ) ( 8073 * ) + NEW met2 ( 8073 1309 ) ( * 1581 ) + NEW met1 ( 8027 1037 ) ( 8073 * ) + NEW met2 ( 8073 1037 ) ( * 1309 ) + NEW met1 ( 8027 765 ) ( 8073 * ) + NEW met2 ( 8073 765 ) ( * 1037 ) + NEW met1 ( 8027 493 ) ( 8073 * ) + NEW met2 ( 8073 493 ) ( * 765 ) + NEW met1 ( 8027 221 ) ( 8073 * ) + NEW met2 ( 8073 221 ) ( * 493 ) + NEW li1 ( 8027 2125 ) L1M1_PR_MR + NEW met1 ( 8073 2125 ) M1M2_PR + NEW li1 ( 8027 1853 ) L1M1_PR_MR + NEW met1 ( 8073 1853 ) M1M2_PR + NEW li1 ( 8027 1581 ) L1M1_PR_MR + NEW met1 ( 8073 1581 ) M1M2_PR + NEW li1 ( 8027 1309 ) L1M1_PR_MR + NEW met1 ( 8073 1309 ) M1M2_PR + NEW li1 ( 8027 1037 ) L1M1_PR_MR + NEW met1 ( 8073 1037 ) M1M2_PR + NEW li1 ( 8027 765 ) L1M1_PR_MR + NEW met1 ( 8073 765 ) M1M2_PR + NEW li1 ( 8027 493 ) L1M1_PR_MR + NEW met1 ( 8073 493 ) M1M2_PR + NEW li1 ( 8027 221 ) L1M1_PR_MR + NEW met1 ( 8073 221 ) M1M2_PR ; + - Q[7] ( PIN Q[7] ) ( storage_7_0_0.bit7.obuf0 Z ) ( storage_6_0_0.bit7.obuf0 Z ) ( storage_5_0_0.bit7.obuf0 Z ) ( storage_4_0_0.bit7.obuf0 Z ) ( storage_3_0_0.bit7.obuf0 Z ) ( storage_2_0_0.bit7.obuf0 Z ) + ( storage_1_0_0.bit7.obuf0 Z ) ( storage_0_0_0.bit7.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 9131 2125 ) ( 9177 * ) + NEW met2 ( 9131 2125 ) ( * 2414 0 ) + NEW met2 ( 9131 1853 ) ( * 2125 ) + NEW met1 ( 9131 1581 ) ( 9177 * ) + NEW met2 ( 9131 1581 ) ( * 1853 ) + NEW met2 ( 9131 1309 ) ( * 1581 ) + NEW met1 ( 9131 1037 ) ( 9177 * ) + NEW met2 ( 9131 1037 ) ( * 1309 ) + NEW met2 ( 9131 765 ) ( * 1037 ) + NEW met1 ( 9131 493 ) ( 9177 * ) + NEW met2 ( 9131 493 ) ( * 765 ) + NEW met2 ( 9131 221 ) ( * 493 ) + NEW li1 ( 9177 2125 ) L1M1_PR_MR + NEW met1 ( 9131 2125 ) M1M2_PR + NEW li1 ( 9131 1853 ) L1M1_PR_MR + NEW met1 ( 9131 1853 ) M1M2_PR + NEW li1 ( 9177 1581 ) L1M1_PR_MR + NEW met1 ( 9131 1581 ) M1M2_PR + NEW li1 ( 9131 1309 ) L1M1_PR_MR + NEW met1 ( 9131 1309 ) M1M2_PR + NEW li1 ( 9177 1037 ) L1M1_PR_MR + NEW met1 ( 9131 1037 ) M1M2_PR + NEW li1 ( 9131 765 ) L1M1_PR_MR + NEW met1 ( 9131 765 ) M1M2_PR + NEW li1 ( 9177 493 ) L1M1_PR_MR + NEW met1 ( 9131 493 ) M1M2_PR + NEW li1 ( 9131 221 ) L1M1_PR_MR + NEW met1 ( 9131 221 ) M1M2_PR ; + - addr_rw[0] ( PIN addr_rw[0] ) ( decoder.inv_0 A ) ( decoder_7.and_layer0 A ) ( decoder_5.and_layer0 A ) ( decoder_3.and_layer0 A ) ( decoder_1.and_layer0 A ) + USE SIGNAL + + ROUTED met1 ( 10327 391 ) ( 10373 * ) + NEW met2 ( 10373 391 ) ( * 442 ) + NEW met3 ( 10373 442 ) ( 10994 * 0 ) + NEW met1 ( 10327 901 ) ( 10373 * ) + NEW met2 ( 10373 442 ) ( * 901 ) + NEW met1 ( 10327 1445 ) ( 10373 * ) + NEW met2 ( 10373 901 ) ( * 1445 ) + NEW met2 ( 10925 1411 ) ( * 1683 ) + NEW met1 ( 10373 1411 ) ( 10925 * ) + NEW met1 ( 10373 1411 ) ( * 1445 ) + NEW met1 ( 10327 1989 ) ( 10373 * ) + NEW met2 ( 10373 1445 ) ( * 1989 ) + NEW li1 ( 10327 391 ) L1M1_PR_MR + NEW met1 ( 10373 391 ) M1M2_PR + NEW met2 ( 10373 442 ) M2M3_PR + NEW li1 ( 10327 901 ) L1M1_PR_MR + NEW met1 ( 10373 901 ) M1M2_PR + NEW li1 ( 10327 1445 ) L1M1_PR_MR + NEW met1 ( 10373 1445 ) M1M2_PR + NEW li1 ( 10925 1683 ) L1M1_PR_MR + NEW met1 ( 10925 1683 ) M1M2_PR + NEW met1 ( 10925 1411 ) M1M2_PR + NEW li1 ( 10327 1989 ) L1M1_PR_MR + NEW met1 ( 10373 1989 ) M1M2_PR ; + - addr_rw[1] ( PIN addr_rw[1] ) ( decoder.inv_1 A ) ( decoder_7.and_layer1 A ) ( decoder_6.and_layer1 A ) ( decoder_3.and_layer1 A ) ( decoder_2.and_layer1 A ) + USE SIGNAL + + ROUTED met2 ( 10925 714 ) ( * 969 ) + NEW met3 ( 10925 714 ) ( 10994 * 0 ) + NEW met1 ( 10557 697 ) ( 10925 * ) + NEW met2 ( 10925 697 ) ( * 714 ) + NEW met1 ( 10557 901 ) ( 10925 * ) + NEW met1 ( 10557 1785 ) ( 10603 * ) + NEW met2 ( 10603 901 ) ( * 1785 ) + NEW met1 ( 10557 1989 ) ( 10603 * ) + NEW met2 ( 10603 1785 ) ( * 1989 ) + NEW li1 ( 10925 969 ) L1M1_PR_MR + NEW met1 ( 10925 969 ) M1M2_PR + NEW met2 ( 10925 714 ) M2M3_PR + NEW li1 ( 10557 697 ) L1M1_PR_MR + NEW met1 ( 10925 697 ) M1M2_PR + NEW li1 ( 10557 901 ) L1M1_PR_MR + NEW met1 ( 10925 901 ) M1M2_PR + NEW li1 ( 10557 1785 ) L1M1_PR_MR + NEW met1 ( 10603 1785 ) M1M2_PR + NEW met1 ( 10603 901 ) M1M2_PR + NEW li1 ( 10557 1989 ) L1M1_PR_MR + NEW met1 ( 10603 1989 ) M1M2_PR ; + - addr_rw[2] ( PIN addr_rw[2] ) ( decoder.inv_2 A ) ( decoder_7.and_layer1 B ) ( decoder_6.and_layer1 B ) ( decoder_5.and_layer1 B ) ( decoder_4.and_layer1 B ) + USE SIGNAL + + ROUTED met3 ( 10925 578 ) ( 10994 * 0 ) + NEW met2 ( 10925 119 ) ( * 578 ) + NEW met1 ( 10649 1207 ) ( 10695 * ) + NEW met2 ( 10695 578 ) ( * 1207 ) + NEW met3 ( 10695 578 ) ( 10925 * ) + NEW met1 ( 10649 1479 ) ( 10695 * ) + NEW met2 ( 10695 1207 ) ( * 1479 ) + NEW met1 ( 10649 1751 ) ( 10695 * ) + NEW met2 ( 10695 1479 ) ( * 1751 ) + NEW met1 ( 10649 2023 ) ( 10695 * ) + NEW met2 ( 10695 1751 ) ( * 2023 ) + NEW met2 ( 10925 578 ) M2M3_PR + NEW li1 ( 10925 119 ) L1M1_PR_MR + NEW met1 ( 10925 119 ) M1M2_PR + NEW li1 ( 10649 1207 ) L1M1_PR_MR + NEW met1 ( 10695 1207 ) M1M2_PR + NEW met2 ( 10695 578 ) M2M3_PR + NEW li1 ( 10649 1479 ) L1M1_PR_MR + NEW met1 ( 10695 1479 ) M1M2_PR + NEW li1 ( 10649 1751 ) L1M1_PR_MR + NEW met1 ( 10695 1751 ) M1M2_PR + NEW li1 ( 10649 2023 ) L1M1_PR_MR + NEW met1 ( 10695 2023 ) M1M2_PR ; + - clk ( PIN clk ) ( storage_7_0_0.cg CLK ) ( storage_6_0_0.cg CLK ) ( storage_5_0_0.cg CLK ) ( storage_4_0_0.cg CLK ) ( storage_3_0_0.cg CLK ) ( storage_2_0_0.cg CLK ) + ( storage_1_0_0.cg CLK ) ( storage_0_0_0.cg CLK ) + USE SIGNAL + + ROUTED met2 ( 9775 119 ) ( * 170 ) + NEW met3 ( 9775 170 ) ( 10994 * 0 ) + NEW met2 ( 9775 170 ) ( * 425 ) + NEW met2 ( 9775 425 ) ( * 663 ) + NEW met2 ( 9775 663 ) ( * 969 ) + NEW met2 ( 9775 969 ) ( * 1207 ) + NEW met2 ( 9775 1207 ) ( * 1513 ) + NEW met2 ( 9729 1734 ) ( * 1751 ) + NEW met2 ( 9729 1734 ) ( 9775 * ) + NEW met2 ( 9775 1513 ) ( * 1734 ) + NEW met2 ( 9729 1751 ) ( * 2057 ) + NEW met1 ( 9775 119 ) M1M2_PR_MR + NEW met2 ( 9775 170 ) M2M3_PR + NEW met1 ( 9775 425 ) M1M2_PR_MR + NEW met1 ( 9775 663 ) M1M2_PR_MR + NEW met1 ( 9775 969 ) M1M2_PR_MR + NEW met1 ( 9775 1207 ) M1M2_PR_MR + NEW met1 ( 9775 1513 ) M1M2_PR_MR + NEW met1 ( 9729 1751 ) M1M2_PR + NEW met1 ( 9729 2057 ) M1M2_PR ; + - decoder_0.decoder0 ( storage_0_0_0.select_inv_0 A ) ( storage_0_0_0.gcand A ) ( decoder_0.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 10143 85 ) ( 10235 * ) + NEW met1 ( 10235 51 ) ( * 85 ) + NEW met1 ( 10235 51 ) ( 10879 * ) + NEW met1 ( 9913 153 ) ( 10143 * ) + NEW met1 ( 10143 85 ) ( * 153 ) + NEW li1 ( 10143 85 ) L1M1_PR_MR + NEW li1 ( 10879 51 ) L1M1_PR_MR + NEW li1 ( 9913 153 ) L1M1_PR_MR ; + - decoder_0.decoder_out ( decoder_0.buf_port0 A ) ( decoder_0.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 10787 85 ) ( * 119 ) + NEW met1 ( 10511 85 ) ( 10787 * ) + NEW li1 ( 10787 119 ) L1M1_PR_MR + NEW li1 ( 10511 85 ) L1M1_PR_MR ; + - decoder_0.layer_in0 ( decoder_0.and_layer1 X ) ( decoder_0.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 10419 153 ) ( * 187 ) + NEW met1 ( 10419 187 ) ( 10741 * ) + NEW li1 ( 10419 153 ) L1M1_PR_MR + NEW li1 ( 10741 187 ) L1M1_PR_MR ; + - decoder_0.layer_in1 + USE SIGNAL ; + - decoder_1.decoder0 ( storage_1_0_0.select_inv_0 A ) ( storage_1_0_0.gcand A ) ( decoder_1.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 10143 493 ) ( 10879 * ) + NEW met1 ( 9913 391 ) ( * 425 ) + NEW met1 ( 9913 425 ) ( 10143 * ) + NEW li1 ( 10143 493 ) L1M1_PR_MR + NEW li1 ( 10879 493 ) L1M1_PR_MR + NEW li1 ( 9913 391 ) L1M1_PR_MR + NEW li1 ( 10143 425 ) L1M1_PR_MR ; + - decoder_1.decoder_out ( decoder_1.buf_port0 A ) ( decoder_1.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 10787 425 ) ( * 459 ) + NEW met1 ( 10511 459 ) ( 10787 * ) + NEW li1 ( 10787 425 ) L1M1_PR_MR + NEW li1 ( 10511 459 ) L1M1_PR_MR ; + - decoder_1.layer_in0 ( decoder_1.and_layer1 X ) ( decoder_1.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 10419 425 ) ( 10741 * ) + NEW li1 ( 10419 425 ) L1M1_PR_MR + NEW li1 ( 10741 425 ) L1M1_PR_MR ; + - decoder_1.layer_in1 + USE SIGNAL ; + - decoder_2.decoder0 ( storage_2_0_0.select_inv_0 A ) ( storage_2_0_0.gcand A ) ( decoder_2.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 10143 629 ) ( 10235 * ) + NEW met1 ( 10235 595 ) ( * 629 ) + NEW met1 ( 10235 595 ) ( 10879 * ) + NEW met1 ( 9913 697 ) ( 10143 * ) + NEW met1 ( 10143 629 ) ( * 697 ) + NEW li1 ( 10143 629 ) L1M1_PR_MR + NEW li1 ( 10879 595 ) L1M1_PR_MR + NEW li1 ( 9913 697 ) L1M1_PR_MR ; + - decoder_2.decoder_out ( decoder_2.buf_port0 A ) ( decoder_2.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 10787 629 ) ( * 663 ) + NEW met1 ( 10511 629 ) ( 10787 * ) + NEW li1 ( 10787 663 ) L1M1_PR_MR + NEW li1 ( 10511 629 ) L1M1_PR_MR ; + - decoder_2.layer_in0 ( decoder_2.and_layer1 X ) ( decoder_2.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 10419 697 ) ( * 731 ) + NEW met1 ( 10419 731 ) ( 10741 * ) + NEW li1 ( 10419 697 ) L1M1_PR_MR + NEW li1 ( 10741 731 ) L1M1_PR_MR ; + - decoder_2.layer_in1 + USE SIGNAL ; + - decoder_3.decoder0 ( storage_3_0_0.select_inv_0 A ) ( storage_3_0_0.gcand A ) ( decoder_3.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 10143 1037 ) ( 10879 * ) + NEW met1 ( 9913 935 ) ( * 969 ) + NEW met1 ( 9913 969 ) ( 10143 * ) + NEW li1 ( 10143 1037 ) L1M1_PR_MR + NEW li1 ( 10879 1037 ) L1M1_PR_MR + NEW li1 ( 9913 935 ) L1M1_PR_MR + NEW li1 ( 10143 969 ) L1M1_PR_MR ; + - decoder_3.decoder_out ( decoder_3.buf_port0 A ) ( decoder_3.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 10787 969 ) ( * 1003 ) + NEW met1 ( 10511 1003 ) ( 10787 * ) + NEW li1 ( 10787 969 ) L1M1_PR_MR + NEW li1 ( 10511 1003 ) L1M1_PR_MR ; + - decoder_3.layer_in0 ( decoder_3.and_layer1 X ) ( decoder_3.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 10419 969 ) ( 10741 * ) + NEW li1 ( 10419 969 ) L1M1_PR_MR + NEW li1 ( 10741 969 ) L1M1_PR_MR ; + - decoder_3.layer_in1 + USE SIGNAL ; + - decoder_4.decoder0 ( storage_4_0_0.select_inv_0 A ) ( storage_4_0_0.gcand A ) ( decoder_4.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 10143 1173 ) ( 10235 * ) + NEW met1 ( 10235 1139 ) ( * 1173 ) + NEW met1 ( 10235 1139 ) ( 10879 * ) + NEW met1 ( 9913 1241 ) ( 10143 * ) + NEW met1 ( 10143 1173 ) ( * 1241 ) + NEW li1 ( 10143 1173 ) L1M1_PR_MR + NEW li1 ( 10879 1139 ) L1M1_PR_MR + NEW li1 ( 9913 1241 ) L1M1_PR_MR ; + - decoder_4.decoder_out ( decoder_4.buf_port0 A ) ( decoder_4.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 10787 1173 ) ( * 1207 ) + NEW met1 ( 10511 1173 ) ( 10787 * ) + NEW li1 ( 10787 1207 ) L1M1_PR_MR + NEW li1 ( 10511 1173 ) L1M1_PR_MR ; + - decoder_4.layer_in0 ( decoder_4.and_layer1 X ) ( decoder_4.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 10419 1241 ) ( * 1275 ) + NEW met1 ( 10419 1275 ) ( 10741 * ) + NEW li1 ( 10419 1241 ) L1M1_PR_MR + NEW li1 ( 10741 1275 ) L1M1_PR_MR ; + - decoder_4.layer_in1 + USE SIGNAL ; + - decoder_5.decoder0 ( storage_5_0_0.select_inv_0 A ) ( storage_5_0_0.gcand A ) ( decoder_5.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 10143 1581 ) ( 10879 * ) + NEW met1 ( 9913 1479 ) ( * 1513 ) + NEW met1 ( 9913 1513 ) ( 10143 * ) + NEW li1 ( 10143 1581 ) L1M1_PR_MR + NEW li1 ( 10879 1581 ) L1M1_PR_MR + NEW li1 ( 9913 1479 ) L1M1_PR_MR + NEW li1 ( 10143 1513 ) L1M1_PR_MR ; + - decoder_5.decoder_out ( decoder_5.buf_port0 A ) ( decoder_5.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 10787 1513 ) ( * 1547 ) + NEW met1 ( 10511 1547 ) ( 10787 * ) + NEW li1 ( 10787 1513 ) L1M1_PR_MR + NEW li1 ( 10511 1547 ) L1M1_PR_MR ; + - decoder_5.layer_in0 ( decoder_5.and_layer1 X ) ( decoder_5.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 10419 1513 ) ( 10741 * ) + NEW li1 ( 10419 1513 ) L1M1_PR_MR + NEW li1 ( 10741 1513 ) L1M1_PR_MR ; + - decoder_5.layer_in1 + USE SIGNAL ; + - decoder_6.decoder0 ( storage_6_0_0.select_inv_0 A ) ( storage_6_0_0.gcand A ) ( decoder_6.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 10143 1717 ) ( 10235 * ) + NEW met1 ( 10235 1683 ) ( * 1717 ) + NEW met1 ( 10235 1683 ) ( 10879 * ) + NEW met1 ( 9913 1785 ) ( 10143 * ) + NEW met1 ( 10143 1717 ) ( * 1785 ) + NEW li1 ( 10143 1717 ) L1M1_PR_MR + NEW li1 ( 10879 1683 ) L1M1_PR_MR + NEW li1 ( 9913 1785 ) L1M1_PR_MR ; + - decoder_6.decoder_out ( decoder_6.buf_port0 A ) ( decoder_6.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 10787 1717 ) ( * 1751 ) + NEW met1 ( 10511 1717 ) ( 10787 * ) + NEW li1 ( 10787 1751 ) L1M1_PR_MR + NEW li1 ( 10511 1717 ) L1M1_PR_MR ; + - decoder_6.layer_in0 ( decoder_6.and_layer1 X ) ( decoder_6.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 10419 1785 ) ( * 1819 ) + NEW met1 ( 10419 1819 ) ( 10741 * ) + NEW li1 ( 10419 1785 ) L1M1_PR_MR + NEW li1 ( 10741 1819 ) L1M1_PR_MR ; + - decoder_6.layer_in1 + USE SIGNAL ; + - decoder_7.decoder0 ( storage_7_0_0.select_inv_0 A ) ( storage_7_0_0.gcand A ) ( decoder_7.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 10143 2125 ) ( 10879 * ) + NEW met1 ( 9913 2023 ) ( * 2057 ) + NEW met1 ( 9913 2057 ) ( 10143 * ) + NEW li1 ( 10143 2125 ) L1M1_PR_MR + NEW li1 ( 10879 2125 ) L1M1_PR_MR + NEW li1 ( 9913 2023 ) L1M1_PR_MR + NEW li1 ( 10143 2057 ) L1M1_PR_MR ; + - decoder_7.decoder_out ( decoder_7.buf_port0 A ) ( decoder_7.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 10787 2057 ) ( * 2091 ) + NEW met1 ( 10511 2091 ) ( 10787 * ) + NEW li1 ( 10787 2057 ) L1M1_PR_MR + NEW li1 ( 10511 2091 ) L1M1_PR_MR ; + - decoder_7.layer_in0 ( decoder_7.and_layer1 X ) ( decoder_7.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 10419 2057 ) ( 10741 * ) + NEW li1 ( 10419 2057 ) L1M1_PR_MR + NEW li1 ( 10741 2057 ) L1M1_PR_MR ; + - decoder_7.layer_in1 + USE SIGNAL ; + - inv.addr0 ( decoder.inv_0 Y ) ( decoder_6.and_layer0 A ) ( decoder_4.and_layer0 A ) ( decoder_2.and_layer0 A ) ( decoder_0.and_layer0 A ) + USE SIGNAL + + ROUTED met1 ( 10327 1819 ) ( * 1853 ) + NEW met1 ( 10327 1853 ) ( 10971 * ) + NEW met2 ( 10327 1275 ) ( * 1819 ) + NEW met2 ( 10327 731 ) ( * 1275 ) + NEW met2 ( 10327 187 ) ( * 731 ) + NEW li1 ( 10327 1819 ) L1M1_PR_MR + NEW li1 ( 10971 1853 ) L1M1_PR_MR + NEW li1 ( 10327 1275 ) L1M1_PR_MR + NEW met1 ( 10327 1275 ) M1M2_PR + NEW met1 ( 10327 1819 ) M1M2_PR + NEW li1 ( 10327 731 ) L1M1_PR_MR + NEW met1 ( 10327 731 ) M1M2_PR + NEW li1 ( 10327 187 ) L1M1_PR_MR + NEW met1 ( 10327 187 ) M1M2_PR ; + - inv.addr1 ( decoder.inv_1 Y ) ( decoder_5.and_layer1 A ) ( decoder_4.and_layer1 A ) ( decoder_1.and_layer1 A ) ( decoder_0.and_layer1 A ) + USE SIGNAL + + ROUTED met2 ( 10557 1241 ) ( * 1445 ) + NEW met2 ( 10971 1037 ) ( * 1241 ) + NEW met1 ( 10557 1241 ) ( 10971 * ) + NEW met2 ( 10557 391 ) ( * 1241 ) + NEW met2 ( 10557 153 ) ( * 391 ) + NEW li1 ( 10557 1241 ) L1M1_PR_MR + NEW met1 ( 10557 1241 ) M1M2_PR + NEW li1 ( 10557 1445 ) L1M1_PR_MR + NEW met1 ( 10557 1445 ) M1M2_PR + NEW li1 ( 10971 1037 ) L1M1_PR_MR + NEW met1 ( 10971 1037 ) M1M2_PR + NEW met1 ( 10971 1241 ) M1M2_PR + NEW li1 ( 10557 391 ) L1M1_PR_MR + NEW met1 ( 10557 391 ) M1M2_PR + NEW li1 ( 10557 153 ) L1M1_PR_MR + NEW met1 ( 10557 153 ) M1M2_PR ; + - inv.addr2 ( decoder.inv_2 Y ) ( decoder_3.and_layer1 B ) ( decoder_2.and_layer1 B ) ( decoder_1.and_layer1 B ) ( decoder_0.and_layer1 B ) + USE SIGNAL + + ROUTED met1 ( 10649 153 ) ( 10971 * ) + NEW met2 ( 10649 153 ) ( * 391 ) + NEW met2 ( 10649 391 ) ( * 663 ) + NEW met2 ( 10649 663 ) ( * 935 ) + NEW li1 ( 10649 153 ) L1M1_PR_MR + NEW li1 ( 10971 153 ) L1M1_PR_MR + NEW li1 ( 10649 391 ) L1M1_PR_MR + NEW met1 ( 10649 391 ) M1M2_PR + NEW met1 ( 10649 153 ) M1M2_PR + NEW li1 ( 10649 663 ) L1M1_PR_MR + NEW met1 ( 10649 663 ) M1M2_PR + NEW li1 ( 10649 935 ) L1M1_PR_MR + NEW met1 ( 10649 935 ) M1M2_PR ; + - storage_0_0_0.bit0.storage ( storage_0_0_0.bit0.obuf0 A ) ( storage_0_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 805 153 ) ( * 187 ) + NEW met1 ( 759 187 ) ( 805 * ) + NEW li1 ( 805 153 ) L1M1_PR_MR + NEW li1 ( 759 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit1.storage ( storage_0_0_0.bit1.obuf0 A ) ( storage_0_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1955 153 ) ( * 187 ) + NEW met1 ( 1909 187 ) ( 1955 * ) + NEW li1 ( 1955 153 ) L1M1_PR_MR + NEW li1 ( 1909 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit2.storage ( storage_0_0_0.bit2.obuf0 A ) ( storage_0_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3105 153 ) ( * 187 ) + NEW met1 ( 3059 187 ) ( 3105 * ) + NEW li1 ( 3105 153 ) L1M1_PR_MR + NEW li1 ( 3059 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit3.storage ( storage_0_0_0.bit3.obuf0 A ) ( storage_0_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4255 153 ) ( * 187 ) + NEW met1 ( 4209 187 ) ( 4255 * ) + NEW li1 ( 4255 153 ) L1M1_PR_MR + NEW li1 ( 4209 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit4.storage ( storage_0_0_0.bit4.obuf0 A ) ( storage_0_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5405 153 ) ( * 187 ) + NEW met1 ( 5359 187 ) ( 5405 * ) + NEW li1 ( 5405 153 ) L1M1_PR_MR + NEW li1 ( 5359 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit5.storage ( storage_0_0_0.bit5.obuf0 A ) ( storage_0_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6555 153 ) ( * 187 ) + NEW met1 ( 6509 187 ) ( 6555 * ) + NEW li1 ( 6555 153 ) L1M1_PR_MR + NEW li1 ( 6509 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit6.storage ( storage_0_0_0.bit6.obuf0 A ) ( storage_0_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7705 153 ) ( * 187 ) + NEW met1 ( 7659 187 ) ( 7705 * ) + NEW li1 ( 7705 153 ) L1M1_PR_MR + NEW li1 ( 7659 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit7.storage ( storage_0_0_0.bit7.obuf0 A ) ( storage_0_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8855 153 ) ( * 187 ) + NEW met1 ( 8809 187 ) ( 8855 * ) + NEW li1 ( 8855 153 ) L1M1_PR_MR + NEW li1 ( 8809 187 ) L1M1_PR_MR ; + - storage_0_0_0.gclock ( storage_0_0_0.cg GCLK ) ( storage_0_0_0.bit7.bit CLK ) ( storage_0_0_0.bit6.bit CLK ) ( storage_0_0_0.bit5.bit CLK ) ( storage_0_0_0.bit4.bit CLK ) ( storage_0_0_0.bit3.bit CLK ) ( storage_0_0_0.bit2.bit CLK ) + ( storage_0_0_0.bit1.bit CLK ) ( storage_0_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 1219 153 ) ( * 221 ) + NEW met1 ( 69 85 ) ( * 119 ) + NEW met1 ( 69 85 ) ( 851 * ) + NEW met1 ( 851 85 ) ( * 153 ) + NEW met1 ( 851 153 ) ( 1219 * ) + NEW met1 ( 2369 153 ) ( * 187 ) + NEW met1 ( 2185 187 ) ( 2369 * ) + NEW met1 ( 2185 187 ) ( * 221 ) + NEW met1 ( 3105 119 ) ( 3519 * ) + NEW met1 ( 3105 85 ) ( * 119 ) + NEW met1 ( 2369 85 ) ( 3105 * ) + NEW met1 ( 2369 85 ) ( * 153 ) + NEW met1 ( 4669 85 ) ( * 119 ) + NEW met1 ( 3519 85 ) ( 4669 * ) + NEW met1 ( 3519 85 ) ( * 119 ) + NEW met1 ( 5727 153 ) ( 5819 * ) + NEW met2 ( 5727 51 ) ( * 153 ) + NEW met1 ( 4669 51 ) ( 5727 * ) + NEW met1 ( 4669 51 ) ( * 85 ) + NEW met1 ( 6785 153 ) ( 6969 * ) + NEW met1 ( 6785 153 ) ( * 221 ) + NEW met1 ( 5819 221 ) ( 6785 * ) + NEW met1 ( 5819 153 ) ( * 221 ) + NEW met1 ( 6969 153 ) ( * 221 ) + NEW met1 ( 1219 221 ) ( 2185 * ) + NEW met1 ( 8119 51 ) ( * 119 ) + NEW met1 ( 8119 51 ) ( 9867 * ) + NEW met1 ( 7751 187 ) ( * 221 ) + NEW met1 ( 7751 187 ) ( 8119 * ) + NEW met1 ( 8119 119 ) ( * 187 ) + NEW met1 ( 6969 221 ) ( 7751 * ) + NEW li1 ( 1219 153 ) L1M1_PR_MR + NEW li1 ( 69 119 ) L1M1_PR_MR + NEW li1 ( 2369 153 ) L1M1_PR_MR + NEW li1 ( 3519 119 ) L1M1_PR_MR + NEW li1 ( 4669 119 ) L1M1_PR_MR + NEW li1 ( 5819 153 ) L1M1_PR_MR + NEW met1 ( 5727 153 ) M1M2_PR + NEW met1 ( 5727 51 ) M1M2_PR + NEW li1 ( 6969 153 ) L1M1_PR_MR + NEW li1 ( 8119 119 ) L1M1_PR_MR + NEW li1 ( 9867 51 ) L1M1_PR_MR ; + - storage_0_0_0.select0_b ( storage_0_0_0.select_inv_0 Y ) ( storage_0_0_0.bit7.obuf0 TE_B ) ( storage_0_0_0.bit6.obuf0 TE_B ) ( storage_0_0_0.bit5.obuf0 TE_B ) ( storage_0_0_0.bit4.obuf0 TE_B ) ( storage_0_0_0.bit3.obuf0 TE_B ) ( storage_0_0_0.bit2.obuf0 TE_B ) + ( storage_0_0_0.bit1.obuf0 TE_B ) ( storage_0_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 897 85 ) ( * 119 ) + NEW met1 ( 6647 85 ) ( * 119 ) + NEW met1 ( 5497 119 ) ( 5773 * ) + NEW met2 ( 5773 34 ) ( * 119 ) + NEW met2 ( 5773 34 ) ( 5865 * ) + NEW met2 ( 5865 34 ) ( * 51 ) + NEW met1 ( 5865 51 ) ( 6647 * ) + NEW met1 ( 6647 51 ) ( * 85 ) + NEW met1 ( 4347 153 ) ( 4715 * ) + NEW met1 ( 4715 85 ) ( * 153 ) + NEW met1 ( 4715 85 ) ( 5497 * ) + NEW met1 ( 5497 85 ) ( * 119 ) + NEW met1 ( 3197 153 ) ( 3473 * ) + NEW met1 ( 3473 153 ) ( * 221 ) + NEW met1 ( 3473 221 ) ( 4347 * ) + NEW met1 ( 4347 153 ) ( * 221 ) + NEW met1 ( 2047 153 ) ( 2277 * ) + NEW met2 ( 2277 153 ) ( * 221 ) + NEW met1 ( 2277 221 ) ( 3197 * ) + NEW met1 ( 3197 153 ) ( * 221 ) + NEW met1 ( 2047 85 ) ( * 153 ) + NEW met1 ( 897 85 ) ( 2047 * ) + NEW met1 ( 8947 153 ) ( * 187 ) + NEW met1 ( 8947 187 ) ( 10189 * ) + NEW met1 ( 7797 153 ) ( 8073 * ) + NEW met2 ( 8073 153 ) ( * 170 ) + NEW met2 ( 8073 170 ) ( 8119 * ) + NEW met2 ( 8119 170 ) ( * 221 ) + NEW met1 ( 8119 221 ) ( 8947 * ) + NEW met1 ( 8947 187 ) ( * 221 ) + NEW met1 ( 7797 85 ) ( * 153 ) + NEW met1 ( 6647 85 ) ( 7797 * ) + NEW li1 ( 897 119 ) L1M1_PR_MR + NEW li1 ( 6647 119 ) L1M1_PR_MR + NEW li1 ( 5497 119 ) L1M1_PR_MR + NEW met1 ( 5773 119 ) M1M2_PR + NEW met1 ( 5865 51 ) M1M2_PR + NEW li1 ( 4347 153 ) L1M1_PR_MR + NEW li1 ( 3197 153 ) L1M1_PR_MR + NEW li1 ( 2047 153 ) L1M1_PR_MR + NEW met1 ( 2277 153 ) M1M2_PR + NEW met1 ( 2277 221 ) M1M2_PR + NEW li1 ( 8947 153 ) L1M1_PR_MR + NEW li1 ( 10189 187 ) L1M1_PR_MR + NEW li1 ( 7797 153 ) L1M1_PR_MR + NEW met1 ( 8073 153 ) M1M2_PR + NEW met1 ( 8119 221 ) M1M2_PR ; + - storage_0_0_0.we0 ( storage_0_0_0.gcand X ) ( storage_0_0_0.cg GATE ) + USE SIGNAL + + ROUTED met2 ( 9453 153 ) ( * 221 ) + NEW met1 ( 9453 221 ) ( 10097 * ) + NEW li1 ( 9453 153 ) L1M1_PR_MR + NEW met1 ( 9453 153 ) M1M2_PR + NEW met1 ( 9453 221 ) M1M2_PR + NEW li1 ( 10097 221 ) L1M1_PR_MR ; + - storage_1_0_0.bit0.storage ( storage_1_0_0.bit0.obuf0 A ) ( storage_1_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 759 391 ) ( 805 * ) + NEW met1 ( 759 357 ) ( * 391 ) + NEW li1 ( 805 391 ) L1M1_PR_MR + NEW li1 ( 759 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit1.storage ( storage_1_0_0.bit1.obuf0 A ) ( storage_1_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1909 391 ) ( 1955 * ) + NEW met1 ( 1909 357 ) ( * 391 ) + NEW li1 ( 1955 391 ) L1M1_PR_MR + NEW li1 ( 1909 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit2.storage ( storage_1_0_0.bit2.obuf0 A ) ( storage_1_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3059 391 ) ( 3105 * ) + NEW met1 ( 3059 357 ) ( * 391 ) + NEW li1 ( 3105 391 ) L1M1_PR_MR + NEW li1 ( 3059 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit3.storage ( storage_1_0_0.bit3.obuf0 A ) ( storage_1_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4209 391 ) ( 4255 * ) + NEW met1 ( 4209 357 ) ( * 391 ) + NEW li1 ( 4255 391 ) L1M1_PR_MR + NEW li1 ( 4209 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit4.storage ( storage_1_0_0.bit4.obuf0 A ) ( storage_1_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5359 391 ) ( 5405 * ) + NEW met1 ( 5359 357 ) ( * 391 ) + NEW li1 ( 5405 391 ) L1M1_PR_MR + NEW li1 ( 5359 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit5.storage ( storage_1_0_0.bit5.obuf0 A ) ( storage_1_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6509 391 ) ( 6555 * ) + NEW met1 ( 6509 357 ) ( * 391 ) + NEW li1 ( 6555 391 ) L1M1_PR_MR + NEW li1 ( 6509 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit6.storage ( storage_1_0_0.bit6.obuf0 A ) ( storage_1_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7659 391 ) ( 7705 * ) + NEW met1 ( 7659 357 ) ( * 391 ) + NEW li1 ( 7705 391 ) L1M1_PR_MR + NEW li1 ( 7659 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit7.storage ( storage_1_0_0.bit7.obuf0 A ) ( storage_1_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8809 391 ) ( 8855 * ) + NEW met1 ( 8809 357 ) ( * 391 ) + NEW li1 ( 8855 391 ) L1M1_PR_MR + NEW li1 ( 8809 357 ) L1M1_PR_MR ; + - storage_1_0_0.gclock ( storage_1_0_0.cg GCLK ) ( storage_1_0_0.bit7.bit CLK ) ( storage_1_0_0.bit6.bit CLK ) ( storage_1_0_0.bit5.bit CLK ) ( storage_1_0_0.bit4.bit CLK ) ( storage_1_0_0.bit3.bit CLK ) ( storage_1_0_0.bit2.bit CLK ) + ( storage_1_0_0.bit1.bit CLK ) ( storage_1_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 69 425 ) ( 1219 * ) + NEW met1 ( 3519 425 ) ( * 459 ) + NEW met1 ( 3473 459 ) ( 3519 * ) + NEW met1 ( 3473 425 ) ( * 459 ) + NEW met1 ( 2369 425 ) ( 3473 * ) + NEW met1 ( 4485 391 ) ( 4669 * ) + NEW met2 ( 4485 391 ) ( * 493 ) + NEW met1 ( 3519 493 ) ( 4485 * ) + NEW met1 ( 3519 459 ) ( * 493 ) + NEW met1 ( 5819 323 ) ( * 391 ) + NEW met1 ( 4669 323 ) ( 5819 * ) + NEW met1 ( 4669 323 ) ( * 391 ) + NEW met1 ( 6969 323 ) ( * 391 ) + NEW met1 ( 5819 323 ) ( 6969 * ) + NEW met1 ( 1219 425 ) ( 2369 * ) + NEW met1 ( 8119 323 ) ( * 391 ) + NEW met1 ( 8119 323 ) ( 9867 * ) + NEW met1 ( 6969 323 ) ( 8119 * ) + NEW li1 ( 1219 425 ) L1M1_PR_MR + NEW li1 ( 69 425 ) L1M1_PR_MR + NEW li1 ( 2369 425 ) L1M1_PR_MR + NEW li1 ( 3519 425 ) L1M1_PR_MR + NEW li1 ( 4669 391 ) L1M1_PR_MR + NEW met1 ( 4485 391 ) M1M2_PR + NEW met1 ( 4485 493 ) M1M2_PR + NEW li1 ( 5819 391 ) L1M1_PR_MR + NEW li1 ( 6969 391 ) L1M1_PR_MR + NEW li1 ( 8119 391 ) L1M1_PR_MR + NEW li1 ( 9867 323 ) L1M1_PR_MR ; + - storage_1_0_0.select0_b ( storage_1_0_0.select_inv_0 Y ) ( storage_1_0_0.bit7.obuf0 TE_B ) ( storage_1_0_0.bit6.obuf0 TE_B ) ( storage_1_0_0.bit5.obuf0 TE_B ) ( storage_1_0_0.bit4.obuf0 TE_B ) ( storage_1_0_0.bit3.obuf0 TE_B ) ( storage_1_0_0.bit2.obuf0 TE_B ) + ( storage_1_0_0.bit1.obuf0 TE_B ) ( storage_1_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 897 323 ) ( * 391 ) + NEW met1 ( 5497 425 ) ( 6647 * ) + NEW met1 ( 4347 425 ) ( 5497 * ) + NEW met1 ( 3197 391 ) ( 3565 * ) + NEW met1 ( 3565 391 ) ( * 425 ) + NEW met1 ( 3565 425 ) ( 4347 * ) + NEW met1 ( 2047 323 ) ( * 391 ) + NEW met1 ( 2047 323 ) ( 3197 * ) + NEW met1 ( 3197 323 ) ( * 391 ) + NEW met1 ( 897 323 ) ( 2047 * ) + NEW met1 ( 8947 357 ) ( * 391 ) + NEW met1 ( 8947 357 ) ( 10189 * ) + NEW met1 ( 7797 425 ) ( * 459 ) + NEW met1 ( 7797 459 ) ( 8119 * ) + NEW met1 ( 8119 459 ) ( * 493 ) + NEW met1 ( 8119 493 ) ( 8947 * ) + NEW met2 ( 8947 391 ) ( * 493 ) + NEW met1 ( 6647 425 ) ( 7797 * ) + NEW li1 ( 897 391 ) L1M1_PR_MR + NEW li1 ( 6647 425 ) L1M1_PR_MR + NEW li1 ( 5497 425 ) L1M1_PR_MR + NEW li1 ( 4347 425 ) L1M1_PR_MR + NEW li1 ( 3197 391 ) L1M1_PR_MR + NEW li1 ( 2047 391 ) L1M1_PR_MR + NEW li1 ( 8947 391 ) L1M1_PR_MR + NEW li1 ( 10189 357 ) L1M1_PR_MR + NEW li1 ( 7797 425 ) L1M1_PR_MR + NEW met1 ( 8947 493 ) M1M2_PR + NEW met1 ( 8947 391 ) M1M2_PR ; + - storage_1_0_0.we0 ( storage_1_0_0.gcand X ) ( storage_1_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 9453 493 ) ( 10097 * ) + NEW li1 ( 9453 493 ) L1M1_PR_MR + NEW li1 ( 10097 493 ) L1M1_PR_MR ; + - storage_2_0_0.bit0.storage ( storage_2_0_0.bit0.obuf0 A ) ( storage_2_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 759 663 ) ( 805 * ) + NEW met1 ( 759 595 ) ( * 663 ) + NEW li1 ( 805 663 ) L1M1_PR_MR + NEW li1 ( 759 595 ) L1M1_PR_MR ; + - storage_2_0_0.bit1.storage ( storage_2_0_0.bit1.obuf0 A ) ( storage_2_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1955 663 ) ( * 731 ) + NEW met1 ( 1909 731 ) ( 1955 * ) + NEW li1 ( 1955 663 ) L1M1_PR_MR + NEW li1 ( 1909 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit2.storage ( storage_2_0_0.bit2.obuf0 A ) ( storage_2_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3059 663 ) ( 3105 * ) + NEW met1 ( 3059 595 ) ( * 663 ) + NEW li1 ( 3105 663 ) L1M1_PR_MR + NEW li1 ( 3059 595 ) L1M1_PR_MR ; + - storage_2_0_0.bit3.storage ( storage_2_0_0.bit3.obuf0 A ) ( storage_2_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4209 595 ) ( 4255 * ) + NEW met2 ( 4255 595 ) ( * 663 ) + NEW met1 ( 4254 663 ) ( 4255 * ) + NEW li1 ( 4209 595 ) L1M1_PR_MR + NEW met1 ( 4255 595 ) M1M2_PR + NEW met1 ( 4255 663 ) M1M2_PR + NEW li1 ( 4254 663 ) L1M1_PR_MR ; + - storage_2_0_0.bit4.storage ( storage_2_0_0.bit4.obuf0 A ) ( storage_2_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5359 663 ) ( 5405 * ) + NEW met1 ( 5359 595 ) ( * 663 ) + NEW li1 ( 5405 663 ) L1M1_PR_MR + NEW li1 ( 5359 595 ) L1M1_PR_MR ; + - storage_2_0_0.bit5.storage ( storage_2_0_0.bit5.obuf0 A ) ( storage_2_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6509 663 ) ( 6555 * ) + NEW met1 ( 6509 663 ) ( * 731 ) + NEW li1 ( 6555 663 ) L1M1_PR_MR + NEW li1 ( 6509 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit6.storage ( storage_2_0_0.bit6.obuf0 A ) ( storage_2_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7705 697 ) ( * 731 ) + NEW met1 ( 7659 731 ) ( 7705 * ) + NEW li1 ( 7705 697 ) L1M1_PR_MR + NEW li1 ( 7659 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit7.storage ( storage_2_0_0.bit7.obuf0 A ) ( storage_2_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8855 697 ) ( * 731 ) + NEW met1 ( 8809 731 ) ( 8855 * ) + NEW li1 ( 8855 697 ) L1M1_PR_MR + NEW li1 ( 8809 731 ) L1M1_PR_MR ; + - storage_2_0_0.gclock ( storage_2_0_0.cg GCLK ) ( storage_2_0_0.bit7.bit CLK ) ( storage_2_0_0.bit6.bit CLK ) ( storage_2_0_0.bit5.bit CLK ) ( storage_2_0_0.bit4.bit CLK ) ( storage_2_0_0.bit3.bit CLK ) ( storage_2_0_0.bit2.bit CLK ) + ( storage_2_0_0.bit1.bit CLK ) ( storage_2_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 943 663 ) ( 1219 * ) + NEW met1 ( 943 663 ) ( * 697 ) + NEW met1 ( 713 697 ) ( 943 * ) + NEW met1 ( 713 629 ) ( * 697 ) + NEW met1 ( 69 629 ) ( 713 * ) + NEW met1 ( 69 629 ) ( * 663 ) + NEW met1 ( 1219 629 ) ( * 663 ) + NEW met2 ( 6969 493 ) ( * 663 ) + NEW met1 ( 6969 493 ) ( 7153 * ) + NEW met1 ( 7153 459 ) ( * 493 ) + NEW met1 ( 6969 459 ) ( * 493 ) + NEW met1 ( 6210 459 ) ( 6969 * ) + NEW met1 ( 2093 663 ) ( 2369 * ) + NEW met1 ( 2093 663 ) ( * 697 ) + NEW met1 ( 2001 697 ) ( 2093 * ) + NEW met1 ( 2001 629 ) ( * 697 ) + NEW met1 ( 3243 663 ) ( 3519 * ) + NEW met1 ( 3243 663 ) ( * 765 ) + NEW met1 ( 2369 765 ) ( 3243 * ) + NEW met1 ( 2369 663 ) ( * 765 ) + NEW met1 ( 4393 663 ) ( 4669 * ) + NEW met1 ( 4393 663 ) ( * 697 ) + NEW met1 ( 4163 697 ) ( 4393 * ) + NEW met1 ( 4163 663 ) ( * 697 ) + NEW met1 ( 3519 663 ) ( 4163 * ) + NEW met1 ( 5543 663 ) ( 5819 * ) + NEW met1 ( 5543 663 ) ( * 765 ) + NEW met1 ( 4669 765 ) ( 5543 * ) + NEW met1 ( 4669 663 ) ( * 765 ) + NEW met1 ( 6210 459 ) ( * 493 ) + NEW met1 ( 5819 493 ) ( 6210 * ) + NEW met2 ( 5819 493 ) ( * 663 ) + NEW met1 ( 1219 629 ) ( 2001 * ) + NEW met1 ( 8119 595 ) ( * 663 ) + NEW met1 ( 8119 595 ) ( 9867 * ) + NEW met2 ( 7613 459 ) ( * 595 ) + NEW met1 ( 7613 595 ) ( 8119 * ) + NEW met1 ( 7153 459 ) ( 7613 * ) + NEW li1 ( 1219 663 ) L1M1_PR_MR + NEW li1 ( 69 663 ) L1M1_PR_MR + NEW li1 ( 6969 663 ) L1M1_PR_MR + NEW met1 ( 6969 663 ) M1M2_PR + NEW met1 ( 6969 493 ) M1M2_PR + NEW li1 ( 2369 663 ) L1M1_PR_MR + NEW li1 ( 3519 663 ) L1M1_PR_MR + NEW li1 ( 4669 663 ) L1M1_PR_MR + NEW li1 ( 5819 663 ) L1M1_PR_MR + NEW met1 ( 5819 493 ) M1M2_PR + NEW met1 ( 5819 663 ) M1M2_PR + NEW li1 ( 8119 663 ) L1M1_PR_MR + NEW li1 ( 9867 595 ) L1M1_PR_MR + NEW met1 ( 7613 459 ) M1M2_PR + NEW met1 ( 7613 595 ) M1M2_PR ; + - storage_2_0_0.select0_b ( storage_2_0_0.select_inv_0 Y ) ( storage_2_0_0.bit7.obuf0 TE_B ) ( storage_2_0_0.bit6.obuf0 TE_B ) ( storage_2_0_0.bit5.obuf0 TE_B ) ( storage_2_0_0.bit4.obuf0 TE_B ) ( storage_2_0_0.bit3.obuf0 TE_B ) ( storage_2_0_0.bit2.obuf0 TE_B ) + ( storage_2_0_0.bit1.obuf0 TE_B ) ( storage_2_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 897 595 ) ( * 663 ) + NEW met1 ( 3013 697 ) ( 3151 * ) + NEW met1 ( 5313 697 ) ( 5451 * ) + NEW met1 ( 2047 629 ) ( * 663 ) + NEW met1 ( 2047 629 ) ( 2415 * ) + NEW met1 ( 2415 629 ) ( * 663 ) + NEW met1 ( 2415 663 ) ( 3013 * ) + NEW met1 ( 2047 595 ) ( * 629 ) + NEW met1 ( 6647 629 ) ( * 663 ) + NEW met1 ( 5497 629 ) ( * 663 ) + NEW met1 ( 5497 629 ) ( 6647 * ) + NEW met1 ( 5451 663 ) ( 5497 * ) + NEW met1 ( 4347 629 ) ( * 663 ) + NEW met1 ( 4347 629 ) ( 4715 * ) + NEW met1 ( 4715 629 ) ( * 663 ) + NEW met1 ( 4715 663 ) ( 5313 * ) + NEW met1 ( 3197 595 ) ( * 663 ) + NEW met1 ( 3197 595 ) ( 3749 * ) + NEW met1 ( 3749 595 ) ( * 629 ) + NEW met1 ( 3749 629 ) ( 4347 * ) + NEW met1 ( 3151 663 ) ( 3197 * ) + NEW met1 ( 897 595 ) ( 2047 * ) + NEW met1 ( 3013 663 ) ( * 697 ) + NEW met1 ( 3151 663 ) ( * 697 ) + NEW met1 ( 5313 663 ) ( * 697 ) + NEW met1 ( 5451 663 ) ( * 697 ) + NEW met1 ( 8947 697 ) ( * 731 ) + NEW met1 ( 8947 731 ) ( 10189 * ) + NEW met1 ( 7797 697 ) ( 8119 * ) + NEW met1 ( 8119 697 ) ( * 765 ) + NEW met1 ( 8119 765 ) ( 8947 * ) + NEW met1 ( 8947 731 ) ( * 765 ) + NEW met1 ( 7797 629 ) ( * 697 ) + NEW met1 ( 6647 629 ) ( 7797 * ) + NEW li1 ( 897 663 ) L1M1_PR_MR + NEW li1 ( 2047 663 ) L1M1_PR_MR + NEW li1 ( 6647 663 ) L1M1_PR_MR + NEW li1 ( 5497 663 ) L1M1_PR_MR + NEW li1 ( 4347 663 ) L1M1_PR_MR + NEW li1 ( 3197 663 ) L1M1_PR_MR + NEW li1 ( 8947 697 ) L1M1_PR_MR + NEW li1 ( 10189 731 ) L1M1_PR_MR + NEW li1 ( 7797 697 ) L1M1_PR_MR ; + - storage_2_0_0.we0 ( storage_2_0_0.gcand X ) ( storage_2_0_0.cg GATE ) + USE SIGNAL + + ROUTED met2 ( 9453 697 ) ( * 765 ) + NEW met1 ( 9453 765 ) ( 10097 * ) + NEW li1 ( 9453 697 ) L1M1_PR_MR + NEW met1 ( 9453 697 ) M1M2_PR + NEW met1 ( 9453 765 ) M1M2_PR + NEW li1 ( 10097 765 ) L1M1_PR_MR ; + - storage_3_0_0.bit0.storage ( storage_3_0_0.bit0.obuf0 A ) ( storage_3_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 759 935 ) ( 805 * ) + NEW met1 ( 759 901 ) ( * 935 ) + NEW li1 ( 805 935 ) L1M1_PR_MR + NEW li1 ( 759 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit1.storage ( storage_3_0_0.bit1.obuf0 A ) ( storage_3_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1909 935 ) ( 1955 * ) + NEW met1 ( 1909 901 ) ( * 935 ) + NEW li1 ( 1955 935 ) L1M1_PR_MR + NEW li1 ( 1909 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit2.storage ( storage_3_0_0.bit2.obuf0 A ) ( storage_3_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3059 935 ) ( 3105 * ) + NEW met1 ( 3059 901 ) ( * 935 ) + NEW li1 ( 3105 935 ) L1M1_PR_MR + NEW li1 ( 3059 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit3.storage ( storage_3_0_0.bit3.obuf0 A ) ( storage_3_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4209 935 ) ( 4255 * ) + NEW met1 ( 4209 901 ) ( * 935 ) + NEW li1 ( 4255 935 ) L1M1_PR_MR + NEW li1 ( 4209 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit4.storage ( storage_3_0_0.bit4.obuf0 A ) ( storage_3_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5359 935 ) ( 5405 * ) + NEW met1 ( 5359 901 ) ( * 935 ) + NEW li1 ( 5405 935 ) L1M1_PR_MR + NEW li1 ( 5359 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit5.storage ( storage_3_0_0.bit5.obuf0 A ) ( storage_3_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6509 935 ) ( 6555 * ) + NEW met1 ( 6509 901 ) ( * 935 ) + NEW li1 ( 6555 935 ) L1M1_PR_MR + NEW li1 ( 6509 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit6.storage ( storage_3_0_0.bit6.obuf0 A ) ( storage_3_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7659 935 ) ( 7705 * ) + NEW met1 ( 7659 901 ) ( * 935 ) + NEW li1 ( 7705 935 ) L1M1_PR_MR + NEW li1 ( 7659 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit7.storage ( storage_3_0_0.bit7.obuf0 A ) ( storage_3_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8809 935 ) ( 8855 * ) + NEW met1 ( 8809 901 ) ( * 935 ) + NEW li1 ( 8855 935 ) L1M1_PR_MR + NEW li1 ( 8809 901 ) L1M1_PR_MR ; + - storage_3_0_0.gclock ( storage_3_0_0.cg GCLK ) ( storage_3_0_0.bit7.bit CLK ) ( storage_3_0_0.bit6.bit CLK ) ( storage_3_0_0.bit5.bit CLK ) ( storage_3_0_0.bit4.bit CLK ) ( storage_3_0_0.bit3.bit CLK ) ( storage_3_0_0.bit2.bit CLK ) + ( storage_3_0_0.bit1.bit CLK ) ( storage_3_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 1219 867 ) ( * 935 ) + NEW met1 ( 69 969 ) ( 851 * ) + NEW met1 ( 851 935 ) ( * 969 ) + NEW met1 ( 851 935 ) ( 1219 * ) + NEW met1 ( 6969 867 ) ( * 935 ) + NEW met1 ( 2369 867 ) ( * 935 ) + NEW met1 ( 3519 867 ) ( * 935 ) + NEW met1 ( 2369 867 ) ( 3519 * ) + NEW met1 ( 4669 867 ) ( * 935 ) + NEW met1 ( 3519 867 ) ( 4669 * ) + NEW met1 ( 5819 867 ) ( * 935 ) + NEW met1 ( 4669 867 ) ( 5819 * ) + NEW met1 ( 1219 867 ) ( 2369 * ) + NEW met1 ( 5819 867 ) ( 6969 * ) + NEW met1 ( 8119 867 ) ( * 935 ) + NEW met1 ( 8119 867 ) ( 9867 * ) + NEW met1 ( 6969 867 ) ( 8119 * ) + NEW li1 ( 1219 935 ) L1M1_PR_MR + NEW li1 ( 69 969 ) L1M1_PR_MR + NEW li1 ( 6969 935 ) L1M1_PR_MR + NEW li1 ( 2369 935 ) L1M1_PR_MR + NEW li1 ( 3519 935 ) L1M1_PR_MR + NEW li1 ( 4669 935 ) L1M1_PR_MR + NEW li1 ( 5819 935 ) L1M1_PR_MR + NEW li1 ( 8119 935 ) L1M1_PR_MR + NEW li1 ( 9867 867 ) L1M1_PR_MR ; + - storage_3_0_0.select0_b ( storage_3_0_0.select_inv_0 Y ) ( storage_3_0_0.bit7.obuf0 TE_B ) ( storage_3_0_0.bit6.obuf0 TE_B ) ( storage_3_0_0.bit5.obuf0 TE_B ) ( storage_3_0_0.bit4.obuf0 TE_B ) ( storage_3_0_0.bit3.obuf0 TE_B ) ( storage_3_0_0.bit2.obuf0 TE_B ) + ( storage_3_0_0.bit1.obuf0 TE_B ) ( storage_3_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 4347 969 ) ( 5497 * ) + NEW met1 ( 3197 969 ) ( 4347 * ) + NEW met1 ( 2047 969 ) ( 3197 * ) + NEW met1 ( 897 969 ) ( 2047 * ) + NEW met1 ( 5497 969 ) ( 6647 * ) + NEW met1 ( 8947 901 ) ( * 935 ) + NEW met1 ( 8947 901 ) ( 10189 * ) + NEW met1 ( 7797 969 ) ( * 1003 ) + NEW met1 ( 7797 1003 ) ( 8119 * ) + NEW met1 ( 8119 1003 ) ( * 1037 ) + NEW met1 ( 8119 1037 ) ( 8947 * ) + NEW met2 ( 8947 935 ) ( * 1037 ) + NEW met1 ( 6647 969 ) ( 7797 * ) + NEW li1 ( 897 969 ) L1M1_PR_MR + NEW li1 ( 6647 969 ) L1M1_PR_MR + NEW li1 ( 5497 969 ) L1M1_PR_MR + NEW li1 ( 4347 969 ) L1M1_PR_MR + NEW li1 ( 3197 969 ) L1M1_PR_MR + NEW li1 ( 2047 969 ) L1M1_PR_MR + NEW li1 ( 8947 935 ) L1M1_PR_MR + NEW li1 ( 10189 901 ) L1M1_PR_MR + NEW li1 ( 7797 969 ) L1M1_PR_MR + NEW met1 ( 8947 1037 ) M1M2_PR + NEW met1 ( 8947 935 ) M1M2_PR ; + - storage_3_0_0.we0 ( storage_3_0_0.gcand X ) ( storage_3_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 9453 1037 ) ( 10097 * ) + NEW li1 ( 9453 1037 ) L1M1_PR_MR + NEW li1 ( 10097 1037 ) L1M1_PR_MR ; + - storage_4_0_0.bit0.storage ( storage_4_0_0.bit0.obuf0 A ) ( storage_4_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 805 1241 ) ( * 1275 ) + NEW met1 ( 759 1275 ) ( 805 * ) + NEW li1 ( 805 1241 ) L1M1_PR_MR + NEW li1 ( 759 1275 ) L1M1_PR_MR ; + - storage_4_0_0.bit1.storage ( storage_4_0_0.bit1.obuf0 A ) ( storage_4_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1955 1241 ) ( * 1275 ) + NEW met1 ( 1909 1275 ) ( 1955 * ) + NEW li1 ( 1955 1241 ) L1M1_PR_MR + NEW li1 ( 1909 1275 ) L1M1_PR_MR ; + - storage_4_0_0.bit2.storage ( storage_4_0_0.bit2.obuf0 A ) ( storage_4_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3105 1241 ) ( * 1275 ) + NEW met1 ( 3059 1275 ) ( 3105 * ) + NEW li1 ( 3105 1241 ) L1M1_PR_MR + NEW li1 ( 3059 1275 ) L1M1_PR_MR ; + - storage_4_0_0.bit3.storage ( storage_4_0_0.bit3.obuf0 A ) ( storage_4_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4255 1241 ) ( * 1275 ) + NEW met1 ( 4209 1275 ) ( 4255 * ) + NEW li1 ( 4255 1241 ) L1M1_PR_MR + NEW li1 ( 4209 1275 ) L1M1_PR_MR ; + - storage_4_0_0.bit4.storage ( storage_4_0_0.bit4.obuf0 A ) ( storage_4_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5405 1241 ) ( * 1275 ) + NEW met1 ( 5359 1275 ) ( 5405 * ) + NEW li1 ( 5405 1241 ) L1M1_PR_MR + NEW li1 ( 5359 1275 ) L1M1_PR_MR ; + - storage_4_0_0.bit5.storage ( storage_4_0_0.bit5.obuf0 A ) ( storage_4_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6555 1241 ) ( * 1275 ) + NEW met1 ( 6509 1275 ) ( 6555 * ) + NEW li1 ( 6555 1241 ) L1M1_PR_MR + NEW li1 ( 6509 1275 ) L1M1_PR_MR ; + - storage_4_0_0.bit6.storage ( storage_4_0_0.bit6.obuf0 A ) ( storage_4_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7705 1241 ) ( * 1275 ) + NEW met1 ( 7659 1275 ) ( 7705 * ) + NEW li1 ( 7705 1241 ) L1M1_PR_MR + NEW li1 ( 7659 1275 ) L1M1_PR_MR ; + - storage_4_0_0.bit7.storage ( storage_4_0_0.bit7.obuf0 A ) ( storage_4_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8855 1241 ) ( * 1275 ) + NEW met1 ( 8809 1275 ) ( 8855 * ) + NEW li1 ( 8855 1241 ) L1M1_PR_MR + NEW li1 ( 8809 1275 ) L1M1_PR_MR ; + - storage_4_0_0.gclock ( storage_4_0_0.cg GCLK ) ( storage_4_0_0.bit7.bit CLK ) ( storage_4_0_0.bit6.bit CLK ) ( storage_4_0_0.bit5.bit CLK ) ( storage_4_0_0.bit4.bit CLK ) ( storage_4_0_0.bit3.bit CLK ) ( storage_4_0_0.bit2.bit CLK ) + ( storage_4_0_0.bit1.bit CLK ) ( storage_4_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 1219 1241 ) ( * 1309 ) + NEW met1 ( 69 1173 ) ( * 1207 ) + NEW met1 ( 69 1173 ) ( 851 * ) + NEW met1 ( 851 1173 ) ( * 1241 ) + NEW met1 ( 851 1241 ) ( 1219 * ) + NEW met1 ( 6969 1173 ) ( * 1207 ) + NEW met1 ( 2185 1241 ) ( 2369 * ) + NEW met1 ( 2185 1241 ) ( * 1309 ) + NEW met1 ( 3381 1241 ) ( 3519 * ) + NEW met1 ( 3381 1241 ) ( * 1309 ) + NEW met1 ( 2369 1309 ) ( 3381 * ) + NEW met1 ( 2369 1241 ) ( * 1309 ) + NEW met1 ( 4485 1241 ) ( 4669 * ) + NEW met1 ( 4485 1241 ) ( * 1309 ) + NEW met1 ( 3519 1309 ) ( 4485 * ) + NEW met1 ( 3519 1241 ) ( * 1309 ) + NEW met1 ( 5819 1241 ) ( * 1275 ) + NEW met1 ( 5681 1275 ) ( 5819 * ) + NEW met1 ( 5681 1275 ) ( * 1309 ) + NEW met1 ( 4669 1309 ) ( 5681 * ) + NEW met1 ( 4669 1241 ) ( * 1309 ) + NEW met1 ( 5819 1173 ) ( * 1241 ) + NEW met1 ( 1219 1309 ) ( 2185 * ) + NEW met1 ( 5819 1173 ) ( 6969 * ) + NEW met1 ( 8119 1139 ) ( * 1207 ) + NEW met1 ( 8119 1139 ) ( 9867 * ) + NEW met1 ( 6969 1173 ) ( 8119 * ) + NEW li1 ( 1219 1241 ) L1M1_PR_MR + NEW li1 ( 69 1207 ) L1M1_PR_MR + NEW li1 ( 6969 1207 ) L1M1_PR_MR + NEW li1 ( 2369 1241 ) L1M1_PR_MR + NEW li1 ( 3519 1241 ) L1M1_PR_MR + NEW li1 ( 4669 1241 ) L1M1_PR_MR + NEW li1 ( 5819 1241 ) L1M1_PR_MR + NEW li1 ( 8119 1207 ) L1M1_PR_MR + NEW li1 ( 9867 1139 ) L1M1_PR_MR ; + - storage_4_0_0.select0_b ( storage_4_0_0.select_inv_0 Y ) ( storage_4_0_0.bit7.obuf0 TE_B ) ( storage_4_0_0.bit6.obuf0 TE_B ) ( storage_4_0_0.bit5.obuf0 TE_B ) ( storage_4_0_0.bit4.obuf0 TE_B ) ( storage_4_0_0.bit3.obuf0 TE_B ) ( storage_4_0_0.bit2.obuf0 TE_B ) + ( storage_4_0_0.bit1.obuf0 TE_B ) ( storage_4_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 897 1173 ) ( * 1207 ) + NEW met1 ( 6647 1241 ) ( * 1309 ) + NEW met1 ( 6969 1275 ) ( * 1309 ) + NEW met1 ( 6647 1275 ) ( 6969 * ) + NEW met1 ( 5497 1241 ) ( 5773 * ) + NEW met2 ( 5773 1241 ) ( * 1309 ) + NEW met1 ( 4347 1173 ) ( * 1207 ) + NEW met1 ( 4347 1173 ) ( 5497 * ) + NEW met1 ( 5497 1173 ) ( * 1241 ) + NEW met1 ( 3197 1173 ) ( * 1207 ) + NEW met1 ( 3197 1173 ) ( 4347 * ) + NEW met1 ( 2047 1173 ) ( * 1207 ) + NEW met1 ( 2047 1173 ) ( 3197 * ) + NEW met1 ( 897 1173 ) ( 2047 * ) + NEW met1 ( 5773 1309 ) ( 6647 * ) + NEW met1 ( 8947 1241 ) ( * 1275 ) + NEW met1 ( 8947 1275 ) ( 10189 * ) + NEW met1 ( 7797 1241 ) ( 8119 * ) + NEW met1 ( 8119 1241 ) ( * 1309 ) + NEW met1 ( 8119 1309 ) ( 8947 * ) + NEW met1 ( 8947 1275 ) ( * 1309 ) + NEW met1 ( 7797 1241 ) ( * 1309 ) + NEW met1 ( 6969 1309 ) ( 7797 * ) + NEW li1 ( 897 1207 ) L1M1_PR_MR + NEW li1 ( 6647 1241 ) L1M1_PR_MR + NEW li1 ( 5497 1241 ) L1M1_PR_MR + NEW met1 ( 5773 1241 ) M1M2_PR + NEW met1 ( 5773 1309 ) M1M2_PR + NEW li1 ( 4347 1207 ) L1M1_PR_MR + NEW li1 ( 3197 1207 ) L1M1_PR_MR + NEW li1 ( 2047 1207 ) L1M1_PR_MR + NEW li1 ( 8947 1241 ) L1M1_PR_MR + NEW li1 ( 10189 1275 ) L1M1_PR_MR + NEW li1 ( 7797 1241 ) L1M1_PR_MR ; + - storage_4_0_0.we0 ( storage_4_0_0.gcand X ) ( storage_4_0_0.cg GATE ) + USE SIGNAL + + ROUTED met2 ( 9453 1241 ) ( * 1309 ) + NEW met1 ( 9453 1309 ) ( 10097 * ) + NEW li1 ( 9453 1241 ) L1M1_PR_MR + NEW met1 ( 9453 1241 ) M1M2_PR + NEW met1 ( 9453 1309 ) M1M2_PR + NEW li1 ( 10097 1309 ) L1M1_PR_MR ; + - storage_5_0_0.bit0.storage ( storage_5_0_0.bit0.obuf0 A ) ( storage_5_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 759 1479 ) ( 805 * ) + NEW met1 ( 759 1445 ) ( * 1479 ) + NEW li1 ( 805 1479 ) L1M1_PR_MR + NEW li1 ( 759 1445 ) L1M1_PR_MR ; + - storage_5_0_0.bit1.storage ( storage_5_0_0.bit1.obuf0 A ) ( storage_5_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1909 1479 ) ( 1955 * ) + NEW met1 ( 1909 1445 ) ( * 1479 ) + NEW li1 ( 1955 1479 ) L1M1_PR_MR + NEW li1 ( 1909 1445 ) L1M1_PR_MR ; + - storage_5_0_0.bit2.storage ( storage_5_0_0.bit2.obuf0 A ) ( storage_5_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3059 1479 ) ( 3105 * ) + NEW met1 ( 3059 1445 ) ( * 1479 ) + NEW li1 ( 3105 1479 ) L1M1_PR_MR + NEW li1 ( 3059 1445 ) L1M1_PR_MR ; + - storage_5_0_0.bit3.storage ( storage_5_0_0.bit3.obuf0 A ) ( storage_5_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4209 1479 ) ( 4255 * ) + NEW met1 ( 4209 1445 ) ( * 1479 ) + NEW li1 ( 4255 1479 ) L1M1_PR_MR + NEW li1 ( 4209 1445 ) L1M1_PR_MR ; + - storage_5_0_0.bit4.storage ( storage_5_0_0.bit4.obuf0 A ) ( storage_5_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5359 1479 ) ( 5405 * ) + NEW met1 ( 5359 1445 ) ( * 1479 ) + NEW li1 ( 5405 1479 ) L1M1_PR_MR + NEW li1 ( 5359 1445 ) L1M1_PR_MR ; + - storage_5_0_0.bit5.storage ( storage_5_0_0.bit5.obuf0 A ) ( storage_5_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6509 1479 ) ( 6555 * ) + NEW met1 ( 6509 1445 ) ( * 1479 ) + NEW li1 ( 6555 1479 ) L1M1_PR_MR + NEW li1 ( 6509 1445 ) L1M1_PR_MR ; + - storage_5_0_0.bit6.storage ( storage_5_0_0.bit6.obuf0 A ) ( storage_5_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7659 1479 ) ( 7705 * ) + NEW met1 ( 7659 1445 ) ( * 1479 ) + NEW li1 ( 7705 1479 ) L1M1_PR_MR + NEW li1 ( 7659 1445 ) L1M1_PR_MR ; + - storage_5_0_0.bit7.storage ( storage_5_0_0.bit7.obuf0 A ) ( storage_5_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8809 1479 ) ( 8855 * ) + NEW met1 ( 8809 1445 ) ( * 1479 ) + NEW li1 ( 8855 1479 ) L1M1_PR_MR + NEW li1 ( 8809 1445 ) L1M1_PR_MR ; + - storage_5_0_0.gclock ( storage_5_0_0.cg GCLK ) ( storage_5_0_0.bit7.bit CLK ) ( storage_5_0_0.bit6.bit CLK ) ( storage_5_0_0.bit5.bit CLK ) ( storage_5_0_0.bit4.bit CLK ) ( storage_5_0_0.bit3.bit CLK ) ( storage_5_0_0.bit2.bit CLK ) + ( storage_5_0_0.bit1.bit CLK ) ( storage_5_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 1219 1411 ) ( * 1479 ) + NEW met1 ( 69 1513 ) ( 851 * ) + NEW met1 ( 851 1479 ) ( * 1513 ) + NEW met1 ( 851 1479 ) ( 1219 * ) + NEW met1 ( 6969 1513 ) ( 7153 * ) + NEW met1 ( 7153 1513 ) ( * 1547 ) + NEW met1 ( 6969 1411 ) ( * 1513 ) + NEW met1 ( 2369 1411 ) ( * 1479 ) + NEW met1 ( 3519 1411 ) ( * 1479 ) + NEW met1 ( 2369 1411 ) ( 3519 * ) + NEW met1 ( 4669 1411 ) ( * 1479 ) + NEW met1 ( 3519 1411 ) ( 4669 * ) + NEW met1 ( 5819 1411 ) ( * 1479 ) + NEW met1 ( 4669 1411 ) ( 5819 * ) + NEW met1 ( 1219 1411 ) ( 2369 * ) + NEW met1 ( 5819 1411 ) ( 6969 * ) + NEW met1 ( 8119 1513 ) ( 9223 * ) + NEW met1 ( 9223 1513 ) ( * 1581 ) + NEW met1 ( 9223 1581 ) ( 9867 * ) + NEW met1 ( 8119 1513 ) ( * 1547 ) + NEW met1 ( 7153 1547 ) ( 8119 * ) + NEW li1 ( 1219 1479 ) L1M1_PR_MR + NEW li1 ( 69 1513 ) L1M1_PR_MR + NEW li1 ( 6969 1513 ) L1M1_PR_MR + NEW li1 ( 2369 1479 ) L1M1_PR_MR + NEW li1 ( 3519 1479 ) L1M1_PR_MR + NEW li1 ( 4669 1479 ) L1M1_PR_MR + NEW li1 ( 5819 1479 ) L1M1_PR_MR + NEW li1 ( 8119 1513 ) L1M1_PR_MR + NEW li1 ( 9867 1581 ) L1M1_PR_MR ; + - storage_5_0_0.select0_b ( storage_5_0_0.select_inv_0 Y ) ( storage_5_0_0.bit7.obuf0 TE_B ) ( storage_5_0_0.bit6.obuf0 TE_B ) ( storage_5_0_0.bit5.obuf0 TE_B ) ( storage_5_0_0.bit4.obuf0 TE_B ) ( storage_5_0_0.bit3.obuf0 TE_B ) ( storage_5_0_0.bit2.obuf0 TE_B ) + ( storage_5_0_0.bit1.obuf0 TE_B ) ( storage_5_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 6647 1513 ) ( 6923 * ) + NEW met1 ( 6923 1513 ) ( * 1581 ) + NEW met1 ( 6210 1513 ) ( 6647 * ) + NEW met1 ( 5497 1513 ) ( * 1547 ) + NEW met1 ( 5497 1547 ) ( 6210 * ) + NEW met1 ( 6210 1513 ) ( * 1547 ) + NEW met1 ( 4347 1513 ) ( 5497 * ) + NEW met1 ( 3197 1513 ) ( 4347 * ) + NEW met1 ( 2047 1513 ) ( 3197 * ) + NEW met1 ( 897 1513 ) ( 2047 * ) + NEW met1 ( 8947 1445 ) ( * 1479 ) + NEW met1 ( 8947 1445 ) ( 10189 * ) + NEW met1 ( 7797 1411 ) ( * 1479 ) + NEW met1 ( 7797 1411 ) ( 8947 * ) + NEW met1 ( 8947 1411 ) ( * 1445 ) + NEW met2 ( 7797 1479 ) ( * 1581 ) + NEW met1 ( 6923 1581 ) ( 7797 * ) + NEW li1 ( 897 1513 ) L1M1_PR_MR + NEW li1 ( 6647 1513 ) L1M1_PR_MR + NEW li1 ( 5497 1513 ) L1M1_PR_MR + NEW li1 ( 4347 1513 ) L1M1_PR_MR + NEW li1 ( 3197 1513 ) L1M1_PR_MR + NEW li1 ( 2047 1513 ) L1M1_PR_MR + NEW li1 ( 8947 1479 ) L1M1_PR_MR + NEW li1 ( 10189 1445 ) L1M1_PR_MR + NEW li1 ( 7797 1479 ) L1M1_PR_MR + NEW met1 ( 7797 1581 ) M1M2_PR + NEW met1 ( 7797 1479 ) M1M2_PR ; + - storage_5_0_0.we0 ( storage_5_0_0.gcand X ) ( storage_5_0_0.cg GATE ) + USE SIGNAL + + ROUTED met2 ( 9453 1411 ) ( * 1479 ) + NEW met1 ( 9453 1411 ) ( 10097 * ) + NEW li1 ( 9453 1479 ) L1M1_PR_MR + NEW met1 ( 9453 1479 ) M1M2_PR + NEW met1 ( 9453 1411 ) M1M2_PR + NEW li1 ( 10097 1411 ) L1M1_PR_MR ; + - storage_6_0_0.bit0.storage ( storage_6_0_0.bit0.obuf0 A ) ( storage_6_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 805 1785 ) ( * 1819 ) + NEW met1 ( 759 1819 ) ( 805 * ) + NEW li1 ( 805 1785 ) L1M1_PR_MR + NEW li1 ( 759 1819 ) L1M1_PR_MR ; + - storage_6_0_0.bit1.storage ( storage_6_0_0.bit1.obuf0 A ) ( storage_6_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1955 1785 ) ( * 1819 ) + NEW met1 ( 1909 1819 ) ( 1955 * ) + NEW li1 ( 1955 1785 ) L1M1_PR_MR + NEW li1 ( 1909 1819 ) L1M1_PR_MR ; + - storage_6_0_0.bit2.storage ( storage_6_0_0.bit2.obuf0 A ) ( storage_6_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3105 1785 ) ( * 1819 ) + NEW met1 ( 3059 1819 ) ( 3105 * ) + NEW li1 ( 3105 1785 ) L1M1_PR_MR + NEW li1 ( 3059 1819 ) L1M1_PR_MR ; + - storage_6_0_0.bit3.storage ( storage_6_0_0.bit3.obuf0 A ) ( storage_6_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4255 1785 ) ( * 1819 ) + NEW met1 ( 4209 1819 ) ( 4255 * ) + NEW li1 ( 4255 1785 ) L1M1_PR_MR + NEW li1 ( 4209 1819 ) L1M1_PR_MR ; + - storage_6_0_0.bit4.storage ( storage_6_0_0.bit4.obuf0 A ) ( storage_6_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5405 1785 ) ( * 1819 ) + NEW met1 ( 5359 1819 ) ( 5405 * ) + NEW li1 ( 5405 1785 ) L1M1_PR_MR + NEW li1 ( 5359 1819 ) L1M1_PR_MR ; + - storage_6_0_0.bit5.storage ( storage_6_0_0.bit5.obuf0 A ) ( storage_6_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6555 1785 ) ( * 1819 ) + NEW met1 ( 6509 1819 ) ( 6555 * ) + NEW li1 ( 6555 1785 ) L1M1_PR_MR + NEW li1 ( 6509 1819 ) L1M1_PR_MR ; + - storage_6_0_0.bit6.storage ( storage_6_0_0.bit6.obuf0 A ) ( storage_6_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7705 1785 ) ( * 1819 ) + NEW met1 ( 7659 1819 ) ( 7705 * ) + NEW li1 ( 7705 1785 ) L1M1_PR_MR + NEW li1 ( 7659 1819 ) L1M1_PR_MR ; + - storage_6_0_0.bit7.storage ( storage_6_0_0.bit7.obuf0 A ) ( storage_6_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8855 1785 ) ( * 1819 ) + NEW met1 ( 8809 1819 ) ( 8855 * ) + NEW li1 ( 8855 1785 ) L1M1_PR_MR + NEW li1 ( 8809 1819 ) L1M1_PR_MR ; + - storage_6_0_0.gclock ( storage_6_0_0.cg GCLK ) ( storage_6_0_0.bit7.bit CLK ) ( storage_6_0_0.bit6.bit CLK ) ( storage_6_0_0.bit5.bit CLK ) ( storage_6_0_0.bit4.bit CLK ) ( storage_6_0_0.bit3.bit CLK ) ( storage_6_0_0.bit2.bit CLK ) + ( storage_6_0_0.bit1.bit CLK ) ( storage_6_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 1219 1683 ) ( * 1751 ) + NEW met1 ( 69 1717 ) ( * 1751 ) + NEW met1 ( 69 1717 ) ( 1219 * ) + NEW met1 ( 6969 1717 ) ( * 1751 ) + NEW met1 ( 6969 1683 ) ( * 1717 ) + NEW met1 ( 3381 1785 ) ( 3519 * ) + NEW met1 ( 3381 1785 ) ( * 1853 ) + NEW met1 ( 4485 1751 ) ( 4669 * ) + NEW met1 ( 4485 1751 ) ( * 1853 ) + NEW met1 ( 3519 1853 ) ( 4485 * ) + NEW met1 ( 3519 1785 ) ( * 1853 ) + NEW met1 ( 4715 1717 ) ( * 1751 ) + NEW met1 ( 4669 1751 ) ( 4715 * ) + NEW met1 ( 5819 1683 ) ( * 1751 ) + NEW met1 ( 5819 1683 ) ( 6969 * ) + NEW met2 ( 2277 1683 ) ( * 1853 ) + NEW met1 ( 2369 1751 ) ( 2415 * ) + NEW met2 ( 2415 1683 ) ( * 1751 ) + NEW met1 ( 2277 1683 ) ( 2415 * ) + NEW met1 ( 1219 1683 ) ( 2277 * ) + NEW met1 ( 2277 1853 ) ( 3381 * ) + NEW met1 ( 5520 1751 ) ( 5819 * ) + NEW met1 ( 5520 1717 ) ( * 1751 ) + NEW met1 ( 4715 1717 ) ( 5520 * ) + NEW met1 ( 8119 1683 ) ( * 1751 ) + NEW met1 ( 8119 1683 ) ( 9867 * ) + NEW met1 ( 6969 1717 ) ( 8119 * ) + NEW li1 ( 1219 1751 ) L1M1_PR_MR + NEW li1 ( 69 1751 ) L1M1_PR_MR + NEW li1 ( 6969 1751 ) L1M1_PR_MR + NEW li1 ( 3519 1785 ) L1M1_PR_MR + NEW li1 ( 4669 1751 ) L1M1_PR_MR + NEW li1 ( 5819 1751 ) L1M1_PR_MR + NEW met1 ( 2277 1683 ) M1M2_PR + NEW met1 ( 2277 1853 ) M1M2_PR + NEW li1 ( 2369 1751 ) L1M1_PR_MR + NEW met1 ( 2415 1751 ) M1M2_PR + NEW met1 ( 2415 1683 ) M1M2_PR + NEW li1 ( 8119 1751 ) L1M1_PR_MR + NEW li1 ( 9867 1683 ) L1M1_PR_MR ; + - storage_6_0_0.select0_b ( storage_6_0_0.select_inv_0 Y ) ( storage_6_0_0.bit7.obuf0 TE_B ) ( storage_6_0_0.bit6.obuf0 TE_B ) ( storage_6_0_0.bit5.obuf0 TE_B ) ( storage_6_0_0.bit4.obuf0 TE_B ) ( storage_6_0_0.bit3.obuf0 TE_B ) ( storage_6_0_0.bit2.obuf0 TE_B ) + ( storage_6_0_0.bit1.obuf0 TE_B ) ( storage_6_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 1265 1751 ) ( * 1785 ) + NEW met1 ( 897 1785 ) ( 1265 * ) + NEW met1 ( 6647 1785 ) ( 6877 * ) + NEW met1 ( 6877 1785 ) ( * 1853 ) + NEW met1 ( 6647 1717 ) ( * 1785 ) + NEW met1 ( 6210 1717 ) ( 6647 * ) + NEW met1 ( 5865 1751 ) ( * 1785 ) + NEW met1 ( 5865 1751 ) ( 6210 * ) + NEW met1 ( 6210 1717 ) ( * 1751 ) + NEW met1 ( 4347 1683 ) ( * 1751 ) + NEW met1 ( 3197 1717 ) ( * 1751 ) + NEW met1 ( 3197 1717 ) ( 4347 * ) + NEW met1 ( 1265 1751 ) ( 2047 * ) + NEW met2 ( 2323 1751 ) ( * 1802 ) + NEW met2 ( 2323 1802 ) ( 2461 * ) + NEW met2 ( 2461 1717 ) ( * 1802 ) + NEW met1 ( 2047 1751 ) ( 2323 * ) + NEW met1 ( 2461 1717 ) ( 3197 * ) + NEW met2 ( 5497 1683 ) ( * 1785 ) + NEW met1 ( 4347 1683 ) ( 5497 * ) + NEW met1 ( 5497 1785 ) ( 5865 * ) + NEW met1 ( 8947 1785 ) ( * 1819 ) + NEW met1 ( 8947 1819 ) ( 10189 * ) + NEW met1 ( 7797 1785 ) ( 8119 * ) + NEW met1 ( 8119 1785 ) ( * 1853 ) + NEW met1 ( 8119 1853 ) ( 8947 * ) + NEW met1 ( 8947 1819 ) ( * 1853 ) + NEW met1 ( 7797 1785 ) ( * 1853 ) + NEW met1 ( 6877 1853 ) ( 7797 * ) + NEW li1 ( 897 1785 ) L1M1_PR_MR + NEW li1 ( 6647 1785 ) L1M1_PR_MR + NEW li1 ( 4347 1751 ) L1M1_PR_MR + NEW li1 ( 3197 1751 ) L1M1_PR_MR + NEW li1 ( 2047 1751 ) L1M1_PR_MR + NEW met1 ( 2323 1751 ) M1M2_PR + NEW met1 ( 2461 1717 ) M1M2_PR + NEW met1 ( 5497 1785 ) M1M2_PR + NEW met1 ( 5497 1683 ) M1M2_PR + NEW li1 ( 5497 1785 ) L1M1_PR_MR + NEW li1 ( 8947 1785 ) L1M1_PR_MR + NEW li1 ( 10189 1819 ) L1M1_PR_MR + NEW li1 ( 7797 1785 ) L1M1_PR_MR + NEW met1 ( 5497 1785 ) RECT ( -35 -7 0 7 ) ; + - storage_6_0_0.we0 ( storage_6_0_0.gcand X ) ( storage_6_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 9453 1785 ) ( 9821 * ) + NEW met1 ( 9821 1717 ) ( * 1785 ) + NEW met1 ( 9821 1717 ) ( 10097 * ) + NEW li1 ( 9453 1785 ) L1M1_PR_MR + NEW li1 ( 10097 1717 ) L1M1_PR_MR ; + - storage_7_0_0.bit0.storage ( storage_7_0_0.bit0.obuf0 A ) ( storage_7_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 759 2023 ) ( 805 * ) + NEW met1 ( 759 1989 ) ( * 2023 ) + NEW li1 ( 805 2023 ) L1M1_PR_MR + NEW li1 ( 759 1989 ) L1M1_PR_MR ; + - storage_7_0_0.bit1.storage ( storage_7_0_0.bit1.obuf0 A ) ( storage_7_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1909 2023 ) ( 1955 * ) + NEW met1 ( 1909 1989 ) ( * 2023 ) + NEW li1 ( 1955 2023 ) L1M1_PR_MR + NEW li1 ( 1909 1989 ) L1M1_PR_MR ; + - storage_7_0_0.bit2.storage ( storage_7_0_0.bit2.obuf0 A ) ( storage_7_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3059 2023 ) ( 3105 * ) + NEW met1 ( 3059 1989 ) ( * 2023 ) + NEW li1 ( 3105 2023 ) L1M1_PR_MR + NEW li1 ( 3059 1989 ) L1M1_PR_MR ; + - storage_7_0_0.bit3.storage ( storage_7_0_0.bit3.obuf0 A ) ( storage_7_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4209 2023 ) ( 4255 * ) + NEW met1 ( 4209 1989 ) ( * 2023 ) + NEW li1 ( 4255 2023 ) L1M1_PR_MR + NEW li1 ( 4209 1989 ) L1M1_PR_MR ; + - storage_7_0_0.bit4.storage ( storage_7_0_0.bit4.obuf0 A ) ( storage_7_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5359 2023 ) ( 5405 * ) + NEW met1 ( 5359 1989 ) ( * 2023 ) + NEW li1 ( 5405 2023 ) L1M1_PR_MR + NEW li1 ( 5359 1989 ) L1M1_PR_MR ; + - storage_7_0_0.bit5.storage ( storage_7_0_0.bit5.obuf0 A ) ( storage_7_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6509 2023 ) ( 6555 * ) + NEW met1 ( 6509 1989 ) ( * 2023 ) + NEW li1 ( 6555 2023 ) L1M1_PR_MR + NEW li1 ( 6509 1989 ) L1M1_PR_MR ; + - storage_7_0_0.bit6.storage ( storage_7_0_0.bit6.obuf0 A ) ( storage_7_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7659 2023 ) ( 7705 * ) + NEW met1 ( 7659 1989 ) ( * 2023 ) + NEW li1 ( 7705 2023 ) L1M1_PR_MR + NEW li1 ( 7659 1989 ) L1M1_PR_MR ; + - storage_7_0_0.bit7.storage ( storage_7_0_0.bit7.obuf0 A ) ( storage_7_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8809 2023 ) ( 8855 * ) + NEW met1 ( 8809 1989 ) ( * 2023 ) + NEW li1 ( 8855 2023 ) L1M1_PR_MR + NEW li1 ( 8809 1989 ) L1M1_PR_MR ; + - storage_7_0_0.gclock ( storage_7_0_0.cg GCLK ) ( storage_7_0_0.bit7.bit CLK ) ( storage_7_0_0.bit6.bit CLK ) ( storage_7_0_0.bit5.bit CLK ) ( storage_7_0_0.bit4.bit CLK ) ( storage_7_0_0.bit3.bit CLK ) ( storage_7_0_0.bit2.bit CLK ) + ( storage_7_0_0.bit1.bit CLK ) ( storage_7_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 1219 1955 ) ( * 2023 ) + NEW met1 ( 69 1955 ) ( * 2023 ) + NEW met1 ( 69 1955 ) ( 1219 * ) + NEW met1 ( 6969 1955 ) ( * 2023 ) + NEW met1 ( 2369 1955 ) ( * 2023 ) + NEW met1 ( 3519 1955 ) ( * 2023 ) + NEW met1 ( 2369 1955 ) ( 3519 * ) + NEW met1 ( 4669 1955 ) ( * 2023 ) + NEW met1 ( 3519 1955 ) ( 4669 * ) + NEW met1 ( 5819 1955 ) ( * 2023 ) + NEW met1 ( 4669 1955 ) ( 5819 * ) + NEW met1 ( 1219 1955 ) ( 2369 * ) + NEW met1 ( 5819 1955 ) ( 6969 * ) + NEW met1 ( 8119 1955 ) ( * 2023 ) + NEW met1 ( 8119 1955 ) ( 9867 * ) + NEW met1 ( 6969 1955 ) ( 8119 * ) + NEW li1 ( 1219 2023 ) L1M1_PR_MR + NEW li1 ( 69 2023 ) L1M1_PR_MR + NEW li1 ( 6969 2023 ) L1M1_PR_MR + NEW li1 ( 2369 2023 ) L1M1_PR_MR + NEW li1 ( 3519 2023 ) L1M1_PR_MR + NEW li1 ( 4669 2023 ) L1M1_PR_MR + NEW li1 ( 5819 2023 ) L1M1_PR_MR + NEW li1 ( 8119 2023 ) L1M1_PR_MR + NEW li1 ( 9867 1955 ) L1M1_PR_MR ; + - storage_7_0_0.select0_b ( storage_7_0_0.select_inv_0 Y ) ( storage_7_0_0.bit7.obuf0 TE_B ) ( storage_7_0_0.bit6.obuf0 TE_B ) ( storage_7_0_0.bit5.obuf0 TE_B ) ( storage_7_0_0.bit4.obuf0 TE_B ) ( storage_7_0_0.bit3.obuf0 TE_B ) ( storage_7_0_0.bit2.obuf0 TE_B ) + ( storage_7_0_0.bit1.obuf0 TE_B ) ( storage_7_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 897 2057 ) ( * 2091 ) + NEW met1 ( 6647 2057 ) ( * 2091 ) + NEW met1 ( 6210 2057 ) ( 6647 * ) + NEW met1 ( 2047 2057 ) ( * 2091 ) + NEW met1 ( 3197 2057 ) ( * 2091 ) + NEW met1 ( 2047 2091 ) ( 3197 * ) + NEW met1 ( 4347 2057 ) ( * 2091 ) + NEW met1 ( 3197 2091 ) ( 4347 * ) + NEW met1 ( 5497 2057 ) ( * 2091 ) + NEW met1 ( 4347 2091 ) ( 5497 * ) + NEW met1 ( 6210 2057 ) ( * 2091 ) + NEW met1 ( 5497 2091 ) ( 6210 * ) + NEW met1 ( 897 2091 ) ( 2047 * ) + NEW met1 ( 8947 1989 ) ( * 2023 ) + NEW met1 ( 8947 1989 ) ( 10189 * ) + NEW met1 ( 7797 2057 ) ( * 2091 ) + NEW met1 ( 7797 2091 ) ( 8947 * ) + NEW met1 ( 8947 2023 ) ( * 2091 ) + NEW met1 ( 6647 2091 ) ( 7797 * ) + NEW li1 ( 897 2057 ) L1M1_PR_MR + NEW li1 ( 6647 2057 ) L1M1_PR_MR + NEW li1 ( 2047 2057 ) L1M1_PR_MR + NEW li1 ( 3197 2057 ) L1M1_PR_MR + NEW li1 ( 4347 2057 ) L1M1_PR_MR + NEW li1 ( 5497 2057 ) L1M1_PR_MR + NEW li1 ( 8947 2023 ) L1M1_PR_MR + NEW li1 ( 10189 1989 ) L1M1_PR_MR + NEW li1 ( 7797 2057 ) L1M1_PR_MR ; + - storage_7_0_0.we0 ( storage_7_0_0.gcand X ) ( storage_7_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 9453 2125 ) ( 10097 * ) + NEW li1 ( 9453 2125 ) L1M1_PR_MR + NEW li1 ( 10097 2125 ) L1M1_PR_MR ; + - we[0] ( PIN we[0] ) ( storage_7_0_0.gcand B ) ( storage_6_0_0.gcand B ) ( storage_5_0_0.gcand B ) ( storage_4_0_0.gcand B ) ( storage_3_0_0.gcand B ) ( storage_2_0_0.gcand B ) + ( storage_1_0_0.gcand B ) ( storage_0_0_0.gcand B ) + USE SIGNAL + + ROUTED met1 ( 10005 391 ) ( 10097 * ) + NEW met2 ( 10097 306 ) ( * 391 ) + NEW met3 ( 10097 306 ) ( 10994 * 0 ) + NEW met1 ( 10005 119 ) ( 10051 * ) + NEW met2 ( 10051 119 ) ( * 306 ) + NEW met2 ( 10051 306 ) ( 10097 * ) + NEW met1 ( 10005 663 ) ( 10051 * ) + NEW met2 ( 10051 306 ) ( * 663 ) + NEW met1 ( 10005 935 ) ( 10051 * ) + NEW met2 ( 10051 663 ) ( * 935 ) + NEW met1 ( 10005 1207 ) ( 10051 * ) + NEW met2 ( 10051 935 ) ( * 1207 ) + NEW met1 ( 10005 1479 ) ( 10051 * ) + NEW met2 ( 10051 1207 ) ( * 1479 ) + NEW met1 ( 10005 1751 ) ( 10051 * ) + NEW met2 ( 10051 1479 ) ( * 1751 ) + NEW met1 ( 10005 2023 ) ( 10051 * ) + NEW met2 ( 10051 1751 ) ( * 2023 ) + NEW li1 ( 10005 391 ) L1M1_PR_MR + NEW met1 ( 10097 391 ) M1M2_PR + NEW met2 ( 10097 306 ) M2M3_PR + NEW li1 ( 10005 119 ) L1M1_PR_MR + NEW met1 ( 10051 119 ) M1M2_PR + NEW li1 ( 10005 663 ) L1M1_PR_MR + NEW met1 ( 10051 663 ) M1M2_PR + NEW li1 ( 10005 935 ) L1M1_PR_MR + NEW met1 ( 10051 935 ) M1M2_PR + NEW li1 ( 10005 1207 ) L1M1_PR_MR + NEW met1 ( 10051 1207 ) M1M2_PR + NEW li1 ( 10005 1479 ) L1M1_PR_MR + NEW met1 ( 10051 1479 ) M1M2_PR + NEW li1 ( 10005 1751 ) L1M1_PR_MR + NEW met1 ( 10051 1751 ) M1M2_PR + NEW li1 ( 10005 2023 ) L1M1_PR_MR + NEW met1 ( 10051 2023 ) M1M2_PR ; +END NETS +END DESIGN diff --git a/src/ram/test/make_8x8.lefok b/src/ram/test/make_8x8.lefok new file mode 100644 index 00000000000..31b51310f11 --- /dev/null +++ b/src/ram/test/make_8x8.lefok @@ -0,0 +1,281 @@ +VERSION 5.8 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MACRO RAM8x8 + FOREIGN RAM8x8 0 0 ; + CLASS BLOCK ; + SIZE 110.4 BY 24.48 ; + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 109.6 1.55 110.4 1.85 ; + END + END clk + PIN we[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 109.6 2.91 110.4 3.21 ; + END + END we[0] + PIN addr_rw[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 109.6 4.27 110.4 4.57 ; + END + END addr_rw[0] + PIN addr_rw[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 109.6 6.99 110.4 7.29 ; + END + END addr_rw[1] + PIN addr_rw[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 109.6 5.63 110.4 5.93 ; + END + END addr_rw[2] + PIN D[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 1.08 23.995 1.22 24.48 ; + END + END D[0] + PIN Q[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 23.995 11.34 24.48 ; + END + END Q[0] + PIN D[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 23.995 12.26 24.48 ; + END + END D[1] + PIN Q[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 23.995 22.38 24.48 ; + END + END Q[1] + PIN D[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 23.995 24.22 24.48 ; + END + END D[2] + PIN Q[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.2 23.995 34.34 24.48 ; + END + END Q[2] + PIN D[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 23.995 35.26 24.48 ; + END + END D[3] + PIN Q[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 23.995 45.38 24.48 ; + END + END Q[3] + PIN D[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 23.995 47.22 24.48 ; + END + END D[4] + PIN Q[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 23.995 57.34 24.48 ; + END + END Q[4] + PIN D[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 23.995 58.26 24.48 ; + END + END D[5] + PIN Q[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 23.995 68.38 24.48 ; + END + END Q[5] + PIN D[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.08 23.995 70.22 24.48 ; + END + END D[6] + PIN Q[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.2 23.995 80.34 24.48 ; + END + END Q[6] + PIN D[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.12 23.995 81.26 24.48 ; + END + END D[7] + PIN Q[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 91.24 23.995 91.38 24.48 ; + END + END Q[7] + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met3 ; + RECT 110.1 19.76 110.4 20.24 ; + RECT 0 19.76 0.3 20.24 ; + LAYER met2 ; + RECT 79.76 24.34 80.24 24.48 ; + RECT 79.76 0 80.24 0.14 ; + RECT 39.76 24.34 40.24 24.48 ; + RECT 39.76 0 40.24 0.14 ; + LAYER met1 ; + RECT 110.26 21.52 110.4 22 ; + RECT 0 21.52 0.14 22 ; + RECT 110.26 16.08 110.4 16.56 ; + RECT 0 16.08 0.14 16.56 ; + RECT 110.26 10.64 110.4 11.12 ; + RECT 0 10.64 0.14 11.12 ; + RECT 110.26 5.2 110.4 5.68 ; + RECT 0 5.2 0.14 5.68 ; + RECT 110.26 -0.24 110.4 0.24 ; + RECT 0 -0.24 0.14 0.24 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met3 ; + RECT 110.1 9.76 110.4 10.24 ; + RECT 0 9.76 0.3 10.24 ; + LAYER met2 ; + RECT 99.76 24.34 100.24 24.48 ; + RECT 99.76 0 100.24 0.14 ; + RECT 59.76 24.34 60.24 24.48 ; + RECT 59.76 0 60.24 0.14 ; + RECT 19.76 24.34 20.24 24.48 ; + RECT 19.76 0 20.24 0.14 ; + LAYER met1 ; + RECT 110.26 24.24 110.4 24.72 ; + RECT 0 24.24 0.14 24.72 ; + RECT 110.26 18.8 110.4 19.28 ; + RECT 0 18.8 0.14 19.28 ; + RECT 110.26 13.36 110.4 13.84 ; + RECT 0 13.36 0.14 13.84 ; + RECT 110.26 7.92 110.4 8.4 ; + RECT 0 7.92 0.14 8.4 ; + RECT 110.26 2.48 110.4 2.96 ; + RECT 0 2.48 0.14 2.96 ; + END + END VDD + OBS + LAYER li1 ; + RECT 0 -0.085 110.4 24.565 ; + LAYER met1 ; + RECT 0 -0.24 110.4 24.72 ; + LAYER met2 ; + RECT 59.76 0 60.24 0.27 ; + RECT 57.66 0.27 60.24 0.35 ; + RECT 19.76 0 20.24 1.03 ; + RECT 39.76 -0.24 40.24 1.03 ; + RECT 57.14 0.35 60.24 1.03 ; + RECT 79.76 -0.24 80.24 1.03 ; + RECT 99.76 0 100.24 1.03 ; + RECT 97.62 1.03 109.38 1.37 ; + RECT 1.94 1.03 2.2 2.05 ; + RECT 13.44 1.03 25.2 2.05 ; + RECT 36.44 1.03 60.24 2.05 ; + RECT 70.94 1.03 82.7 2.05 ; + RECT 94.4 1.37 109.38 2.05 ; + RECT 1.94 2.05 109.38 5.595 ; + RECT 1.94 5.595 109.39 10.21 ; + RECT 1.94 10.21 109.84 12.57 ; + RECT 1.94 12.57 109.38 16.99 ; + RECT 1.94 16.99 107.08 20.39 ; + RECT 1.94 20.39 100.24 22.43 ; + RECT 1.02 22.79 1.28 23.11 ; + RECT 11.2 22.43 24.28 23.11 ; + RECT 34.2 22.43 47.28 23.11 ; + RECT 57.2 22.43 70.28 23.11 ; + RECT 79.76 22.43 81.32 23.11 ; + RECT 1.08 23.11 1.22 24.14 ; + RECT 11.2 23.11 24.22 24.14 ; + RECT 34.2 23.11 47.22 24.14 ; + RECT 57.2 23.11 70.22 24.14 ; + RECT 79.76 23.11 81.26 24.14 ; + RECT 91.24 22.43 100.24 24.14 ; + RECT 79.76 24.14 80.8 24.21 ; + RECT 39.76 24.14 40.24 24.48 ; + RECT 79.76 24.21 80.24 24.48 ; + RECT 19.76 24.14 20.24 24.72 ; + RECT 59.76 24.14 60.24 24.72 ; + RECT 99.76 24.14 100.24 24.72 ; + LAYER met3 ; + RECT 0 9.76 97.585 20.24 ; + RECT 97.585 1.535 97.915 20.24 ; + RECT 97.915 1.55 109.94 20.24 ; + RECT 109.94 9.76 110.4 20.24 ; + END +END RAM8x8 +END LIBRARY diff --git a/src/ram/test/make_8x8.ok b/src/ram/test/make_8x8.ok new file mode 100644 index 00000000000..df0295717d7 --- /dev/null +++ b/src/ram/test/make_8x8.ok @@ -0,0 +1,79 @@ +[INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells +[INFO RAM-0003] Generating RAM8x8 +[INFO RAM-0016] Selected inverter cell sky130_fd_sc_hd__clkinv_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__clkinv_1: Y +[INFO RAM-0016] Selected tristate cell sky130_fd_sc_hd__ebufn_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__ebufn_1: Z +[INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__and2_0: X +[INFO RAM-0016] Selected storage cell sky130_fd_sc_hd__dfxtp_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__dfxtp_1: Q +[INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__dlclkp_1: GCLK +[INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__buf_1: X +[INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 +[INFO RAM-0024] Behavioral Verilog written for RAM8x8 +[INFO PDN-0001] Inserting grid: ram_grid +[INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-110.40u at the TOP edge. +[INFO PPL-0067] Restrict pins [ clk we[0] addr_rw[0] addr_rw[1] addr_rw[2] ... ] to region 0.00u-24.48u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 270 +[INFO PPL-0002] Number of I/O 21 +[INFO PPL-0003] Number of I/O w/sink 21 +[INFO PPL-0004] Number of I/O w/o sink 0 +[INFO PPL-0005] Slots per section 200 +[INFO PPL-0008] Successfully assigned pins to sections. +[INFO PPL-0012] I/O nets HPWL: 330.99 um. +[INFO DPL-0001] Placed 48 filler instances. +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[INFO DRT-0167] List of default vias: + Layer via + default via: M1M2_PR + Layer via2 + default via: M2M3_PR + Layer via3 + default via: M3M4_PR + Layer via4 + default via: M4M5_PR +[INFO DRT-0168] Init region query. +[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. +[INFO DRT-0033] FR_VIA shape region query size = 0. +[INFO DRT-0033] li1 shape region query size = 7559. +[INFO DRT-0033] mcon shape region query size = 564. +[INFO DRT-0033] met1 shape region query size = 1257. +[INFO DRT-0033] via shape region query size = 25. +[INFO DRT-0033] met2 shape region query size = 61. +[INFO DRT-0033] via2 shape region query size = 5. +[INFO DRT-0033] met3 shape region query size = 16. +[INFO DRT-0033] via3 shape region query size = 0. +[INFO DRT-0033] met4 shape region query size = 0. +[INFO DRT-0033] via4 shape region query size = 0. +[INFO DRT-0033] met5 shape region query size = 0. +[INFO DRT-0178] Init guide query. +[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. +[INFO DRT-0036] FR_VIA guide region query size = 0. +[INFO DRT-0036] li1 guide region query size = 334. +[INFO DRT-0036] mcon guide region query size = 0. +[INFO DRT-0036] met1 guide region query size = 214. +[INFO DRT-0036] via guide region query size = 0. +[INFO DRT-0036] met2 guide region query size = 57. +[INFO DRT-0036] via2 guide region query size = 0. +[INFO DRT-0036] met3 guide region query size = 5. +[INFO DRT-0036] via3 guide region query size = 0. +[INFO DRT-0036] met4 guide region query size = 0. +[INFO DRT-0036] via4 guide region query size = 0. +[INFO DRT-0036] met5 guide region query size = 0. +[INFO DRT-0179] Init gr pin query. +No differences found. +No differences found. +No differences found. diff --git a/src/ram/test/make_8x8.tcl b/src/ram/test/make_8x8.tcl new file mode 100644 index 00000000000..724a62ba075 --- /dev/null +++ b/src/ram/test/make_8x8.tcl @@ -0,0 +1,39 @@ +source "helpers.tcl" + +set_thread_count [expr [cpu_count] / 4] + +read_liberty sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib + +read_lef sky130hd/sky130hd.tlef +read_lef sky130hd/sky130_fd_sc_hd_merged.lef + +set behavioral_file [make_result_file make_8x8_behavioral.v] + +generate_ram \ + -mask_size 8 \ + -word_size 8 \ + -num_words 8 \ + -read_ports 1 \ + -power_pin VPWR \ + -ground_pin VGND \ + -routing_layer {met1 0.48} \ + -ver_layer {met2 0.48 40} \ + -hor_layer {met3 0.48 20} \ + -filler_cells {sky130_fd_sc_hd__fill_1 sky130_fd_sc_hd__fill_2 \ + sky130_fd_sc_hd__fill_4 sky130_fd_sc_hd__fill_8} \ + -tapcell sky130_fd_sc_hd__tap_1 \ + -max_tap_dist 15 \ + -write_behavioral_verilog $behavioral_file + +set verilog_file [make_result_file make_8x8.v] +write_verilog $verilog_file + +set lef_file [make_result_file make_8x8.lef] +write_abstract_lef $lef_file +diff_files make_8x8.lefok $lef_file + +set def_file [make_result_file make_8x8.def] +write_def $def_file +diff_files make_8x8.defok $def_file + +diff_files make_8x8_behavioral.vok $behavioral_file diff --git a/src/ram/test/make_8x8_behavioral.vok b/src/ram/test/make_8x8_behavioral.vok new file mode 100644 index 00000000000..c81b3a42750 --- /dev/null +++ b/src/ram/test/make_8x8_behavioral.vok @@ -0,0 +1,32 @@ +module RAM8x8 ( + clk, + D, + Q, + addr_rw, + we +); + input clk; + input [7:0] D; + output reg [7:0] Q; + input [2:0] addr_rw; + input [0:0] we; + + // memory array declaration + reg [7:0] mem[0:7]; + + // write logic + integer i; + always @(posedge clk) begin + for (i = 0; i < 1; i = i + 1) begin + if (we[i]) begin + mem[addr_rw][i*8 +:8] <= D[i*8 +:8]; + end + end + end + + // read logic + always @(*) begin + Q = mem[addr_rw]; + end + +endmodule diff --git a/src/ram/test/make_8x8_mux2_sky130.defok b/src/ram/test/make_8x8_mux2_sky130.defok new file mode 100644 index 00000000000..342f59a910e --- /dev/null +++ b/src/ram/test/make_8x8_mux2_sky130.defok @@ -0,0 +1,2967 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN RAM8x8 ; +UNITS DISTANCE MICRONS 100 ; +DIEAREA ( 0 0 ) ( 21390 1360 ) ; +ROW RAM_ROW0 unithd 0 0 N DO 465 BY 1 STEP 46 0 ; +ROW RAM_ROW1 unithd 0 272 FS DO 465 BY 1 STEP 46 0 ; +ROW RAM_ROW2 unithd 0 544 N DO 465 BY 1 STEP 46 0 ; +ROW RAM_ROW3 unithd 0 816 FS DO 465 BY 1 STEP 46 0 ; +ROW RAM_ROW4 unithd 0 1088 N DO 465 BY 1 STEP 46 0 ; +TRACKS X 23 DO 465 STEP 46 LAYER li1 ; +TRACKS Y 17 DO 40 STEP 34 LAYER li1 ; +TRACKS X 17 DO 629 STEP 34 LAYER met1 ; +TRACKS Y 17 DO 40 STEP 34 LAYER met1 ; +TRACKS X 23 DO 465 STEP 46 LAYER met2 ; +TRACKS Y 23 DO 29 STEP 46 LAYER met2 ; +TRACKS X 34 DO 314 STEP 68 LAYER met3 ; +TRACKS Y 34 DO 20 STEP 68 LAYER met3 ; +TRACKS X 46 DO 232 STEP 92 LAYER met4 ; +TRACKS Y 46 DO 15 STEP 92 LAYER met4 ; +TRACKS X 170 DO 63 STEP 340 LAYER met5 ; +TRACKS Y 170 DO 4 STEP 340 LAYER met5 ; +GCELLGRID X 0 DO 31 STEP 690 ; +GCELLGRID Y 0 DO 1 STEP 690 ; +VIAS 2 ; + - via2_3_480_480_1_1_320_320 + VIARULE M1M2_PR + CUTSIZE 15 15 + LAYERS met1 via met2 + CUTSPACING 17 17 + ENCLOSURE 8 16 16 8 ; + - via3_4_480_480_1_1_400_400 + VIARULE M2M3_PR + CUTSIZE 20 20 + LAYERS met2 via2 met3 + CUTSPACING 20 20 + ENCLOSURE 14 8 6 14 ; +END VIAS +COMPONENTS 366 ; + - FILLER_1_462 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 21252 272 ) FS ; + - FILLER_1_464 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 21344 272 ) FS ; + - FILLER_3_462 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 21252 816 ) FS ; + - FILLER_3_464 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 21344 816 ) FS ; + - FILLER_4_104 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4784 1088 ) N ; + - FILLER_4_112 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5152 1088 ) N ; + - FILLER_4_12 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 552 1088 ) N ; + - FILLER_4_120 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 5520 1088 ) N ; + - FILLER_4_124 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5704 1088 ) N ; + - FILLER_4_135 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6210 1088 ) N ; + - FILLER_4_143 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 6578 1088 ) N ; + - FILLER_4_147 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 6762 1088 ) N ; + - FILLER_4_149 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 6854 1088 ) N ; + - FILLER_4_154 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7084 1088 ) N ; + - FILLER_4_162 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7452 1088 ) N ; + - FILLER_4_170 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 7820 1088 ) N ; + - FILLER_4_174 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 8004 1088 ) N ; + - FILLER_4_185 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8510 1088 ) N ; + - FILLER_4_193 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8878 1088 ) N ; + - FILLER_4_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 1088 ) N ; + - FILLER_4_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 1088 ) N ; + - FILLER_4_20 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 920 1088 ) N ; + - FILLER_4_204 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 9384 1088 ) N ; + - FILLER_4_212 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 9752 1088 ) N ; + - FILLER_4_220 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 10120 1088 ) N ; + - FILLER_4_224 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 10304 1088 ) N ; + - FILLER_4_235 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 10810 1088 ) N ; + - FILLER_4_24 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 1104 1088 ) N ; + - FILLER_4_243 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 11178 1088 ) N ; + - FILLER_4_247 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 11362 1088 ) N ; + - FILLER_4_249 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 11454 1088 ) N ; + - FILLER_4_254 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 11684 1088 ) N ; + - FILLER_4_262 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 12052 1088 ) N ; + - FILLER_4_270 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 12420 1088 ) N ; + - FILLER_4_274 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 12604 1088 ) N ; + - FILLER_4_285 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 13110 1088 ) N ; + - FILLER_4_293 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 13478 1088 ) N ; + - FILLER_4_297 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 13662 1088 ) N ; + - FILLER_4_299 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 13754 1088 ) N ; + - FILLER_4_304 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 13984 1088 ) N ; + - FILLER_4_312 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 14352 1088 ) N ; + - FILLER_4_320 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 14720 1088 ) N ; + - FILLER_4_324 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 14904 1088 ) N ; + - FILLER_4_335 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 15410 1088 ) N ; + - FILLER_4_343 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 15778 1088 ) N ; + - FILLER_4_347 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 15962 1088 ) N ; + - FILLER_4_349 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 16054 1088 ) N ; + - FILLER_4_35 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1610 1088 ) N ; + - FILLER_4_354 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 16284 1088 ) N ; + - FILLER_4_362 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 16652 1088 ) N ; + - FILLER_4_370 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 17020 1088 ) N ; + - FILLER_4_374 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 17204 1088 ) N ; + - FILLER_4_385 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 17710 1088 ) N ; + - FILLER_4_393 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 18078 1088 ) N ; + - FILLER_4_397 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 18262 1088 ) N ; + - FILLER_4_399 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 18354 1088 ) N ; + - FILLER_4_4 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 184 1088 ) N ; + - FILLER_4_401 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 18446 1088 ) N ; + - FILLER_4_409 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 18814 1088 ) N ; + - FILLER_4_417 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 19182 1088 ) N ; + - FILLER_4_425 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 19550 1088 ) N ; + - FILLER_4_427 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 19642 1088 ) N ; + - FILLER_4_43 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 1978 1088 ) N ; + - FILLER_4_432 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 19872 1088 ) N ; + - FILLER_4_440 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 20240 1088 ) N ; + - FILLER_4_448 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 20608 1088 ) N ; + - FILLER_4_456 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 20976 1088 ) N ; + - FILLER_4_460 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 21160 1088 ) N ; + - FILLER_4_462 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 21252 1088 ) N ; + - FILLER_4_464 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 21344 1088 ) N ; + - FILLER_4_47 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 2162 1088 ) N ; + - FILLER_4_49 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 2254 1088 ) N ; + - FILLER_4_54 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2484 1088 ) N ; + - FILLER_4_62 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2852 1088 ) N ; + - FILLER_4_70 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 3220 1088 ) N ; + - FILLER_4_74 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 3404 1088 ) N ; + - FILLER_4_85 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3910 1088 ) N ; + - FILLER_4_93 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 4278 1088 ) N ; + - FILLER_4_97 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 4462 1088 ) N ; + - FILLER_4_99 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 4554 1088 ) N ; + - buffer.in[0] sky130_fd_sc_hd__buf_1 + PLACED ( 46 1088 ) N ; + - buffer.in[1] sky130_fd_sc_hd__buf_1 + PLACED ( 2346 1088 ) N ; + - buffer.in[2] sky130_fd_sc_hd__buf_1 + PLACED ( 4646 1088 ) N ; + - buffer.in[3] sky130_fd_sc_hd__buf_1 + PLACED ( 6946 1088 ) N ; + - buffer.in[4] sky130_fd_sc_hd__buf_1 + PLACED ( 9246 1088 ) N ; + - buffer.in[5] sky130_fd_sc_hd__buf_1 + PLACED ( 11546 1088 ) N ; + - buffer.in[6] sky130_fd_sc_hd__buf_1 + PLACED ( 13846 1088 ) N ; + - buffer.in[7] sky130_fd_sc_hd__buf_1 + PLACED ( 16146 1088 ) N ; + - decoder.inv_1 sky130_fd_sc_hd__clkinv_1 + PLACED ( 21252 544 ) N ; + - decoder.inv_2 sky130_fd_sc_hd__clkinv_1 + PLACED ( 21252 0 ) N ; + - decoder_0.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 20838 0 ) N ; + - decoder_0.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 21068 0 ) N ; + - decoder_1.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 20838 272 ) FS ; + - decoder_1.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 21068 272 ) FS ; + - decoder_2.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 20838 544 ) N ; + - decoder_2.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 21068 544 ) N ; + - decoder_3.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 20838 816 ) FS ; + - decoder_3.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 21068 816 ) FS ; + - mux_slice0_bit0.aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 1196 1088 ) N ; + - mux_slice0_bit0.inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 1472 1088 ) N ; + - mux_slice0_bit1.aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 3496 1088 ) N ; + - mux_slice0_bit1.inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 3772 1088 ) N ; + - mux_slice0_bit2.aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 5796 1088 ) N ; + - mux_slice0_bit2.inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 6072 1088 ) N ; + - mux_slice0_bit3.aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 8096 1088 ) N ; + - mux_slice0_bit3.inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 8372 1088 ) N ; + - mux_slice0_bit4.aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 10396 1088 ) N ; + - mux_slice0_bit4.inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 10672 1088 ) N ; + - mux_slice0_bit5.aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 12696 1088 ) N ; + - mux_slice0_bit5.inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 12972 1088 ) N ; + - mux_slice0_bit6.aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 14996 1088 ) N ; + - mux_slice0_bit6.inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 15272 1088 ) N ; + - mux_slice0_bit7.aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 17296 1088 ) N ; + - mux_slice0_bit7.inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 17572 1088 ) N ; + - storage_0_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 0 ) N ; + - storage_0_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 0 ) N ; + - storage_0_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 0 ) N ; + - storage_0_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 0 ) N ; + - storage_0_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 0 ) N ; + - storage_0_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 0 ) N ; + - storage_0_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 0 ) N ; + - storage_0_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 0 ) N ; + - storage_0_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 9246 0 ) N ; + - storage_0_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 9982 0 ) N ; + - storage_0_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 11546 0 ) N ; + - storage_0_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 12282 0 ) N ; + - storage_0_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 13846 0 ) N ; + - storage_0_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 14582 0 ) N ; + - storage_0_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 16146 0 ) N ; + - storage_0_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 16882 0 ) N ; + - storage_0_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 18446 0 ) N ; + - storage_0_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 19320 0 ) N ; + - storage_0_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 19550 0 ) N ; + - storage_0_0_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 19090 0 ) N ; + - storage_0_1_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 0 ) N ; + - storage_0_1_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 0 ) N ; + - storage_0_1_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 0 ) N ; + - storage_0_1_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 0 ) N ; + - storage_0_1_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 0 ) N ; + - storage_0_1_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 0 ) N ; + - storage_0_1_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 0 ) N ; + - storage_0_1_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 0 ) N ; + - storage_0_1_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 10396 0 ) N ; + - storage_0_1_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 11132 0 ) N ; + - storage_0_1_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 12696 0 ) N ; + - storage_0_1_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 13432 0 ) N ; + - storage_0_1_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 14996 0 ) N ; + - storage_0_1_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 15732 0 ) N ; + - storage_0_1_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 17296 0 ) N ; + - storage_0_1_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 18032 0 ) N ; + - storage_0_1_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 19734 0 ) N ; + - storage_0_1_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 20608 0 ) N ; + - storage_0_1_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 20378 0 ) N ; + - storage_1_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 272 ) FS ; + - storage_1_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 272 ) FS ; + - storage_1_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 272 ) FS ; + - storage_1_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 272 ) FS ; + - storage_1_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 272 ) FS ; + - storage_1_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 272 ) FS ; + - storage_1_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 272 ) FS ; + - storage_1_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 272 ) FS ; + - storage_1_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 9246 272 ) FS ; + - storage_1_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 9982 272 ) FS ; + - storage_1_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 11546 272 ) FS ; + - storage_1_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 12282 272 ) FS ; + - storage_1_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 13846 272 ) FS ; + - storage_1_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 14582 272 ) FS ; + - storage_1_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 16146 272 ) FS ; + - storage_1_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 16882 272 ) FS ; + - storage_1_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 18446 272 ) FS ; + - storage_1_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 19320 272 ) FS ; + - storage_1_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 19550 272 ) FS ; + - storage_1_0_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 19090 272 ) FS ; + - storage_1_1_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 272 ) FS ; + - storage_1_1_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 272 ) FS ; + - storage_1_1_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 272 ) FS ; + - storage_1_1_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 272 ) FS ; + - storage_1_1_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 272 ) FS ; + - storage_1_1_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 272 ) FS ; + - storage_1_1_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 272 ) FS ; + - storage_1_1_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 272 ) FS ; + - storage_1_1_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 10396 272 ) FS ; + - storage_1_1_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 11132 272 ) FS ; + - storage_1_1_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 12696 272 ) FS ; + - storage_1_1_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 13432 272 ) FS ; + - storage_1_1_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 14996 272 ) FS ; + - storage_1_1_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 15732 272 ) FS ; + - storage_1_1_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 17296 272 ) FS ; + - storage_1_1_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 18032 272 ) FS ; + - storage_1_1_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 19734 272 ) FS ; + - storage_1_1_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 20608 272 ) FS ; + - storage_1_1_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 20378 272 ) FS ; + - storage_2_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 544 ) N ; + - storage_2_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 544 ) N ; + - storage_2_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 544 ) N ; + - storage_2_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 544 ) N ; + - storage_2_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 544 ) N ; + - storage_2_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 544 ) N ; + - storage_2_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 544 ) N ; + - storage_2_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 544 ) N ; + - storage_2_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 9246 544 ) N ; + - storage_2_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 9982 544 ) N ; + - storage_2_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 11546 544 ) N ; + - storage_2_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 12282 544 ) N ; + - storage_2_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 13846 544 ) N ; + - storage_2_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 14582 544 ) N ; + - storage_2_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 16146 544 ) N ; + - storage_2_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 16882 544 ) N ; + - storage_2_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 18446 544 ) N ; + - storage_2_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 19320 544 ) N ; + - storage_2_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 19550 544 ) N ; + - storage_2_0_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 19090 544 ) N ; + - storage_2_1_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 544 ) N ; + - storage_2_1_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 544 ) N ; + - storage_2_1_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 544 ) N ; + - storage_2_1_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 544 ) N ; + - storage_2_1_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 544 ) N ; + - storage_2_1_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 544 ) N ; + - storage_2_1_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 544 ) N ; + - storage_2_1_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 544 ) N ; + - storage_2_1_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 10396 544 ) N ; + - storage_2_1_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 11132 544 ) N ; + - storage_2_1_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 12696 544 ) N ; + - storage_2_1_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 13432 544 ) N ; + - storage_2_1_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 14996 544 ) N ; + - storage_2_1_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 15732 544 ) N ; + - storage_2_1_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 17296 544 ) N ; + - storage_2_1_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 18032 544 ) N ; + - storage_2_1_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 19734 544 ) N ; + - storage_2_1_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 20608 544 ) N ; + - storage_2_1_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 20378 544 ) N ; + - storage_3_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 816 ) FS ; + - storage_3_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 816 ) FS ; + - storage_3_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 816 ) FS ; + - storage_3_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 816 ) FS ; + - storage_3_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 816 ) FS ; + - storage_3_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 816 ) FS ; + - storage_3_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 816 ) FS ; + - storage_3_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 816 ) FS ; + - storage_3_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 9246 816 ) FS ; + - storage_3_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 9982 816 ) FS ; + - storage_3_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 11546 816 ) FS ; + - storage_3_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 12282 816 ) FS ; + - storage_3_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 13846 816 ) FS ; + - storage_3_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 14582 816 ) FS ; + - storage_3_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 16146 816 ) FS ; + - storage_3_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 16882 816 ) FS ; + - storage_3_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 18446 816 ) FS ; + - storage_3_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 19320 816 ) FS ; + - storage_3_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 19550 816 ) FS ; + - storage_3_0_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 19090 816 ) FS ; + - storage_3_1_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 816 ) FS ; + - storage_3_1_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 816 ) FS ; + - storage_3_1_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 816 ) FS ; + - storage_3_1_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 816 ) FS ; + - storage_3_1_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 816 ) FS ; + - storage_3_1_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 816 ) FS ; + - storage_3_1_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 816 ) FS ; + - storage_3_1_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 816 ) FS ; + - storage_3_1_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 10396 816 ) FS ; + - storage_3_1_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 11132 816 ) FS ; + - storage_3_1_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 12696 816 ) FS ; + - storage_3_1_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 13432 816 ) FS ; + - storage_3_1_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 14996 816 ) FS ; + - storage_3_1_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 15732 816 ) FS ; + - storage_3_1_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 17296 816 ) FS ; + - storage_3_1_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 18032 816 ) FS ; + - storage_3_1_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 19734 816 ) FS ; + - storage_3_1_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 20608 816 ) FS ; + - storage_3_1_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 20378 816 ) FS ; + - tapcell.cell0_0 sky130_fd_sc_hd__tap_1 + PLACED ( 0 0 ) N ; + - tapcell.cell0_1 sky130_fd_sc_hd__tap_1 + PLACED ( 0 272 ) FS ; + - tapcell.cell0_2 sky130_fd_sc_hd__tap_1 + PLACED ( 0 544 ) N ; + - tapcell.cell0_3 sky130_fd_sc_hd__tap_1 + PLACED ( 0 816 ) FS ; + - tapcell.cell0_4 sky130_fd_sc_hd__tap_1 + PLACED ( 0 1088 ) N ; + - tapcell.cell10_0 sky130_fd_sc_hd__tap_1 + PLACED ( 11500 0 ) N ; + - tapcell.cell10_1 sky130_fd_sc_hd__tap_1 + PLACED ( 11500 272 ) FS ; + - tapcell.cell10_2 sky130_fd_sc_hd__tap_1 + PLACED ( 11500 544 ) N ; + - tapcell.cell10_3 sky130_fd_sc_hd__tap_1 + PLACED ( 11500 816 ) FS ; + - tapcell.cell10_4 sky130_fd_sc_hd__tap_1 + PLACED ( 11500 1088 ) N ; + - tapcell.cell11_0 sky130_fd_sc_hd__tap_1 + PLACED ( 12650 0 ) N ; + - tapcell.cell11_1 sky130_fd_sc_hd__tap_1 + PLACED ( 12650 272 ) FS ; + - tapcell.cell11_2 sky130_fd_sc_hd__tap_1 + PLACED ( 12650 544 ) N ; + - tapcell.cell11_3 sky130_fd_sc_hd__tap_1 + PLACED ( 12650 816 ) FS ; + - tapcell.cell11_4 sky130_fd_sc_hd__tap_1 + PLACED ( 12650 1088 ) N ; + - tapcell.cell12_0 sky130_fd_sc_hd__tap_1 + PLACED ( 13800 0 ) N ; + - tapcell.cell12_1 sky130_fd_sc_hd__tap_1 + PLACED ( 13800 272 ) FS ; + - tapcell.cell12_2 sky130_fd_sc_hd__tap_1 + PLACED ( 13800 544 ) N ; + - tapcell.cell12_3 sky130_fd_sc_hd__tap_1 + PLACED ( 13800 816 ) FS ; + - tapcell.cell12_4 sky130_fd_sc_hd__tap_1 + PLACED ( 13800 1088 ) N ; + - tapcell.cell13_0 sky130_fd_sc_hd__tap_1 + PLACED ( 14950 0 ) N ; + - tapcell.cell13_1 sky130_fd_sc_hd__tap_1 + PLACED ( 14950 272 ) FS ; + - tapcell.cell13_2 sky130_fd_sc_hd__tap_1 + PLACED ( 14950 544 ) N ; + - tapcell.cell13_3 sky130_fd_sc_hd__tap_1 + PLACED ( 14950 816 ) FS ; + - tapcell.cell13_4 sky130_fd_sc_hd__tap_1 + PLACED ( 14950 1088 ) N ; + - tapcell.cell14_0 sky130_fd_sc_hd__tap_1 + PLACED ( 16100 0 ) N ; + - tapcell.cell14_1 sky130_fd_sc_hd__tap_1 + PLACED ( 16100 272 ) FS ; + - tapcell.cell14_2 sky130_fd_sc_hd__tap_1 + PLACED ( 16100 544 ) N ; + - tapcell.cell14_3 sky130_fd_sc_hd__tap_1 + PLACED ( 16100 816 ) FS ; + - tapcell.cell14_4 sky130_fd_sc_hd__tap_1 + PLACED ( 16100 1088 ) N ; + - tapcell.cell15_0 sky130_fd_sc_hd__tap_1 + PLACED ( 17250 0 ) N ; + - tapcell.cell15_1 sky130_fd_sc_hd__tap_1 + PLACED ( 17250 272 ) FS ; + - tapcell.cell15_2 sky130_fd_sc_hd__tap_1 + PLACED ( 17250 544 ) N ; + - tapcell.cell15_3 sky130_fd_sc_hd__tap_1 + PLACED ( 17250 816 ) FS ; + - tapcell.cell15_4 sky130_fd_sc_hd__tap_1 + PLACED ( 17250 1088 ) N ; + - tapcell.cell16_0 sky130_fd_sc_hd__tap_1 + PLACED ( 18400 0 ) N ; + - tapcell.cell16_1 sky130_fd_sc_hd__tap_1 + PLACED ( 18400 272 ) FS ; + - tapcell.cell16_2 sky130_fd_sc_hd__tap_1 + PLACED ( 18400 544 ) N ; + - tapcell.cell16_3 sky130_fd_sc_hd__tap_1 + PLACED ( 18400 816 ) FS ; + - tapcell.cell16_4 sky130_fd_sc_hd__tap_1 + PLACED ( 18400 1088 ) N ; + - tapcell.cell17_0 sky130_fd_sc_hd__tap_1 + PLACED ( 19688 0 ) N ; + - tapcell.cell17_1 sky130_fd_sc_hd__tap_1 + PLACED ( 19688 272 ) FS ; + - tapcell.cell17_2 sky130_fd_sc_hd__tap_1 + PLACED ( 19688 544 ) N ; + - tapcell.cell17_3 sky130_fd_sc_hd__tap_1 + PLACED ( 19688 816 ) FS ; + - tapcell.cell17_4 sky130_fd_sc_hd__tap_1 + PLACED ( 19688 1088 ) N ; + - tapcell.cell18_0 sky130_fd_sc_hd__tap_1 + PLACED ( 21206 0 ) N ; + - tapcell.cell18_1 sky130_fd_sc_hd__tap_1 + PLACED ( 21206 272 ) FS ; + - tapcell.cell18_2 sky130_fd_sc_hd__tap_1 + PLACED ( 21206 544 ) N ; + - tapcell.cell18_3 sky130_fd_sc_hd__tap_1 + PLACED ( 21206 816 ) FS ; + - tapcell.cell18_4 sky130_fd_sc_hd__tap_1 + PLACED ( 21206 1088 ) N ; + - tapcell.cell1_0 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 0 ) N ; + - tapcell.cell1_1 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 272 ) FS ; + - tapcell.cell1_2 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 544 ) N ; + - tapcell.cell1_3 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 816 ) FS ; + - tapcell.cell1_4 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 1088 ) N ; + - tapcell.cell2_0 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 0 ) N ; + - tapcell.cell2_1 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 272 ) FS ; + - tapcell.cell2_2 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 544 ) N ; + - tapcell.cell2_3 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 816 ) FS ; + - tapcell.cell2_4 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 1088 ) N ; + - tapcell.cell3_0 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 0 ) N ; + - tapcell.cell3_1 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 272 ) FS ; + - tapcell.cell3_2 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 544 ) N ; + - tapcell.cell3_3 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 816 ) FS ; + - tapcell.cell3_4 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 1088 ) N ; + - tapcell.cell4_0 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 0 ) N ; + - tapcell.cell4_1 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 272 ) FS ; + - tapcell.cell4_2 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 544 ) N ; + - tapcell.cell4_3 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 816 ) FS ; + - tapcell.cell4_4 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1088 ) N ; + - tapcell.cell5_0 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 0 ) N ; + - tapcell.cell5_1 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 272 ) FS ; + - tapcell.cell5_2 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 544 ) N ; + - tapcell.cell5_3 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 816 ) FS ; + - tapcell.cell5_4 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 1088 ) N ; + - tapcell.cell6_0 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 0 ) N ; + - tapcell.cell6_1 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 272 ) FS ; + - tapcell.cell6_2 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 544 ) N ; + - tapcell.cell6_3 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 816 ) FS ; + - tapcell.cell6_4 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 1088 ) N ; + - tapcell.cell7_0 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 0 ) N ; + - tapcell.cell7_1 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 272 ) FS ; + - tapcell.cell7_2 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 544 ) N ; + - tapcell.cell7_3 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 816 ) FS ; + - tapcell.cell7_4 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 1088 ) N ; + - tapcell.cell8_0 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 0 ) N ; + - tapcell.cell8_1 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 272 ) FS ; + - tapcell.cell8_2 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 544 ) N ; + - tapcell.cell8_3 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 816 ) FS ; + - tapcell.cell8_4 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 1088 ) N ; + - tapcell.cell9_0 sky130_fd_sc_hd__tap_1 + PLACED ( 10350 0 ) N ; + - tapcell.cell9_1 sky130_fd_sc_hd__tap_1 + PLACED ( 10350 272 ) FS ; + - tapcell.cell9_2 sky130_fd_sc_hd__tap_1 + PLACED ( 10350 544 ) N ; + - tapcell.cell9_3 sky130_fd_sc_hd__tap_1 + PLACED ( 10350 816 ) FS ; + - tapcell.cell9_4 sky130_fd_sc_hd__tap_1 + PLACED ( 10350 1088 ) N ; + - word_sel.inv_addr_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 19734 1088 ) N ; +END COMPONENTS +PINS 23 ; + - D[0] + NET D[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 115 1335 ) N ; + - D[1] + NET D[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 2415 1335 ) N ; + - D[2] + NET D[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 2875 1335 ) N ; + - D[3] + NET D[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 6923 1335 ) N ; + - D[4] + NET D[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 9315 1335 ) N ; + - D[5] + NET D[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 11615 1335 ) N ; + - D[6] + NET D[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 13915 1335 ) N ; + - D[7] + NET D[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 16215 1335 ) N ; + - Q[0] + NET Q[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 1587 1335 ) N ; + - Q[1] + NET Q[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 2783 1335 ) N ; + - Q[2] + NET Q[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 2967 1335 ) N ; + - Q[3] + NET Q[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 8487 1335 ) N ; + - Q[4] + NET Q[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 10787 1335 ) N ; + - Q[5] + NET Q[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 13087 1335 ) N ; + - Q[6] + NET Q[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 15387 1335 ) N ; + - Q[7] + NET Q[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 17687 1335 ) N ; + - VDD + NET VDD + SPECIAL + DIRECTION INOUT + USE POWER + + PORT + + LAYER met3 ( -15 -24 ) ( 15 24 ) + + LAYER met3 ( -21375 -24 ) ( -21345 24 ) + + LAYER met2 ( -399 846 ) ( -351 860 ) + + LAYER met2 ( -399 -500 ) ( -351 -486 ) + + LAYER met2 ( -2399 846 ) ( -2351 860 ) + + LAYER met2 ( -2399 -500 ) ( -2351 -486 ) + + LAYER met2 ( -4399 846 ) ( -4351 860 ) + + LAYER met2 ( -4399 -500 ) ( -4351 -486 ) + + LAYER met2 ( -6399 846 ) ( -6351 860 ) + + LAYER met2 ( -6399 -500 ) ( -6351 -486 ) + + LAYER met2 ( -8399 846 ) ( -8351 860 ) + + LAYER met2 ( -8399 -500 ) ( -8351 -486 ) + + LAYER met2 ( -10399 846 ) ( -10351 860 ) + + LAYER met2 ( -10399 -500 ) ( -10351 -486 ) + + LAYER met2 ( -12399 846 ) ( -12351 860 ) + + LAYER met2 ( -12399 -500 ) ( -12351 -486 ) + + LAYER met2 ( -14399 846 ) ( -14351 860 ) + + LAYER met2 ( -14399 -500 ) ( -14351 -486 ) + + LAYER met2 ( -16399 846 ) ( -16351 860 ) + + LAYER met2 ( -16399 -500 ) ( -16351 -486 ) + + LAYER met2 ( -18399 846 ) ( -18351 860 ) + + LAYER met2 ( -18399 -500 ) ( -18351 -486 ) + + LAYER met2 ( -20399 846 ) ( -20351 860 ) + + LAYER met2 ( -20399 -500 ) ( -20351 -486 ) + + LAYER met1 ( 1 836 ) ( 15 884 ) + + LAYER met1 ( -21375 836 ) ( -21361 884 ) + + LAYER met1 ( 1 292 ) ( 15 340 ) + + LAYER met1 ( -21375 292 ) ( -21361 340 ) + + LAYER met1 ( 1 -252 ) ( 15 -204 ) + + LAYER met1 ( -21375 -252 ) ( -21361 -204 ) + + FIXED ( 21375 500 ) N ; + - VSS + NET VSS + SPECIAL + DIRECTION INOUT + USE GROUND + + PORT + + LAYER met3 ( -15 -24 ) ( 15 24 ) + + LAYER met3 ( -21375 -24 ) ( -21345 24 ) + + LAYER met2 ( -1399 346 ) ( -1351 360 ) + + LAYER met2 ( -1399 -1000 ) ( -1351 -986 ) + + LAYER met2 ( -3399 346 ) ( -3351 360 ) + + LAYER met2 ( -3399 -1000 ) ( -3351 -986 ) + + LAYER met2 ( -5399 346 ) ( -5351 360 ) + + LAYER met2 ( -5399 -1000 ) ( -5351 -986 ) + + LAYER met2 ( -7399 346 ) ( -7351 360 ) + + LAYER met2 ( -7399 -1000 ) ( -7351 -986 ) + + LAYER met2 ( -9399 346 ) ( -9351 360 ) + + LAYER met2 ( -9399 -1000 ) ( -9351 -986 ) + + LAYER met2 ( -11399 346 ) ( -11351 360 ) + + LAYER met2 ( -11399 -1000 ) ( -11351 -986 ) + + LAYER met2 ( -13399 346 ) ( -13351 360 ) + + LAYER met2 ( -13399 -1000 ) ( -13351 -986 ) + + LAYER met2 ( -15399 346 ) ( -15351 360 ) + + LAYER met2 ( -15399 -1000 ) ( -15351 -986 ) + + LAYER met2 ( -17399 346 ) ( -17351 360 ) + + LAYER met2 ( -17399 -1000 ) ( -17351 -986 ) + + LAYER met2 ( -19399 346 ) ( -19351 360 ) + + LAYER met2 ( -19399 -1000 ) ( -19351 -986 ) + + LAYER met1 ( 1 64 ) ( 15 112 ) + + LAYER met1 ( -21375 64 ) ( -21361 112 ) + + LAYER met1 ( 1 -480 ) ( 15 -432 ) + + LAYER met1 ( -21375 -480 ) ( -21361 -432 ) + + LAYER met1 ( 1 -1024 ) ( 15 -976 ) + + LAYER met1 ( -21375 -1024 ) ( -21361 -976 ) + + FIXED ( 21375 1000 ) N ; + - addr_rw[0] + NET addr_rw[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 21350 442 ) N ; + - addr_rw[1] + NET addr_rw[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 21350 578 ) N ; + - addr_rw[2] + NET addr_rw[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 21350 714 ) N ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 21350 170 ) N ; + - we[0] + NET we[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 21350 306 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD ( PIN VDD ) ( tapcell.cell18_4 VPWR ) ( tapcell.cell18_3 VPWR ) ( tapcell.cell18_2 VPWR ) ( tapcell.cell18_1 VPWR ) ( tapcell.cell18_0 VPWR ) ( tapcell.cell17_4 VPWR ) + ( tapcell.cell17_3 VPWR ) ( tapcell.cell17_2 VPWR ) ( tapcell.cell17_1 VPWR ) ( tapcell.cell17_0 VPWR ) ( tapcell.cell16_4 VPWR ) ( tapcell.cell16_3 VPWR ) ( tapcell.cell16_2 VPWR ) ( tapcell.cell16_1 VPWR ) + ( tapcell.cell16_0 VPWR ) ( tapcell.cell15_4 VPWR ) ( tapcell.cell15_3 VPWR ) ( tapcell.cell15_2 VPWR ) ( tapcell.cell15_1 VPWR ) ( tapcell.cell15_0 VPWR ) ( tapcell.cell14_4 VPWR ) ( tapcell.cell14_3 VPWR ) + ( tapcell.cell14_2 VPWR ) ( tapcell.cell14_1 VPWR ) ( tapcell.cell14_0 VPWR ) ( tapcell.cell13_4 VPWR ) ( tapcell.cell13_3 VPWR ) ( tapcell.cell13_2 VPWR ) ( tapcell.cell13_1 VPWR ) ( tapcell.cell13_0 VPWR ) + ( tapcell.cell12_4 VPWR ) ( tapcell.cell12_3 VPWR ) ( tapcell.cell12_2 VPWR ) ( tapcell.cell12_1 VPWR ) ( tapcell.cell12_0 VPWR ) ( tapcell.cell11_4 VPWR ) ( tapcell.cell11_3 VPWR ) ( tapcell.cell11_2 VPWR ) + ( tapcell.cell11_1 VPWR ) ( tapcell.cell11_0 VPWR ) ( tapcell.cell10_4 VPWR ) ( tapcell.cell10_3 VPWR ) ( tapcell.cell10_2 VPWR ) ( tapcell.cell10_1 VPWR ) ( tapcell.cell10_0 VPWR ) ( tapcell.cell9_4 VPWR ) + ( tapcell.cell9_3 VPWR ) ( tapcell.cell9_2 VPWR ) ( tapcell.cell9_1 VPWR ) ( tapcell.cell9_0 VPWR ) ( tapcell.cell8_4 VPWR ) ( tapcell.cell8_3 VPWR ) ( tapcell.cell8_2 VPWR ) ( tapcell.cell8_1 VPWR ) + ( tapcell.cell8_0 VPWR ) ( tapcell.cell7_4 VPWR ) ( tapcell.cell7_3 VPWR ) ( tapcell.cell7_2 VPWR ) ( tapcell.cell7_1 VPWR ) ( tapcell.cell7_0 VPWR ) ( tapcell.cell6_4 VPWR ) ( tapcell.cell6_3 VPWR ) + ( tapcell.cell6_2 VPWR ) ( tapcell.cell6_1 VPWR ) ( tapcell.cell6_0 VPWR ) ( tapcell.cell5_4 VPWR ) ( tapcell.cell5_3 VPWR ) ( tapcell.cell5_2 VPWR ) ( tapcell.cell5_1 VPWR ) ( tapcell.cell5_0 VPWR ) + ( tapcell.cell4_4 VPWR ) ( tapcell.cell4_3 VPWR ) ( tapcell.cell4_2 VPWR ) ( tapcell.cell4_1 VPWR ) ( tapcell.cell4_0 VPWR ) ( tapcell.cell3_4 VPWR ) ( tapcell.cell3_3 VPWR ) ( tapcell.cell3_2 VPWR ) + ( tapcell.cell3_1 VPWR ) ( tapcell.cell3_0 VPWR ) ( tapcell.cell2_4 VPWR ) ( tapcell.cell2_3 VPWR ) ( tapcell.cell2_2 VPWR ) ( tapcell.cell2_1 VPWR ) ( tapcell.cell2_0 VPWR ) ( tapcell.cell1_4 VPWR ) + ( tapcell.cell1_3 VPWR ) ( tapcell.cell1_2 VPWR ) ( tapcell.cell1_1 VPWR ) ( tapcell.cell1_0 VPWR ) ( tapcell.cell0_4 VPWR ) ( tapcell.cell0_3 VPWR ) ( tapcell.cell0_2 VPWR ) ( tapcell.cell0_1 VPWR ) + ( tapcell.cell0_0 VPWR ) ( decoder.inv_1 VPWR ) ( decoder.inv_2 VPWR ) ( buffer.in[7] VPWR ) ( buffer.in[6] VPWR ) ( buffer.in[5] VPWR ) ( buffer.in[4] VPWR ) ( buffer.in[3] VPWR ) + ( buffer.in[2] VPWR ) ( buffer.in[1] VPWR ) ( buffer.in[0] VPWR ) ( mux_slice0_bit7.inv VPWR ) ( mux_slice0_bit7.aoi VPWR ) ( mux_slice0_bit6.inv VPWR ) ( mux_slice0_bit6.aoi VPWR ) ( mux_slice0_bit5.inv VPWR ) + ( mux_slice0_bit5.aoi VPWR ) ( mux_slice0_bit4.inv VPWR ) ( mux_slice0_bit4.aoi VPWR ) ( mux_slice0_bit3.inv VPWR ) ( mux_slice0_bit3.aoi VPWR ) ( mux_slice0_bit2.inv VPWR ) ( mux_slice0_bit2.aoi VPWR ) ( mux_slice0_bit1.inv VPWR ) + ( mux_slice0_bit1.aoi VPWR ) ( mux_slice0_bit0.inv VPWR ) ( mux_slice0_bit0.aoi VPWR ) ( storage_3_1_0.gcand VPWR ) ( storage_3_1_0.word_and VPWR ) ( storage_3_1_0.cg VPWR ) ( storage_3_1_0.bit7.obuf0 VPWR ) ( storage_3_1_0.bit7.bit VPWR ) + ( storage_3_1_0.bit6.obuf0 VPWR ) ( storage_3_1_0.bit6.bit VPWR ) ( storage_3_1_0.bit5.obuf0 VPWR ) ( storage_3_1_0.bit5.bit VPWR ) ( storage_3_1_0.bit4.obuf0 VPWR ) ( storage_3_1_0.bit4.bit VPWR ) ( storage_3_1_0.bit3.obuf0 VPWR ) ( storage_3_1_0.bit3.bit VPWR ) + ( storage_3_1_0.bit2.obuf0 VPWR ) ( storage_3_1_0.bit2.bit VPWR ) ( storage_3_1_0.bit1.obuf0 VPWR ) ( storage_3_1_0.bit1.bit VPWR ) ( storage_3_1_0.bit0.obuf0 VPWR ) ( storage_3_1_0.bit0.bit VPWR ) ( storage_3_0_0.select_inv_0 VPWR ) ( storage_3_0_0.gcand VPWR ) + ( storage_3_0_0.word_and VPWR ) ( storage_3_0_0.cg VPWR ) ( storage_3_0_0.bit7.obuf0 VPWR ) ( storage_3_0_0.bit7.bit VPWR ) ( storage_3_0_0.bit6.obuf0 VPWR ) ( storage_3_0_0.bit6.bit VPWR ) ( storage_3_0_0.bit5.obuf0 VPWR ) ( storage_3_0_0.bit5.bit VPWR ) + ( storage_3_0_0.bit4.obuf0 VPWR ) ( storage_3_0_0.bit4.bit VPWR ) ( storage_3_0_0.bit3.obuf0 VPWR ) ( storage_3_0_0.bit3.bit VPWR ) ( storage_3_0_0.bit2.obuf0 VPWR ) ( storage_3_0_0.bit2.bit VPWR ) ( storage_3_0_0.bit1.obuf0 VPWR ) ( storage_3_0_0.bit1.bit VPWR ) + ( storage_3_0_0.bit0.obuf0 VPWR ) ( storage_3_0_0.bit0.bit VPWR ) ( storage_2_1_0.gcand VPWR ) ( storage_2_1_0.word_and VPWR ) ( storage_2_1_0.cg VPWR ) ( storage_2_1_0.bit7.obuf0 VPWR ) ( storage_2_1_0.bit7.bit VPWR ) ( storage_2_1_0.bit6.obuf0 VPWR ) + ( storage_2_1_0.bit6.bit VPWR ) ( storage_2_1_0.bit5.obuf0 VPWR ) ( storage_2_1_0.bit5.bit VPWR ) ( storage_2_1_0.bit4.obuf0 VPWR ) ( storage_2_1_0.bit4.bit VPWR ) ( storage_2_1_0.bit3.obuf0 VPWR ) ( storage_2_1_0.bit3.bit VPWR ) ( storage_2_1_0.bit2.obuf0 VPWR ) + ( storage_2_1_0.bit2.bit VPWR ) ( storage_2_1_0.bit1.obuf0 VPWR ) ( storage_2_1_0.bit1.bit VPWR ) ( storage_2_1_0.bit0.obuf0 VPWR ) ( storage_2_1_0.bit0.bit VPWR ) ( storage_2_0_0.select_inv_0 VPWR ) ( storage_2_0_0.gcand VPWR ) ( storage_2_0_0.word_and VPWR ) + ( storage_2_0_0.cg VPWR ) ( storage_2_0_0.bit7.obuf0 VPWR ) ( storage_2_0_0.bit7.bit VPWR ) ( storage_2_0_0.bit6.obuf0 VPWR ) ( storage_2_0_0.bit6.bit VPWR ) ( storage_2_0_0.bit5.obuf0 VPWR ) ( storage_2_0_0.bit5.bit VPWR ) ( storage_2_0_0.bit4.obuf0 VPWR ) + ( storage_2_0_0.bit4.bit VPWR ) ( storage_2_0_0.bit3.obuf0 VPWR ) ( storage_2_0_0.bit3.bit VPWR ) ( storage_2_0_0.bit2.obuf0 VPWR ) ( storage_2_0_0.bit2.bit VPWR ) ( storage_2_0_0.bit1.obuf0 VPWR ) ( storage_2_0_0.bit1.bit VPWR ) ( storage_2_0_0.bit0.obuf0 VPWR ) + ( storage_2_0_0.bit0.bit VPWR ) ( storage_1_1_0.gcand VPWR ) ( storage_1_1_0.word_and VPWR ) ( storage_1_1_0.cg VPWR ) ( storage_1_1_0.bit7.obuf0 VPWR ) ( storage_1_1_0.bit7.bit VPWR ) ( storage_1_1_0.bit6.obuf0 VPWR ) ( storage_1_1_0.bit6.bit VPWR ) + ( storage_1_1_0.bit5.obuf0 VPWR ) ( storage_1_1_0.bit5.bit VPWR ) ( storage_1_1_0.bit4.obuf0 VPWR ) ( storage_1_1_0.bit4.bit VPWR ) ( storage_1_1_0.bit3.obuf0 VPWR ) ( storage_1_1_0.bit3.bit VPWR ) ( storage_1_1_0.bit2.obuf0 VPWR ) ( storage_1_1_0.bit2.bit VPWR ) + ( storage_1_1_0.bit1.obuf0 VPWR ) ( storage_1_1_0.bit1.bit VPWR ) ( storage_1_1_0.bit0.obuf0 VPWR ) ( storage_1_1_0.bit0.bit VPWR ) ( storage_1_0_0.select_inv_0 VPWR ) ( storage_1_0_0.gcand VPWR ) ( storage_1_0_0.word_and VPWR ) ( storage_1_0_0.cg VPWR ) + ( storage_1_0_0.bit7.obuf0 VPWR ) ( storage_1_0_0.bit7.bit VPWR ) ( storage_1_0_0.bit6.obuf0 VPWR ) ( storage_1_0_0.bit6.bit VPWR ) ( storage_1_0_0.bit5.obuf0 VPWR ) ( storage_1_0_0.bit5.bit VPWR ) ( storage_1_0_0.bit4.obuf0 VPWR ) ( storage_1_0_0.bit4.bit VPWR ) + ( storage_1_0_0.bit3.obuf0 VPWR ) ( storage_1_0_0.bit3.bit VPWR ) ( storage_1_0_0.bit2.obuf0 VPWR ) ( storage_1_0_0.bit2.bit VPWR ) ( storage_1_0_0.bit1.obuf0 VPWR ) ( storage_1_0_0.bit1.bit VPWR ) ( storage_1_0_0.bit0.obuf0 VPWR ) ( storage_1_0_0.bit0.bit VPWR ) + ( storage_0_1_0.gcand VPWR ) ( storage_0_1_0.word_and VPWR ) ( storage_0_1_0.cg VPWR ) ( storage_0_1_0.bit7.obuf0 VPWR ) ( storage_0_1_0.bit7.bit VPWR ) ( storage_0_1_0.bit6.obuf0 VPWR ) ( storage_0_1_0.bit6.bit VPWR ) ( storage_0_1_0.bit5.obuf0 VPWR ) + ( storage_0_1_0.bit5.bit VPWR ) ( storage_0_1_0.bit4.obuf0 VPWR ) ( storage_0_1_0.bit4.bit VPWR ) ( storage_0_1_0.bit3.obuf0 VPWR ) ( storage_0_1_0.bit3.bit VPWR ) ( storage_0_1_0.bit2.obuf0 VPWR ) ( storage_0_1_0.bit2.bit VPWR ) ( storage_0_1_0.bit1.obuf0 VPWR ) + ( storage_0_1_0.bit1.bit VPWR ) ( storage_0_1_0.bit0.obuf0 VPWR ) ( storage_0_1_0.bit0.bit VPWR ) ( storage_0_0_0.select_inv_0 VPWR ) ( storage_0_0_0.gcand VPWR ) ( storage_0_0_0.word_and VPWR ) ( storage_0_0_0.cg VPWR ) ( storage_0_0_0.bit7.obuf0 VPWR ) + ( storage_0_0_0.bit7.bit VPWR ) ( storage_0_0_0.bit6.obuf0 VPWR ) ( storage_0_0_0.bit6.bit VPWR ) ( storage_0_0_0.bit5.obuf0 VPWR ) ( storage_0_0_0.bit5.bit VPWR ) ( storage_0_0_0.bit4.obuf0 VPWR ) ( storage_0_0_0.bit4.bit VPWR ) ( storage_0_0_0.bit3.obuf0 VPWR ) + ( storage_0_0_0.bit3.bit VPWR ) ( storage_0_0_0.bit2.obuf0 VPWR ) ( storage_0_0_0.bit2.bit VPWR ) ( storage_0_0_0.bit1.obuf0 VPWR ) ( storage_0_0_0.bit1.bit VPWR ) ( storage_0_0_0.bit0.obuf0 VPWR ) ( storage_0_0_0.bit0.bit VPWR ) ( word_sel.inv_addr_0 VPWR ) + ( decoder_3.buf_port0 VPWR ) ( decoder_3.and_layer0 VPWR ) ( decoder_2.buf_port0 VPWR ) ( decoder_2.and_layer0 VPWR ) ( decoder_1.buf_port0 VPWR ) ( decoder_1.and_layer0 VPWR ) ( decoder_0.buf_port0 VPWR ) ( decoder_0.and_layer0 VPWR ) + USE POWER + + ROUTED met3 48 + SHAPE STRIPE ( 0 500 ) ( 21390 500 ) + NEW met2 48 + SHAPE STRIPE ( 21000 0 ) ( 21000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 19000 0 ) ( 19000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 17000 0 ) ( 17000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 15000 0 ) ( 15000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 13000 0 ) ( 13000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 11000 0 ) ( 11000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 9000 0 ) ( 9000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 7000 0 ) ( 7000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 5000 0 ) ( 5000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 3000 0 ) ( 3000 1384 ) + NEW met2 48 + SHAPE STRIPE ( 1000 0 ) ( 1000 1384 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1360 ) ( 21390 1360 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 816 ) ( 21390 816 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 272 ) ( 21390 272 ) + NEW met2 0 + SHAPE STRIPE ( 21000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 19000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 17000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 15000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 13000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 11000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 9000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 7000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 5000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 3000 500 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 1000 500 ) via3_4_480_480_1_1_400_400 + NEW met1 0 + SHAPE STRIPE ( 21000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 21000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 21000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 19000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 19000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 19000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 17000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 17000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 17000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 15000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 15000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 15000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 13000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 13000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 13000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 11000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 11000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 11000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 9000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 9000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 9000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 7000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 7000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 7000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 5000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 5000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 5000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 3000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 3000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 3000 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 1000 1360 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 1000 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 1000 272 ) via2_3_480_480_1_1_320_320 ; + - VSS ( PIN VSS ) ( tapcell.cell18_4 VGND ) ( tapcell.cell18_3 VGND ) ( tapcell.cell18_2 VGND ) ( tapcell.cell18_1 VGND ) ( tapcell.cell18_0 VGND ) ( tapcell.cell17_4 VGND ) + ( tapcell.cell17_3 VGND ) ( tapcell.cell17_2 VGND ) ( tapcell.cell17_1 VGND ) ( tapcell.cell17_0 VGND ) ( tapcell.cell16_4 VGND ) ( tapcell.cell16_3 VGND ) ( tapcell.cell16_2 VGND ) ( tapcell.cell16_1 VGND ) + ( tapcell.cell16_0 VGND ) ( tapcell.cell15_4 VGND ) ( tapcell.cell15_3 VGND ) ( tapcell.cell15_2 VGND ) ( tapcell.cell15_1 VGND ) ( tapcell.cell15_0 VGND ) ( tapcell.cell14_4 VGND ) ( tapcell.cell14_3 VGND ) + ( tapcell.cell14_2 VGND ) ( tapcell.cell14_1 VGND ) ( tapcell.cell14_0 VGND ) ( tapcell.cell13_4 VGND ) ( tapcell.cell13_3 VGND ) ( tapcell.cell13_2 VGND ) ( tapcell.cell13_1 VGND ) ( tapcell.cell13_0 VGND ) + ( tapcell.cell12_4 VGND ) ( tapcell.cell12_3 VGND ) ( tapcell.cell12_2 VGND ) ( tapcell.cell12_1 VGND ) ( tapcell.cell12_0 VGND ) ( tapcell.cell11_4 VGND ) ( tapcell.cell11_3 VGND ) ( tapcell.cell11_2 VGND ) + ( tapcell.cell11_1 VGND ) ( tapcell.cell11_0 VGND ) ( tapcell.cell10_4 VGND ) ( tapcell.cell10_3 VGND ) ( tapcell.cell10_2 VGND ) ( tapcell.cell10_1 VGND ) ( tapcell.cell10_0 VGND ) ( tapcell.cell9_4 VGND ) + ( tapcell.cell9_3 VGND ) ( tapcell.cell9_2 VGND ) ( tapcell.cell9_1 VGND ) ( tapcell.cell9_0 VGND ) ( tapcell.cell8_4 VGND ) ( tapcell.cell8_3 VGND ) ( tapcell.cell8_2 VGND ) ( tapcell.cell8_1 VGND ) + ( tapcell.cell8_0 VGND ) ( tapcell.cell7_4 VGND ) ( tapcell.cell7_3 VGND ) ( tapcell.cell7_2 VGND ) ( tapcell.cell7_1 VGND ) ( tapcell.cell7_0 VGND ) ( tapcell.cell6_4 VGND ) ( tapcell.cell6_3 VGND ) + ( tapcell.cell6_2 VGND ) ( tapcell.cell6_1 VGND ) ( tapcell.cell6_0 VGND ) ( tapcell.cell5_4 VGND ) ( tapcell.cell5_3 VGND ) ( tapcell.cell5_2 VGND ) ( tapcell.cell5_1 VGND ) ( tapcell.cell5_0 VGND ) + ( tapcell.cell4_4 VGND ) ( tapcell.cell4_3 VGND ) ( tapcell.cell4_2 VGND ) ( tapcell.cell4_1 VGND ) ( tapcell.cell4_0 VGND ) ( tapcell.cell3_4 VGND ) ( tapcell.cell3_3 VGND ) ( tapcell.cell3_2 VGND ) + ( tapcell.cell3_1 VGND ) ( tapcell.cell3_0 VGND ) ( tapcell.cell2_4 VGND ) ( tapcell.cell2_3 VGND ) ( tapcell.cell2_2 VGND ) ( tapcell.cell2_1 VGND ) ( tapcell.cell2_0 VGND ) ( tapcell.cell1_4 VGND ) + ( tapcell.cell1_3 VGND ) ( tapcell.cell1_2 VGND ) ( tapcell.cell1_1 VGND ) ( tapcell.cell1_0 VGND ) ( tapcell.cell0_4 VGND ) ( tapcell.cell0_3 VGND ) ( tapcell.cell0_2 VGND ) ( tapcell.cell0_1 VGND ) + ( tapcell.cell0_0 VGND ) ( decoder.inv_1 VGND ) ( decoder.inv_2 VGND ) ( buffer.in[7] VGND ) ( buffer.in[6] VGND ) ( buffer.in[5] VGND ) ( buffer.in[4] VGND ) ( buffer.in[3] VGND ) + ( buffer.in[2] VGND ) ( buffer.in[1] VGND ) ( buffer.in[0] VGND ) ( mux_slice0_bit7.inv VGND ) ( mux_slice0_bit7.aoi VGND ) ( mux_slice0_bit6.inv VGND ) ( mux_slice0_bit6.aoi VGND ) ( mux_slice0_bit5.inv VGND ) + ( mux_slice0_bit5.aoi VGND ) ( mux_slice0_bit4.inv VGND ) ( mux_slice0_bit4.aoi VGND ) ( mux_slice0_bit3.inv VGND ) ( mux_slice0_bit3.aoi VGND ) ( mux_slice0_bit2.inv VGND ) ( mux_slice0_bit2.aoi VGND ) ( mux_slice0_bit1.inv VGND ) + ( mux_slice0_bit1.aoi VGND ) ( mux_slice0_bit0.inv VGND ) ( mux_slice0_bit0.aoi VGND ) ( storage_3_1_0.gcand VGND ) ( storage_3_1_0.word_and VGND ) ( storage_3_1_0.cg VGND ) ( storage_3_1_0.bit7.obuf0 VGND ) ( storage_3_1_0.bit7.bit VGND ) + ( storage_3_1_0.bit6.obuf0 VGND ) ( storage_3_1_0.bit6.bit VGND ) ( storage_3_1_0.bit5.obuf0 VGND ) ( storage_3_1_0.bit5.bit VGND ) ( storage_3_1_0.bit4.obuf0 VGND ) ( storage_3_1_0.bit4.bit VGND ) ( storage_3_1_0.bit3.obuf0 VGND ) ( storage_3_1_0.bit3.bit VGND ) + ( storage_3_1_0.bit2.obuf0 VGND ) ( storage_3_1_0.bit2.bit VGND ) ( storage_3_1_0.bit1.obuf0 VGND ) ( storage_3_1_0.bit1.bit VGND ) ( storage_3_1_0.bit0.obuf0 VGND ) ( storage_3_1_0.bit0.bit VGND ) ( storage_3_0_0.select_inv_0 VGND ) ( storage_3_0_0.gcand VGND ) + ( storage_3_0_0.word_and VGND ) ( storage_3_0_0.cg VGND ) ( storage_3_0_0.bit7.obuf0 VGND ) ( storage_3_0_0.bit7.bit VGND ) ( storage_3_0_0.bit6.obuf0 VGND ) ( storage_3_0_0.bit6.bit VGND ) ( storage_3_0_0.bit5.obuf0 VGND ) ( storage_3_0_0.bit5.bit VGND ) + ( storage_3_0_0.bit4.obuf0 VGND ) ( storage_3_0_0.bit4.bit VGND ) ( storage_3_0_0.bit3.obuf0 VGND ) ( storage_3_0_0.bit3.bit VGND ) ( storage_3_0_0.bit2.obuf0 VGND ) ( storage_3_0_0.bit2.bit VGND ) ( storage_3_0_0.bit1.obuf0 VGND ) ( storage_3_0_0.bit1.bit VGND ) + ( storage_3_0_0.bit0.obuf0 VGND ) ( storage_3_0_0.bit0.bit VGND ) ( storage_2_1_0.gcand VGND ) ( storage_2_1_0.word_and VGND ) ( storage_2_1_0.cg VGND ) ( storage_2_1_0.bit7.obuf0 VGND ) ( storage_2_1_0.bit7.bit VGND ) ( storage_2_1_0.bit6.obuf0 VGND ) + ( storage_2_1_0.bit6.bit VGND ) ( storage_2_1_0.bit5.obuf0 VGND ) ( storage_2_1_0.bit5.bit VGND ) ( storage_2_1_0.bit4.obuf0 VGND ) ( storage_2_1_0.bit4.bit VGND ) ( storage_2_1_0.bit3.obuf0 VGND ) ( storage_2_1_0.bit3.bit VGND ) ( storage_2_1_0.bit2.obuf0 VGND ) + ( storage_2_1_0.bit2.bit VGND ) ( storage_2_1_0.bit1.obuf0 VGND ) ( storage_2_1_0.bit1.bit VGND ) ( storage_2_1_0.bit0.obuf0 VGND ) ( storage_2_1_0.bit0.bit VGND ) ( storage_2_0_0.select_inv_0 VGND ) ( storage_2_0_0.gcand VGND ) ( storage_2_0_0.word_and VGND ) + ( storage_2_0_0.cg VGND ) ( storage_2_0_0.bit7.obuf0 VGND ) ( storage_2_0_0.bit7.bit VGND ) ( storage_2_0_0.bit6.obuf0 VGND ) ( storage_2_0_0.bit6.bit VGND ) ( storage_2_0_0.bit5.obuf0 VGND ) ( storage_2_0_0.bit5.bit VGND ) ( storage_2_0_0.bit4.obuf0 VGND ) + ( storage_2_0_0.bit4.bit VGND ) ( storage_2_0_0.bit3.obuf0 VGND ) ( storage_2_0_0.bit3.bit VGND ) ( storage_2_0_0.bit2.obuf0 VGND ) ( storage_2_0_0.bit2.bit VGND ) ( storage_2_0_0.bit1.obuf0 VGND ) ( storage_2_0_0.bit1.bit VGND ) ( storage_2_0_0.bit0.obuf0 VGND ) + ( storage_2_0_0.bit0.bit VGND ) ( storage_1_1_0.gcand VGND ) ( storage_1_1_0.word_and VGND ) ( storage_1_1_0.cg VGND ) ( storage_1_1_0.bit7.obuf0 VGND ) ( storage_1_1_0.bit7.bit VGND ) ( storage_1_1_0.bit6.obuf0 VGND ) ( storage_1_1_0.bit6.bit VGND ) + ( storage_1_1_0.bit5.obuf0 VGND ) ( storage_1_1_0.bit5.bit VGND ) ( storage_1_1_0.bit4.obuf0 VGND ) ( storage_1_1_0.bit4.bit VGND ) ( storage_1_1_0.bit3.obuf0 VGND ) ( storage_1_1_0.bit3.bit VGND ) ( storage_1_1_0.bit2.obuf0 VGND ) ( storage_1_1_0.bit2.bit VGND ) + ( storage_1_1_0.bit1.obuf0 VGND ) ( storage_1_1_0.bit1.bit VGND ) ( storage_1_1_0.bit0.obuf0 VGND ) ( storage_1_1_0.bit0.bit VGND ) ( storage_1_0_0.select_inv_0 VGND ) ( storage_1_0_0.gcand VGND ) ( storage_1_0_0.word_and VGND ) ( storage_1_0_0.cg VGND ) + ( storage_1_0_0.bit7.obuf0 VGND ) ( storage_1_0_0.bit7.bit VGND ) ( storage_1_0_0.bit6.obuf0 VGND ) ( storage_1_0_0.bit6.bit VGND ) ( storage_1_0_0.bit5.obuf0 VGND ) ( storage_1_0_0.bit5.bit VGND ) ( storage_1_0_0.bit4.obuf0 VGND ) ( storage_1_0_0.bit4.bit VGND ) + ( storage_1_0_0.bit3.obuf0 VGND ) ( storage_1_0_0.bit3.bit VGND ) ( storage_1_0_0.bit2.obuf0 VGND ) ( storage_1_0_0.bit2.bit VGND ) ( storage_1_0_0.bit1.obuf0 VGND ) ( storage_1_0_0.bit1.bit VGND ) ( storage_1_0_0.bit0.obuf0 VGND ) ( storage_1_0_0.bit0.bit VGND ) + ( storage_0_1_0.gcand VGND ) ( storage_0_1_0.word_and VGND ) ( storage_0_1_0.cg VGND ) ( storage_0_1_0.bit7.obuf0 VGND ) ( storage_0_1_0.bit7.bit VGND ) ( storage_0_1_0.bit6.obuf0 VGND ) ( storage_0_1_0.bit6.bit VGND ) ( storage_0_1_0.bit5.obuf0 VGND ) + ( storage_0_1_0.bit5.bit VGND ) ( storage_0_1_0.bit4.obuf0 VGND ) ( storage_0_1_0.bit4.bit VGND ) ( storage_0_1_0.bit3.obuf0 VGND ) ( storage_0_1_0.bit3.bit VGND ) ( storage_0_1_0.bit2.obuf0 VGND ) ( storage_0_1_0.bit2.bit VGND ) ( storage_0_1_0.bit1.obuf0 VGND ) + ( storage_0_1_0.bit1.bit VGND ) ( storage_0_1_0.bit0.obuf0 VGND ) ( storage_0_1_0.bit0.bit VGND ) ( storage_0_0_0.select_inv_0 VGND ) ( storage_0_0_0.gcand VGND ) ( storage_0_0_0.word_and VGND ) ( storage_0_0_0.cg VGND ) ( storage_0_0_0.bit7.obuf0 VGND ) + ( storage_0_0_0.bit7.bit VGND ) ( storage_0_0_0.bit6.obuf0 VGND ) ( storage_0_0_0.bit6.bit VGND ) ( storage_0_0_0.bit5.obuf0 VGND ) ( storage_0_0_0.bit5.bit VGND ) ( storage_0_0_0.bit4.obuf0 VGND ) ( storage_0_0_0.bit4.bit VGND ) ( storage_0_0_0.bit3.obuf0 VGND ) + ( storage_0_0_0.bit3.bit VGND ) ( storage_0_0_0.bit2.obuf0 VGND ) ( storage_0_0_0.bit2.bit VGND ) ( storage_0_0_0.bit1.obuf0 VGND ) ( storage_0_0_0.bit1.bit VGND ) ( storage_0_0_0.bit0.obuf0 VGND ) ( storage_0_0_0.bit0.bit VGND ) ( word_sel.inv_addr_0 VGND ) + ( decoder_3.buf_port0 VGND ) ( decoder_3.and_layer0 VGND ) ( decoder_2.buf_port0 VGND ) ( decoder_2.and_layer0 VGND ) ( decoder_1.buf_port0 VGND ) ( decoder_1.and_layer0 VGND ) ( decoder_0.buf_port0 VGND ) ( decoder_0.and_layer0 VGND ) + USE GROUND + + ROUTED met3 48 + SHAPE STRIPE ( 0 1000 ) ( 21390 1000 ) + NEW met2 48 + SHAPE STRIPE ( 20000 -24 ) ( 20000 1360 ) + NEW met2 48 + SHAPE STRIPE ( 18000 -24 ) ( 18000 1360 ) + NEW met2 48 + SHAPE STRIPE ( 16000 -24 ) ( 16000 1360 ) + NEW met2 48 + SHAPE STRIPE ( 14000 -24 ) ( 14000 1360 ) + NEW met2 48 + SHAPE STRIPE ( 12000 -24 ) ( 12000 1360 ) + NEW met2 48 + SHAPE STRIPE ( 10000 -24 ) ( 10000 1360 ) + NEW met2 48 + SHAPE STRIPE ( 8000 -24 ) ( 8000 1360 ) + NEW met2 48 + SHAPE STRIPE ( 6000 -24 ) ( 6000 1360 ) + NEW met2 48 + SHAPE STRIPE ( 4000 -24 ) ( 4000 1360 ) + NEW met2 48 + SHAPE STRIPE ( 2000 -24 ) ( 2000 1360 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1088 ) ( 21390 1088 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 544 ) ( 21390 544 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 0 ) ( 21390 0 ) + NEW met2 0 + SHAPE STRIPE ( 20000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 18000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 16000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 14000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 12000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 10000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 8000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 6000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 4000 1000 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 2000 1000 ) via3_4_480_480_1_1_400_400 + NEW met1 0 + SHAPE STRIPE ( 20000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 20000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 20000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 18000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 18000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 18000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 16000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 16000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 16000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 14000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 14000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 14000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 12000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 12000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 12000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 1088 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 0 ) via2_3_480_480_1_1_320_320 ; +END SPECIALNETS +NETS 160 ; + - D[0] ( PIN D[0] ) ( buffer.in[0] A ) + USE SIGNAL + + ROUTED met2 ( 115 1207 ) ( * 1326 0 ) + NEW met1 ( 69 1207 ) ( 115 * ) + NEW met1 ( 115 1207 ) M1M2_PR + NEW li1 ( 69 1207 ) L1M1_PR_MR ; + - D[1] ( PIN D[1] ) ( buffer.in[1] A ) + USE SIGNAL + + ROUTED met2 ( 2415 1207 ) ( * 1326 0 ) + NEW met1 ( 2369 1207 ) ( 2415 * ) + NEW met1 ( 2415 1207 ) M1M2_PR + NEW li1 ( 2369 1207 ) L1M1_PR_MR ; + - D[2] ( PIN D[2] ) ( buffer.in[2] A ) + USE SIGNAL + + ROUTED met2 ( 2875 1275 ) ( * 1326 0 ) + NEW met1 ( 2875 1275 ) ( 4669 * ) + NEW met1 ( 4669 1207 ) ( * 1275 ) + NEW met1 ( 2875 1275 ) M1M2_PR + NEW li1 ( 4669 1207 ) L1M1_PR_MR ; + - D[3] ( PIN D[3] ) ( buffer.in[3] A ) + USE SIGNAL + + ROUTED met2 ( 6923 1207 ) ( * 1326 0 ) + NEW met1 ( 6923 1207 ) ( 6969 * ) + NEW met1 ( 6923 1207 ) M1M2_PR + NEW li1 ( 6969 1207 ) L1M1_PR_MR ; + - D[4] ( PIN D[4] ) ( buffer.in[4] A ) + USE SIGNAL + + ROUTED met2 ( 9315 1207 ) ( * 1326 0 ) + NEW met1 ( 9269 1207 ) ( 9315 * ) + NEW met1 ( 9315 1207 ) M1M2_PR + NEW li1 ( 9269 1207 ) L1M1_PR_MR ; + - D[5] ( PIN D[5] ) ( buffer.in[5] A ) + USE SIGNAL + + ROUTED met2 ( 11615 1207 ) ( * 1326 0 ) + NEW met1 ( 11569 1207 ) ( 11615 * ) + NEW met1 ( 11615 1207 ) M1M2_PR + NEW li1 ( 11569 1207 ) L1M1_PR_MR ; + - D[6] ( PIN D[6] ) ( buffer.in[6] A ) + USE SIGNAL + + ROUTED met2 ( 13915 1207 ) ( * 1326 0 ) + NEW met1 ( 13869 1207 ) ( 13915 * ) + NEW met1 ( 13915 1207 ) M1M2_PR + NEW li1 ( 13869 1207 ) L1M1_PR_MR ; + - D[7] ( PIN D[7] ) ( buffer.in[7] A ) + USE SIGNAL + + ROUTED met2 ( 16215 1207 ) ( * 1326 0 ) + NEW met1 ( 16169 1207 ) ( 16215 * ) + NEW met1 ( 16215 1207 ) M1M2_PR + NEW li1 ( 16169 1207 ) L1M1_PR_MR ; + - D_nets.b0 ( buffer.in[0] X ) ( storage_3_1_0.bit0.bit D ) ( storage_3_0_0.bit0.bit D ) ( storage_2_1_0.bit0.bit D ) ( storage_2_0_0.bit0.bit D ) ( storage_1_1_0.bit0.bit D ) ( storage_1_0_0.bit0.bit D ) + ( storage_0_1_0.bit0.bit D ) ( storage_0_0_0.bit0.bit D ) + USE SIGNAL + + ROUTED met1 ( 202 969 ) ( 207 * ) + NEW met2 ( 207 969 ) ( * 1139 ) + NEW met1 ( 161 1139 ) ( 207 * ) + NEW met1 ( 202 663 ) ( 207 * ) + NEW met2 ( 207 663 ) ( * 969 ) + NEW met1 ( 202 425 ) ( 207 * ) + NEW met2 ( 207 425 ) ( * 663 ) + NEW met1 ( 202 119 ) ( 207 * ) + NEW met2 ( 207 119 ) ( * 425 ) + NEW met1 ( 1265 425 ) ( 1347 * ) + NEW met1 ( 1265 391 ) ( * 425 ) + NEW met1 ( 1173 391 ) ( 1265 * ) + NEW met1 ( 1173 391 ) ( * 425 ) + NEW met1 ( 207 425 ) ( 1173 * ) + NEW met1 ( 1352 629 ) ( 1357 * ) + NEW met2 ( 1357 425 ) ( * 629 ) + NEW met1 ( 1347 425 ) ( 1357 * ) + NEW met1 ( 1352 1003 ) ( 1357 * ) + NEW met2 ( 1357 629 ) ( * 1003 ) + NEW met1 ( 1352 85 ) ( 1357 * ) + NEW met2 ( 1357 85 ) ( * 425 ) + NEW li1 ( 202 969 ) L1M1_PR_MR + NEW met1 ( 207 969 ) M1M2_PR + NEW met1 ( 207 1139 ) M1M2_PR + NEW li1 ( 161 1139 ) L1M1_PR_MR + NEW li1 ( 202 663 ) L1M1_PR_MR + NEW met1 ( 207 663 ) M1M2_PR + NEW li1 ( 202 425 ) L1M1_PR_MR + NEW met1 ( 207 425 ) M1M2_PR + NEW li1 ( 202 119 ) L1M1_PR_MR + NEW met1 ( 207 119 ) M1M2_PR + NEW li1 ( 1347 425 ) L1M1_PR_MR + NEW li1 ( 1352 629 ) L1M1_PR_MR + NEW met1 ( 1357 629 ) M1M2_PR + NEW met1 ( 1357 425 ) M1M2_PR + NEW li1 ( 1352 1003 ) L1M1_PR_MR + NEW met1 ( 1357 1003 ) M1M2_PR + NEW li1 ( 1352 85 ) L1M1_PR_MR + NEW met1 ( 1357 85 ) M1M2_PR + NEW met1 ( 202 969 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 663 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 119 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 629 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 85 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b1 ( buffer.in[1] X ) ( storage_3_1_0.bit1.bit D ) ( storage_3_0_0.bit1.bit D ) ( storage_2_1_0.bit1.bit D ) ( storage_2_0_0.bit1.bit D ) ( storage_1_1_0.bit1.bit D ) ( storage_1_0_0.bit1.bit D ) + ( storage_0_1_0.bit1.bit D ) ( storage_0_0_0.bit1.bit D ) + USE SIGNAL + + ROUTED met1 ( 2415 969 ) ( 2497 * ) + NEW met2 ( 2415 969 ) ( * 1139 ) + NEW met1 ( 2415 1139 ) ( 2461 * ) + NEW met1 ( 2502 629 ) ( 2507 * ) + NEW met2 ( 2507 629 ) ( * 969 ) + NEW met1 ( 2497 969 ) ( 2507 * ) + NEW met1 ( 2502 425 ) ( 2507 * ) + NEW met2 ( 2507 425 ) ( * 629 ) + NEW met1 ( 2502 85 ) ( 2507 * ) + NEW met2 ( 2507 85 ) ( * 425 ) + NEW met1 ( 3652 85 ) ( 3657 * ) + NEW met1 ( 3657 51 ) ( * 85 ) + NEW met1 ( 2507 51 ) ( 3657 * ) + NEW met1 ( 2507 51 ) ( * 85 ) + NEW met1 ( 3652 425 ) ( 3657 * ) + NEW met2 ( 3657 85 ) ( * 425 ) + NEW met1 ( 3652 629 ) ( 3657 * ) + NEW met2 ( 3657 425 ) ( * 629 ) + NEW met1 ( 3652 969 ) ( 3657 * ) + NEW met2 ( 3657 629 ) ( * 969 ) + NEW li1 ( 2497 969 ) L1M1_PR_MR + NEW met1 ( 2415 969 ) M1M2_PR + NEW met1 ( 2415 1139 ) M1M2_PR + NEW li1 ( 2461 1139 ) L1M1_PR_MR + NEW li1 ( 2502 629 ) L1M1_PR_MR + NEW met1 ( 2507 629 ) M1M2_PR + NEW met1 ( 2507 969 ) M1M2_PR + NEW li1 ( 2502 425 ) L1M1_PR_MR + NEW met1 ( 2507 425 ) M1M2_PR + NEW li1 ( 2502 85 ) L1M1_PR_MR + NEW met1 ( 2507 85 ) M1M2_PR + NEW li1 ( 3652 85 ) L1M1_PR_MR + NEW li1 ( 3652 425 ) L1M1_PR_MR + NEW met1 ( 3657 425 ) M1M2_PR + NEW met1 ( 3657 85 ) M1M2_PR + NEW li1 ( 3652 629 ) L1M1_PR_MR + NEW met1 ( 3657 629 ) M1M2_PR + NEW li1 ( 3652 969 ) L1M1_PR_MR + NEW met1 ( 3657 969 ) M1M2_PR + NEW met1 ( 2507 629 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 2507 425 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 2502 85 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 3652 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 3657 629 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 3652 969 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b2 ( buffer.in[2] X ) ( storage_3_1_0.bit2.bit D ) ( storage_3_0_0.bit2.bit D ) ( storage_2_1_0.bit2.bit D ) ( storage_2_0_0.bit2.bit D ) ( storage_1_1_0.bit2.bit D ) ( storage_1_0_0.bit2.bit D ) + ( storage_0_1_0.bit2.bit D ) ( storage_0_0_0.bit2.bit D ) + USE SIGNAL + + ROUTED met1 ( 5865 425 ) ( 5947 * ) + NEW met2 ( 5865 425 ) ( * 629 ) + NEW met1 ( 5865 85 ) ( 5941 * ) + NEW met2 ( 5865 85 ) ( * 425 ) + NEW met1 ( 5865 969 ) ( 5947 * ) + NEW met2 ( 5865 629 ) ( * 969 ) + NEW met1 ( 4802 969 ) ( 4807 * ) + NEW met2 ( 4807 969 ) ( * 1139 ) + NEW met1 ( 4761 1139 ) ( 4807 * ) + NEW met1 ( 4802 629 ) ( 4807 * ) + NEW met2 ( 4807 629 ) ( * 969 ) + NEW met1 ( 4802 425 ) ( 4807 * ) + NEW met2 ( 4807 425 ) ( * 629 ) + NEW met1 ( 4802 85 ) ( 4807 * ) + NEW met2 ( 4807 85 ) ( * 425 ) + NEW met1 ( 4807 629 ) ( 5941 * ) + NEW li1 ( 5941 629 ) L1M1_PR_MR + NEW li1 ( 5947 425 ) L1M1_PR_MR + NEW met1 ( 5865 425 ) M1M2_PR + NEW met1 ( 5865 629 ) M1M2_PR + NEW li1 ( 5941 85 ) L1M1_PR_MR + NEW met1 ( 5865 85 ) M1M2_PR + NEW li1 ( 5947 969 ) L1M1_PR_MR + NEW met1 ( 5865 969 ) M1M2_PR + NEW li1 ( 4802 969 ) L1M1_PR_MR + NEW met1 ( 4807 969 ) M1M2_PR + NEW met1 ( 4807 1139 ) M1M2_PR + NEW li1 ( 4761 1139 ) L1M1_PR_MR + NEW li1 ( 4802 629 ) L1M1_PR_MR + NEW met1 ( 4807 629 ) M1M2_PR + NEW li1 ( 4802 425 ) L1M1_PR_MR + NEW met1 ( 4807 425 ) M1M2_PR + NEW li1 ( 4802 85 ) L1M1_PR_MR + NEW met1 ( 4807 85 ) M1M2_PR + NEW met1 ( 4802 969 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 4807 629 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 4802 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 4807 85 ) RECT ( 0 -7 31 7 ) ; + - D_nets.b3 ( buffer.in[3] X ) ( storage_3_1_0.bit3.bit D ) ( storage_3_0_0.bit3.bit D ) ( storage_2_1_0.bit3.bit D ) ( storage_2_0_0.bit3.bit D ) ( storage_1_1_0.bit3.bit D ) ( storage_1_0_0.bit3.bit D ) + ( storage_0_1_0.bit3.bit D ) ( storage_0_0_0.bit3.bit D ) + USE SIGNAL + + ROUTED met1 ( 8252 425 ) ( 8257 * ) + NEW met2 ( 8257 85 ) ( * 425 ) + NEW met1 ( 8241 85 ) ( 8257 * ) + NEW met1 ( 8252 629 ) ( 8257 * ) + NEW met2 ( 8257 425 ) ( * 629 ) + NEW met1 ( 8252 1003 ) ( 8257 * ) + NEW met2 ( 8257 629 ) ( * 1003 ) + NEW met1 ( 7102 425 ) ( 7107 * ) + NEW met2 ( 7107 85 ) ( * 425 ) + NEW met1 ( 7102 629 ) ( 7107 * ) + NEW met2 ( 7107 425 ) ( * 629 ) + NEW met1 ( 7102 969 ) ( 7107 * ) + NEW met2 ( 7107 629 ) ( * 969 ) + NEW met1 ( 7061 1139 ) ( 7107 * ) + NEW met2 ( 7107 969 ) ( * 1139 ) + NEW met1 ( 7102 85 ) ( 8241 * ) + NEW li1 ( 8241 85 ) L1M1_PR_MR + NEW li1 ( 8252 425 ) L1M1_PR_MR + NEW met1 ( 8257 425 ) M1M2_PR + NEW met1 ( 8257 85 ) M1M2_PR + NEW li1 ( 8252 629 ) L1M1_PR_MR + NEW met1 ( 8257 629 ) M1M2_PR + NEW li1 ( 8252 1003 ) L1M1_PR_MR + NEW met1 ( 8257 1003 ) M1M2_PR + NEW li1 ( 7102 85 ) L1M1_PR_MR + NEW li1 ( 7102 425 ) L1M1_PR_MR + NEW met1 ( 7107 425 ) M1M2_PR + NEW met1 ( 7107 85 ) M1M2_PR + NEW li1 ( 7102 629 ) L1M1_PR_MR + NEW met1 ( 7107 629 ) M1M2_PR + NEW li1 ( 7102 969 ) L1M1_PR_MR + NEW met1 ( 7107 969 ) M1M2_PR + NEW li1 ( 7061 1139 ) L1M1_PR_MR + NEW met1 ( 7107 1139 ) M1M2_PR + NEW met1 ( 8252 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 8252 629 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 8252 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 629 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 969 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b4 ( buffer.in[4] X ) ( storage_3_1_0.bit4.bit D ) ( storage_3_0_0.bit4.bit D ) ( storage_2_1_0.bit4.bit D ) ( storage_2_0_0.bit4.bit D ) ( storage_1_1_0.bit4.bit D ) ( storage_1_0_0.bit4.bit D ) + ( storage_0_1_0.bit4.bit D ) ( storage_0_0_0.bit4.bit D ) + USE SIGNAL + + ROUTED met1 ( 9402 969 ) ( 9407 * ) + NEW met2 ( 9407 969 ) ( * 1139 ) + NEW met1 ( 9361 1139 ) ( 9407 * ) + NEW met1 ( 9402 629 ) ( 9407 * ) + NEW met2 ( 9407 629 ) ( * 969 ) + NEW met1 ( 9402 425 ) ( 9407 * ) + NEW met2 ( 9407 425 ) ( * 629 ) + NEW met1 ( 9402 85 ) ( 9407 * ) + NEW met2 ( 9407 85 ) ( * 425 ) + NEW met1 ( 9407 425 ) ( 10547 * ) + NEW met1 ( 10552 85 ) ( 10557 * ) + NEW met2 ( 10557 85 ) ( * 425 ) + NEW met1 ( 10547 425 ) ( 10557 * ) + NEW met1 ( 10552 629 ) ( 10557 * ) + NEW met2 ( 10557 425 ) ( * 629 ) + NEW met1 ( 10552 1003 ) ( 10557 * ) + NEW met2 ( 10557 629 ) ( * 1003 ) + NEW li1 ( 9402 969 ) L1M1_PR_MR + NEW met1 ( 9407 969 ) M1M2_PR + NEW met1 ( 9407 1139 ) M1M2_PR + NEW li1 ( 9361 1139 ) L1M1_PR_MR + NEW li1 ( 9402 629 ) L1M1_PR_MR + NEW met1 ( 9407 629 ) M1M2_PR + NEW li1 ( 9402 425 ) L1M1_PR_MR + NEW met1 ( 9407 425 ) M1M2_PR + NEW li1 ( 9402 85 ) L1M1_PR_MR + NEW met1 ( 9407 85 ) M1M2_PR + NEW li1 ( 10547 425 ) L1M1_PR_MR + NEW li1 ( 10552 85 ) L1M1_PR_MR + NEW met1 ( 10557 85 ) M1M2_PR + NEW met1 ( 10557 425 ) M1M2_PR + NEW li1 ( 10552 629 ) L1M1_PR_MR + NEW met1 ( 10557 629 ) M1M2_PR + NEW li1 ( 10552 1003 ) L1M1_PR_MR + NEW met1 ( 10557 1003 ) M1M2_PR + NEW met1 ( 9402 969 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 9402 629 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 9402 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 9402 85 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 10552 85 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 10552 629 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 10552 1003 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b5 ( buffer.in[5] X ) ( storage_3_1_0.bit5.bit D ) ( storage_3_0_0.bit5.bit D ) ( storage_2_1_0.bit5.bit D ) ( storage_2_0_0.bit5.bit D ) ( storage_1_1_0.bit5.bit D ) ( storage_1_0_0.bit5.bit D ) + ( storage_0_1_0.bit5.bit D ) ( storage_0_0_0.bit5.bit D ) + USE SIGNAL + + ROUTED met1 ( 11702 969 ) ( 11707 * ) + NEW met2 ( 11707 969 ) ( * 1139 ) + NEW met1 ( 11661 1139 ) ( 11707 * ) + NEW met1 ( 11702 629 ) ( 11707 * ) + NEW met2 ( 11707 629 ) ( * 969 ) + NEW met1 ( 11702 459 ) ( 11707 * ) + NEW met2 ( 11707 459 ) ( * 629 ) + NEW met1 ( 11702 85 ) ( 11707 * ) + NEW met2 ( 11707 85 ) ( * 459 ) + NEW met1 ( 12847 51 ) ( * 85 ) + NEW met1 ( 11707 51 ) ( 12847 * ) + NEW met1 ( 11707 51 ) ( * 85 ) + NEW met1 ( 12852 425 ) ( 12857 * ) + NEW met2 ( 12857 85 ) ( * 425 ) + NEW met1 ( 12847 85 ) ( 12857 * ) + NEW met1 ( 12852 1003 ) ( 12857 * ) + NEW met2 ( 12857 425 ) ( * 1003 ) + NEW met1 ( 12852 629 ) ( 12857 * ) + NEW li1 ( 11702 969 ) L1M1_PR_MR + NEW met1 ( 11707 969 ) M1M2_PR + NEW met1 ( 11707 1139 ) M1M2_PR + NEW li1 ( 11661 1139 ) L1M1_PR_MR + NEW li1 ( 11702 629 ) L1M1_PR_MR + NEW met1 ( 11707 629 ) M1M2_PR + NEW li1 ( 11702 459 ) L1M1_PR_MR + NEW met1 ( 11707 459 ) M1M2_PR + NEW li1 ( 11702 85 ) L1M1_PR_MR + NEW met1 ( 11707 85 ) M1M2_PR + NEW li1 ( 12847 85 ) L1M1_PR_MR + NEW li1 ( 12852 425 ) L1M1_PR_MR + NEW met1 ( 12857 425 ) M1M2_PR + NEW met1 ( 12857 85 ) M1M2_PR + NEW li1 ( 12852 1003 ) L1M1_PR_MR + NEW met1 ( 12857 1003 ) M1M2_PR + NEW li1 ( 12852 629 ) L1M1_PR_MR + NEW met1 ( 12857 629 ) M1M2_PR + NEW met1 ( 11702 969 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 11702 629 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 11707 459 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 11702 85 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 12852 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 12852 1003 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 12857 629 ) RECT ( 0 -7 31 7 ) ; + - D_nets.b6 ( buffer.in[6] X ) ( storage_3_1_0.bit6.bit D ) ( storage_3_0_0.bit6.bit D ) ( storage_2_1_0.bit6.bit D ) ( storage_2_0_0.bit6.bit D ) ( storage_1_1_0.bit6.bit D ) ( storage_1_0_0.bit6.bit D ) + ( storage_0_1_0.bit6.bit D ) ( storage_0_0_0.bit6.bit D ) + USE SIGNAL + + ROUTED met1 ( 13915 1003 ) ( 13991 * ) + NEW met2 ( 13915 1003 ) ( * 1139 ) + NEW met1 ( 13915 1139 ) ( 13961 * ) + NEW met1 ( 14002 629 ) ( 14053 * ) + NEW met2 ( 14053 629 ) ( * 1003 ) + NEW met1 ( 13991 1003 ) ( 14053 * ) + NEW met1 ( 14002 425 ) ( 14145 * ) + NEW met2 ( 14145 425 ) ( * 629 ) + NEW met2 ( 14053 629 ) ( 14145 * ) + NEW met1 ( 14002 85 ) ( 14145 * ) + NEW met2 ( 14145 85 ) ( * 425 ) + NEW met1 ( 14145 85 ) ( 15141 * ) + NEW met1 ( 15152 425 ) ( 15157 * ) + NEW met2 ( 15157 85 ) ( * 425 ) + NEW met1 ( 15141 85 ) ( 15157 * ) + NEW met1 ( 15152 629 ) ( 15157 * ) + NEW met2 ( 15157 425 ) ( * 629 ) + NEW met1 ( 15152 1003 ) ( 15157 * ) + NEW met2 ( 15157 629 ) ( * 1003 ) + NEW li1 ( 13991 1003 ) L1M1_PR_MR + NEW met1 ( 13915 1003 ) M1M2_PR + NEW met1 ( 13915 1139 ) M1M2_PR + NEW li1 ( 13961 1139 ) L1M1_PR_MR + NEW li1 ( 14002 629 ) L1M1_PR_MR + NEW met1 ( 14053 629 ) M1M2_PR + NEW met1 ( 14053 1003 ) M1M2_PR + NEW li1 ( 14002 425 ) L1M1_PR_MR + NEW met1 ( 14145 425 ) M1M2_PR + NEW li1 ( 14002 85 ) L1M1_PR_MR + NEW met1 ( 14145 85 ) M1M2_PR + NEW li1 ( 15141 85 ) L1M1_PR_MR + NEW li1 ( 15152 425 ) L1M1_PR_MR + NEW met1 ( 15157 425 ) M1M2_PR + NEW met1 ( 15157 85 ) M1M2_PR + NEW li1 ( 15152 629 ) L1M1_PR_MR + NEW met1 ( 15157 629 ) M1M2_PR + NEW li1 ( 15152 1003 ) L1M1_PR_MR + NEW met1 ( 15157 1003 ) M1M2_PR + NEW met1 ( 15152 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 15152 629 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 15152 1003 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b7 ( buffer.in[7] X ) ( storage_3_1_0.bit7.bit D ) ( storage_3_0_0.bit7.bit D ) ( storage_2_1_0.bit7.bit D ) ( storage_2_0_0.bit7.bit D ) ( storage_1_1_0.bit7.bit D ) ( storage_1_0_0.bit7.bit D ) + ( storage_0_1_0.bit7.bit D ) ( storage_0_0_0.bit7.bit D ) + USE SIGNAL + + ROUTED met1 ( 16302 969 ) ( 16307 * ) + NEW met2 ( 16307 969 ) ( * 1139 ) + NEW met1 ( 16261 1139 ) ( 16307 * ) + NEW met1 ( 16302 629 ) ( 16307 * ) + NEW met2 ( 16307 629 ) ( * 969 ) + NEW met1 ( 16302 51 ) ( * 119 ) + NEW met1 ( 16302 51 ) ( 16491 * ) + NEW met2 ( 16491 51 ) ( * 629 ) + NEW met1 ( 16307 629 ) ( 16491 * ) + NEW met1 ( 16302 459 ) ( 16353 * ) + NEW met2 ( 16353 391 ) ( * 459 ) + NEW met2 ( 16353 391 ) ( 16491 * ) + NEW met1 ( 16491 51 ) ( 17250 * ) + NEW met1 ( 17250 85 ) ( 17441 * ) + NEW met1 ( 17250 51 ) ( * 85 ) + NEW met1 ( 17452 425 ) ( 17457 * ) + NEW met2 ( 17457 85 ) ( * 425 ) + NEW met1 ( 17441 85 ) ( 17457 * ) + NEW met1 ( 17452 629 ) ( 17457 * ) + NEW met2 ( 17457 425 ) ( * 629 ) + NEW met1 ( 17452 969 ) ( 17457 * ) + NEW met2 ( 17457 629 ) ( * 969 ) + NEW li1 ( 16302 969 ) L1M1_PR_MR + NEW met1 ( 16307 969 ) M1M2_PR + NEW met1 ( 16307 1139 ) M1M2_PR + NEW li1 ( 16261 1139 ) L1M1_PR_MR + NEW li1 ( 16302 629 ) L1M1_PR_MR + NEW met1 ( 16307 629 ) M1M2_PR + NEW li1 ( 16302 119 ) L1M1_PR_MR + NEW met1 ( 16491 51 ) M1M2_PR + NEW met1 ( 16491 629 ) M1M2_PR + NEW li1 ( 16302 459 ) L1M1_PR_MR + NEW met1 ( 16353 459 ) M1M2_PR + NEW li1 ( 17441 85 ) L1M1_PR_MR + NEW li1 ( 17452 425 ) L1M1_PR_MR + NEW met1 ( 17457 425 ) M1M2_PR + NEW met1 ( 17457 85 ) M1M2_PR + NEW li1 ( 17452 629 ) L1M1_PR_MR + NEW met1 ( 17457 629 ) M1M2_PR + NEW li1 ( 17452 969 ) L1M1_PR_MR + NEW met1 ( 17457 969 ) M1M2_PR + NEW met1 ( 16302 969 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 16302 629 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 17452 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 17452 629 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 17452 969 ) RECT ( -31 -7 0 7 ) ; + - Q[0] ( PIN Q[0] ) ( mux_slice0_bit0.inv Y ) + USE SIGNAL + + ROUTED met2 ( 1587 1309 ) ( * 1326 0 ) + NEW met1 ( 1541 1309 ) ( 1587 * ) + NEW met1 ( 1587 1309 ) M1M2_PR + NEW li1 ( 1541 1309 ) L1M1_PR_MR ; + - Q[1] ( PIN Q[1] ) ( mux_slice0_bit1.inv Y ) + USE SIGNAL + + ROUTED met2 ( 2783 1309 ) ( * 1326 0 ) + NEW met1 ( 2783 1309 ) ( 3841 * ) + NEW met1 ( 2783 1309 ) M1M2_PR + NEW li1 ( 3841 1309 ) L1M1_PR_MR ; + - Q[2] ( PIN Q[2] ) ( mux_slice0_bit2.inv Y ) + USE SIGNAL + + ROUTED met2 ( 6141 1258 ) ( * 1275 ) + NEW met3 ( 3450 1258 ) ( 6141 * ) + NEW met2 ( 2921 1326 ) ( 2967 * 0 ) + NEW met3 ( 2921 1326 ) ( 3450 * ) + NEW met3 ( 3450 1258 ) ( * 1326 ) + NEW met2 ( 6141 1258 ) M2M3_PR + NEW li1 ( 6141 1275 ) L1M1_PR_MR + NEW met1 ( 6141 1275 ) M1M2_PR + NEW met2 ( 2921 1326 ) M2M3_PR ; + - Q[3] ( PIN Q[3] ) ( mux_slice0_bit3.inv Y ) + USE SIGNAL + + ROUTED met2 ( 8487 1309 ) ( * 1326 0 ) + NEW met1 ( 8441 1309 ) ( 8487 * ) + NEW met1 ( 8487 1309 ) M1M2_PR + NEW li1 ( 8441 1309 ) L1M1_PR_MR ; + - Q[4] ( PIN Q[4] ) ( mux_slice0_bit4.inv Y ) + USE SIGNAL + + ROUTED met2 ( 10787 1309 ) ( * 1326 0 ) + NEW met1 ( 10741 1309 ) ( 10787 * ) + NEW met1 ( 10787 1309 ) M1M2_PR + NEW li1 ( 10741 1309 ) L1M1_PR_MR ; + - Q[5] ( PIN Q[5] ) ( mux_slice0_bit5.inv Y ) + USE SIGNAL + + ROUTED met2 ( 13087 1207 ) ( * 1326 0 ) + NEW li1 ( 13087 1207 ) L1M1_PR_MR + NEW met1 ( 13087 1207 ) M1M2_PR ; + - Q[6] ( PIN Q[6] ) ( mux_slice0_bit6.inv Y ) + USE SIGNAL + + ROUTED met2 ( 15387 1309 ) ( * 1326 0 ) + NEW met1 ( 15341 1309 ) ( 15387 * ) + NEW met1 ( 15387 1309 ) M1M2_PR + NEW li1 ( 15341 1309 ) L1M1_PR_MR ; + - Q[7] ( PIN Q[7] ) ( mux_slice0_bit7.inv Y ) + USE SIGNAL + + ROUTED met2 ( 17687 1309 ) ( * 1326 0 ) + NEW met1 ( 17641 1309 ) ( 17687 * ) + NEW met1 ( 17687 1309 ) M1M2_PR + NEW li1 ( 17641 1309 ) L1M1_PR_MR ; + - addr_rw[0] ( PIN addr_rw[0] ) ( mux_slice0_bit7.aoi B1 ) ( mux_slice0_bit6.aoi B1 ) ( mux_slice0_bit5.aoi B1 ) ( mux_slice0_bit4.aoi B1 ) ( mux_slice0_bit3.aoi B1 ) ( mux_slice0_bit2.aoi B1 ) + ( mux_slice0_bit1.aoi B1 ) ( mux_slice0_bit0.aoi B1 ) ( storage_3_1_0.word_and B ) ( storage_2_1_0.word_and B ) ( storage_1_1_0.word_and B ) ( storage_0_1_0.word_and B ) ( word_sel.inv_addr_0 A ) + USE SIGNAL + + ROUTED met1 ( 1311 1139 ) ( * 1173 ) + NEW met2 ( 10511 1173 ) ( * 1275 ) + NEW met1 ( 8211 1275 ) ( 10511 * ) + NEW met1 ( 8211 1207 ) ( * 1275 ) + NEW met1 ( 12811 1207 ) ( * 1275 ) + NEW met1 ( 10511 1275 ) ( 12811 * ) + NEW met2 ( 15111 1173 ) ( * 1275 ) + NEW met1 ( 12811 1275 ) ( 15111 * ) + NEW met1 ( 7590 1207 ) ( 8211 * ) + NEW met2 ( 5911 1173 ) ( * 1309 ) + NEW met1 ( 5911 1309 ) ( 7590 * ) + NEW met1 ( 7590 1207 ) ( * 1309 ) + NEW met1 ( 5911 1139 ) ( * 1173 ) + NEW met1 ( 5520 1139 ) ( 5911 * ) + NEW met1 ( 3611 1139 ) ( * 1173 ) + NEW met1 ( 3611 1139 ) ( 3703 * ) + NEW met1 ( 3703 1139 ) ( * 1173 ) + NEW met1 ( 3703 1173 ) ( 5520 * ) + NEW met1 ( 5520 1139 ) ( * 1173 ) + NEW met1 ( 2139 1139 ) ( * 1173 ) + NEW met1 ( 2139 1173 ) ( 2507 * ) + NEW met1 ( 2507 1139 ) ( * 1173 ) + NEW met1 ( 2507 1139 ) ( 3611 * ) + NEW met1 ( 1311 1139 ) ( 2139 * ) + NEW met1 ( 17365 1173 ) ( 17411 * ) + NEW met2 ( 17365 1173 ) ( * 1275 ) + NEW met1 ( 19757 1207 ) ( * 1275 ) + NEW met1 ( 17365 1275 ) ( 19757 * ) + NEW met2 ( 20493 969 ) ( * 1207 ) + NEW met1 ( 19757 1207 ) ( 20493 * ) + NEW met2 ( 20493 697 ) ( * 969 ) + NEW met2 ( 20493 425 ) ( * 697 ) + NEW met2 ( 20493 153 ) ( * 425 ) + NEW met3 ( 21350 374 ) ( * 442 0 ) + NEW met3 ( 20493 374 ) ( 21350 * ) + NEW met1 ( 15111 1275 ) ( 17365 * ) + NEW li1 ( 1311 1173 ) L1M1_PR_MR + NEW li1 ( 8211 1207 ) L1M1_PR_MR + NEW li1 ( 10511 1173 ) L1M1_PR_MR + NEW met1 ( 10511 1173 ) M1M2_PR + NEW met1 ( 10511 1275 ) M1M2_PR + NEW li1 ( 12811 1207 ) L1M1_PR_MR + NEW li1 ( 15111 1173 ) L1M1_PR_MR + NEW met1 ( 15111 1173 ) M1M2_PR + NEW met1 ( 15111 1275 ) M1M2_PR + NEW li1 ( 5911 1173 ) L1M1_PR_MR + NEW met1 ( 5911 1173 ) M1M2_PR + NEW met1 ( 5911 1309 ) M1M2_PR + NEW li1 ( 3611 1173 ) L1M1_PR_MR + NEW li1 ( 17411 1173 ) L1M1_PR_MR + NEW met1 ( 17365 1173 ) M1M2_PR + NEW met1 ( 17365 1275 ) M1M2_PR + NEW li1 ( 19757 1207 ) L1M1_PR_MR + NEW li1 ( 20493 969 ) L1M1_PR_MR + NEW met1 ( 20493 969 ) M1M2_PR + NEW met1 ( 20493 1207 ) M1M2_PR + NEW li1 ( 20493 697 ) L1M1_PR_MR + NEW met1 ( 20493 697 ) M1M2_PR + NEW li1 ( 20493 425 ) L1M1_PR_MR + NEW met1 ( 20493 425 ) M1M2_PR + NEW li1 ( 20493 153 ) L1M1_PR_MR + NEW met1 ( 20493 153 ) M1M2_PR + NEW met2 ( 20493 374 ) M2M3_PR ; + - addr_rw[1] ( PIN addr_rw[1] ) ( decoder.inv_1 A ) ( decoder_3.and_layer0 A ) ( decoder_1.and_layer0 A ) + USE SIGNAL + + ROUTED met2 ( 21275 578 ) ( * 595 ) + NEW met3 ( 21275 578 ) ( 21350 * 0 ) + NEW met1 ( 20861 357 ) ( 21275 * ) + NEW met2 ( 21275 357 ) ( * 578 ) + NEW met1 ( 20861 901 ) ( 21275 * ) + NEW met2 ( 21275 595 ) ( * 901 ) + NEW li1 ( 21275 595 ) L1M1_PR_MR + NEW met1 ( 21275 595 ) M1M2_PR + NEW met2 ( 21275 578 ) M2M3_PR + NEW li1 ( 20861 357 ) L1M1_PR_MR + NEW met1 ( 21275 357 ) M1M2_PR + NEW li1 ( 20861 901 ) L1M1_PR_MR + NEW met1 ( 21275 901 ) M1M2_PR ; + - addr_rw[2] ( PIN addr_rw[2] ) ( decoder.inv_2 A ) ( decoder_3.and_layer0 B ) ( decoder_2.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 20953 629 ) ( * 663 ) + NEW met1 ( 20953 629 ) ( 21137 * ) + NEW met2 ( 21137 119 ) ( * 629 ) + NEW met1 ( 21137 119 ) ( 21275 * ) + NEW met1 ( 20953 935 ) ( 21137 * ) + NEW met2 ( 21137 629 ) ( * 935 ) + NEW met3 ( 21137 714 ) ( 21350 * 0 ) + NEW li1 ( 20953 663 ) L1M1_PR_MR + NEW met1 ( 21137 629 ) M1M2_PR + NEW met1 ( 21137 119 ) M1M2_PR + NEW li1 ( 21275 119 ) L1M1_PR_MR + NEW li1 ( 20953 935 ) L1M1_PR_MR + NEW met1 ( 21137 935 ) M1M2_PR + NEW met2 ( 21137 714 ) M2M3_PR ; + - clk ( PIN clk ) ( storage_3_1_0.cg CLK ) ( storage_3_0_0.cg CLK ) ( storage_2_1_0.cg CLK ) ( storage_2_0_0.cg CLK ) ( storage_1_1_0.cg CLK ) ( storage_1_0_0.cg CLK ) + ( storage_0_1_0.cg CLK ) ( storage_0_0_0.cg CLK ) + USE SIGNAL + + ROUTED met2 ( 18929 51 ) ( * 119 ) + NEW met2 ( 18929 119 ) ( * 425 ) + NEW met2 ( 18929 425 ) ( * 663 ) + NEW met2 ( 18929 663 ) ( * 969 ) + NEW met2 ( 20263 119 ) ( * 170 ) + NEW met3 ( 20263 170 ) ( 21350 * 0 ) + NEW met2 ( 20263 170 ) ( * 425 ) + NEW met2 ( 20263 425 ) ( * 663 ) + NEW met2 ( 20263 663 ) ( * 969 ) + NEW met1 ( 19757 51 ) ( * 119 0 ) + NEW met1 ( 18929 51 ) ( 19757 * ) + NEW met1 ( 18929 119 ) M1M2_PR + NEW met1 ( 18929 51 ) M1M2_PR + NEW met1 ( 18929 425 ) M1M2_PR + NEW met1 ( 18929 663 ) M1M2_PR + NEW met1 ( 18929 969 ) M1M2_PR + NEW met1 ( 20263 119 ) M1M2_PR_MR + NEW met2 ( 20263 170 ) M2M3_PR + NEW met1 ( 20263 425 ) M1M2_PR_MR + NEW met1 ( 20263 663 ) M1M2_PR_MR + NEW met1 ( 20263 969 ) M1M2_PR_MR ; + - decoder_0.decoder0 ( storage_0_1_0.word_and A ) ( storage_0_0_0.select_inv_0 A ) ( storage_0_0_0.word_and A ) ( decoder_0.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 19113 153 ) ( 19159 * ) + NEW met2 ( 19159 153 ) ( * 170 ) + NEW met1 ( 20401 187 ) ( * 221 ) + NEW met1 ( 20401 221 ) ( 21183 * ) + NEW met1 ( 19573 85 ) ( 19665 * ) + NEW met2 ( 19665 85 ) ( * 221 ) + NEW met1 ( 19665 221 ) ( 20401 * ) + NEW met3 ( 19159 170 ) ( 19665 * ) + NEW li1 ( 19113 153 ) L1M1_PR_MR + NEW met1 ( 19159 153 ) M1M2_PR + NEW met2 ( 19159 170 ) M2M3_PR + NEW li1 ( 20401 187 ) L1M1_PR_MR + NEW li1 ( 21183 221 ) L1M1_PR_MR + NEW li1 ( 19573 85 ) L1M1_PR_MR + NEW met1 ( 19665 85 ) M1M2_PR + NEW met1 ( 19665 221 ) M1M2_PR + NEW met2 ( 19665 170 ) M2M3_PR ; + - decoder_0.decoder_out ( decoder_0.buf_port0 A ) ( decoder_0.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 21045 119 ) ( 21091 * ) + NEW li1 ( 21091 119 ) L1M1_PR_MR + NEW li1 ( 21045 119 ) L1M1_PR_MR ; + - decoder_0.layer_in0 + USE SIGNAL ; + - decoder_1.decoder0 ( storage_1_1_0.word_and A ) ( storage_1_0_0.select_inv_0 A ) ( storage_1_0_0.word_and A ) ( decoder_1.buf_port0 X ) + USE SIGNAL + + ROUTED met2 ( 19113 391 ) ( * 493 ) + NEW met1 ( 20401 323 ) ( * 357 ) + NEW met1 ( 20401 323 ) ( 21183 * ) + NEW met2 ( 19573 323 ) ( * 425 ) + NEW met1 ( 19573 323 ) ( 20401 * ) + NEW met1 ( 19113 493 ) ( 19573 * ) + NEW li1 ( 19113 391 ) L1M1_PR_MR + NEW met1 ( 19113 391 ) M1M2_PR + NEW met1 ( 19113 493 ) M1M2_PR + NEW li1 ( 20401 357 ) L1M1_PR_MR + NEW li1 ( 21183 323 ) L1M1_PR_MR + NEW li1 ( 19573 425 ) L1M1_PR_MR + NEW met1 ( 19573 425 ) M1M2_PR + NEW met1 ( 19573 323 ) M1M2_PR + NEW li1 ( 19573 493 ) L1M1_PR_MR ; + - decoder_1.decoder_out ( decoder_1.buf_port0 A ) ( decoder_1.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 21045 425 ) ( 21091 * ) + NEW li1 ( 21091 425 ) L1M1_PR_MR + NEW li1 ( 21045 425 ) L1M1_PR_MR ; + - decoder_1.layer_in0 + USE SIGNAL ; + - decoder_2.decoder0 ( storage_2_1_0.word_and A ) ( storage_2_0_0.select_inv_0 A ) ( storage_2_0_0.word_and A ) ( decoder_2.buf_port0 X ) + USE SIGNAL + + ROUTED met1 ( 19113 697 ) ( 19251 * ) + NEW met1 ( 19251 663 ) ( * 697 ) + NEW met1 ( 20401 731 ) ( 21183 * ) + NEW met1 ( 19573 663 ) ( 19665 * ) + NEW met2 ( 19665 663 ) ( * 731 ) + NEW met1 ( 19665 731 ) ( 20401 * ) + NEW met1 ( 19251 663 ) ( 19573 * ) + NEW li1 ( 19113 697 ) L1M1_PR_MR + NEW li1 ( 20401 731 ) L1M1_PR_MR + NEW li1 ( 21183 731 ) L1M1_PR_MR + NEW li1 ( 19573 663 ) L1M1_PR_MR + NEW met1 ( 19665 663 ) M1M2_PR + NEW met1 ( 19665 731 ) M1M2_PR ; + - decoder_2.decoder_out ( decoder_2.buf_port0 A ) ( decoder_2.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 21045 663 ) ( 21091 * ) + NEW li1 ( 21091 663 ) L1M1_PR_MR + NEW li1 ( 21045 663 ) L1M1_PR_MR ; + - decoder_2.layer_in0 + USE SIGNAL ; + - decoder_3.decoder0 ( storage_3_1_0.word_and A ) ( storage_3_0_0.select_inv_0 A ) ( storage_3_0_0.word_and A ) ( decoder_3.buf_port0 X ) + USE SIGNAL + + ROUTED met2 ( 19113 935 ) ( * 1037 ) + NEW met1 ( 20401 867 ) ( * 901 ) + NEW met1 ( 20401 867 ) ( 21183 * ) + NEW met2 ( 19573 867 ) ( * 969 ) + NEW met1 ( 19573 867 ) ( 20401 * ) + NEW met1 ( 19113 1037 ) ( 19573 * ) + NEW li1 ( 19113 935 ) L1M1_PR_MR + NEW met1 ( 19113 935 ) M1M2_PR + NEW met1 ( 19113 1037 ) M1M2_PR + NEW li1 ( 20401 901 ) L1M1_PR_MR + NEW li1 ( 21183 867 ) L1M1_PR_MR + NEW li1 ( 19573 969 ) L1M1_PR_MR + NEW met1 ( 19573 969 ) M1M2_PR + NEW met1 ( 19573 867 ) M1M2_PR + NEW li1 ( 19573 1037 ) L1M1_PR_MR ; + - decoder_3.decoder_out ( decoder_3.buf_port0 A ) ( decoder_3.and_layer0 X ) + USE SIGNAL + + ROUTED met1 ( 21045 969 ) ( 21091 * ) + NEW li1 ( 21091 969 ) L1M1_PR_MR + NEW li1 ( 21045 969 ) L1M1_PR_MR ; + - decoder_3.layer_in0 + USE SIGNAL ; + - inv.addr0 ( mux_slice0_bit7.aoi A1 ) ( mux_slice0_bit6.aoi A1 ) ( mux_slice0_bit5.aoi A1 ) ( mux_slice0_bit4.aoi A1 ) ( mux_slice0_bit3.aoi A1 ) ( mux_slice0_bit2.aoi A1 ) ( mux_slice0_bit1.aoi A1 ) + ( mux_slice0_bit0.aoi A1 ) ( storage_3_0_0.word_and B ) ( storage_2_0_0.word_and B ) ( storage_1_0_0.word_and B ) ( storage_0_0_0.word_and B ) ( word_sel.inv_addr_0 Y ) + USE SIGNAL + + ROUTED met1 ( 1311 1207 ) ( * 1275 ) + NEW met1 ( 1311 1207 ) ( 1357 * ) + NEW met1 ( 1357 1173 ) ( * 1207 ) + NEW met2 ( 8257 1173 ) ( * 1190 ) + NEW met1 ( 10557 1173 ) ( * 1207 ) + NEW met1 ( 10373 1207 ) ( 10557 * ) + NEW met1 ( 10373 1173 ) ( * 1207 ) + NEW met1 ( 8257 1173 ) ( 10373 * ) + NEW met1 ( 12765 1173 ) ( 12857 * ) + NEW met1 ( 12765 1173 ) ( * 1207 ) + NEW met1 ( 12673 1207 ) ( 12765 * ) + NEW met1 ( 12673 1173 ) ( * 1207 ) + NEW met1 ( 10557 1173 ) ( 12673 * ) + NEW met1 ( 15157 1173 ) ( * 1207 ) + NEW met1 ( 14973 1207 ) ( 15157 * ) + NEW met1 ( 14973 1173 ) ( * 1207 ) + NEW met1 ( 12857 1173 ) ( 14973 * ) + NEW met1 ( 17181 1173 ) ( * 1241 ) + NEW met1 ( 15157 1173 ) ( 17181 * ) + NEW met2 ( 17457 1173 ) ( * 1190 ) + NEW met2 ( 17411 1190 ) ( 17457 * ) + NEW met2 ( 17411 1190 ) ( * 1241 ) + NEW met2 ( 19205 935 ) ( * 1173 ) + NEW met1 ( 17457 1173 ) ( 19205 * ) + NEW met2 ( 19205 663 ) ( * 935 ) + NEW met2 ( 19205 391 ) ( * 663 ) + NEW met2 ( 19205 119 ) ( * 391 ) + NEW met1 ( 17181 1241 ) ( 17411 * ) + NEW met1 ( 5957 1173 ) ( 6049 * ) + NEW met1 ( 6049 1139 ) ( * 1173 ) + NEW met1 ( 6049 1139 ) ( 6095 * ) + NEW met2 ( 6095 1139 ) ( * 1190 ) + NEW met3 ( 6095 1190 ) ( 8257 * ) + NEW met2 ( 3657 1173 ) ( * 1190 ) + NEW met1 ( 2461 1207 ) ( * 1275 ) + NEW met1 ( 2461 1207 ) ( 3657 * ) + NEW met1 ( 3657 1173 ) ( * 1207 ) + NEW met1 ( 1311 1275 ) ( 2461 * ) + NEW met3 ( 3657 1190 ) ( 6095 * ) + NEW met1 ( 19205 1173 ) ( 19803 * ) + NEW li1 ( 1357 1173 ) L1M1_PR_MR + NEW li1 ( 8257 1173 ) L1M1_PR_MR + NEW met1 ( 8257 1173 ) M1M2_PR + NEW met2 ( 8257 1190 ) M2M3_PR + NEW li1 ( 10557 1173 ) L1M1_PR_MR + NEW li1 ( 12857 1173 ) L1M1_PR_MR + NEW li1 ( 15157 1173 ) L1M1_PR_MR + NEW li1 ( 17457 1173 ) L1M1_PR_MR + NEW met1 ( 17457 1173 ) M1M2_PR + NEW met1 ( 17411 1241 ) M1M2_PR + NEW li1 ( 19205 935 ) L1M1_PR_MR + NEW met1 ( 19205 935 ) M1M2_PR + NEW met1 ( 19205 1173 ) M1M2_PR + NEW li1 ( 19205 663 ) L1M1_PR_MR + NEW met1 ( 19205 663 ) M1M2_PR + NEW li1 ( 19205 391 ) L1M1_PR_MR + NEW met1 ( 19205 391 ) M1M2_PR + NEW li1 ( 19205 119 ) L1M1_PR_MR + NEW met1 ( 19205 119 ) M1M2_PR + NEW li1 ( 5957 1173 ) L1M1_PR_MR + NEW met1 ( 6095 1139 ) M1M2_PR + NEW met2 ( 6095 1190 ) M2M3_PR + NEW li1 ( 3657 1173 ) L1M1_PR_MR + NEW met1 ( 3657 1173 ) M1M2_PR + NEW met2 ( 3657 1190 ) M2M3_PR + NEW li1 ( 19803 1173 ) L1M1_PR_MR ; + - inv.addr1 ( decoder.inv_1 Y ) ( decoder_2.and_layer0 A ) ( decoder_0.and_layer0 A ) + USE SIGNAL + + ROUTED met1 ( 20861 697 ) ( 21321 * ) + NEW met2 ( 20861 187 ) ( * 697 ) + NEW li1 ( 20861 697 ) L1M1_PR_MR + NEW li1 ( 21321 697 ) L1M1_PR_MR + NEW li1 ( 20861 187 ) L1M1_PR_MR + NEW met1 ( 20861 187 ) M1M2_PR + NEW met1 ( 20861 697 ) M1M2_PR ; + - inv.addr2 ( decoder.inv_2 Y ) ( decoder_1.and_layer0 B ) ( decoder_0.and_layer0 B ) + USE SIGNAL + + ROUTED met1 ( 20953 153 ) ( 21321 * ) + NEW met1 ( 20907 391 ) ( 20953 * ) + NEW met2 ( 20907 153 ) ( * 391 ) + NEW met1 ( 20907 153 ) ( 20953 * ) + NEW li1 ( 20953 153 ) L1M1_PR_MR + NEW li1 ( 21321 153 ) L1M1_PR_MR + NEW li1 ( 20953 391 ) L1M1_PR_MR + NEW met1 ( 20907 391 ) M1M2_PR + NEW met1 ( 20907 153 ) M1M2_PR ; + - mux_slice0_bit0.aoi_out ( mux_slice0_bit0.inv A ) ( mux_slice0_bit0.aoi Y ) + USE SIGNAL + + ROUTED met1 ( 1495 1207 ) ( * 1241 ) + NEW met1 ( 1357 1241 ) ( 1495 * ) + NEW li1 ( 1357 1241 ) L1M1_PR_MR + NEW li1 ( 1495 1207 ) L1M1_PR_MR ; + - mux_slice0_bit1.aoi_out ( mux_slice0_bit1.inv A ) ( mux_slice0_bit1.aoi Y ) + USE SIGNAL + + ROUTED met1 ( 3795 1207 ) ( * 1241 ) + NEW met1 ( 3657 1241 ) ( 3795 * ) + NEW li1 ( 3795 1207 ) L1M1_PR_MR + NEW li1 ( 3657 1241 ) L1M1_PR_MR ; + - mux_slice0_bit2.aoi_out ( mux_slice0_bit2.inv A ) ( mux_slice0_bit2.aoi Y ) + USE SIGNAL + + ROUTED met1 ( 6095 1207 ) ( * 1241 ) + NEW met1 ( 5957 1241 ) ( 6095 * ) + NEW li1 ( 6095 1207 ) L1M1_PR_MR + NEW li1 ( 5957 1241 ) L1M1_PR_MR ; + - mux_slice0_bit3.aoi_out ( mux_slice0_bit3.inv A ) ( mux_slice0_bit3.aoi Y ) + USE SIGNAL + + ROUTED met1 ( 8395 1207 ) ( * 1241 ) + NEW met1 ( 8257 1241 ) ( 8395 * ) + NEW li1 ( 8395 1207 ) L1M1_PR_MR + NEW li1 ( 8257 1241 ) L1M1_PR_MR ; + - mux_slice0_bit4.aoi_out ( mux_slice0_bit4.inv A ) ( mux_slice0_bit4.aoi Y ) + USE SIGNAL + + ROUTED met1 ( 10695 1207 ) ( * 1241 ) + NEW met1 ( 10557 1241 ) ( 10695 * ) + NEW li1 ( 10695 1207 ) L1M1_PR_MR + NEW li1 ( 10557 1241 ) L1M1_PR_MR ; + - mux_slice0_bit5.aoi_out ( mux_slice0_bit5.inv A ) ( mux_slice0_bit5.aoi Y ) + USE SIGNAL + + ROUTED met1 ( 12995 1207 ) ( * 1241 ) + NEW met1 ( 12857 1241 ) ( 12995 * ) + NEW li1 ( 12995 1207 ) L1M1_PR_MR + NEW li1 ( 12857 1241 ) L1M1_PR_MR ; + - mux_slice0_bit6.aoi_out ( mux_slice0_bit6.inv A ) ( mux_slice0_bit6.aoi Y ) + USE SIGNAL + + ROUTED met1 ( 15295 1207 ) ( * 1241 ) + NEW met1 ( 15157 1241 ) ( 15295 * ) + NEW li1 ( 15295 1207 ) L1M1_PR_MR + NEW li1 ( 15157 1241 ) L1M1_PR_MR ; + - mux_slice0_bit7.aoi_out ( mux_slice0_bit7.inv A ) ( mux_slice0_bit7.aoi Y ) + USE SIGNAL + + ROUTED met1 ( 17595 1207 ) ( * 1241 ) + NEW met1 ( 17457 1241 ) ( 17595 * ) + NEW li1 ( 17595 1207 ) L1M1_PR_MR + NEW li1 ( 17457 1241 ) L1M1_PR_MR ; + - row0.select0_b ( storage_0_1_0.bit7.obuf0 TE_B ) ( storage_0_1_0.bit6.obuf0 TE_B ) ( storage_0_1_0.bit5.obuf0 TE_B ) ( storage_0_1_0.bit4.obuf0 TE_B ) ( storage_0_1_0.bit3.obuf0 TE_B ) ( storage_0_1_0.bit2.obuf0 TE_B ) ( storage_0_1_0.bit1.obuf0 TE_B ) + ( storage_0_1_0.bit0.obuf0 TE_B ) ( storage_0_0_0.select_inv_0 Y ) ( storage_0_0_0.bit7.obuf0 TE_B ) ( storage_0_0_0.bit6.obuf0 TE_B ) ( storage_0_0_0.bit5.obuf0 TE_B ) ( storage_0_0_0.bit4.obuf0 TE_B ) ( storage_0_0_0.bit3.obuf0 TE_B ) ( storage_0_0_0.bit2.obuf0 TE_B ) + ( storage_0_0_0.bit1.obuf0 TE_B ) ( storage_0_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 15847 153 ) ( 16123 * ) + NEW met2 ( 16123 153 ) ( * 221 ) + NEW met1 ( 16123 221 ) ( 17089 * ) + NEW met2 ( 17089 119 ) ( * 221 ) + NEW met1 ( 14697 119 ) ( 14973 * ) + NEW met1 ( 14973 117 ) ( * 119 ) + NEW met1 ( 14973 117 ) ( 15019 * ) + NEW met1 ( 15019 117 ) ( * 119 ) + NEW met1 ( 15019 119 ) ( 15847 * ) + NEW met1 ( 15847 119 ) ( * 153 ) + NEW met1 ( 13547 119 ) ( 14697 * ) + NEW met1 ( 12397 85 ) ( * 119 ) + NEW met1 ( 12397 85 ) ( 12811 * ) + NEW met1 ( 12811 85 ) ( * 119 ) + NEW met1 ( 12811 119 ) ( 13547 * ) + NEW met1 ( 11247 119 ) ( 11615 * ) + NEW met2 ( 11615 34 ) ( * 119 ) + NEW met2 ( 11615 34 ) ( 11753 * ) + NEW met2 ( 11753 34 ) ( * 85 ) + NEW met1 ( 11753 85 ) ( 12397 * ) + NEW met1 ( 10097 119 ) ( 11247 * ) + NEW met1 ( 8947 119 ) ( 10097 * ) + NEW met1 ( 7797 119 ) ( 8947 * ) + NEW met1 ( 897 119 ) ( 2047 * ) + NEW met1 ( 2047 119 ) ( * 153 ) + NEW met1 ( 18147 153 ) ( * 221 ) + NEW met1 ( 17273 119 ) ( * 221 ) + NEW met1 ( 17273 221 ) ( 18147 * ) + NEW met1 ( 16997 119 ) ( 17273 * ) + NEW met1 ( 6647 153 ) ( 7015 * ) + NEW met1 ( 7015 119 ) ( * 153 ) + NEW met1 ( 5865 119 ) ( * 153 ) + NEW met1 ( 5865 119 ) ( 6647 * ) + NEW met1 ( 6647 119 ) ( * 153 ) + NEW met1 ( 7015 119 ) ( 7797 * ) + NEW met1 ( 2415 119 ) ( 3197 * ) + NEW met1 ( 2415 119 ) ( * 153 ) + NEW met1 ( 3611 119 ) ( 4347 * ) + NEW met1 ( 3611 85 ) ( * 119 ) + NEW met1 ( 3197 85 ) ( 3611 * ) + NEW met1 ( 3197 85 ) ( * 119 ) + NEW met1 ( 4761 119 ) ( 5497 * ) + NEW met1 ( 4761 85 ) ( * 119 ) + NEW met1 ( 4347 85 ) ( 4761 * ) + NEW met1 ( 4347 85 ) ( * 119 ) + NEW met1 ( 5497 119 ) ( * 153 ) + NEW met1 ( 2047 153 ) ( 2415 * ) + NEW met1 ( 5497 153 ) ( 5865 * ) + NEW met1 ( 18147 221 ) ( 19619 * ) + NEW li1 ( 16997 119 ) L1M1_PR_MR + NEW li1 ( 15847 153 ) L1M1_PR_MR + NEW met1 ( 16123 153 ) M1M2_PR + NEW met1 ( 16123 221 ) M1M2_PR + NEW met1 ( 17089 221 ) M1M2_PR + NEW met1 ( 17089 119 ) M1M2_PR + NEW li1 ( 14697 119 ) L1M1_PR_MR + NEW li1 ( 13547 119 ) L1M1_PR_MR + NEW li1 ( 12397 119 ) L1M1_PR_MR + NEW li1 ( 11247 119 ) L1M1_PR_MR + NEW met1 ( 11615 119 ) M1M2_PR + NEW met1 ( 11753 85 ) M1M2_PR + NEW li1 ( 10097 119 ) L1M1_PR_MR + NEW li1 ( 8947 119 ) L1M1_PR_MR + NEW li1 ( 7797 119 ) L1M1_PR_MR + NEW li1 ( 2047 153 ) L1M1_PR_MR + NEW li1 ( 897 119 ) L1M1_PR_MR + NEW li1 ( 18147 153 ) L1M1_PR_MR + NEW li1 ( 6647 153 ) L1M1_PR_MR + NEW li1 ( 3197 119 ) L1M1_PR_MR + NEW li1 ( 4347 119 ) L1M1_PR_MR + NEW li1 ( 5497 119 ) L1M1_PR_MR + NEW li1 ( 19619 221 ) L1M1_PR_MR ; + - row1.select0_b ( storage_1_1_0.bit7.obuf0 TE_B ) ( storage_1_1_0.bit6.obuf0 TE_B ) ( storage_1_1_0.bit5.obuf0 TE_B ) ( storage_1_1_0.bit4.obuf0 TE_B ) ( storage_1_1_0.bit3.obuf0 TE_B ) ( storage_1_1_0.bit2.obuf0 TE_B ) ( storage_1_1_0.bit1.obuf0 TE_B ) + ( storage_1_1_0.bit0.obuf0 TE_B ) ( storage_1_0_0.select_inv_0 Y ) ( storage_1_0_0.bit7.obuf0 TE_B ) ( storage_1_0_0.bit6.obuf0 TE_B ) ( storage_1_0_0.bit5.obuf0 TE_B ) ( storage_1_0_0.bit4.obuf0 TE_B ) ( storage_1_0_0.bit3.obuf0 TE_B ) ( storage_1_0_0.bit2.obuf0 TE_B ) + ( storage_1_0_0.bit1.obuf0 TE_B ) ( storage_1_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met2 ( 15847 374 ) ( * 425 ) + NEW met3 ( 15847 374 ) ( 17089 * ) + NEW met2 ( 17089 374 ) ( * 425 ) + NEW met1 ( 14697 425 ) ( * 459 ) + NEW met1 ( 14697 459 ) ( 15847 * ) + NEW met1 ( 15847 425 ) ( * 459 ) + NEW met1 ( 13547 425 ) ( * 459 ) + NEW met1 ( 13547 459 ) ( 14697 * ) + NEW met1 ( 12397 425 ) ( * 459 ) + NEW met1 ( 12397 459 ) ( 13547 * ) + NEW met1 ( 11247 425 ) ( 12397 * ) + NEW met1 ( 10097 391 ) ( 10373 * ) + NEW met2 ( 10373 391 ) ( * 493 ) + NEW met1 ( 10373 493 ) ( 11247 * ) + NEW met1 ( 11247 425 ) ( * 493 ) + NEW met1 ( 8947 323 ) ( * 391 ) + NEW met1 ( 8947 323 ) ( 10097 * ) + NEW met1 ( 10097 323 ) ( * 391 ) + NEW met1 ( 7797 323 ) ( * 391 ) + NEW met1 ( 7797 323 ) ( 8947 * ) + NEW met1 ( 897 323 ) ( * 391 ) + NEW met1 ( 897 323 ) ( 2047 * ) + NEW met1 ( 2047 323 ) ( * 391 ) + NEW met1 ( 18147 391 ) ( 19021 * ) + NEW met1 ( 19021 391 ) ( * 425 ) + NEW met1 ( 17273 425 ) ( * 459 ) + NEW met1 ( 17273 459 ) ( 18147 * ) + NEW met1 ( 18147 391 ) ( * 459 ) + NEW met1 ( 16997 425 ) ( 17273 * ) + NEW met1 ( 6647 425 ) ( * 459 ) + NEW met1 ( 6969 323 ) ( * 357 ) + NEW met1 ( 6647 357 ) ( 6969 * ) + NEW met1 ( 6647 357 ) ( * 425 ) + NEW met1 ( 6969 323 ) ( 7797 * ) + NEW met1 ( 3197 425 ) ( * 459 ) + NEW met1 ( 2461 459 ) ( 3197 * ) + NEW met1 ( 2461 425 ) ( * 459 ) + NEW met1 ( 2323 425 ) ( 2461 * ) + NEW met1 ( 2323 391 ) ( * 425 ) + NEW met1 ( 4347 425 ) ( * 459 ) + NEW met1 ( 3197 459 ) ( 4347 * ) + NEW met1 ( 5497 425 ) ( * 459 ) + NEW met1 ( 2047 391 ) ( 2323 * ) + NEW met1 ( 4347 459 ) ( 6647 * ) + NEW met1 ( 19481 391 ) ( * 425 ) + NEW met1 ( 19481 391 ) ( 19619 * ) + NEW met1 ( 19021 425 ) ( 19481 * ) + NEW li1 ( 16997 425 ) L1M1_PR_MR + NEW li1 ( 15847 425 ) L1M1_PR_MR + NEW met1 ( 15847 425 ) M1M2_PR + NEW met2 ( 15847 374 ) M2M3_PR + NEW met2 ( 17089 374 ) M2M3_PR + NEW met1 ( 17089 425 ) M1M2_PR + NEW li1 ( 14697 425 ) L1M1_PR_MR + NEW li1 ( 13547 425 ) L1M1_PR_MR + NEW li1 ( 12397 425 ) L1M1_PR_MR + NEW li1 ( 11247 425 ) L1M1_PR_MR + NEW li1 ( 10097 391 ) L1M1_PR_MR + NEW met1 ( 10373 391 ) M1M2_PR + NEW met1 ( 10373 493 ) M1M2_PR + NEW li1 ( 8947 391 ) L1M1_PR_MR + NEW li1 ( 7797 391 ) L1M1_PR_MR + NEW li1 ( 2047 391 ) L1M1_PR_MR + NEW li1 ( 897 391 ) L1M1_PR_MR + NEW li1 ( 18147 391 ) L1M1_PR_MR + NEW li1 ( 6647 425 ) L1M1_PR_MR + NEW li1 ( 3197 425 ) L1M1_PR_MR + NEW li1 ( 4347 425 ) L1M1_PR_MR + NEW li1 ( 5497 425 ) L1M1_PR_MR + NEW li1 ( 19619 391 ) L1M1_PR_MR + NEW met1 ( 5497 459 ) RECT ( -25 -7 0 7 ) ; + - row2.select0_b ( storage_2_1_0.bit7.obuf0 TE_B ) ( storage_2_1_0.bit6.obuf0 TE_B ) ( storage_2_1_0.bit5.obuf0 TE_B ) ( storage_2_1_0.bit4.obuf0 TE_B ) ( storage_2_1_0.bit3.obuf0 TE_B ) ( storage_2_1_0.bit2.obuf0 TE_B ) ( storage_2_1_0.bit1.obuf0 TE_B ) + ( storage_2_1_0.bit0.obuf0 TE_B ) ( storage_2_0_0.select_inv_0 Y ) ( storage_2_0_0.bit7.obuf0 TE_B ) ( storage_2_0_0.bit6.obuf0 TE_B ) ( storage_2_0_0.bit5.obuf0 TE_B ) ( storage_2_0_0.bit4.obuf0 TE_B ) ( storage_2_0_0.bit3.obuf0 TE_B ) ( storage_2_0_0.bit2.obuf0 TE_B ) + ( storage_2_0_0.bit1.obuf0 TE_B ) ( storage_2_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 15847 663 ) ( 16997 * ) + NEW met1 ( 16997 663 ) ( * 697 ) + NEW met1 ( 14697 663 ) ( 15847 * ) + NEW met1 ( 13547 595 ) ( * 663 ) + NEW met1 ( 13547 595 ) ( 14099 * ) + NEW met1 ( 14099 595 ) ( * 629 ) + NEW met1 ( 14099 629 ) ( 14697 * ) + NEW met1 ( 14697 629 ) ( * 663 ) + NEW met2 ( 12397 595 ) ( * 663 ) + NEW met1 ( 12397 595 ) ( 13547 * ) + NEW met1 ( 11247 629 ) ( * 663 ) + NEW met1 ( 11247 629 ) ( 11615 * ) + NEW met1 ( 11615 595 ) ( * 629 ) + NEW met1 ( 11615 595 ) ( 12397 * ) + NEW met1 ( 10097 697 ) ( 10465 * ) + NEW met1 ( 10465 663 ) ( * 697 ) + NEW met1 ( 10465 663 ) ( 11247 * ) + NEW met1 ( 8947 663 ) ( 10097 * ) + NEW met1 ( 10097 663 ) ( * 697 ) + NEW met1 ( 7797 697 ) ( 8165 * ) + NEW met1 ( 8165 663 ) ( * 697 ) + NEW met1 ( 8165 663 ) ( 8947 * ) + NEW met1 ( 7797 663 ) ( * 697 ) + NEW met1 ( 897 697 ) ( 1265 * ) + NEW met1 ( 1265 663 ) ( * 697 ) + NEW met1 ( 1265 663 ) ( 2047 * ) + NEW met1 ( 18147 697 ) ( * 731 ) + NEW met1 ( 17365 663 ) ( * 697 ) + NEW met1 ( 17365 663 ) ( 18147 * ) + NEW met1 ( 18147 663 ) ( * 697 ) + NEW met1 ( 16997 697 ) ( 17365 * ) + NEW met1 ( 6647 697 ) ( 7015 * ) + NEW met1 ( 7015 663 ) ( * 697 ) + NEW met1 ( 5865 663 ) ( * 697 ) + NEW met1 ( 5865 663 ) ( 6647 * ) + NEW met1 ( 6647 663 ) ( * 697 ) + NEW met1 ( 7015 663 ) ( 7797 * ) + NEW met1 ( 3611 663 ) ( 4347 * ) + NEW met1 ( 3611 629 ) ( * 663 ) + NEW met1 ( 3197 629 ) ( 3611 * ) + NEW met1 ( 3197 629 ) ( * 663 ) + NEW met1 ( 4761 663 ) ( 5497 * ) + NEW met1 ( 4761 629 ) ( * 663 ) + NEW met1 ( 4347 629 ) ( 4761 * ) + NEW met1 ( 4347 629 ) ( * 663 ) + NEW met1 ( 5497 663 ) ( * 697 ) + NEW met1 ( 2047 663 ) ( 3197 * ) + NEW met1 ( 5497 697 ) ( 5865 * ) + NEW met1 ( 18147 731 ) ( 19619 * ) + NEW li1 ( 16997 697 ) L1M1_PR_MR + NEW li1 ( 15847 663 ) L1M1_PR_MR + NEW li1 ( 14697 663 ) L1M1_PR_MR + NEW li1 ( 13547 663 ) L1M1_PR_MR + NEW li1 ( 12397 663 ) L1M1_PR_MR + NEW met1 ( 12397 663 ) M1M2_PR + NEW met1 ( 12397 595 ) M1M2_PR + NEW li1 ( 11247 663 ) L1M1_PR_MR + NEW li1 ( 10097 697 ) L1M1_PR_MR + NEW li1 ( 8947 663 ) L1M1_PR_MR + NEW li1 ( 7797 697 ) L1M1_PR_MR + NEW li1 ( 2047 663 ) L1M1_PR_MR + NEW li1 ( 897 697 ) L1M1_PR_MR + NEW li1 ( 18147 697 ) L1M1_PR_MR + NEW li1 ( 6647 697 ) L1M1_PR_MR + NEW li1 ( 3197 663 ) L1M1_PR_MR + NEW li1 ( 4347 663 ) L1M1_PR_MR + NEW li1 ( 5497 663 ) L1M1_PR_MR + NEW li1 ( 19619 731 ) L1M1_PR_MR ; + - row3.select0_b ( storage_3_1_0.bit7.obuf0 TE_B ) ( storage_3_1_0.bit6.obuf0 TE_B ) ( storage_3_1_0.bit5.obuf0 TE_B ) ( storage_3_1_0.bit4.obuf0 TE_B ) ( storage_3_1_0.bit3.obuf0 TE_B ) ( storage_3_1_0.bit2.obuf0 TE_B ) ( storage_3_1_0.bit1.obuf0 TE_B ) + ( storage_3_1_0.bit0.obuf0 TE_B ) ( storage_3_0_0.select_inv_0 Y ) ( storage_3_0_0.bit7.obuf0 TE_B ) ( storage_3_0_0.bit6.obuf0 TE_B ) ( storage_3_0_0.bit5.obuf0 TE_B ) ( storage_3_0_0.bit4.obuf0 TE_B ) ( storage_3_0_0.bit3.obuf0 TE_B ) ( storage_3_0_0.bit2.obuf0 TE_B ) + ( storage_3_0_0.bit1.obuf0 TE_B ) ( storage_3_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 16997 969 ) ( * 1003 ) + NEW met1 ( 15847 935 ) ( 16215 * ) + NEW met1 ( 16215 935 ) ( * 1003 ) + NEW met1 ( 16215 1003 ) ( 16997 * ) + NEW met2 ( 14697 918 ) ( * 935 ) + NEW met3 ( 14697 918 ) ( 15847 * ) + NEW met2 ( 15847 918 ) ( * 935 ) + NEW met1 ( 13547 935 ) ( 13915 * ) + NEW met1 ( 13915 935 ) ( * 969 ) + NEW met1 ( 13915 969 ) ( 14651 * ) + NEW met1 ( 14651 935 ) ( * 969 ) + NEW met1 ( 14651 935 ) ( 14697 * ) + NEW met2 ( 12397 918 ) ( * 935 ) + NEW met3 ( 12397 918 ) ( 13547 * ) + NEW met2 ( 13547 918 ) ( * 935 ) + NEW met2 ( 11247 918 ) ( * 935 ) + NEW met3 ( 11247 918 ) ( 12397 * ) + NEW met2 ( 10097 918 ) ( * 935 ) + NEW met3 ( 10097 918 ) ( 11247 * ) + NEW met2 ( 8947 918 ) ( * 935 ) + NEW met3 ( 8947 918 ) ( 10097 * ) + NEW met2 ( 7797 918 ) ( * 935 ) + NEW met3 ( 7797 918 ) ( 8947 * ) + NEW met1 ( 897 901 ) ( * 935 ) + NEW met1 ( 897 901 ) ( 1173 * ) + NEW met1 ( 1173 867 ) ( * 901 ) + NEW met1 ( 1173 867 ) ( 2047 * ) + NEW met1 ( 2047 867 ) ( * 935 ) + NEW met1 ( 18147 935 ) ( 19021 * ) + NEW met1 ( 19021 935 ) ( * 969 ) + NEW met1 ( 18147 935 ) ( * 1003 ) + NEW met1 ( 16997 1003 ) ( 18147 * ) + NEW met2 ( 6647 918 ) ( * 935 ) + NEW met1 ( 6647 867 ) ( * 935 ) + NEW met3 ( 6647 918 ) ( 7797 * ) + NEW met1 ( 3197 969 ) ( * 1003 ) + NEW met1 ( 2323 1003 ) ( 3197 * ) + NEW met1 ( 2323 935 ) ( * 1003 ) + NEW met1 ( 4347 867 ) ( * 935 ) + NEW met1 ( 3519 867 ) ( 4347 * ) + NEW met1 ( 3519 867 ) ( * 901 ) + NEW met1 ( 3197 901 ) ( 3519 * ) + NEW met1 ( 3197 901 ) ( * 969 ) + NEW met1 ( 4669 867 ) ( * 901 ) + NEW met1 ( 4347 901 ) ( 4669 * ) + NEW met1 ( 5497 867 ) ( * 935 ) + NEW met1 ( 2047 935 ) ( 2323 * ) + NEW met1 ( 4669 867 ) ( 6647 * ) + NEW met1 ( 19481 935 ) ( * 969 ) + NEW met1 ( 19481 935 ) ( 19619 * ) + NEW met1 ( 19021 969 ) ( 19481 * ) + NEW li1 ( 16997 969 ) L1M1_PR_MR + NEW li1 ( 15847 935 ) L1M1_PR_MR + NEW li1 ( 14697 935 ) L1M1_PR_MR + NEW met1 ( 14697 935 ) M1M2_PR + NEW met2 ( 14697 918 ) M2M3_PR + NEW met2 ( 15847 918 ) M2M3_PR + NEW met1 ( 15847 935 ) M1M2_PR + NEW li1 ( 13547 935 ) L1M1_PR_MR + NEW li1 ( 12397 935 ) L1M1_PR_MR + NEW met1 ( 12397 935 ) M1M2_PR + NEW met2 ( 12397 918 ) M2M3_PR + NEW met2 ( 13547 918 ) M2M3_PR + NEW met1 ( 13547 935 ) M1M2_PR + NEW li1 ( 11247 935 ) L1M1_PR_MR + NEW met1 ( 11247 935 ) M1M2_PR + NEW met2 ( 11247 918 ) M2M3_PR + NEW li1 ( 10097 935 ) L1M1_PR_MR + NEW met1 ( 10097 935 ) M1M2_PR + NEW met2 ( 10097 918 ) M2M3_PR + NEW li1 ( 8947 935 ) L1M1_PR_MR + NEW met1 ( 8947 935 ) M1M2_PR + NEW met2 ( 8947 918 ) M2M3_PR + NEW li1 ( 7797 935 ) L1M1_PR_MR + NEW met1 ( 7797 935 ) M1M2_PR + NEW met2 ( 7797 918 ) M2M3_PR + NEW li1 ( 2047 935 ) L1M1_PR_MR + NEW li1 ( 897 935 ) L1M1_PR_MR + NEW li1 ( 18147 935 ) L1M1_PR_MR + NEW li1 ( 6647 935 ) L1M1_PR_MR + NEW met1 ( 6647 935 ) M1M2_PR + NEW met2 ( 6647 918 ) M2M3_PR + NEW li1 ( 3197 969 ) L1M1_PR_MR + NEW li1 ( 4347 935 ) L1M1_PR_MR + NEW li1 ( 5497 935 ) L1M1_PR_MR + NEW li1 ( 19619 935 ) L1M1_PR_MR ; + - storage_0_0_0.bit0.storage ( storage_0_0_0.bit0.obuf0 A ) ( storage_0_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 805 153 ) ( * 187 ) + NEW met1 ( 759 187 ) ( 805 * ) + NEW li1 ( 805 153 ) L1M1_PR_MR + NEW li1 ( 759 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit1.storage ( storage_0_0_0.bit1.obuf0 A ) ( storage_0_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3105 153 ) ( * 187 ) + NEW met1 ( 3059 187 ) ( 3105 * ) + NEW li1 ( 3105 153 ) L1M1_PR_MR + NEW li1 ( 3059 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit2.storage ( storage_0_0_0.bit2.obuf0 A ) ( storage_0_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5405 153 ) ( * 187 ) + NEW met1 ( 5359 187 ) ( 5405 * ) + NEW li1 ( 5405 153 ) L1M1_PR_MR + NEW li1 ( 5359 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit3.storage ( storage_0_0_0.bit3.obuf0 A ) ( storage_0_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7705 153 ) ( * 187 ) + NEW met1 ( 7659 187 ) ( 7705 * ) + NEW li1 ( 7705 153 ) L1M1_PR_MR + NEW li1 ( 7659 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit4.storage ( storage_0_0_0.bit4.obuf0 A ) ( storage_0_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 10005 153 ) ( * 187 ) + NEW met1 ( 9959 187 ) ( 10005 * ) + NEW li1 ( 10005 153 ) L1M1_PR_MR + NEW li1 ( 9959 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit5.storage ( storage_0_0_0.bit5.obuf0 A ) ( storage_0_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 12305 153 ) ( * 187 ) + NEW met1 ( 12259 187 ) ( 12305 * ) + NEW li1 ( 12305 153 ) L1M1_PR_MR + NEW li1 ( 12259 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit6.storage ( storage_0_0_0.bit6.obuf0 A ) ( storage_0_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 14605 153 ) ( * 187 ) + NEW met1 ( 14559 187 ) ( 14605 * ) + NEW li1 ( 14605 153 ) L1M1_PR_MR + NEW li1 ( 14559 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit7.storage ( storage_0_0_0.bit7.obuf0 A ) ( storage_0_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 16905 153 ) ( * 187 ) + NEW met1 ( 16859 187 ) ( 16905 * ) + NEW li1 ( 16905 153 ) L1M1_PR_MR + NEW li1 ( 16859 187 ) L1M1_PR_MR ; + - storage_0_0_0.gclock ( storage_0_0_0.cg GCLK ) ( storage_0_0_0.bit7.bit CLK ) ( storage_0_0_0.bit6.bit CLK ) ( storage_0_0_0.bit5.bit CLK ) ( storage_0_0_0.bit4.bit CLK ) ( storage_0_0_0.bit3.bit CLK ) ( storage_0_0_0.bit2.bit CLK ) + ( storage_0_0_0.bit1.bit CLK ) ( storage_0_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met2 ( 16169 153 ) ( * 170 ) + NEW met2 ( 13869 153 ) ( * 170 ) + NEW met3 ( 13869 170 ) ( 16169 * ) + NEW met2 ( 11569 102 ) ( * 153 ) + NEW met3 ( 11569 102 ) ( 12466 * ) + NEW met3 ( 12466 102 ) ( * 170 ) + NEW met3 ( 12466 170 ) ( 13869 * ) + NEW met2 ( 9269 102 ) ( * 153 ) + NEW met3 ( 9269 102 ) ( 11569 * ) + NEW met1 ( 69 51 ) ( * 119 ) + NEW met2 ( 19067 153 ) ( * 170 ) + NEW met3 ( 16169 170 ) ( 19067 * ) + NEW met1 ( 6923 119 ) ( 6969 * ) + NEW met2 ( 6923 102 ) ( * 119 ) + NEW met3 ( 6923 102 ) ( 9269 * ) + NEW met2 ( 4669 102 ) ( * 119 ) + NEW met2 ( 2369 102 ) ( * 119 ) + NEW met3 ( 2369 102 ) ( 4669 * ) + NEW met1 ( 2369 51 ) ( * 119 ) + NEW met1 ( 69 51 ) ( 2369 * ) + NEW met3 ( 4669 102 ) ( 6923 * ) + NEW li1 ( 16169 153 ) L1M1_PR_MR + NEW met1 ( 16169 153 ) M1M2_PR + NEW met2 ( 16169 170 ) M2M3_PR + NEW li1 ( 13869 153 ) L1M1_PR_MR + NEW met1 ( 13869 153 ) M1M2_PR + NEW met2 ( 13869 170 ) M2M3_PR + NEW li1 ( 11569 153 ) L1M1_PR_MR + NEW met1 ( 11569 153 ) M1M2_PR + NEW met2 ( 11569 102 ) M2M3_PR + NEW li1 ( 9269 153 ) L1M1_PR_MR + NEW met1 ( 9269 153 ) M1M2_PR + NEW met2 ( 9269 102 ) M2M3_PR + NEW li1 ( 69 119 ) L1M1_PR_MR + NEW met2 ( 19067 170 ) M2M3_PR + NEW li1 ( 19067 153 ) L1M1_PR_MR + NEW met1 ( 19067 153 ) M1M2_PR + NEW li1 ( 6969 119 ) L1M1_PR_MR + NEW met1 ( 6923 119 ) M1M2_PR + NEW met2 ( 6923 102 ) M2M3_PR + NEW li1 ( 4669 119 ) L1M1_PR_MR + NEW met1 ( 4669 119 ) M1M2_PR + NEW met2 ( 4669 102 ) M2M3_PR + NEW li1 ( 2369 119 ) L1M1_PR_MR + NEW met1 ( 2369 119 ) M1M2_PR + NEW met2 ( 2369 102 ) M2M3_PR ; + - storage_0_0_0.we0 ( storage_0_0_0.gcand X ) ( storage_0_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 18653 85 ) ( 19527 * ) + NEW li1 ( 18653 85 ) L1M1_PR_MR + NEW li1 ( 19527 85 ) L1M1_PR_MR ; + - storage_0_0_0.write_sel ( storage_0_0_0.gcand A ) ( storage_0_0_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 19297 153 ) ( 19343 * ) + NEW li1 ( 19297 153 ) L1M1_PR_MR + NEW li1 ( 19343 153 ) L1M1_PR_MR ; + - storage_0_1_0.bit0.storage ( storage_0_1_0.bit0.obuf0 A ) ( storage_0_1_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1955 153 ) ( * 187 ) + NEW met1 ( 1909 187 ) ( 1955 * ) + NEW li1 ( 1955 153 ) L1M1_PR_MR + NEW li1 ( 1909 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit1.storage ( storage_0_1_0.bit1.obuf0 A ) ( storage_0_1_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4255 153 ) ( * 187 ) + NEW met1 ( 4209 187 ) ( 4255 * ) + NEW li1 ( 4255 153 ) L1M1_PR_MR + NEW li1 ( 4209 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit2.storage ( storage_0_1_0.bit2.obuf0 A ) ( storage_0_1_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6555 153 ) ( * 187 ) + NEW met1 ( 6509 187 ) ( 6555 * ) + NEW li1 ( 6555 153 ) L1M1_PR_MR + NEW li1 ( 6509 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit3.storage ( storage_0_1_0.bit3.obuf0 A ) ( storage_0_1_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8855 153 ) ( * 187 ) + NEW met1 ( 8809 187 ) ( 8855 * ) + NEW li1 ( 8855 153 ) L1M1_PR_MR + NEW li1 ( 8809 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit4.storage ( storage_0_1_0.bit4.obuf0 A ) ( storage_0_1_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 11155 153 ) ( * 187 ) + NEW met1 ( 11109 187 ) ( 11155 * ) + NEW li1 ( 11155 153 ) L1M1_PR_MR + NEW li1 ( 11109 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit5.storage ( storage_0_1_0.bit5.obuf0 A ) ( storage_0_1_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 13455 153 ) ( * 187 ) + NEW met1 ( 13409 187 ) ( 13455 * ) + NEW li1 ( 13455 153 ) L1M1_PR_MR + NEW li1 ( 13409 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit6.storage ( storage_0_1_0.bit6.obuf0 A ) ( storage_0_1_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 15755 153 ) ( * 187 ) + NEW met1 ( 15709 187 ) ( 15755 * ) + NEW li1 ( 15755 153 ) L1M1_PR_MR + NEW li1 ( 15709 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit7.storage ( storage_0_1_0.bit7.obuf0 A ) ( storage_0_1_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 18055 153 ) ( * 187 ) + NEW met1 ( 18009 187 ) ( 18055 * ) + NEW li1 ( 18055 153 ) L1M1_PR_MR + NEW li1 ( 18009 187 ) L1M1_PR_MR ; + - storage_0_1_0.gclock ( storage_0_1_0.cg GCLK ) ( storage_0_1_0.bit7.bit CLK ) ( storage_0_1_0.bit6.bit CLK ) ( storage_0_1_0.bit5.bit CLK ) ( storage_0_1_0.bit4.bit CLK ) ( storage_0_1_0.bit3.bit CLK ) ( storage_0_1_0.bit2.bit CLK ) + ( storage_0_1_0.bit1.bit CLK ) ( storage_0_1_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 14927 153 ) ( 15019 * ) + NEW met2 ( 14927 102 ) ( * 153 ) + NEW met2 ( 12719 102 ) ( * 119 ) + NEW met3 ( 12719 102 ) ( 14927 * ) + NEW met2 ( 10419 34 ) ( * 153 ) + NEW met3 ( 10419 34 ) ( 12558 * ) + NEW met3 ( 12558 34 ) ( * 102 ) + NEW met3 ( 12558 102 ) ( 12719 * ) + NEW met1 ( 8119 153 ) ( * 221 ) + NEW met1 ( 8119 221 ) ( 10051 * ) + NEW met1 ( 10051 153 ) ( * 221 ) + NEW met1 ( 10051 153 ) ( 10419 * ) + NEW met1 ( 7751 187 ) ( * 221 ) + NEW met1 ( 7751 187 ) ( 8119 * ) + NEW met1 ( 1219 153 ) ( * 221 ) + NEW met1 ( 17319 119 ) ( 18285 * ) + NEW met1 ( 18285 119 ) ( * 187 ) + NEW met2 ( 17319 102 ) ( * 119 ) + NEW met3 ( 14927 102 ) ( 17319 * ) + NEW met2 ( 5819 119 ) ( * 221 ) + NEW met1 ( 5819 51 ) ( * 119 ) + NEW met1 ( 5819 221 ) ( 7751 * ) + NEW met1 ( 1219 221 ) ( 2070 * ) + NEW met1 ( 3519 153 ) ( * 221 ) + NEW met1 ( 3519 221 ) ( 4623 * ) + NEW met2 ( 4623 51 ) ( * 221 ) + NEW met1 ( 2070 187 ) ( * 221 ) + NEW met1 ( 2070 187 ) ( 2323 * ) + NEW met1 ( 2323 187 ) ( * 221 ) + NEW met1 ( 2323 221 ) ( 3151 * ) + NEW met1 ( 3151 187 ) ( * 221 ) + NEW met1 ( 3151 187 ) ( 3519 * ) + NEW met1 ( 4623 51 ) ( 5819 * ) + NEW met1 ( 18285 187 ) ( 20355 * ) + NEW li1 ( 15019 153 ) L1M1_PR_MR + NEW met1 ( 14927 153 ) M1M2_PR + NEW met2 ( 14927 102 ) M2M3_PR + NEW li1 ( 12719 119 ) L1M1_PR_MR + NEW met1 ( 12719 119 ) M1M2_PR + NEW met2 ( 12719 102 ) M2M3_PR + NEW li1 ( 10419 153 ) L1M1_PR_MR + NEW met1 ( 10419 153 ) M1M2_PR + NEW met2 ( 10419 34 ) M2M3_PR + NEW li1 ( 8119 153 ) L1M1_PR_MR + NEW li1 ( 1219 153 ) L1M1_PR_MR + NEW li1 ( 17319 119 ) L1M1_PR_MR + NEW met2 ( 17319 102 ) M2M3_PR + NEW met1 ( 17319 119 ) M1M2_PR + NEW li1 ( 5819 119 ) L1M1_PR_MR + NEW met1 ( 5819 119 ) M1M2_PR + NEW met1 ( 5819 221 ) M1M2_PR + NEW li1 ( 3519 153 ) L1M1_PR_MR + NEW met1 ( 4623 221 ) M1M2_PR + NEW met1 ( 4623 51 ) M1M2_PR + NEW li1 ( 20355 187 ) L1M1_PR_MR ; + - storage_0_1_0.we0 ( storage_0_1_0.gcand X ) ( storage_0_1_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 19941 51 ) ( 20815 * ) + NEW li1 ( 19941 51 ) L1M1_PR_MR + NEW li1 ( 20815 51 ) L1M1_PR_MR ; + - storage_0_1_0.write_sel ( storage_0_1_0.gcand A ) ( storage_0_1_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 20585 153 ) ( 20631 * ) + NEW li1 ( 20631 153 ) L1M1_PR_MR + NEW li1 ( 20585 153 ) L1M1_PR_MR ; + - storage_1_0_0.bit0.storage ( storage_1_0_0.bit0.obuf0 A ) ( storage_1_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 759 391 ) ( 805 * ) + NEW met1 ( 759 357 ) ( * 391 ) + NEW li1 ( 805 391 ) L1M1_PR_MR + NEW li1 ( 759 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit1.storage ( storage_1_0_0.bit1.obuf0 A ) ( storage_1_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3059 391 ) ( 3105 * ) + NEW met1 ( 3059 357 ) ( * 391 ) + NEW li1 ( 3105 391 ) L1M1_PR_MR + NEW li1 ( 3059 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit2.storage ( storage_1_0_0.bit2.obuf0 A ) ( storage_1_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5359 391 ) ( 5405 * ) + NEW met1 ( 5359 357 ) ( * 391 ) + NEW li1 ( 5405 391 ) L1M1_PR_MR + NEW li1 ( 5359 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit3.storage ( storage_1_0_0.bit3.obuf0 A ) ( storage_1_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7659 391 ) ( 7705 * ) + NEW met1 ( 7659 357 ) ( * 391 ) + NEW li1 ( 7705 391 ) L1M1_PR_MR + NEW li1 ( 7659 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit4.storage ( storage_1_0_0.bit4.obuf0 A ) ( storage_1_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 9959 391 ) ( 10005 * ) + NEW met1 ( 9959 357 ) ( * 391 ) + NEW li1 ( 10005 391 ) L1M1_PR_MR + NEW li1 ( 9959 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit5.storage ( storage_1_0_0.bit5.obuf0 A ) ( storage_1_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 12259 391 ) ( 12305 * ) + NEW met1 ( 12259 357 ) ( * 391 ) + NEW li1 ( 12305 391 ) L1M1_PR_MR + NEW li1 ( 12259 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit6.storage ( storage_1_0_0.bit6.obuf0 A ) ( storage_1_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 14559 391 ) ( 14605 * ) + NEW met1 ( 14559 357 ) ( * 391 ) + NEW li1 ( 14605 391 ) L1M1_PR_MR + NEW li1 ( 14559 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit7.storage ( storage_1_0_0.bit7.obuf0 A ) ( storage_1_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 16859 391 ) ( 16905 * ) + NEW met1 ( 16859 357 ) ( * 391 ) + NEW li1 ( 16905 391 ) L1M1_PR_MR + NEW li1 ( 16859 357 ) L1M1_PR_MR ; + - storage_1_0_0.gclock ( storage_1_0_0.cg GCLK ) ( storage_1_0_0.bit7.bit CLK ) ( storage_1_0_0.bit6.bit CLK ) ( storage_1_0_0.bit5.bit CLK ) ( storage_1_0_0.bit4.bit CLK ) ( storage_1_0_0.bit3.bit CLK ) ( storage_1_0_0.bit2.bit CLK ) + ( storage_1_0_0.bit1.bit CLK ) ( storage_1_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met2 ( 16169 391 ) ( * 493 ) + NEW met2 ( 13869 306 ) ( * 391 ) + NEW met3 ( 13869 306 ) ( 16169 * ) + NEW met2 ( 16169 306 ) ( * 391 ) + NEW met2 ( 11569 306 ) ( * 391 ) + NEW met3 ( 11569 306 ) ( 13869 * ) + NEW met1 ( 9269 425 ) ( * 459 ) + NEW met1 ( 9269 459 ) ( 11201 * ) + NEW met1 ( 11201 391 ) ( * 459 ) + NEW met1 ( 11201 391 ) ( 11569 * ) + NEW met1 ( 69 425 ) ( * 459 ) + NEW met1 ( 16169 493 ) ( 19067 * ) + NEW met1 ( 6923 391 ) ( 6969 * ) + NEW met2 ( 6923 306 ) ( * 391 ) + NEW met1 ( 6969 391 ) ( * 459 ) + NEW met1 ( 6969 459 ) ( 9269 * ) + NEW met2 ( 4669 306 ) ( * 391 ) + NEW met1 ( 2369 323 ) ( * 391 ) + NEW met1 ( 2369 323 ) ( 4255 * ) + NEW met1 ( 4255 323 ) ( * 357 ) + NEW met1 ( 4255 357 ) ( 4669 * ) + NEW met1 ( 4669 357 ) ( * 391 ) + NEW met2 ( 2369 391 ) ( * 459 ) + NEW met1 ( 69 459 ) ( 2369 * ) + NEW met3 ( 4669 306 ) ( 6923 * ) + NEW li1 ( 16169 391 ) L1M1_PR_MR + NEW met1 ( 16169 391 ) M1M2_PR + NEW met1 ( 16169 493 ) M1M2_PR + NEW li1 ( 13869 391 ) L1M1_PR_MR + NEW met1 ( 13869 391 ) M1M2_PR + NEW met2 ( 13869 306 ) M2M3_PR + NEW met2 ( 16169 306 ) M2M3_PR + NEW li1 ( 11569 391 ) L1M1_PR_MR + NEW met1 ( 11569 391 ) M1M2_PR + NEW met2 ( 11569 306 ) M2M3_PR + NEW li1 ( 9269 425 ) L1M1_PR_MR + NEW li1 ( 69 425 ) L1M1_PR_MR + NEW li1 ( 19067 493 ) L1M1_PR_MR + NEW li1 ( 6969 391 ) L1M1_PR_MR + NEW met1 ( 6923 391 ) M1M2_PR + NEW met2 ( 6923 306 ) M2M3_PR + NEW li1 ( 4669 391 ) L1M1_PR_MR + NEW met1 ( 4669 391 ) M1M2_PR + NEW met2 ( 4669 306 ) M2M3_PR + NEW li1 ( 2369 391 ) L1M1_PR_MR + NEW met1 ( 2369 459 ) M1M2_PR + NEW met1 ( 2369 391 ) M1M2_PR ; + - storage_1_0_0.we0 ( storage_1_0_0.gcand X ) ( storage_1_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 18653 459 ) ( 19527 * ) + NEW li1 ( 18653 459 ) L1M1_PR_MR + NEW li1 ( 19527 459 ) L1M1_PR_MR ; + - storage_1_0_0.write_sel ( storage_1_0_0.gcand A ) ( storage_1_0_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 19297 357 ) ( 19343 * ) + NEW li1 ( 19297 357 ) L1M1_PR_MR + NEW li1 ( 19343 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit0.storage ( storage_1_1_0.bit0.obuf0 A ) ( storage_1_1_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1909 391 ) ( 1955 * ) + NEW met1 ( 1909 357 ) ( * 391 ) + NEW li1 ( 1955 391 ) L1M1_PR_MR + NEW li1 ( 1909 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit1.storage ( storage_1_1_0.bit1.obuf0 A ) ( storage_1_1_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4209 391 ) ( 4255 * ) + NEW met1 ( 4209 357 ) ( * 391 ) + NEW li1 ( 4255 391 ) L1M1_PR_MR + NEW li1 ( 4209 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit2.storage ( storage_1_1_0.bit2.obuf0 A ) ( storage_1_1_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6509 391 ) ( 6555 * ) + NEW met1 ( 6509 357 ) ( * 391 ) + NEW li1 ( 6555 391 ) L1M1_PR_MR + NEW li1 ( 6509 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit3.storage ( storage_1_1_0.bit3.obuf0 A ) ( storage_1_1_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8809 391 ) ( 8855 * ) + NEW met1 ( 8809 357 ) ( * 391 ) + NEW li1 ( 8855 391 ) L1M1_PR_MR + NEW li1 ( 8809 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit4.storage ( storage_1_1_0.bit4.obuf0 A ) ( storage_1_1_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 11109 391 ) ( 11155 * ) + NEW met1 ( 11109 357 ) ( * 391 ) + NEW li1 ( 11155 391 ) L1M1_PR_MR + NEW li1 ( 11109 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit5.storage ( storage_1_1_0.bit5.obuf0 A ) ( storage_1_1_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 13409 391 ) ( 13455 * ) + NEW met1 ( 13409 357 ) ( * 391 ) + NEW li1 ( 13455 391 ) L1M1_PR_MR + NEW li1 ( 13409 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit6.storage ( storage_1_1_0.bit6.obuf0 A ) ( storage_1_1_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 15709 391 ) ( 15755 * ) + NEW met1 ( 15709 357 ) ( * 391 ) + NEW li1 ( 15755 391 ) L1M1_PR_MR + NEW li1 ( 15709 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit7.storage ( storage_1_1_0.bit7.obuf0 A ) ( storage_1_1_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 18009 391 ) ( 18055 * ) + NEW met1 ( 18009 357 ) ( * 391 ) + NEW li1 ( 18055 391 ) L1M1_PR_MR + NEW li1 ( 18009 357 ) L1M1_PR_MR ; + - storage_1_1_0.gclock ( storage_1_1_0.cg GCLK ) ( storage_1_1_0.bit7.bit CLK ) ( storage_1_1_0.bit6.bit CLK ) ( storage_1_1_0.bit5.bit CLK ) ( storage_1_1_0.bit4.bit CLK ) ( storage_1_1_0.bit3.bit CLK ) ( storage_1_1_0.bit2.bit CLK ) + ( storage_1_1_0.bit1.bit CLK ) ( storage_1_1_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 15019 323 ) ( * 391 ) + NEW met1 ( 12719 323 ) ( * 391 ) + NEW met1 ( 12719 323 ) ( 15019 * ) + NEW met1 ( 10419 323 ) ( * 391 ) + NEW met1 ( 10419 323 ) ( 12719 * ) + NEW met2 ( 8119 425 ) ( * 493 ) + NEW met1 ( 8119 493 ) ( 10143 * ) + NEW met2 ( 10143 357 ) ( * 493 ) + NEW met1 ( 10143 357 ) ( 10419 * ) + NEW met2 ( 8119 374 ) ( * 425 ) + NEW met2 ( 1219 306 ) ( * 425 ) + NEW met1 ( 18055 323 ) ( * 357 ) + NEW met1 ( 18055 357 ) ( 18423 * ) + NEW met1 ( 18423 323 ) ( * 357 ) + NEW met1 ( 17319 323 ) ( * 391 ) + NEW met1 ( 15019 323 ) ( 18055 * ) + NEW met2 ( 5819 374 ) ( * 391 ) + NEW met3 ( 5819 374 ) ( 8119 * ) + NEW met3 ( 1219 306 ) ( 2070 * ) + NEW met2 ( 3519 374 ) ( * 391 ) + NEW met3 ( 2070 306 ) ( * 374 ) + NEW met3 ( 2070 374 ) ( 3519 * ) + NEW met3 ( 3519 374 ) ( 5819 * ) + NEW met1 ( 19389 323 ) ( * 357 ) + NEW met1 ( 19389 357 ) ( 20355 * ) + NEW met1 ( 18423 323 ) ( 19389 * ) + NEW li1 ( 15019 391 ) L1M1_PR_MR + NEW li1 ( 12719 391 ) L1M1_PR_MR + NEW li1 ( 10419 391 ) L1M1_PR_MR + NEW li1 ( 8119 425 ) L1M1_PR_MR + NEW met1 ( 8119 425 ) M1M2_PR + NEW met1 ( 8119 493 ) M1M2_PR + NEW met1 ( 10143 493 ) M1M2_PR + NEW met1 ( 10143 357 ) M1M2_PR + NEW met2 ( 8119 374 ) M2M3_PR + NEW li1 ( 1219 425 ) L1M1_PR_MR + NEW met1 ( 1219 425 ) M1M2_PR + NEW met2 ( 1219 306 ) M2M3_PR + NEW li1 ( 17319 391 ) L1M1_PR_MR + NEW li1 ( 5819 391 ) L1M1_PR_MR + NEW met1 ( 5819 391 ) M1M2_PR + NEW met2 ( 5819 374 ) M2M3_PR + NEW li1 ( 3519 391 ) L1M1_PR_MR + NEW met1 ( 3519 391 ) M1M2_PR + NEW met2 ( 3519 374 ) M2M3_PR + NEW li1 ( 20355 357 ) L1M1_PR_MR ; + - storage_1_1_0.we0 ( storage_1_1_0.gcand X ) ( storage_1_1_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 19941 493 ) ( 20815 * ) + NEW li1 ( 19941 493 ) L1M1_PR_MR + NEW li1 ( 20815 493 ) L1M1_PR_MR ; + - storage_1_1_0.write_sel ( storage_1_1_0.gcand A ) ( storage_1_1_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 20585 357 ) ( 20631 * ) + NEW li1 ( 20631 357 ) L1M1_PR_MR + NEW li1 ( 20585 357 ) L1M1_PR_MR ; + - storage_2_0_0.bit0.storage ( storage_2_0_0.bit0.obuf0 A ) ( storage_2_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 805 697 ) ( * 731 ) + NEW met1 ( 759 731 ) ( 805 * ) + NEW li1 ( 805 697 ) L1M1_PR_MR + NEW li1 ( 759 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit1.storage ( storage_2_0_0.bit1.obuf0 A ) ( storage_2_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3105 697 ) ( * 731 ) + NEW met1 ( 3059 731 ) ( 3105 * ) + NEW li1 ( 3105 697 ) L1M1_PR_MR + NEW li1 ( 3059 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit2.storage ( storage_2_0_0.bit2.obuf0 A ) ( storage_2_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5405 697 ) ( * 731 ) + NEW met1 ( 5359 731 ) ( 5405 * ) + NEW li1 ( 5405 697 ) L1M1_PR_MR + NEW li1 ( 5359 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit3.storage ( storage_2_0_0.bit3.obuf0 A ) ( storage_2_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7705 697 ) ( * 731 ) + NEW met1 ( 7659 731 ) ( 7705 * ) + NEW li1 ( 7705 697 ) L1M1_PR_MR + NEW li1 ( 7659 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit4.storage ( storage_2_0_0.bit4.obuf0 A ) ( storage_2_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 10005 697 ) ( * 731 ) + NEW met1 ( 9959 731 ) ( 10005 * ) + NEW li1 ( 10005 697 ) L1M1_PR_MR + NEW li1 ( 9959 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit5.storage ( storage_2_0_0.bit5.obuf0 A ) ( storage_2_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 12305 697 ) ( * 731 ) + NEW met1 ( 12259 731 ) ( 12305 * ) + NEW li1 ( 12305 697 ) L1M1_PR_MR + NEW li1 ( 12259 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit6.storage ( storage_2_0_0.bit6.obuf0 A ) ( storage_2_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 14605 697 ) ( * 731 ) + NEW met1 ( 14559 731 ) ( 14605 * ) + NEW li1 ( 14605 697 ) L1M1_PR_MR + NEW li1 ( 14559 731 ) L1M1_PR_MR ; + - storage_2_0_0.bit7.storage ( storage_2_0_0.bit7.obuf0 A ) ( storage_2_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 16905 697 ) ( * 731 ) + NEW met1 ( 16859 731 ) ( 16905 * ) + NEW li1 ( 16905 697 ) L1M1_PR_MR + NEW li1 ( 16859 731 ) L1M1_PR_MR ; + - storage_2_0_0.gclock ( storage_2_0_0.cg GCLK ) ( storage_2_0_0.bit7.bit CLK ) ( storage_2_0_0.bit6.bit CLK ) ( storage_2_0_0.bit5.bit CLK ) ( storage_2_0_0.bit4.bit CLK ) ( storage_2_0_0.bit3.bit CLK ) ( storage_2_0_0.bit2.bit CLK ) + ( storage_2_0_0.bit1.bit CLK ) ( storage_2_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 16169 697 ) ( * 765 ) + NEW met1 ( 16169 765 ) ( 16951 * ) + NEW met1 ( 16951 731 ) ( * 765 ) + NEW met1 ( 13869 663 ) ( 14191 * ) + NEW met2 ( 14191 595 ) ( * 663 ) + NEW met1 ( 14191 595 ) ( 16169 * ) + NEW met2 ( 16169 595 ) ( * 697 ) + NEW met1 ( 11569 663 ) ( 11753 * ) + NEW met1 ( 11753 629 ) ( * 663 ) + NEW met1 ( 11753 629 ) ( 12443 * ) + NEW met1 ( 12443 629 ) ( * 663 ) + NEW met1 ( 12443 663 ) ( 13501 * ) + NEW met1 ( 13501 663 ) ( * 697 ) + NEW met1 ( 13501 697 ) ( 13869 * ) + NEW met1 ( 13869 663 ) ( * 697 ) + NEW met1 ( 9269 697 ) ( * 765 ) + NEW met1 ( 9269 765 ) ( 11201 * ) + NEW met1 ( 11201 731 ) ( * 765 ) + NEW met1 ( 11201 731 ) ( 11569 * ) + NEW met1 ( 11569 663 ) ( * 731 ) + NEW met1 ( 69 697 ) ( * 765 ) + NEW met1 ( 69 765 ) ( 2001 * ) + NEW met1 ( 2001 731 ) ( * 765 ) + NEW met1 ( 17273 731 ) ( * 765 ) + NEW met1 ( 17273 765 ) ( 19067 * ) + NEW met1 ( 16951 731 ) ( 17273 * ) + NEW met1 ( 6831 663 ) ( 6969 * ) + NEW met1 ( 6831 595 ) ( * 663 ) + NEW met2 ( 6923 663 ) ( * 765 ) + NEW met1 ( 6923 765 ) ( 9269 * ) + NEW met2 ( 4669 595 ) ( * 663 ) + NEW met1 ( 2369 697 ) ( * 765 ) + NEW met1 ( 2369 765 ) ( 3151 * ) + NEW met1 ( 3151 731 ) ( * 765 ) + NEW met1 ( 3151 731 ) ( 3473 * ) + NEW met1 ( 3473 731 ) ( * 765 ) + NEW met1 ( 3473 765 ) ( 4669 * ) + NEW met2 ( 4669 663 ) ( * 765 ) + NEW met1 ( 2001 731 ) ( 2369 * ) + NEW met1 ( 4669 595 ) ( 6831 * ) + NEW li1 ( 16169 697 ) L1M1_PR_MR + NEW li1 ( 13869 663 ) L1M1_PR_MR + NEW met1 ( 14191 663 ) M1M2_PR + NEW met1 ( 14191 595 ) M1M2_PR + NEW met1 ( 16169 595 ) M1M2_PR + NEW met1 ( 16169 697 ) M1M2_PR + NEW li1 ( 11569 663 ) L1M1_PR_MR + NEW li1 ( 9269 697 ) L1M1_PR_MR + NEW li1 ( 69 697 ) L1M1_PR_MR + NEW li1 ( 19067 765 ) L1M1_PR_MR + NEW li1 ( 6969 663 ) L1M1_PR_MR + NEW met1 ( 6923 765 ) M1M2_PR + NEW met1 ( 6923 663 ) M1M2_PR + NEW li1 ( 4669 663 ) L1M1_PR_MR + NEW met1 ( 4669 663 ) M1M2_PR + NEW met1 ( 4669 595 ) M1M2_PR + NEW li1 ( 2369 697 ) L1M1_PR_MR + NEW met1 ( 4669 765 ) M1M2_PR ; + - storage_2_0_0.we0 ( storage_2_0_0.gcand X ) ( storage_2_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 18653 629 ) ( 19527 * ) + NEW li1 ( 18653 629 ) L1M1_PR_MR + NEW li1 ( 19527 629 ) L1M1_PR_MR ; + - storage_2_0_0.write_sel ( storage_2_0_0.gcand A ) ( storage_2_0_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 19297 697 ) ( 19343 * ) + NEW li1 ( 19297 697 ) L1M1_PR_MR + NEW li1 ( 19343 697 ) L1M1_PR_MR ; + - storage_2_1_0.bit0.storage ( storage_2_1_0.bit0.obuf0 A ) ( storage_2_1_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1955 697 ) ( * 731 ) + NEW met1 ( 1909 731 ) ( 1955 * ) + NEW li1 ( 1955 697 ) L1M1_PR_MR + NEW li1 ( 1909 731 ) L1M1_PR_MR ; + - storage_2_1_0.bit1.storage ( storage_2_1_0.bit1.obuf0 A ) ( storage_2_1_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4255 697 ) ( * 731 ) + NEW met1 ( 4209 731 ) ( 4255 * ) + NEW li1 ( 4255 697 ) L1M1_PR_MR + NEW li1 ( 4209 731 ) L1M1_PR_MR ; + - storage_2_1_0.bit2.storage ( storage_2_1_0.bit2.obuf0 A ) ( storage_2_1_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6555 697 ) ( * 731 ) + NEW met1 ( 6509 731 ) ( 6555 * ) + NEW li1 ( 6555 697 ) L1M1_PR_MR + NEW li1 ( 6509 731 ) L1M1_PR_MR ; + - storage_2_1_0.bit3.storage ( storage_2_1_0.bit3.obuf0 A ) ( storage_2_1_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8855 697 ) ( * 731 ) + NEW met1 ( 8809 731 ) ( 8855 * ) + NEW li1 ( 8855 697 ) L1M1_PR_MR + NEW li1 ( 8809 731 ) L1M1_PR_MR ; + - storage_2_1_0.bit4.storage ( storage_2_1_0.bit4.obuf0 A ) ( storage_2_1_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 11155 697 ) ( * 731 ) + NEW met1 ( 11109 731 ) ( 11155 * ) + NEW li1 ( 11155 697 ) L1M1_PR_MR + NEW li1 ( 11109 731 ) L1M1_PR_MR ; + - storage_2_1_0.bit5.storage ( storage_2_1_0.bit5.obuf0 A ) ( storage_2_1_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 13455 697 ) ( * 731 ) + NEW met1 ( 13409 731 ) ( 13455 * ) + NEW li1 ( 13455 697 ) L1M1_PR_MR + NEW li1 ( 13409 731 ) L1M1_PR_MR ; + - storage_2_1_0.bit6.storage ( storage_2_1_0.bit6.obuf0 A ) ( storage_2_1_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 15755 697 ) ( * 731 ) + NEW met1 ( 15709 731 ) ( 15755 * ) + NEW li1 ( 15755 697 ) L1M1_PR_MR + NEW li1 ( 15709 731 ) L1M1_PR_MR ; + - storage_2_1_0.bit7.storage ( storage_2_1_0.bit7.obuf0 A ) ( storage_2_1_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 18055 697 ) ( * 731 ) + NEW met1 ( 18009 731 ) ( 18055 * ) + NEW li1 ( 18055 697 ) L1M1_PR_MR + NEW li1 ( 18009 731 ) L1M1_PR_MR ; + - storage_2_1_0.gclock ( storage_2_1_0.cg GCLK ) ( storage_2_1_0.bit7.bit CLK ) ( storage_2_1_0.bit6.bit CLK ) ( storage_2_1_0.bit5.bit CLK ) ( storage_2_1_0.bit4.bit CLK ) ( storage_2_1_0.bit3.bit CLK ) ( storage_2_1_0.bit2.bit CLK ) + ( storage_2_1_0.bit1.bit CLK ) ( storage_2_1_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 15019 697 ) ( * 765 ) + NEW met1 ( 15019 765 ) ( 15111 * ) + NEW met2 ( 15111 765 ) ( * 782 ) + NEW met3 ( 15111 782 ) ( 16238 * ) + NEW met3 ( 16238 714 ) ( * 782 ) + NEW met1 ( 12719 697 ) ( * 765 ) + NEW met1 ( 12719 765 ) ( 13501 * ) + NEW met1 ( 13501 731 ) ( * 765 ) + NEW met1 ( 13501 731 ) ( 13823 * ) + NEW met1 ( 13823 731 ) ( * 765 ) + NEW met1 ( 13823 765 ) ( 14651 * ) + NEW met1 ( 14651 731 ) ( * 765 ) + NEW met1 ( 14651 731 ) ( 15019 * ) + NEW met1 ( 10419 595 ) ( * 663 ) + NEW met1 ( 10419 595 ) ( 11431 * ) + NEW met2 ( 11431 595 ) ( * 765 ) + NEW met1 ( 11431 765 ) ( 12351 * ) + NEW met1 ( 12351 731 ) ( * 765 ) + NEW met1 ( 12351 731 ) ( 12719 * ) + NEW met1 ( 8119 595 ) ( * 663 ) + NEW met1 ( 8119 595 ) ( 10419 * ) + NEW met2 ( 1219 646 ) ( * 663 ) + NEW met1 ( 17319 595 ) ( * 663 ) + NEW met1 ( 17319 595 ) ( 17503 * ) + NEW met1 ( 17503 595 ) ( * 629 ) + NEW met1 ( 17503 629 ) ( 18423 * ) + NEW met1 ( 18423 595 ) ( * 629 ) + NEW met2 ( 17319 663 ) ( * 714 ) + NEW met3 ( 16238 714 ) ( 17319 * ) + NEW met2 ( 5819 646 ) ( * 663 ) + NEW met3 ( 5819 646 ) ( 7061 * ) + NEW met2 ( 7061 595 ) ( * 646 ) + NEW met1 ( 7061 595 ) ( 8119 * ) + NEW met2 ( 3519 646 ) ( * 663 ) + NEW met3 ( 1219 646 ) ( 3519 * ) + NEW met3 ( 3519 646 ) ( 5819 * ) + NEW met2 ( 19849 595 ) ( * 765 ) + NEW met1 ( 19849 765 ) ( 20355 * ) + NEW met1 ( 18423 595 ) ( 19849 * ) + NEW li1 ( 15019 697 ) L1M1_PR_MR + NEW met1 ( 15111 765 ) M1M2_PR + NEW met2 ( 15111 782 ) M2M3_PR + NEW li1 ( 12719 697 ) L1M1_PR_MR + NEW li1 ( 10419 663 ) L1M1_PR_MR + NEW met1 ( 11431 595 ) M1M2_PR + NEW met1 ( 11431 765 ) M1M2_PR + NEW li1 ( 8119 663 ) L1M1_PR_MR + NEW li1 ( 1219 663 ) L1M1_PR_MR + NEW met1 ( 1219 663 ) M1M2_PR + NEW met2 ( 1219 646 ) M2M3_PR + NEW li1 ( 17319 663 ) L1M1_PR_MR + NEW met2 ( 17319 714 ) M2M3_PR + NEW met1 ( 17319 663 ) M1M2_PR + NEW li1 ( 5819 663 ) L1M1_PR_MR + NEW met1 ( 5819 663 ) M1M2_PR + NEW met2 ( 5819 646 ) M2M3_PR + NEW met2 ( 7061 646 ) M2M3_PR + NEW met1 ( 7061 595 ) M1M2_PR + NEW li1 ( 3519 663 ) L1M1_PR_MR + NEW met1 ( 3519 663 ) M1M2_PR + NEW met2 ( 3519 646 ) M2M3_PR + NEW met1 ( 19849 595 ) M1M2_PR + NEW met1 ( 19849 765 ) M1M2_PR + NEW li1 ( 20355 765 ) L1M1_PR_MR ; + - storage_2_1_0.we0 ( storage_2_1_0.gcand X ) ( storage_2_1_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 19941 595 ) ( 20815 * ) + NEW li1 ( 19941 595 ) L1M1_PR_MR + NEW li1 ( 20815 595 ) L1M1_PR_MR ; + - storage_2_1_0.write_sel ( storage_2_1_0.gcand A ) ( storage_2_1_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 20585 697 ) ( 20631 * ) + NEW li1 ( 20631 697 ) L1M1_PR_MR + NEW li1 ( 20585 697 ) L1M1_PR_MR ; + - storage_3_0_0.bit0.storage ( storage_3_0_0.bit0.obuf0 A ) ( storage_3_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 759 935 ) ( 805 * ) + NEW met1 ( 759 901 ) ( * 935 ) + NEW li1 ( 805 935 ) L1M1_PR_MR + NEW li1 ( 759 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit1.storage ( storage_3_0_0.bit1.obuf0 A ) ( storage_3_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3059 935 ) ( 3105 * ) + NEW met1 ( 3059 901 ) ( * 935 ) + NEW li1 ( 3105 935 ) L1M1_PR_MR + NEW li1 ( 3059 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit2.storage ( storage_3_0_0.bit2.obuf0 A ) ( storage_3_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5359 935 ) ( 5405 * ) + NEW met1 ( 5359 901 ) ( * 935 ) + NEW li1 ( 5405 935 ) L1M1_PR_MR + NEW li1 ( 5359 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit3.storage ( storage_3_0_0.bit3.obuf0 A ) ( storage_3_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7659 935 ) ( 7705 * ) + NEW met1 ( 7659 901 ) ( * 935 ) + NEW li1 ( 7705 935 ) L1M1_PR_MR + NEW li1 ( 7659 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit4.storage ( storage_3_0_0.bit4.obuf0 A ) ( storage_3_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 9959 935 ) ( 10005 * ) + NEW met1 ( 9959 901 ) ( * 935 ) + NEW li1 ( 10005 935 ) L1M1_PR_MR + NEW li1 ( 9959 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit5.storage ( storage_3_0_0.bit5.obuf0 A ) ( storage_3_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 12259 935 ) ( 12305 * ) + NEW met1 ( 12259 901 ) ( * 935 ) + NEW li1 ( 12305 935 ) L1M1_PR_MR + NEW li1 ( 12259 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit6.storage ( storage_3_0_0.bit6.obuf0 A ) ( storage_3_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 14559 935 ) ( 14605 * ) + NEW met1 ( 14559 901 ) ( * 935 ) + NEW li1 ( 14605 935 ) L1M1_PR_MR + NEW li1 ( 14559 901 ) L1M1_PR_MR ; + - storage_3_0_0.bit7.storage ( storage_3_0_0.bit7.obuf0 A ) ( storage_3_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 16859 935 ) ( 16905 * ) + NEW met1 ( 16859 901 ) ( * 935 ) + NEW li1 ( 16905 935 ) L1M1_PR_MR + NEW li1 ( 16859 901 ) L1M1_PR_MR ; + - storage_3_0_0.gclock ( storage_3_0_0.cg GCLK ) ( storage_3_0_0.bit7.bit CLK ) ( storage_3_0_0.bit6.bit CLK ) ( storage_3_0_0.bit5.bit CLK ) ( storage_3_0_0.bit4.bit CLK ) ( storage_3_0_0.bit3.bit CLK ) ( storage_3_0_0.bit2.bit CLK ) + ( storage_3_0_0.bit1.bit CLK ) ( storage_3_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 16169 969 ) ( * 1037 ) + NEW met1 ( 13869 969 ) ( * 1037 ) + NEW met1 ( 13869 1037 ) ( 14697 * ) + NEW met1 ( 14697 969 ) ( * 1037 ) + NEW met1 ( 14697 969 ) ( 16169 * ) + NEW met2 ( 11569 969 ) ( * 1037 ) + NEW met1 ( 11569 1037 ) ( 12489 * ) + NEW met1 ( 12489 969 ) ( * 1037 ) + NEW met1 ( 12489 969 ) ( 13869 * ) + NEW met1 ( 9269 867 ) ( * 935 ) + NEW met1 ( 9269 867 ) ( 10925 * ) + NEW met1 ( 10925 867 ) ( * 969 ) + NEW met1 ( 10925 969 ) ( 11569 * ) + NEW met2 ( 9269 850 ) ( * 867 ) + NEW met1 ( 69 969 ) ( * 1003 ) + NEW met1 ( 69 1003 ) ( 943 * ) + NEW met1 ( 943 935 ) ( * 1003 ) + NEW met1 ( 943 935 ) ( 1265 * ) + NEW met1 ( 1265 935 ) ( * 969 ) + NEW met1 ( 16169 1037 ) ( 19067 * ) + NEW met1 ( 6923 935 ) ( 6969 * ) + NEW met2 ( 6923 850 ) ( * 935 ) + NEW met3 ( 6923 850 ) ( 9269 * ) + NEW met2 ( 4669 850 ) ( * 935 ) + NEW met2 ( 2369 850 ) ( * 935 ) + NEW met3 ( 2369 850 ) ( 4669 * ) + NEW met2 ( 2277 918 ) ( * 969 ) + NEW met2 ( 2277 918 ) ( 2369 * ) + NEW met1 ( 1265 969 ) ( 2277 * ) + NEW met3 ( 4669 850 ) ( 6923 * ) + NEW li1 ( 16169 969 ) L1M1_PR_MR + NEW li1 ( 13869 969 ) L1M1_PR_MR + NEW li1 ( 11569 969 ) L1M1_PR_MR + NEW met1 ( 11569 969 ) M1M2_PR + NEW met1 ( 11569 1037 ) M1M2_PR + NEW li1 ( 9269 935 ) L1M1_PR_MR + NEW met2 ( 9269 850 ) M2M3_PR + NEW met1 ( 9269 867 ) M1M2_PR + NEW li1 ( 69 969 ) L1M1_PR_MR + NEW li1 ( 19067 1037 ) L1M1_PR_MR + NEW li1 ( 6969 935 ) L1M1_PR_MR + NEW met1 ( 6923 935 ) M1M2_PR + NEW met2 ( 6923 850 ) M2M3_PR + NEW li1 ( 4669 935 ) L1M1_PR_MR + NEW met1 ( 4669 935 ) M1M2_PR + NEW met2 ( 4669 850 ) M2M3_PR + NEW li1 ( 2369 935 ) L1M1_PR_MR + NEW met1 ( 2369 935 ) M1M2_PR + NEW met2 ( 2369 850 ) M2M3_PR + NEW met1 ( 2277 969 ) M1M2_PR ; + - storage_3_0_0.we0 ( storage_3_0_0.gcand X ) ( storage_3_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 18653 1003 ) ( 19527 * ) + NEW li1 ( 18653 1003 ) L1M1_PR_MR + NEW li1 ( 19527 1003 ) L1M1_PR_MR ; + - storage_3_0_0.write_sel ( storage_3_0_0.gcand A ) ( storage_3_0_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 19297 901 ) ( 19343 * ) + NEW li1 ( 19297 901 ) L1M1_PR_MR + NEW li1 ( 19343 901 ) L1M1_PR_MR ; + - storage_3_1_0.bit0.storage ( storage_3_1_0.bit0.obuf0 A ) ( storage_3_1_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1909 935 ) ( 1955 * ) + NEW met1 ( 1909 901 ) ( * 935 ) + NEW li1 ( 1955 935 ) L1M1_PR_MR + NEW li1 ( 1909 901 ) L1M1_PR_MR ; + - storage_3_1_0.bit1.storage ( storage_3_1_0.bit1.obuf0 A ) ( storage_3_1_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4209 935 ) ( 4255 * ) + NEW met1 ( 4209 901 ) ( * 935 ) + NEW li1 ( 4255 935 ) L1M1_PR_MR + NEW li1 ( 4209 901 ) L1M1_PR_MR ; + - storage_3_1_0.bit2.storage ( storage_3_1_0.bit2.obuf0 A ) ( storage_3_1_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6509 935 ) ( 6555 * ) + NEW met1 ( 6509 901 ) ( * 935 ) + NEW li1 ( 6555 935 ) L1M1_PR_MR + NEW li1 ( 6509 901 ) L1M1_PR_MR ; + - storage_3_1_0.bit3.storage ( storage_3_1_0.bit3.obuf0 A ) ( storage_3_1_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8809 935 ) ( 8855 * ) + NEW met1 ( 8809 901 ) ( * 935 ) + NEW li1 ( 8855 935 ) L1M1_PR_MR + NEW li1 ( 8809 901 ) L1M1_PR_MR ; + - storage_3_1_0.bit4.storage ( storage_3_1_0.bit4.obuf0 A ) ( storage_3_1_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 11109 935 ) ( 11155 * ) + NEW met1 ( 11109 901 ) ( * 935 ) + NEW li1 ( 11155 935 ) L1M1_PR_MR + NEW li1 ( 11109 901 ) L1M1_PR_MR ; + - storage_3_1_0.bit5.storage ( storage_3_1_0.bit5.obuf0 A ) ( storage_3_1_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 13409 935 ) ( 13455 * ) + NEW met1 ( 13409 901 ) ( * 935 ) + NEW li1 ( 13455 935 ) L1M1_PR_MR + NEW li1 ( 13409 901 ) L1M1_PR_MR ; + - storage_3_1_0.bit6.storage ( storage_3_1_0.bit6.obuf0 A ) ( storage_3_1_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 15709 935 ) ( 15755 * ) + NEW met1 ( 15709 901 ) ( * 935 ) + NEW li1 ( 15755 935 ) L1M1_PR_MR + NEW li1 ( 15709 901 ) L1M1_PR_MR ; + - storage_3_1_0.bit7.storage ( storage_3_1_0.bit7.obuf0 A ) ( storage_3_1_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 18009 935 ) ( 18055 * ) + NEW met1 ( 18009 901 ) ( * 935 ) + NEW li1 ( 18055 935 ) L1M1_PR_MR + NEW li1 ( 18009 901 ) L1M1_PR_MR ; + - storage_3_1_0.gclock ( storage_3_1_0.cg GCLK ) ( storage_3_1_0.bit7.bit CLK ) ( storage_3_1_0.bit6.bit CLK ) ( storage_3_1_0.bit5.bit CLK ) ( storage_3_1_0.bit4.bit CLK ) ( storage_3_1_0.bit3.bit CLK ) ( storage_3_1_0.bit2.bit CLK ) + ( storage_3_1_0.bit1.bit CLK ) ( storage_3_1_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 15019 867 ) ( * 935 ) + NEW met1 ( 12719 867 ) ( * 935 ) + NEW met1 ( 12719 867 ) ( 14605 * ) + NEW met1 ( 14605 867 ) ( * 901 ) + NEW met1 ( 14605 901 ) ( 15019 * ) + NEW met1 ( 10419 969 ) ( 10603 * ) + NEW met1 ( 10603 969 ) ( * 1003 ) + NEW met1 ( 10603 1003 ) ( 12443 * ) + NEW met1 ( 12443 935 ) ( * 1003 ) + NEW met1 ( 12443 935 ) ( 12719 * ) + NEW met1 ( 8119 969 ) ( 8349 * ) + NEW met1 ( 8349 969 ) ( * 1003 ) + NEW met1 ( 8349 1003 ) ( 9453 * ) + NEW met1 ( 9453 969 ) ( * 1003 ) + NEW met1 ( 9453 969 ) ( 10419 * ) + NEW met2 ( 1219 918 ) ( * 969 ) + NEW met1 ( 18055 867 ) ( * 901 ) + NEW met1 ( 18055 901 ) ( 18423 * ) + NEW met1 ( 18423 867 ) ( * 901 ) + NEW met1 ( 17319 867 ) ( * 935 ) + NEW met1 ( 15019 867 ) ( 18055 * ) + NEW met1 ( 7590 969 ) ( 8119 * ) + NEW met1 ( 5819 969 ) ( * 1003 ) + NEW met1 ( 5819 1003 ) ( 7590 * ) + NEW met1 ( 7590 969 ) ( * 1003 ) + NEW met2 ( 3519 918 ) ( * 935 ) + NEW met1 ( 3519 935 ) ( * 1003 ) + NEW met3 ( 1219 918 ) ( 3519 * ) + NEW met1 ( 3519 1003 ) ( 5819 * ) + NEW met1 ( 19389 867 ) ( * 901 ) + NEW met1 ( 19389 901 ) ( 20355 * ) + NEW met1 ( 18423 867 ) ( 19389 * ) + NEW li1 ( 15019 935 ) L1M1_PR_MR + NEW li1 ( 12719 935 ) L1M1_PR_MR + NEW li1 ( 10419 969 ) L1M1_PR_MR + NEW li1 ( 8119 969 ) L1M1_PR_MR + NEW li1 ( 1219 969 ) L1M1_PR_MR + NEW met1 ( 1219 969 ) M1M2_PR + NEW met2 ( 1219 918 ) M2M3_PR + NEW li1 ( 17319 935 ) L1M1_PR_MR + NEW li1 ( 5819 969 ) L1M1_PR_MR + NEW li1 ( 3519 935 ) L1M1_PR_MR + NEW met1 ( 3519 935 ) M1M2_PR + NEW met2 ( 3519 918 ) M2M3_PR + NEW li1 ( 20355 901 ) L1M1_PR_MR ; + - storage_3_1_0.we0 ( storage_3_1_0.gcand X ) ( storage_3_1_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 19941 1037 ) ( 20815 * ) + NEW li1 ( 19941 1037 ) L1M1_PR_MR + NEW li1 ( 20815 1037 ) L1M1_PR_MR ; + - storage_3_1_0.write_sel ( storage_3_1_0.gcand A ) ( storage_3_1_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 20585 901 ) ( 20631 * ) + NEW li1 ( 20631 901 ) L1M1_PR_MR + NEW li1 ( 20585 901 ) L1M1_PR_MR ; + - we[0] ( PIN we[0] ) ( storage_3_1_0.gcand B ) ( storage_3_0_0.gcand B ) ( storage_2_1_0.gcand B ) ( storage_2_0_0.gcand B ) ( storage_1_1_0.gcand B ) ( storage_1_0_0.gcand B ) + ( storage_0_1_0.gcand B ) ( storage_0_0_0.gcand B ) + USE SIGNAL + + ROUTED met2 ( 20723 306 ) ( * 391 ) + NEW met3 ( 20723 306 ) ( 21350 * 0 ) + NEW met2 ( 20723 153 ) ( * 306 ) + NEW met2 ( 20723 391 ) ( * 663 ) + NEW met2 ( 20723 663 ) ( * 935 ) + NEW met2 ( 19435 153 ) ( * 306 ) + NEW met3 ( 19435 306 ) ( 20723 * ) + NEW met2 ( 19435 306 ) ( * 391 ) + NEW met2 ( 19435 391 ) ( * 697 ) + NEW met2 ( 19435 697 ) ( * 935 ) + NEW li1 ( 20723 391 ) L1M1_PR_MR + NEW met1 ( 20723 391 ) M1M2_PR + NEW met2 ( 20723 306 ) M2M3_PR + NEW li1 ( 20723 153 ) L1M1_PR_MR + NEW met1 ( 20723 153 ) M1M2_PR + NEW li1 ( 20723 663 ) L1M1_PR_MR + NEW met1 ( 20723 663 ) M1M2_PR + NEW li1 ( 20723 935 ) L1M1_PR_MR + NEW met1 ( 20723 935 ) M1M2_PR + NEW li1 ( 19435 153 ) L1M1_PR_MR + NEW met1 ( 19435 153 ) M1M2_PR + NEW met2 ( 19435 306 ) M2M3_PR + NEW li1 ( 19435 391 ) L1M1_PR_MR + NEW met1 ( 19435 391 ) M1M2_PR + NEW li1 ( 19435 697 ) L1M1_PR_MR + NEW met1 ( 19435 697 ) M1M2_PR + NEW li1 ( 19435 935 ) L1M1_PR_MR + NEW met1 ( 19435 935 ) M1M2_PR ; + - word_q.w0_b0 ( mux_slice0_bit0.aoi A2 ) ( storage_3_0_0.bit0.obuf0 Z ) ( storage_2_0_0.bit0.obuf0 Z ) ( storage_1_0_0.bit0.obuf0 Z ) ( storage_0_0_0.bit0.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 1127 731 ) ( * 867 ) + NEW met2 ( 1127 493 ) ( * 731 ) + NEW met2 ( 1127 221 ) ( * 493 ) + NEW met2 ( 1403 1037 ) ( * 1207 ) + NEW met1 ( 1403 1207 ) ( 1405 * ) + NEW met1 ( 1127 1037 ) ( 1403 * ) + NEW li1 ( 1127 1037 ) L1M1_PR_MR + NEW li1 ( 1127 731 ) L1M1_PR_MR + NEW met1 ( 1127 731 ) M1M2_PR + NEW li1 ( 1127 867 ) L1M1_PR_MR + NEW met1 ( 1127 867 ) M1M2_PR + NEW li1 ( 1127 493 ) L1M1_PR_MR + NEW met1 ( 1127 493 ) M1M2_PR + NEW li1 ( 1127 221 ) L1M1_PR_MR + NEW met1 ( 1127 221 ) M1M2_PR + NEW met1 ( 1403 1037 ) M1M2_PR + NEW met1 ( 1403 1207 ) M1M2_PR + NEW li1 ( 1405 1207 ) L1M1_PR_MR ; + - word_q.w0_b1 ( mux_slice0_bit1.aoi A2 ) ( storage_3_0_0.bit1.obuf0 Z ) ( storage_2_0_0.bit1.obuf0 Z ) ( storage_1_0_0.bit1.obuf0 Z ) ( storage_0_0_0.bit1.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 3427 1037 ) ( 3703 * ) + NEW met2 ( 3703 1037 ) ( * 1207 ) + NEW met1 ( 3703 1207 ) ( 3705 * ) + NEW met2 ( 3427 765 ) ( * 867 ) + NEW met2 ( 3427 493 ) ( * 765 ) + NEW met2 ( 3427 221 ) ( * 493 ) + NEW li1 ( 3427 1037 ) L1M1_PR_MR + NEW met1 ( 3703 1037 ) M1M2_PR + NEW met1 ( 3703 1207 ) M1M2_PR + NEW li1 ( 3705 1207 ) L1M1_PR_MR + NEW li1 ( 3427 765 ) L1M1_PR_MR + NEW met1 ( 3427 765 ) M1M2_PR + NEW li1 ( 3427 867 ) L1M1_PR_MR + NEW met1 ( 3427 867 ) M1M2_PR + NEW li1 ( 3427 493 ) L1M1_PR_MR + NEW met1 ( 3427 493 ) M1M2_PR + NEW li1 ( 3427 221 ) L1M1_PR_MR + NEW met1 ( 3427 221 ) M1M2_PR ; + - word_q.w0_b2 ( mux_slice0_bit2.aoi A2 ) ( storage_3_0_0.bit2.obuf0 Z ) ( storage_2_0_0.bit2.obuf0 Z ) ( storage_1_0_0.bit2.obuf0 Z ) ( storage_0_0_0.bit2.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 5727 1037 ) ( * 1207 ) + NEW met1 ( 5727 1207 ) ( 6005 * ) + NEW met2 ( 5727 765 ) ( * 1037 ) + NEW met2 ( 5727 493 ) ( * 765 ) + NEW met2 ( 5727 221 ) ( * 493 ) + NEW li1 ( 5727 1037 ) L1M1_PR_MR + NEW met1 ( 5727 1037 ) M1M2_PR + NEW met1 ( 5727 1207 ) M1M2_PR + NEW li1 ( 6005 1207 ) L1M1_PR_MR + NEW li1 ( 5727 765 ) L1M1_PR_MR + NEW met1 ( 5727 765 ) M1M2_PR + NEW li1 ( 5727 493 ) L1M1_PR_MR + NEW met1 ( 5727 493 ) M1M2_PR + NEW li1 ( 5727 221 ) L1M1_PR_MR + NEW met1 ( 5727 221 ) M1M2_PR ; + - word_q.w0_b3 ( mux_slice0_bit3.aoi A2 ) ( storage_3_0_0.bit3.obuf0 Z ) ( storage_2_0_0.bit3.obuf0 Z ) ( storage_1_0_0.bit3.obuf0 Z ) ( storage_0_0_0.bit3.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 8027 1037 ) ( 8303 * ) + NEW met2 ( 8303 1037 ) ( * 1207 ) + NEW met1 ( 8303 1207 ) ( 8305 * ) + NEW met2 ( 7935 731 ) ( * 867 ) + NEW met1 ( 7935 493 ) ( 8027 * ) + NEW met2 ( 7935 493 ) ( * 731 ) + NEW met2 ( 7935 221 ) ( * 493 ) + NEW li1 ( 8027 1037 ) L1M1_PR_MR + NEW met1 ( 8303 1037 ) M1M2_PR + NEW met1 ( 8303 1207 ) M1M2_PR + NEW li1 ( 8305 1207 ) L1M1_PR_MR + NEW li1 ( 7935 731 ) L1M1_PR_MR + NEW met1 ( 7935 731 ) M1M2_PR + NEW li1 ( 7935 867 ) L1M1_PR_MR + NEW met1 ( 7935 867 ) M1M2_PR + NEW li1 ( 8027 493 ) L1M1_PR_MR + NEW met1 ( 7935 493 ) M1M2_PR + NEW li1 ( 7935 221 ) L1M1_PR_MR + NEW met1 ( 7935 221 ) M1M2_PR ; + - word_q.w0_b4 ( mux_slice0_bit4.aoi A2 ) ( storage_3_0_0.bit4.obuf0 Z ) ( storage_2_0_0.bit4.obuf0 Z ) ( storage_1_0_0.bit4.obuf0 Z ) ( storage_0_0_0.bit4.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 10327 1003 ) ( 10373 * ) + NEW met2 ( 10373 986 ) ( * 1003 ) + NEW met2 ( 10373 986 ) ( 10465 * ) + NEW met2 ( 10465 986 ) ( * 1054 ) + NEW met2 ( 10465 1054 ) ( 10603 * ) + NEW met2 ( 10603 1054 ) ( * 1207 ) + NEW met1 ( 10603 1207 ) ( 10605 * ) + NEW met1 ( 10327 731 ) ( 10373 * ) + NEW met2 ( 10373 731 ) ( * 986 ) + NEW met2 ( 10327 493 ) ( * 578 ) + NEW met2 ( 10327 578 ) ( 10373 * ) + NEW met2 ( 10373 578 ) ( * 731 ) + NEW met2 ( 10327 221 ) ( * 493 ) + NEW li1 ( 10327 1003 ) L1M1_PR_MR + NEW met1 ( 10373 1003 ) M1M2_PR + NEW met1 ( 10603 1207 ) M1M2_PR + NEW li1 ( 10605 1207 ) L1M1_PR_MR + NEW li1 ( 10327 731 ) L1M1_PR_MR + NEW met1 ( 10373 731 ) M1M2_PR + NEW li1 ( 10327 493 ) L1M1_PR_MR + NEW met1 ( 10327 493 ) M1M2_PR + NEW li1 ( 10327 221 ) L1M1_PR_MR + NEW met1 ( 10327 221 ) M1M2_PR ; + - word_q.w0_b5 ( mux_slice0_bit5.aoi A2 ) ( storage_3_0_0.bit5.obuf0 Z ) ( storage_2_0_0.bit5.obuf0 Z ) ( storage_1_0_0.bit5.obuf0 Z ) ( storage_0_0_0.bit5.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 12627 901 ) ( 12673 * ) + NEW met2 ( 12673 901 ) ( * 1037 ) + NEW met1 ( 12673 1037 ) ( 12903 * ) + NEW met2 ( 12903 1037 ) ( * 1207 ) + NEW met1 ( 12903 1207 ) ( 12905 * ) + NEW met1 ( 12627 765 ) ( 12673 * ) + NEW met2 ( 12673 765 ) ( * 901 ) + NEW met1 ( 12627 493 ) ( 12673 * ) + NEW met2 ( 12673 493 ) ( * 765 ) + NEW met1 ( 12627 221 ) ( 12673 * ) + NEW met2 ( 12673 221 ) ( * 493 ) + NEW li1 ( 12627 901 ) L1M1_PR_MR + NEW met1 ( 12673 901 ) M1M2_PR + NEW met1 ( 12673 1037 ) M1M2_PR + NEW met1 ( 12903 1037 ) M1M2_PR + NEW met1 ( 12903 1207 ) M1M2_PR + NEW li1 ( 12905 1207 ) L1M1_PR_MR + NEW li1 ( 12627 765 ) L1M1_PR_MR + NEW met1 ( 12673 765 ) M1M2_PR + NEW li1 ( 12627 493 ) L1M1_PR_MR + NEW met1 ( 12673 493 ) M1M2_PR + NEW li1 ( 12627 221 ) L1M1_PR_MR + NEW met1 ( 12673 221 ) M1M2_PR ; + - word_q.w0_b6 ( mux_slice0_bit6.aoi A2 ) ( storage_3_0_0.bit6.obuf0 Z ) ( storage_2_0_0.bit6.obuf0 Z ) ( storage_1_0_0.bit6.obuf0 Z ) ( storage_0_0_0.bit6.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 14927 1037 ) ( 15203 * ) + NEW met2 ( 15203 1037 ) ( * 1207 ) + NEW met1 ( 15203 1207 ) ( 15205 * ) + NEW met2 ( 14927 765 ) ( * 867 ) + NEW met2 ( 14927 425 ) ( * 765 ) + NEW met2 ( 14927 221 ) ( * 425 ) + NEW li1 ( 14927 1037 ) L1M1_PR_MR + NEW met1 ( 15203 1037 ) M1M2_PR + NEW met1 ( 15203 1207 ) M1M2_PR + NEW li1 ( 15205 1207 ) L1M1_PR_MR + NEW li1 ( 14927 765 ) L1M1_PR_MR + NEW met1 ( 14927 765 ) M1M2_PR + NEW li1 ( 14927 867 ) L1M1_PR_MR + NEW met1 ( 14927 867 ) M1M2_PR + NEW li1 ( 14927 425 ) L1M1_PR_MR + NEW met1 ( 14927 425 ) M1M2_PR + NEW li1 ( 14927 221 ) L1M1_PR_MR + NEW met1 ( 14927 221 ) M1M2_PR ; + - word_q.w0_b7 ( mux_slice0_bit7.aoi A2 ) ( storage_3_0_0.bit7.obuf0 Z ) ( storage_2_0_0.bit7.obuf0 Z ) ( storage_1_0_0.bit7.obuf0 Z ) ( storage_0_0_0.bit7.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 17227 969 ) ( * 1207 ) + NEW met2 ( 17227 765 ) ( * 969 ) + NEW met2 ( 17227 459 ) ( * 765 ) + NEW met2 ( 17227 221 ) ( * 459 ) + NEW met1 ( 17227 1207 ) ( 17505 * ) + NEW li1 ( 17227 969 ) L1M1_PR_MR + NEW met1 ( 17227 969 ) M1M2_PR + NEW met1 ( 17227 1207 ) M1M2_PR + NEW li1 ( 17227 765 ) L1M1_PR_MR + NEW met1 ( 17227 765 ) M1M2_PR + NEW li1 ( 17227 459 ) L1M1_PR_MR + NEW met1 ( 17227 459 ) M1M2_PR + NEW li1 ( 17227 221 ) L1M1_PR_MR + NEW met1 ( 17227 221 ) M1M2_PR + NEW li1 ( 17505 1207 ) L1M1_PR_MR ; + - word_q.w1_b0 ( mux_slice0_bit0.aoi B2 ) ( storage_3_1_0.bit0.obuf0 Z ) ( storage_2_1_0.bit0.obuf0 Z ) ( storage_1_1_0.bit0.obuf0 Z ) ( storage_0_1_0.bit0.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 1219 1207 ) ( * 1309 ) + NEW met2 ( 1449 1173 ) ( * 1309 ) + NEW met1 ( 1219 1309 ) ( 1449 * ) + NEW met1 ( 2093 901 ) ( 2139 * ) + NEW met2 ( 2093 901 ) ( * 1173 ) + NEW met1 ( 2093 765 ) ( 2139 * ) + NEW met2 ( 2093 765 ) ( * 901 ) + NEW met2 ( 2277 493 ) ( * 595 ) + NEW met2 ( 2277 221 ) ( * 493 ) + NEW met1 ( 1449 1173 ) ( 2093 * ) + NEW li1 ( 1219 1207 ) L1M1_PR_MR + NEW met1 ( 1449 1173 ) M1M2_PR + NEW met1 ( 1449 1309 ) M1M2_PR + NEW li1 ( 2139 901 ) L1M1_PR_MR + NEW met1 ( 2093 901 ) M1M2_PR + NEW met1 ( 2093 1173 ) M1M2_PR + NEW li1 ( 2139 765 ) L1M1_PR_MR + NEW met1 ( 2093 765 ) M1M2_PR + NEW li1 ( 2277 493 ) L1M1_PR_MR + NEW met1 ( 2277 493 ) M1M2_PR + NEW li1 ( 2277 595 ) L1M1_PR_MR + NEW met1 ( 2277 595 ) M1M2_PR + NEW li1 ( 2277 221 ) L1M1_PR_MR + NEW met1 ( 2277 221 ) M1M2_PR ; + - word_q.w1_b1 ( mux_slice0_bit1.aoi B2 ) ( storage_3_1_0.bit1.obuf0 Z ) ( storage_2_1_0.bit1.obuf0 Z ) ( storage_1_1_0.bit1.obuf0 Z ) ( storage_0_1_0.bit1.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 3749 1037 ) ( 4577 * ) + NEW met2 ( 3749 1037 ) ( * 1258 ) + NEW met2 ( 3565 1258 ) ( 3749 * ) + NEW met2 ( 3565 1173 ) ( * 1258 ) + NEW met1 ( 3519 1173 ) ( 3565 * ) + NEW met2 ( 4439 731 ) ( * 867 ) + NEW met1 ( 4439 493 ) ( 4577 * ) + NEW met2 ( 4439 493 ) ( * 731 ) + NEW met2 ( 4439 187 ) ( * 493 ) + NEW li1 ( 4577 1037 ) L1M1_PR_MR + NEW met1 ( 3749 1037 ) M1M2_PR + NEW met1 ( 3565 1173 ) M1M2_PR + NEW li1 ( 3519 1173 ) L1M1_PR_MR + NEW li1 ( 4439 731 ) L1M1_PR_MR + NEW met1 ( 4439 731 ) M1M2_PR + NEW li1 ( 4439 867 ) L1M1_PR_MR + NEW met1 ( 4439 867 ) M1M2_PR + NEW li1 ( 4577 493 ) L1M1_PR_MR + NEW met1 ( 4439 493 ) M1M2_PR + NEW li1 ( 4439 187 ) L1M1_PR_MR + NEW met1 ( 4439 187 ) M1M2_PR ; + - word_q.w1_b2 ( mux_slice0_bit2.aoi B2 ) ( storage_3_1_0.bit2.obuf0 Z ) ( storage_2_1_0.bit2.obuf0 Z ) ( storage_1_1_0.bit2.obuf0 Z ) ( storage_0_1_0.bit2.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 5819 1037 ) ( 6877 * ) + NEW met2 ( 5819 1037 ) ( * 1173 ) + NEW met2 ( 6739 765 ) ( * 867 ) + NEW met1 ( 6739 493 ) ( 6877 * ) + NEW met2 ( 6739 493 ) ( * 765 ) + NEW met2 ( 6739 187 ) ( * 493 ) + NEW li1 ( 6877 1037 ) L1M1_PR_MR + NEW met1 ( 5819 1037 ) M1M2_PR + NEW li1 ( 5819 1173 ) L1M1_PR_MR + NEW met1 ( 5819 1173 ) M1M2_PR + NEW li1 ( 6739 765 ) L1M1_PR_MR + NEW met1 ( 6739 765 ) M1M2_PR + NEW li1 ( 6739 867 ) L1M1_PR_MR + NEW met1 ( 6739 867 ) M1M2_PR + NEW li1 ( 6877 493 ) L1M1_PR_MR + NEW met1 ( 6739 493 ) M1M2_PR + NEW li1 ( 6739 187 ) L1M1_PR_MR + NEW met1 ( 6739 187 ) M1M2_PR ; + - word_q.w1_b3 ( mux_slice0_bit3.aoi B2 ) ( storage_3_1_0.bit3.obuf0 Z ) ( storage_2_1_0.bit3.obuf0 Z ) ( storage_1_1_0.bit3.obuf0 Z ) ( storage_0_1_0.bit3.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 9177 1037 ) ( * 1139 ) + NEW met1 ( 8119 1139 ) ( 9177 * ) + NEW met1 ( 8119 1139 ) ( * 1173 ) + NEW met2 ( 9177 731 ) ( * 1037 ) + NEW met2 ( 9177 425 ) ( * 731 ) + NEW met2 ( 9177 187 ) ( * 425 ) + NEW li1 ( 9177 1037 ) L1M1_PR_MR + NEW met1 ( 9177 1037 ) M1M2_PR + NEW met1 ( 9177 1139 ) M1M2_PR + NEW li1 ( 8119 1173 ) L1M1_PR_MR + NEW li1 ( 9177 731 ) L1M1_PR_MR + NEW met1 ( 9177 731 ) M1M2_PR + NEW li1 ( 9177 425 ) L1M1_PR_MR + NEW met1 ( 9177 425 ) M1M2_PR + NEW li1 ( 9177 187 ) L1M1_PR_MR + NEW met1 ( 9177 187 ) M1M2_PR ; + - word_q.w1_b4 ( mux_slice0_bit4.aoi B2 ) ( storage_3_1_0.bit4.obuf0 Z ) ( storage_2_1_0.bit4.obuf0 Z ) ( storage_1_1_0.bit4.obuf0 Z ) ( storage_0_1_0.bit4.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 10419 1037 ) ( * 1173 ) + NEW met2 ( 11385 765 ) ( * 867 ) + NEW met1 ( 11385 493 ) ( 11477 * ) + NEW met2 ( 11385 493 ) ( * 765 ) + NEW met2 ( 11385 221 ) ( * 493 ) + NEW met1 ( 10419 1037 ) ( 11477 * ) + NEW met1 ( 10419 1037 ) M1M2_PR + NEW li1 ( 10419 1173 ) L1M1_PR_MR + NEW met1 ( 10419 1173 ) M1M2_PR + NEW li1 ( 11477 1037 ) L1M1_PR_MR + NEW li1 ( 11385 765 ) L1M1_PR_MR + NEW met1 ( 11385 765 ) M1M2_PR + NEW li1 ( 11385 867 ) L1M1_PR_MR + NEW met1 ( 11385 867 ) M1M2_PR + NEW li1 ( 11477 493 ) L1M1_PR_MR + NEW met1 ( 11385 493 ) M1M2_PR + NEW li1 ( 11385 221 ) L1M1_PR_MR + NEW met1 ( 11385 221 ) M1M2_PR ; + - word_q.w1_b5 ( mux_slice0_bit5.aoi B2 ) ( storage_3_1_0.bit5.obuf0 Z ) ( storage_2_1_0.bit5.obuf0 Z ) ( storage_1_1_0.bit5.obuf0 Z ) ( storage_0_1_0.bit5.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 13777 1003 ) ( * 1139 ) + NEW met1 ( 12719 1139 ) ( 13777 * ) + NEW met1 ( 12719 1139 ) ( * 1173 ) + NEW met2 ( 13777 765 ) ( * 1003 ) + NEW met2 ( 13777 493 ) ( * 765 ) + NEW met2 ( 13777 221 ) ( * 493 ) + NEW li1 ( 13777 1003 ) L1M1_PR_MR + NEW met1 ( 13777 1003 ) M1M2_PR + NEW met1 ( 13777 1139 ) M1M2_PR + NEW li1 ( 12719 1173 ) L1M1_PR_MR + NEW li1 ( 13777 765 ) L1M1_PR_MR + NEW met1 ( 13777 765 ) M1M2_PR + NEW li1 ( 13777 493 ) L1M1_PR_MR + NEW met1 ( 13777 493 ) M1M2_PR + NEW li1 ( 13777 221 ) L1M1_PR_MR + NEW met1 ( 13777 221 ) M1M2_PR ; + - word_q.w1_b6 ( mux_slice0_bit6.aoi B2 ) ( storage_3_1_0.bit6.obuf0 Z ) ( storage_2_1_0.bit6.obuf0 Z ) ( storage_1_1_0.bit6.obuf0 Z ) ( storage_0_1_0.bit6.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 16077 1037 ) ( * 1139 ) + NEW met2 ( 16077 731 ) ( * 1037 ) + NEW met2 ( 16077 493 ) ( * 731 ) + NEW met2 ( 16077 221 ) ( * 493 ) + NEW met1 ( 15019 1139 ) ( * 1173 ) + NEW met1 ( 15019 1139 ) ( 16077 * ) + NEW li1 ( 16077 1037 ) L1M1_PR_MR + NEW met1 ( 16077 1037 ) M1M2_PR + NEW met1 ( 16077 1139 ) M1M2_PR + NEW li1 ( 16077 731 ) L1M1_PR_MR + NEW met1 ( 16077 731 ) M1M2_PR + NEW li1 ( 16077 493 ) L1M1_PR_MR + NEW met1 ( 16077 493 ) M1M2_PR + NEW li1 ( 16077 221 ) L1M1_PR_MR + NEW met1 ( 16077 221 ) M1M2_PR + NEW li1 ( 15019 1173 ) L1M1_PR_MR ; + - word_q.w1_b7 ( mux_slice0_bit7.aoi B2 ) ( storage_3_1_0.bit7.obuf0 Z ) ( storage_2_1_0.bit7.obuf0 Z ) ( storage_1_1_0.bit7.obuf0 Z ) ( storage_0_1_0.bit7.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 18239 867 ) ( * 1139 ) + NEW met1 ( 17319 1139 ) ( 18239 * ) + NEW met1 ( 17319 1139 ) ( * 1173 ) + NEW met1 ( 18239 697 ) ( 18377 * ) + NEW met2 ( 18239 697 ) ( * 867 ) + NEW met2 ( 18239 323 ) ( * 697 ) + NEW met2 ( 18239 187 ) ( * 323 ) + NEW li1 ( 18239 867 ) L1M1_PR_MR + NEW met1 ( 18239 867 ) M1M2_PR + NEW met1 ( 18239 1139 ) M1M2_PR + NEW li1 ( 17319 1173 ) L1M1_PR_MR + NEW li1 ( 18377 697 ) L1M1_PR_MR + NEW met1 ( 18239 697 ) M1M2_PR + NEW li1 ( 18239 323 ) L1M1_PR_MR + NEW met1 ( 18239 323 ) M1M2_PR + NEW li1 ( 18239 187 ) L1M1_PR_MR + NEW met1 ( 18239 187 ) M1M2_PR ; +END NETS +END DESIGN diff --git a/src/ram/test/make_8x8_mux2_sky130.lefok b/src/ram/test/make_8x8_mux2_sky130.lefok new file mode 100644 index 00000000000..a175b5c77a6 --- /dev/null +++ b/src/ram/test/make_8x8_mux2_sky130.lefok @@ -0,0 +1,367 @@ +VERSION 5.8 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MACRO RAM8x8 + FOREIGN RAM8x8 0 0 ; + CLASS BLOCK ; + SIZE 213.9 BY 13.6 ; + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 213.1 1.55 213.9 1.85 ; + END + END clk + PIN we[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 213.1 2.91 213.9 3.21 ; + END + END we[0] + PIN addr_rw[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 213.1 4.27 213.9 4.57 ; + END + END addr_rw[0] + PIN addr_rw[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 213.1 5.63 213.9 5.93 ; + END + END addr_rw[1] + PIN addr_rw[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 213.1 6.99 213.9 7.29 ; + END + END addr_rw[2] + PIN D[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 1.08 13.115 1.22 13.6 ; + END + END D[0] + PIN Q[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 13.115 15.94 13.6 ; + END + END Q[0] + PIN D[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 13.115 24.22 13.6 ; + END + END D[1] + PIN Q[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.76 13.115 27.9 13.6 ; + END + END Q[1] + PIN D[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 13.115 28.82 13.6 ; + END + END D[2] + PIN Q[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 29.6 13.115 29.74 13.6 ; + END + END Q[2] + PIN D[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 13.115 69.3 13.6 ; + END + END D[3] + PIN Q[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.8 13.115 84.94 13.6 ; + END + END Q[3] + PIN D[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.08 13.115 93.22 13.6 ; + END + END D[4] + PIN Q[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 107.8 13.115 107.94 13.6 ; + END + END Q[4] + PIN D[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 116.08 13.115 116.22 13.6 ; + END + END D[5] + PIN Q[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 130.8 13.115 130.94 13.6 ; + END + END Q[5] + PIN D[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 139.08 13.115 139.22 13.6 ; + END + END D[6] + PIN Q[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 153.8 13.115 153.94 13.6 ; + END + END Q[6] + PIN D[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 162.08 13.115 162.22 13.6 ; + END + END D[7] + PIN Q[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 176.8 13.115 176.94 13.6 ; + END + END Q[7] + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met3 ; + RECT 213.6 9.76 213.9 10.24 ; + RECT 0 9.76 0.3 10.24 ; + LAYER met2 ; + RECT 199.76 13.46 200.24 13.6 ; + RECT 199.76 0 200.24 0.14 ; + RECT 179.76 13.46 180.24 13.6 ; + RECT 179.76 0 180.24 0.14 ; + RECT 159.76 13.46 160.24 13.6 ; + RECT 159.76 0 160.24 0.14 ; + RECT 139.76 13.46 140.24 13.6 ; + RECT 139.76 0 140.24 0.14 ; + RECT 119.76 13.46 120.24 13.6 ; + RECT 119.76 0 120.24 0.14 ; + RECT 99.76 13.46 100.24 13.6 ; + RECT 99.76 0 100.24 0.14 ; + RECT 79.76 13.46 80.24 13.6 ; + RECT 79.76 0 80.24 0.14 ; + RECT 59.76 13.46 60.24 13.6 ; + RECT 59.76 0 60.24 0.14 ; + RECT 39.76 13.46 40.24 13.6 ; + RECT 39.76 0 40.24 0.14 ; + RECT 19.76 13.46 20.24 13.6 ; + RECT 19.76 0 20.24 0.14 ; + LAYER met1 ; + RECT 213.76 10.64 213.9 11.12 ; + RECT 0 10.64 0.14 11.12 ; + RECT 213.76 5.2 213.9 5.68 ; + RECT 0 5.2 0.14 5.68 ; + RECT 213.76 -0.24 213.9 0.24 ; + RECT 0 -0.24 0.14 0.24 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met3 ; + RECT 213.6 4.76 213.9 5.24 ; + RECT 0 4.76 0.3 5.24 ; + LAYER met2 ; + RECT 209.76 13.46 210.24 13.6 ; + RECT 209.76 0 210.24 0.14 ; + RECT 189.76 13.46 190.24 13.6 ; + RECT 189.76 0 190.24 0.14 ; + RECT 169.76 13.46 170.24 13.6 ; + RECT 169.76 0 170.24 0.14 ; + RECT 149.76 13.46 150.24 13.6 ; + RECT 149.76 0 150.24 0.14 ; + RECT 129.76 13.46 130.24 13.6 ; + RECT 129.76 0 130.24 0.14 ; + RECT 109.76 13.46 110.24 13.6 ; + RECT 109.76 0 110.24 0.14 ; + RECT 89.76 13.46 90.24 13.6 ; + RECT 89.76 0 90.24 0.14 ; + RECT 69.76 13.46 70.24 13.6 ; + RECT 69.76 0 70.24 0.14 ; + RECT 49.76 13.46 50.24 13.6 ; + RECT 49.76 0 50.24 0.14 ; + RECT 29.76 13.46 30.24 13.6 ; + RECT 29.76 0 30.24 0.14 ; + RECT 9.76 13.46 10.24 13.6 ; + RECT 9.76 0 10.24 0.14 ; + LAYER met1 ; + RECT 213.76 13.36 213.9 13.84 ; + RECT 0 13.36 0.14 13.84 ; + RECT 213.76 7.92 213.9 8.4 ; + RECT 0 7.92 0.14 8.4 ; + RECT 213.76 2.48 213.9 2.96 ; + RECT 0 2.48 0.14 2.96 ; + END + END VDD + OBS + LAYER li1 ; + RECT 0 -0.085 213.9 13.685 ; + LAYER met1 ; + RECT 0 -0.24 213.9 13.84 ; + LAYER met2 ; + RECT 99.76 -0.24 100.24 0.155 ; + RECT 109.76 0 110.24 0.155 ; + RECT 99.76 0.155 110.24 0.27 ; + RECT 119.76 -0.24 120.24 0.27 ; + RECT 39.76 -0.24 40.24 0.35 ; + RECT 49.76 0 50.24 0.35 ; + RECT 159.76 -0.24 160.24 0.35 ; + RECT 169.76 0 170.24 0.35 ; + RECT 179.76 -0.24 180.24 0.35 ; + RECT 189.76 0 190.24 0.35 ; + RECT 9.76 0 10.24 0.69 ; + RECT 19.76 -0.24 20.24 0.69 ; + RECT 29.76 0 30.24 0.69 ; + RECT 39.76 0.35 50.24 0.69 ; + RECT 59.76 -0.24 60.24 0.69 ; + RECT 69.76 0 70.24 0.69 ; + RECT 79.76 -0.24 80.24 0.69 ; + RECT 89.76 0 90.24 0.69 ; + RECT 99.76 0.27 120.24 0.69 ; + RECT 129.76 0 130.24 0.69 ; + RECT 139.76 -0.24 140.24 0.69 ; + RECT 149.76 0 150.24 0.69 ; + RECT 159.76 0.35 170.24 0.69 ; + RECT 179.76 0.35 190.24 0.69 ; + RECT 199.76 -0.24 200.24 0.69 ; + RECT 9.76 0.69 60.24 0.835 ; + RECT 69.76 0.69 130.24 0.835 ; + RECT 9.76 0.835 130.24 1.03 ; + RECT 139.76 0.69 200.24 1.03 ; + RECT 209.76 0 210.24 1.03 ; + RECT 1.94 1.03 130.24 1.37 ; + RECT 139.76 1.03 211.5 1.37 ; + RECT 1.94 1.37 211.5 3.41 ; + RECT 1.94 3.41 212.88 5.595 ; + RECT 1.94 5.595 212.89 5.965 ; + RECT 1.94 5.965 212.88 9.17 ; + RECT 1.94 9.17 211.5 9.51 ; + RECT 1.94 9.51 210.24 10.19 ; + RECT 1.94 10.19 140.24 11.55 ; + RECT 149.76 10.19 210.24 11.55 ; + RECT 189.76 11.55 210.24 11.89 ; + RECT 1.94 11.55 40.24 11.91 ; + RECT 1.02 11.91 40.24 12.23 ; + RECT 79.76 11.55 140.24 12.23 ; + RECT 199.76 11.89 210.24 12.23 ; + RECT 1.08 12.23 40.24 12.65 ; + RECT 49.76 11.55 70.24 13.25 ; + RECT 1.08 12.65 30.24 13.26 ; + RECT 59.76 13.25 70.24 13.26 ; + RECT 79.76 12.23 120.24 13.26 ; + RECT 129.76 12.23 140.24 13.26 ; + RECT 149.76 11.55 180.24 13.26 ; + RECT 19.76 13.26 30.24 13.445 ; + RECT 19.76 13.445 20.24 13.6 ; + RECT 39.76 12.65 40.24 13.6 ; + RECT 59.76 13.26 60.24 13.6 ; + RECT 79.76 13.26 80.24 13.6 ; + RECT 99.76 13.26 100.24 13.6 ; + RECT 119.76 13.26 120.24 13.6 ; + RECT 139.76 13.26 140.24 13.6 ; + RECT 159.76 13.26 160.24 13.6 ; + RECT 179.76 13.26 180.24 13.6 ; + RECT 199.76 12.23 200.24 13.6 ; + RECT 9.76 13.26 10.24 13.84 ; + RECT 29.76 13.445 30.24 13.84 ; + RECT 49.76 13.25 50.24 13.84 ; + RECT 69.76 13.26 70.24 13.84 ; + RECT 89.76 13.26 90.24 13.84 ; + RECT 109.76 13.26 110.24 13.84 ; + RECT 129.76 13.26 130.24 13.84 ; + RECT 149.76 13.26 150.24 13.84 ; + RECT 169.76 13.26 170.24 13.84 ; + RECT 189.76 11.89 190.24 13.84 ; + RECT 209.76 12.23 210.24 13.84 ; + LAYER met3 ; + RECT 0 4.76 12.025 10.24 ; + RECT 12.025 2.895 23.525 10.24 ; + RECT 23.525 0.855 23.855 10.24 ; + RECT 23.855 0.87 29.045 10.24 ; + RECT 29.045 0.87 29.375 13.425 ; + RECT 29.375 0.87 34.65 13.41 ; + RECT 34.65 0.87 46.525 12.73 ; + RECT 46.525 0.855 46.855 12.73 ; + RECT 46.855 0.87 61.245 12.73 ; + RECT 61.245 0.87 61.575 12.745 ; + RECT 61.575 0.87 69.065 12.05 ; + RECT 69.065 0.855 69.395 12.05 ; + RECT 69.395 0.87 82.405 12.05 ; + RECT 82.405 0.87 82.735 12.065 ; + RECT 82.735 0.87 92.525 10.24 ; + RECT 92.525 0.855 104.025 10.24 ; + RECT 104.025 0.175 104.355 10.24 ; + RECT 104.355 0.19 125.73 10.24 ; + RECT 125.73 0.855 127.355 10.24 ; + RECT 127.355 0.87 149.105 10.24 ; + RECT 149.105 0.855 149.435 10.24 ; + RECT 149.435 0.87 173.025 10.24 ; + RECT 173.025 0.855 173.355 10.24 ; + RECT 173.355 1.55 190.505 10.24 ; + RECT 190.505 1.535 202.795 10.24 ; + RECT 202.795 1.55 213.5 10.24 ; + RECT 213.5 3.59 213.65 10.24 ; + RECT 213.65 4.76 213.9 10.24 ; + END +END RAM8x8 +END LIBRARY diff --git a/src/ram/test/make_8x8_mux2_sky130.ok b/src/ram/test/make_8x8_mux2_sky130.ok new file mode 100644 index 00000000000..e9bde9d233b --- /dev/null +++ b/src/ram/test/make_8x8_mux2_sky130.ok @@ -0,0 +1,78 @@ +[INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells +[INFO RAM-0003] Generating RAM8x8 +[INFO RAM-0016] Selected inverter cell sky130_fd_sc_hd__clkinv_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__clkinv_1: Y +[INFO RAM-0016] Selected tristate cell sky130_fd_sc_hd__ebufn_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__ebufn_1: Z +[INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__and2_0: X +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__dfxtp_1: Q +[INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__dlclkp_1: GCLK +[INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__buf_1: X +[INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 +[INFO RAM-0024] Behavioral Verilog written for RAM8x8 +[INFO PDN-0001] Inserting grid: ram_grid +[INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-213.90u at the TOP edge. +[INFO PPL-0067] Restrict pins [ clk we[0] addr_rw[0] addr_rw[1] addr_rw[2] ... ] to region 0.00u-13.60u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 464 +[INFO PPL-0002] Number of I/O 21 +[INFO PPL-0003] Number of I/O w/sink 21 +[INFO PPL-0004] Number of I/O w/o sink 0 +[INFO PPL-0005] Slots per section 200 +[INFO PPL-0008] Successfully assigned pins to sections. +[INFO PPL-0012] I/O nets HPWL: 389.01 um. +[INFO DPL-0001] Placed 80 filler instances. +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[INFO DRT-0167] List of default vias: + Layer via + default via: M1M2_PR + Layer via2 + default via: M2M3_PR + Layer via3 + default via: M3M4_PR + Layer via4 + default via: M4M5_PR +[INFO DRT-0168] Init region query. +[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. +[INFO DRT-0033] FR_VIA shape region query size = 0. +[INFO DRT-0033] li1 shape region query size = 7785. +[INFO DRT-0033] mcon shape region query size = 574. +[INFO DRT-0033] met1 shape region query size = 1365. +[INFO DRT-0033] via shape region query size = 63. +[INFO DRT-0033] met2 shape region query size = 163. +[INFO DRT-0033] via2 shape region query size = 21. +[INFO DRT-0033] met3 shape region query size = 32. +[INFO DRT-0033] via3 shape region query size = 0. +[INFO DRT-0033] met4 shape region query size = 0. +[INFO DRT-0033] via4 shape region query size = 0. +[INFO DRT-0033] met5 shape region query size = 0. +[INFO DRT-0178] Init guide query. +[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. +[INFO DRT-0036] FR_VIA guide region query size = 0. +[INFO DRT-0036] li1 guide region query size = 351. +[INFO DRT-0036] mcon guide region query size = 0. +[INFO DRT-0036] met1 guide region query size = 218. +[INFO DRT-0036] via guide region query size = 0. +[INFO DRT-0036] met2 guide region query size = 21. +[INFO DRT-0036] via2 guide region query size = 0. +[INFO DRT-0036] met3 guide region query size = 5. +[INFO DRT-0036] via3 guide region query size = 0. +[INFO DRT-0036] met4 guide region query size = 0. +[INFO DRT-0036] via4 guide region query size = 0. +[INFO DRT-0036] met5 guide region query size = 0. +[INFO DRT-0179] Init gr pin query. +No differences found. +No differences found. +No differences found. diff --git a/src/ram/test/make_8x8_mux2_sky130.tcl b/src/ram/test/make_8x8_mux2_sky130.tcl new file mode 100644 index 00000000000..d929ebd61e4 --- /dev/null +++ b/src/ram/test/make_8x8_mux2_sky130.tcl @@ -0,0 +1,32 @@ +source "helpers.tcl" +set_thread_count [expr [cpu_count]] +read_liberty sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib +read_lef sky130hd/sky130hd.tlef +read_lef sky130hd/sky130_fd_sc_hd_merged.lef +set behavioral_file [make_result_file make_8x8_mux2_behavioral.v] +generate_ram \ + -mask_size 8 \ + -word_size 8 \ + -num_words 8 \ + -column_mux_ratio 2 \ + -read_ports 1 \ + -storage_cell sky130_fd_sc_hd__dfxtp_1 \ + -power_pin VPWR \ + -ground_pin VGND \ + -routing_layer {met1 0.48} \ + -ver_layer {met2 0.48 20} \ + -hor_layer {met3 0.48 10} \ + -filler_cells {sky130_fd_sc_hd__fill_1 sky130_fd_sc_hd__fill_2 \ + sky130_fd_sc_hd__fill_4 sky130_fd_sc_hd__fill_8} \ + -tapcell sky130_fd_sc_hd__tap_1 \ + -max_tap_dist 15 \ + -write_behavioral_verilog $behavioral_file + +write_verilog [make_result_file make_8x8_mux2_sky130.v] +set lef_file [make_result_file make_8x8_mux2_sky130.lef] +write_abstract_lef $lef_file +diff_files make_8x8_mux2_sky130.lefok $lef_file +set def_file [make_result_file make_8x8_mux2_sky130.def] +write_def $def_file +diff_files make_8x8_mux2_sky130.defok $def_file +diff_files make_8x8_behavioral.vok $behavioral_file diff --git a/src/ram/test/make_8x8_mux4_sky130.defok b/src/ram/test/make_8x8_mux4_sky130.defok new file mode 100644 index 00000000000..465b56ccde2 --- /dev/null +++ b/src/ram/test/make_8x8_mux4_sky130.defok @@ -0,0 +1,4363 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN RAM8x8 ; +UNITS DISTANCE MICRONS 100 ; +DIEAREA ( 0 0 ) ( 41768 816 ) ; +ROW RAM_ROW0 unithd 0 0 N DO 908 BY 1 STEP 46 0 ; +ROW RAM_ROW1 unithd 0 272 FS DO 908 BY 1 STEP 46 0 ; +ROW RAM_ROW2 unithd 0 544 N DO 908 BY 1 STEP 46 0 ; +TRACKS X 23 DO 908 STEP 46 LAYER li1 ; +TRACKS Y 17 DO 24 STEP 34 LAYER li1 ; +TRACKS X 17 DO 1228 STEP 34 LAYER met1 ; +TRACKS Y 17 DO 24 STEP 34 LAYER met1 ; +TRACKS X 23 DO 908 STEP 46 LAYER met2 ; +TRACKS Y 23 DO 18 STEP 46 LAYER met2 ; +TRACKS X 34 DO 614 STEP 68 LAYER met3 ; +TRACKS Y 34 DO 12 STEP 68 LAYER met3 ; +TRACKS X 46 DO 454 STEP 92 LAYER met4 ; +TRACKS Y 46 DO 9 STEP 92 LAYER met4 ; +TRACKS X 170 DO 123 STEP 340 LAYER met5 ; +TRACKS Y 170 DO 2 STEP 340 LAYER met5 ; +GCELLGRID X 0 DO 60 STEP 690 ; +GCELLGRID Y 0 DO 1 STEP 690 ; +VIAS 2 ; + - via2_3_480_480_1_1_320_320 + VIARULE M1M2_PR + CUTSIZE 15 15 + LAYERS met1 via met2 + CUTSPACING 17 17 + ENCLOSURE 8 16 16 8 ; + - via3_4_480_480_1_1_400_400 + VIARULE M2M3_PR + CUTSIZE 20 20 + LAYERS met2 via2 met3 + CUTSPACING 20 20 + ENCLOSURE 14 8 6 14 ; +END VIAS +COMPONENTS 421 ; + - FILLER_0_903 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 41538 0 ) N ; + - FILLER_1_903 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 41538 272 ) FS ; + - FILLER_1_907 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 41722 272 ) FS ; + - FILLER_2_104 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4784 544 ) N ; + - FILLER_2_112 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5152 544 ) N ; + - FILLER_2_12 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 552 544 ) N ; + - FILLER_2_120 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 5520 544 ) N ; + - FILLER_2_124 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5704 544 ) N ; + - FILLER_2_132 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6072 544 ) N ; + - FILLER_2_140 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6440 544 ) N ; + - FILLER_2_148 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 6808 544 ) N ; + - FILLER_2_157 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7222 544 ) N ; + - FILLER_2_165 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7590 544 ) N ; + - FILLER_2_173 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 7958 544 ) N ; + - FILLER_2_182 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8372 544 ) N ; + - FILLER_2_190 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8740 544 ) N ; + - FILLER_2_198 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9108 544 ) N ; + - FILLER_2_20 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 920 544 ) N ; + - FILLER_2_204 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 9384 544 ) N ; + - FILLER_2_212 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 9752 544 ) N ; + - FILLER_2_220 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 10120 544 ) N ; + - FILLER_2_224 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 10304 544 ) N ; + - FILLER_2_232 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 10672 544 ) N ; + - FILLER_2_24 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 1104 544 ) N ; + - FILLER_2_240 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 11040 544 ) N ; + - FILLER_2_248 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 11408 544 ) N ; + - FILLER_2_257 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 11822 544 ) N ; + - FILLER_2_265 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 12190 544 ) N ; + - FILLER_2_273 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 12558 544 ) N ; + - FILLER_2_282 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 12972 544 ) N ; + - FILLER_2_290 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 13340 544 ) N ; + - FILLER_2_298 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 13708 544 ) N ; + - FILLER_2_304 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 13984 544 ) N ; + - FILLER_2_312 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 14352 544 ) N ; + - FILLER_2_32 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1472 544 ) N ; + - FILLER_2_320 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 14720 544 ) N ; + - FILLER_2_324 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 14904 544 ) N ; + - FILLER_2_332 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 15272 544 ) N ; + - FILLER_2_340 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 15640 544 ) N ; + - FILLER_2_348 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 16008 544 ) N ; + - FILLER_2_357 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 16422 544 ) N ; + - FILLER_2_365 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 16790 544 ) N ; + - FILLER_2_373 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 17158 544 ) N ; + - FILLER_2_382 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 17572 544 ) N ; + - FILLER_2_390 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 17940 544 ) N ; + - FILLER_2_398 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 18308 544 ) N ; + - FILLER_2_4 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 184 544 ) N ; + - FILLER_2_40 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1840 544 ) N ; + - FILLER_2_404 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 18584 544 ) N ; + - FILLER_2_412 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 18952 544 ) N ; + - FILLER_2_420 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 19320 544 ) N ; + - FILLER_2_424 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 19504 544 ) N ; + - FILLER_2_432 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 19872 544 ) N ; + - FILLER_2_440 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 20240 544 ) N ; + - FILLER_2_448 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 20608 544 ) N ; + - FILLER_2_457 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 21022 544 ) N ; + - FILLER_2_465 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 21390 544 ) N ; + - FILLER_2_473 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 21758 544 ) N ; + - FILLER_2_48 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 2208 544 ) N ; + - FILLER_2_482 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 22172 544 ) N ; + - FILLER_2_490 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 22540 544 ) N ; + - FILLER_2_498 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 22908 544 ) N ; + - FILLER_2_504 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 23184 544 ) N ; + - FILLER_2_512 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 23552 544 ) N ; + - FILLER_2_520 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 23920 544 ) N ; + - FILLER_2_524 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 24104 544 ) N ; + - FILLER_2_532 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 24472 544 ) N ; + - FILLER_2_540 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 24840 544 ) N ; + - FILLER_2_548 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 25208 544 ) N ; + - FILLER_2_557 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 25622 544 ) N ; + - FILLER_2_565 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 25990 544 ) N ; + - FILLER_2_57 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2622 544 ) N ; + - FILLER_2_573 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 26358 544 ) N ; + - FILLER_2_582 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 26772 544 ) N ; + - FILLER_2_590 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 27140 544 ) N ; + - FILLER_2_598 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 27508 544 ) N ; + - FILLER_2_604 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 27784 544 ) N ; + - FILLER_2_612 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 28152 544 ) N ; + - FILLER_2_620 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 28520 544 ) N ; + - FILLER_2_624 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 28704 544 ) N ; + - FILLER_2_632 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 29072 544 ) N ; + - FILLER_2_640 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 29440 544 ) N ; + - FILLER_2_648 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 29808 544 ) N ; + - FILLER_2_65 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2990 544 ) N ; + - FILLER_2_657 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 30222 544 ) N ; + - FILLER_2_665 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 30590 544 ) N ; + - FILLER_2_673 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 30958 544 ) N ; + - FILLER_2_682 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 31372 544 ) N ; + - FILLER_2_690 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 31740 544 ) N ; + - FILLER_2_698 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 32108 544 ) N ; + - FILLER_2_704 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 32384 544 ) N ; + - FILLER_2_712 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 32752 544 ) N ; + - FILLER_2_720 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 33120 544 ) N ; + - FILLER_2_724 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 33304 544 ) N ; + - FILLER_2_73 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 3358 544 ) N ; + - FILLER_2_732 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 33672 544 ) N ; + - FILLER_2_740 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 34040 544 ) N ; + - FILLER_2_748 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 34408 544 ) N ; + - FILLER_2_757 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 34822 544 ) N ; + - FILLER_2_765 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 35190 544 ) N ; + - FILLER_2_773 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 35558 544 ) N ; + - FILLER_2_782 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 35972 544 ) N ; + - FILLER_2_790 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 36340 544 ) N ; + - FILLER_2_798 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 36708 544 ) N ; + - FILLER_2_801 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 36846 544 ) N ; + - FILLER_2_809 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 37214 544 ) N ; + - FILLER_2_817 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 37582 544 ) N ; + - FILLER_2_82 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3772 544 ) N ; + - FILLER_2_825 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 37950 544 ) N ; + - FILLER_2_827 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 38042 544 ) N ; + - FILLER_2_829 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 38134 544 ) N ; + - FILLER_2_837 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 38502 544 ) N ; + - FILLER_2_845 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 38870 544 ) N ; + - FILLER_2_854 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 39284 544 ) N ; + - FILLER_2_862 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 39652 544 ) N ; + - FILLER_2_870 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 40020 544 ) N ; + - FILLER_2_90 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4140 544 ) N ; + - FILLER_2_905 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 41630 544 ) N ; + - FILLER_2_907 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 41722 544 ) N ; + - FILLER_2_98 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 4508 544 ) N ; + - buffer.in[0] sky130_fd_sc_hd__buf_1 + PLACED ( 46 544 ) N ; + - buffer.in[1] sky130_fd_sc_hd__buf_1 + PLACED ( 4646 544 ) N ; + - buffer.in[2] sky130_fd_sc_hd__buf_1 + PLACED ( 9246 544 ) N ; + - buffer.in[3] sky130_fd_sc_hd__buf_1 + PLACED ( 13846 544 ) N ; + - buffer.in[4] sky130_fd_sc_hd__buf_1 + PLACED ( 18446 544 ) N ; + - buffer.in[5] sky130_fd_sc_hd__buf_1 + PLACED ( 23046 544 ) N ; + - buffer.in[6] sky130_fd_sc_hd__buf_1 + PLACED ( 27646 544 ) N ; + - buffer.in[7] sky130_fd_sc_hd__buf_1 + PLACED ( 32246 544 ) N ; + - decoder.inv_2 sky130_fd_sc_hd__clkinv_1 + PLACED ( 41630 0 ) N ; + - mux_slice0_bit0.s1_aoi_0 sky130_fd_sc_hd__a22oi_1 + PLACED ( 1196 544 ) N ; + - mux_slice0_bit0.s1_aoi_1 sky130_fd_sc_hd__a22oi_1 + PLACED ( 3496 544 ) N ; + - mux_slice0_bit0.s2_aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 2346 544 ) N ; + - mux_slice0_bit1.s1_aoi_0 sky130_fd_sc_hd__a22oi_1 + PLACED ( 5796 544 ) N ; + - mux_slice0_bit1.s1_aoi_1 sky130_fd_sc_hd__a22oi_1 + PLACED ( 8096 544 ) N ; + - mux_slice0_bit1.s2_aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 6946 544 ) N ; + - mux_slice0_bit2.s1_aoi_0 sky130_fd_sc_hd__a22oi_1 + PLACED ( 10396 544 ) N ; + - mux_slice0_bit2.s1_aoi_1 sky130_fd_sc_hd__a22oi_1 + PLACED ( 12696 544 ) N ; + - mux_slice0_bit2.s2_aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 11546 544 ) N ; + - mux_slice0_bit3.s1_aoi_0 sky130_fd_sc_hd__a22oi_1 + PLACED ( 14996 544 ) N ; + - mux_slice0_bit3.s1_aoi_1 sky130_fd_sc_hd__a22oi_1 + PLACED ( 17296 544 ) N ; + - mux_slice0_bit3.s2_aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 16146 544 ) N ; + - mux_slice0_bit4.s1_aoi_0 sky130_fd_sc_hd__a22oi_1 + PLACED ( 19596 544 ) N ; + - mux_slice0_bit4.s1_aoi_1 sky130_fd_sc_hd__a22oi_1 + PLACED ( 21896 544 ) N ; + - mux_slice0_bit4.s2_aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 20746 544 ) N ; + - mux_slice0_bit5.s1_aoi_0 sky130_fd_sc_hd__a22oi_1 + PLACED ( 24196 544 ) N ; + - mux_slice0_bit5.s1_aoi_1 sky130_fd_sc_hd__a22oi_1 + PLACED ( 26496 544 ) N ; + - mux_slice0_bit5.s2_aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 25346 544 ) N ; + - mux_slice0_bit6.s1_aoi_0 sky130_fd_sc_hd__a22oi_1 + PLACED ( 28796 544 ) N ; + - mux_slice0_bit6.s1_aoi_1 sky130_fd_sc_hd__a22oi_1 + PLACED ( 31096 544 ) N ; + - mux_slice0_bit6.s2_aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 29946 544 ) N ; + - mux_slice0_bit7.s1_aoi_0 sky130_fd_sc_hd__a22oi_1 + PLACED ( 33396 544 ) N ; + - mux_slice0_bit7.s1_aoi_1 sky130_fd_sc_hd__a22oi_1 + PLACED ( 35696 544 ) N ; + - mux_slice0_bit7.s2_aoi sky130_fd_sc_hd__a22oi_1 + PLACED ( 34546 544 ) N ; + - storage_0_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 0 ) N ; + - storage_0_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 0 ) N ; + - storage_0_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 0 ) N ; + - storage_0_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 0 ) N ; + - storage_0_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 9246 0 ) N ; + - storage_0_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 9982 0 ) N ; + - storage_0_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 13846 0 ) N ; + - storage_0_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 14582 0 ) N ; + - storage_0_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 18446 0 ) N ; + - storage_0_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 19182 0 ) N ; + - storage_0_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 23046 0 ) N ; + - storage_0_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 23782 0 ) N ; + - storage_0_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 27646 0 ) N ; + - storage_0_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 28382 0 ) N ; + - storage_0_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 32246 0 ) N ; + - storage_0_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 32982 0 ) N ; + - storage_0_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 36846 0 ) N ; + - storage_0_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 37720 0 ) N ; + - storage_0_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 37950 0 ) N ; + - storage_0_0_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 37490 0 ) N ; + - storage_0_1_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 0 ) N ; + - storage_0_1_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 0 ) N ; + - storage_0_1_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 0 ) N ; + - storage_0_1_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 0 ) N ; + - storage_0_1_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 10396 0 ) N ; + - storage_0_1_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 11132 0 ) N ; + - storage_0_1_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 14996 0 ) N ; + - storage_0_1_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 15732 0 ) N ; + - storage_0_1_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 19596 0 ) N ; + - storage_0_1_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 20332 0 ) N ; + - storage_0_1_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 24196 0 ) N ; + - storage_0_1_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 24932 0 ) N ; + - storage_0_1_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 28796 0 ) N ; + - storage_0_1_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 29532 0 ) N ; + - storage_0_1_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 33396 0 ) N ; + - storage_0_1_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 34132 0 ) N ; + - storage_0_1_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 38134 0 ) N ; + - storage_0_1_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 39008 0 ) N ; + - storage_0_1_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 38778 0 ) N ; + - storage_0_2_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 0 ) N ; + - storage_0_2_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 0 ) N ; + - storage_0_2_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 0 ) N ; + - storage_0_2_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 0 ) N ; + - storage_0_2_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 11546 0 ) N ; + - storage_0_2_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 12282 0 ) N ; + - storage_0_2_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 16146 0 ) N ; + - storage_0_2_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 16882 0 ) N ; + - storage_0_2_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 20746 0 ) N ; + - storage_0_2_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 21482 0 ) N ; + - storage_0_2_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 25346 0 ) N ; + - storage_0_2_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 26082 0 ) N ; + - storage_0_2_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 29946 0 ) N ; + - storage_0_2_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 30682 0 ) N ; + - storage_0_2_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 34546 0 ) N ; + - storage_0_2_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 35282 0 ) N ; + - storage_0_2_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 39284 0 ) N ; + - storage_0_2_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 40158 0 ) N ; + - storage_0_2_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 39928 0 ) N ; + - storage_0_3_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 0 ) N ; + - storage_0_3_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 0 ) N ; + - storage_0_3_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 0 ) N ; + - storage_0_3_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 0 ) N ; + - storage_0_3_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 12696 0 ) N ; + - storage_0_3_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 13432 0 ) N ; + - storage_0_3_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 17296 0 ) N ; + - storage_0_3_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 18032 0 ) N ; + - storage_0_3_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 21896 0 ) N ; + - storage_0_3_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 22632 0 ) N ; + - storage_0_3_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 26496 0 ) N ; + - storage_0_3_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 27232 0 ) N ; + - storage_0_3_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 31096 0 ) N ; + - storage_0_3_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 31832 0 ) N ; + - storage_0_3_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 35696 0 ) N ; + - storage_0_3_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 36432 0 ) N ; + - storage_0_3_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 40434 0 ) N ; + - storage_0_3_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 41308 0 ) N ; + - storage_0_3_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 41078 0 ) N ; + - storage_1_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 272 ) FS ; + - storage_1_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 272 ) FS ; + - storage_1_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 272 ) FS ; + - storage_1_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 272 ) FS ; + - storage_1_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 9246 272 ) FS ; + - storage_1_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 9982 272 ) FS ; + - storage_1_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 13846 272 ) FS ; + - storage_1_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 14582 272 ) FS ; + - storage_1_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 18446 272 ) FS ; + - storage_1_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 19182 272 ) FS ; + - storage_1_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 23046 272 ) FS ; + - storage_1_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 23782 272 ) FS ; + - storage_1_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 27646 272 ) FS ; + - storage_1_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 28382 272 ) FS ; + - storage_1_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 32246 272 ) FS ; + - storage_1_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 32982 272 ) FS ; + - storage_1_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 36846 272 ) FS ; + - storage_1_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 37720 272 ) FS ; + - storage_1_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 37950 272 ) FS ; + - storage_1_0_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 37490 272 ) FS ; + - storage_1_1_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 272 ) FS ; + - storage_1_1_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 272 ) FS ; + - storage_1_1_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 272 ) FS ; + - storage_1_1_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 272 ) FS ; + - storage_1_1_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 10396 272 ) FS ; + - storage_1_1_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 11132 272 ) FS ; + - storage_1_1_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 14996 272 ) FS ; + - storage_1_1_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 15732 272 ) FS ; + - storage_1_1_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 19596 272 ) FS ; + - storage_1_1_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 20332 272 ) FS ; + - storage_1_1_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 24196 272 ) FS ; + - storage_1_1_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 24932 272 ) FS ; + - storage_1_1_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 28796 272 ) FS ; + - storage_1_1_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 29532 272 ) FS ; + - storage_1_1_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 33396 272 ) FS ; + - storage_1_1_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 34132 272 ) FS ; + - storage_1_1_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 38134 272 ) FS ; + - storage_1_1_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 39008 272 ) FS ; + - storage_1_1_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 38778 272 ) FS ; + - storage_1_2_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 272 ) FS ; + - storage_1_2_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 272 ) FS ; + - storage_1_2_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 272 ) FS ; + - storage_1_2_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 272 ) FS ; + - storage_1_2_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 11546 272 ) FS ; + - storage_1_2_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 12282 272 ) FS ; + - storage_1_2_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 16146 272 ) FS ; + - storage_1_2_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 16882 272 ) FS ; + - storage_1_2_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 20746 272 ) FS ; + - storage_1_2_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 21482 272 ) FS ; + - storage_1_2_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 25346 272 ) FS ; + - storage_1_2_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 26082 272 ) FS ; + - storage_1_2_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 29946 272 ) FS ; + - storage_1_2_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 30682 272 ) FS ; + - storage_1_2_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 34546 272 ) FS ; + - storage_1_2_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 35282 272 ) FS ; + - storage_1_2_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 39284 272 ) FS ; + - storage_1_2_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 40158 272 ) FS ; + - storage_1_2_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 39928 272 ) FS ; + - storage_1_3_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 272 ) FS ; + - storage_1_3_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 272 ) FS ; + - storage_1_3_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 272 ) FS ; + - storage_1_3_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 272 ) FS ; + - storage_1_3_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 12696 272 ) FS ; + - storage_1_3_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 13432 272 ) FS ; + - storage_1_3_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 17296 272 ) FS ; + - storage_1_3_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 18032 272 ) FS ; + - storage_1_3_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 21896 272 ) FS ; + - storage_1_3_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 22632 272 ) FS ; + - storage_1_3_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 26496 272 ) FS ; + - storage_1_3_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 27232 272 ) FS ; + - storage_1_3_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 31096 272 ) FS ; + - storage_1_3_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 31832 272 ) FS ; + - storage_1_3_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 35696 272 ) FS ; + - storage_1_3_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 36432 272 ) FS ; + - storage_1_3_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 40434 272 ) FS ; + - storage_1_3_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 41308 272 ) FS ; + - storage_1_3_0.word_and sky130_fd_sc_hd__and2_0 + PLACED ( 41078 272 ) FS ; + - tapcell.cell0_0 sky130_fd_sc_hd__tap_1 + PLACED ( 0 0 ) N ; + - tapcell.cell0_1 sky130_fd_sc_hd__tap_1 + PLACED ( 0 272 ) FS ; + - tapcell.cell0_2 sky130_fd_sc_hd__tap_1 + PLACED ( 0 544 ) N ; + - tapcell.cell10_0 sky130_fd_sc_hd__tap_1 + PLACED ( 11500 0 ) N ; + - tapcell.cell10_1 sky130_fd_sc_hd__tap_1 + PLACED ( 11500 272 ) FS ; + - tapcell.cell10_2 sky130_fd_sc_hd__tap_1 + PLACED ( 11500 544 ) N ; + - tapcell.cell11_0 sky130_fd_sc_hd__tap_1 + PLACED ( 12650 0 ) N ; + - tapcell.cell11_1 sky130_fd_sc_hd__tap_1 + PLACED ( 12650 272 ) FS ; + - tapcell.cell11_2 sky130_fd_sc_hd__tap_1 + PLACED ( 12650 544 ) N ; + - tapcell.cell12_0 sky130_fd_sc_hd__tap_1 + PLACED ( 13800 0 ) N ; + - tapcell.cell12_1 sky130_fd_sc_hd__tap_1 + PLACED ( 13800 272 ) FS ; + - tapcell.cell12_2 sky130_fd_sc_hd__tap_1 + PLACED ( 13800 544 ) N ; + - tapcell.cell13_0 sky130_fd_sc_hd__tap_1 + PLACED ( 14950 0 ) N ; + - tapcell.cell13_1 sky130_fd_sc_hd__tap_1 + PLACED ( 14950 272 ) FS ; + - tapcell.cell13_2 sky130_fd_sc_hd__tap_1 + PLACED ( 14950 544 ) N ; + - tapcell.cell14_0 sky130_fd_sc_hd__tap_1 + PLACED ( 16100 0 ) N ; + - tapcell.cell14_1 sky130_fd_sc_hd__tap_1 + PLACED ( 16100 272 ) FS ; + - tapcell.cell14_2 sky130_fd_sc_hd__tap_1 + PLACED ( 16100 544 ) N ; + - tapcell.cell15_0 sky130_fd_sc_hd__tap_1 + PLACED ( 17250 0 ) N ; + - tapcell.cell15_1 sky130_fd_sc_hd__tap_1 + PLACED ( 17250 272 ) FS ; + - tapcell.cell15_2 sky130_fd_sc_hd__tap_1 + PLACED ( 17250 544 ) N ; + - tapcell.cell16_0 sky130_fd_sc_hd__tap_1 + PLACED ( 18400 0 ) N ; + - tapcell.cell16_1 sky130_fd_sc_hd__tap_1 + PLACED ( 18400 272 ) FS ; + - tapcell.cell16_2 sky130_fd_sc_hd__tap_1 + PLACED ( 18400 544 ) N ; + - tapcell.cell17_0 sky130_fd_sc_hd__tap_1 + PLACED ( 19550 0 ) N ; + - tapcell.cell17_1 sky130_fd_sc_hd__tap_1 + PLACED ( 19550 272 ) FS ; + - tapcell.cell17_2 sky130_fd_sc_hd__tap_1 + PLACED ( 19550 544 ) N ; + - tapcell.cell18_0 sky130_fd_sc_hd__tap_1 + PLACED ( 20700 0 ) N ; + - tapcell.cell18_1 sky130_fd_sc_hd__tap_1 + PLACED ( 20700 272 ) FS ; + - tapcell.cell18_2 sky130_fd_sc_hd__tap_1 + PLACED ( 20700 544 ) N ; + - tapcell.cell19_0 sky130_fd_sc_hd__tap_1 + PLACED ( 21850 0 ) N ; + - tapcell.cell19_1 sky130_fd_sc_hd__tap_1 + PLACED ( 21850 272 ) FS ; + - tapcell.cell19_2 sky130_fd_sc_hd__tap_1 + PLACED ( 21850 544 ) N ; + - tapcell.cell1_0 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 0 ) N ; + - tapcell.cell1_1 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 272 ) FS ; + - tapcell.cell1_2 sky130_fd_sc_hd__tap_1 + PLACED ( 1150 544 ) N ; + - tapcell.cell20_0 sky130_fd_sc_hd__tap_1 + PLACED ( 23000 0 ) N ; + - tapcell.cell20_1 sky130_fd_sc_hd__tap_1 + PLACED ( 23000 272 ) FS ; + - tapcell.cell20_2 sky130_fd_sc_hd__tap_1 + PLACED ( 23000 544 ) N ; + - tapcell.cell21_0 sky130_fd_sc_hd__tap_1 + PLACED ( 24150 0 ) N ; + - tapcell.cell21_1 sky130_fd_sc_hd__tap_1 + PLACED ( 24150 272 ) FS ; + - tapcell.cell21_2 sky130_fd_sc_hd__tap_1 + PLACED ( 24150 544 ) N ; + - tapcell.cell22_0 sky130_fd_sc_hd__tap_1 + PLACED ( 25300 0 ) N ; + - tapcell.cell22_1 sky130_fd_sc_hd__tap_1 + PLACED ( 25300 272 ) FS ; + - tapcell.cell22_2 sky130_fd_sc_hd__tap_1 + PLACED ( 25300 544 ) N ; + - tapcell.cell23_0 sky130_fd_sc_hd__tap_1 + PLACED ( 26450 0 ) N ; + - tapcell.cell23_1 sky130_fd_sc_hd__tap_1 + PLACED ( 26450 272 ) FS ; + - tapcell.cell23_2 sky130_fd_sc_hd__tap_1 + PLACED ( 26450 544 ) N ; + - tapcell.cell24_0 sky130_fd_sc_hd__tap_1 + PLACED ( 27600 0 ) N ; + - tapcell.cell24_1 sky130_fd_sc_hd__tap_1 + PLACED ( 27600 272 ) FS ; + - tapcell.cell24_2 sky130_fd_sc_hd__tap_1 + PLACED ( 27600 544 ) N ; + - tapcell.cell25_0 sky130_fd_sc_hd__tap_1 + PLACED ( 28750 0 ) N ; + - tapcell.cell25_1 sky130_fd_sc_hd__tap_1 + PLACED ( 28750 272 ) FS ; + - tapcell.cell25_2 sky130_fd_sc_hd__tap_1 + PLACED ( 28750 544 ) N ; + - tapcell.cell26_0 sky130_fd_sc_hd__tap_1 + PLACED ( 29900 0 ) N ; + - tapcell.cell26_1 sky130_fd_sc_hd__tap_1 + PLACED ( 29900 272 ) FS ; + - tapcell.cell26_2 sky130_fd_sc_hd__tap_1 + PLACED ( 29900 544 ) N ; + - tapcell.cell27_0 sky130_fd_sc_hd__tap_1 + PLACED ( 31050 0 ) N ; + - tapcell.cell27_1 sky130_fd_sc_hd__tap_1 + PLACED ( 31050 272 ) FS ; + - tapcell.cell27_2 sky130_fd_sc_hd__tap_1 + PLACED ( 31050 544 ) N ; + - tapcell.cell28_0 sky130_fd_sc_hd__tap_1 + PLACED ( 32200 0 ) N ; + - tapcell.cell28_1 sky130_fd_sc_hd__tap_1 + PLACED ( 32200 272 ) FS ; + - tapcell.cell28_2 sky130_fd_sc_hd__tap_1 + PLACED ( 32200 544 ) N ; + - tapcell.cell29_0 sky130_fd_sc_hd__tap_1 + PLACED ( 33350 0 ) N ; + - tapcell.cell29_1 sky130_fd_sc_hd__tap_1 + PLACED ( 33350 272 ) FS ; + - tapcell.cell29_2 sky130_fd_sc_hd__tap_1 + PLACED ( 33350 544 ) N ; + - tapcell.cell2_0 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 0 ) N ; + - tapcell.cell2_1 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 272 ) FS ; + - tapcell.cell2_2 sky130_fd_sc_hd__tap_1 + PLACED ( 2300 544 ) N ; + - tapcell.cell30_0 sky130_fd_sc_hd__tap_1 + PLACED ( 34500 0 ) N ; + - tapcell.cell30_1 sky130_fd_sc_hd__tap_1 + PLACED ( 34500 272 ) FS ; + - tapcell.cell30_2 sky130_fd_sc_hd__tap_1 + PLACED ( 34500 544 ) N ; + - tapcell.cell31_0 sky130_fd_sc_hd__tap_1 + PLACED ( 35650 0 ) N ; + - tapcell.cell31_1 sky130_fd_sc_hd__tap_1 + PLACED ( 35650 272 ) FS ; + - tapcell.cell31_2 sky130_fd_sc_hd__tap_1 + PLACED ( 35650 544 ) N ; + - tapcell.cell32_0 sky130_fd_sc_hd__tap_1 + PLACED ( 36800 0 ) N ; + - tapcell.cell32_1 sky130_fd_sc_hd__tap_1 + PLACED ( 36800 272 ) FS ; + - tapcell.cell32_2 sky130_fd_sc_hd__tap_1 + PLACED ( 36800 544 ) N ; + - tapcell.cell33_0 sky130_fd_sc_hd__tap_1 + PLACED ( 38088 0 ) N ; + - tapcell.cell33_1 sky130_fd_sc_hd__tap_1 + PLACED ( 38088 272 ) FS ; + - tapcell.cell33_2 sky130_fd_sc_hd__tap_1 + PLACED ( 38088 544 ) N ; + - tapcell.cell34_0 sky130_fd_sc_hd__tap_1 + PLACED ( 39238 0 ) N ; + - tapcell.cell34_1 sky130_fd_sc_hd__tap_1 + PLACED ( 39238 272 ) FS ; + - tapcell.cell34_2 sky130_fd_sc_hd__tap_1 + PLACED ( 39238 544 ) N ; + - tapcell.cell35_0 sky130_fd_sc_hd__tap_1 + PLACED ( 40388 0 ) N ; + - tapcell.cell35_1 sky130_fd_sc_hd__tap_1 + PLACED ( 40388 272 ) FS ; + - tapcell.cell35_2 sky130_fd_sc_hd__tap_1 + PLACED ( 40388 544 ) N ; + - tapcell.cell3_0 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 0 ) N ; + - tapcell.cell3_1 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 272 ) FS ; + - tapcell.cell3_2 sky130_fd_sc_hd__tap_1 + PLACED ( 3450 544 ) N ; + - tapcell.cell4_0 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 0 ) N ; + - tapcell.cell4_1 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 272 ) FS ; + - tapcell.cell4_2 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 544 ) N ; + - tapcell.cell5_0 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 0 ) N ; + - tapcell.cell5_1 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 272 ) FS ; + - tapcell.cell5_2 sky130_fd_sc_hd__tap_1 + PLACED ( 5750 544 ) N ; + - tapcell.cell6_0 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 0 ) N ; + - tapcell.cell6_1 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 272 ) FS ; + - tapcell.cell6_2 sky130_fd_sc_hd__tap_1 + PLACED ( 6900 544 ) N ; + - tapcell.cell7_0 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 0 ) N ; + - tapcell.cell7_1 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 272 ) FS ; + - tapcell.cell7_2 sky130_fd_sc_hd__tap_1 + PLACED ( 8050 544 ) N ; + - tapcell.cell8_0 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 0 ) N ; + - tapcell.cell8_1 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 272 ) FS ; + - tapcell.cell8_2 sky130_fd_sc_hd__tap_1 + PLACED ( 9200 544 ) N ; + - tapcell.cell9_0 sky130_fd_sc_hd__tap_1 + PLACED ( 10350 0 ) N ; + - tapcell.cell9_1 sky130_fd_sc_hd__tap_1 + PLACED ( 10350 272 ) FS ; + - tapcell.cell9_2 sky130_fd_sc_hd__tap_1 + PLACED ( 10350 544 ) N ; + - word_sel.and_0 sky130_fd_sc_hd__and2_0 + PLACED ( 40434 544 ) N ; + - word_sel.and_1 sky130_fd_sc_hd__and2_0 + PLACED ( 40664 544 ) N ; + - word_sel.and_2 sky130_fd_sc_hd__and2_0 + PLACED ( 40894 544 ) N ; + - word_sel.and_3 sky130_fd_sc_hd__and2_0 + PLACED ( 41124 544 ) N ; + - word_sel.inv_addr_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 41354 544 ) N ; + - word_sel.inv_addr_1 sky130_fd_sc_hd__clkinv_1 + PLACED ( 41492 544 ) N ; +END COMPONENTS +PINS 23 ; + - D[0] + NET D[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 115 791 ) N ; + - D[1] + NET D[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 4715 791 ) N ; + - D[2] + NET D[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 9315 791 ) N ; + - D[3] + NET D[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 13915 791 ) N ; + - D[4] + NET D[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 18423 791 ) N ; + - D[5] + NET D[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 23115 791 ) N ; + - D[6] + NET D[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 27715 791 ) N ; + - D[7] + NET D[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 32315 791 ) N ; + - Q[0] + NET Q[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 2415 791 ) N ; + - Q[1] + NET Q[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 4899 791 ) N ; + - Q[2] + NET Q[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 11707 791 ) N ; + - Q[3] + NET Q[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 16307 791 ) N ; + - Q[4] + NET Q[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 20907 791 ) N ; + - Q[5] + NET Q[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 25415 791 ) N ; + - Q[6] + NET Q[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 30107 791 ) N ; + - Q[7] + NET Q[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -7 -24 ) ( 7 25 ) + + PLACED ( 34707 791 ) N ; + - VDD + NET VDD + SPECIAL + DIRECTION INOUT + USE POWER + + PORT + + LAYER met3 ( -15 -24 ) ( 15 24 ) + + LAYER met3 ( -41753 -24 ) ( -41723 24 ) + + LAYER met2 ( -277 452 ) ( -229 466 ) + + LAYER met2 ( -277 -350 ) ( -229 -336 ) + + LAYER met2 ( -1277 452 ) ( -1229 466 ) + + LAYER met2 ( -1277 -350 ) ( -1229 -336 ) + + LAYER met2 ( -2277 452 ) ( -2229 466 ) + + LAYER met2 ( -2277 -350 ) ( -2229 -336 ) + + LAYER met2 ( -3277 452 ) ( -3229 466 ) + + LAYER met2 ( -3277 -350 ) ( -3229 -336 ) + + LAYER met2 ( -4277 452 ) ( -4229 466 ) + + LAYER met2 ( -4277 -350 ) ( -4229 -336 ) + + LAYER met2 ( -5277 452 ) ( -5229 466 ) + + LAYER met2 ( -5277 -350 ) ( -5229 -336 ) + + LAYER met2 ( -6277 452 ) ( -6229 466 ) + + LAYER met2 ( -6277 -350 ) ( -6229 -336 ) + + LAYER met2 ( -7277 452 ) ( -7229 466 ) + + LAYER met2 ( -7277 -350 ) ( -7229 -336 ) + + LAYER met2 ( -8277 452 ) ( -8229 466 ) + + LAYER met2 ( -8277 -350 ) ( -8229 -336 ) + + LAYER met2 ( -9277 452 ) ( -9229 466 ) + + LAYER met2 ( -9277 -350 ) ( -9229 -336 ) + + LAYER met2 ( -10277 452 ) ( -10229 466 ) + + LAYER met2 ( -10277 -350 ) ( -10229 -336 ) + + LAYER met2 ( -11277 452 ) ( -11229 466 ) + + LAYER met2 ( -11277 -350 ) ( -11229 -336 ) + + LAYER met2 ( -12277 452 ) ( -12229 466 ) + + LAYER met2 ( -12277 -350 ) ( -12229 -336 ) + + LAYER met2 ( -13277 452 ) ( -13229 466 ) + + LAYER met2 ( -13277 -350 ) ( -13229 -336 ) + + LAYER met2 ( -14277 452 ) ( -14229 466 ) + + LAYER met2 ( -14277 -350 ) ( -14229 -336 ) + + LAYER met2 ( -15277 452 ) ( -15229 466 ) + + LAYER met2 ( -15277 -350 ) ( -15229 -336 ) + + LAYER met2 ( -16277 452 ) ( -16229 466 ) + + LAYER met2 ( -16277 -350 ) ( -16229 -336 ) + + LAYER met2 ( -17277 452 ) ( -17229 466 ) + + LAYER met2 ( -17277 -350 ) ( -17229 -336 ) + + LAYER met2 ( -18277 452 ) ( -18229 466 ) + + LAYER met2 ( -18277 -350 ) ( -18229 -336 ) + + LAYER met2 ( -19277 452 ) ( -19229 466 ) + + LAYER met2 ( -19277 -350 ) ( -19229 -336 ) + + LAYER met2 ( -20277 452 ) ( -20229 466 ) + + LAYER met2 ( -20277 -350 ) ( -20229 -336 ) + + LAYER met2 ( -21277 452 ) ( -21229 466 ) + + LAYER met2 ( -21277 -350 ) ( -21229 -336 ) + + LAYER met2 ( -22277 452 ) ( -22229 466 ) + + LAYER met2 ( -22277 -350 ) ( -22229 -336 ) + + LAYER met2 ( -23277 452 ) ( -23229 466 ) + + LAYER met2 ( -23277 -350 ) ( -23229 -336 ) + + LAYER met2 ( -24277 452 ) ( -24229 466 ) + + LAYER met2 ( -24277 -350 ) ( -24229 -336 ) + + LAYER met2 ( -25277 452 ) ( -25229 466 ) + + LAYER met2 ( -25277 -350 ) ( -25229 -336 ) + + LAYER met2 ( -26277 452 ) ( -26229 466 ) + + LAYER met2 ( -26277 -350 ) ( -26229 -336 ) + + LAYER met2 ( -27277 452 ) ( -27229 466 ) + + LAYER met2 ( -27277 -350 ) ( -27229 -336 ) + + LAYER met2 ( -28277 452 ) ( -28229 466 ) + + LAYER met2 ( -28277 -350 ) ( -28229 -336 ) + + LAYER met2 ( -29277 452 ) ( -29229 466 ) + + LAYER met2 ( -29277 -350 ) ( -29229 -336 ) + + LAYER met2 ( -30277 452 ) ( -30229 466 ) + + LAYER met2 ( -30277 -350 ) ( -30229 -336 ) + + LAYER met2 ( -31277 452 ) ( -31229 466 ) + + LAYER met2 ( -31277 -350 ) ( -31229 -336 ) + + LAYER met2 ( -32277 452 ) ( -32229 466 ) + + LAYER met2 ( -32277 -350 ) ( -32229 -336 ) + + LAYER met2 ( -33277 452 ) ( -33229 466 ) + + LAYER met2 ( -33277 -350 ) ( -33229 -336 ) + + LAYER met2 ( -34277 452 ) ( -34229 466 ) + + LAYER met2 ( -34277 -350 ) ( -34229 -336 ) + + LAYER met2 ( -35277 452 ) ( -35229 466 ) + + LAYER met2 ( -35277 -350 ) ( -35229 -336 ) + + LAYER met2 ( -36277 452 ) ( -36229 466 ) + + LAYER met2 ( -36277 -350 ) ( -36229 -336 ) + + LAYER met2 ( -37277 452 ) ( -37229 466 ) + + LAYER met2 ( -37277 -350 ) ( -37229 -336 ) + + LAYER met2 ( -38277 452 ) ( -38229 466 ) + + LAYER met2 ( -38277 -350 ) ( -38229 -336 ) + + LAYER met2 ( -39277 452 ) ( -39229 466 ) + + LAYER met2 ( -39277 -350 ) ( -39229 -336 ) + + LAYER met2 ( -40277 452 ) ( -40229 466 ) + + LAYER met2 ( -40277 -350 ) ( -40229 -336 ) + + LAYER met2 ( -41277 452 ) ( -41229 466 ) + + LAYER met2 ( -41277 -350 ) ( -41229 -336 ) + + LAYER met1 ( 1 442 ) ( 15 490 ) + + LAYER met1 ( -41753 442 ) ( -41739 490 ) + + LAYER met1 ( 1 -102 ) ( 15 -54 ) + + LAYER met1 ( -41753 -102 ) ( -41739 -54 ) + + FIXED ( 41753 350 ) N ; + - VSS + NET VSS + SPECIAL + DIRECTION INOUT + USE GROUND + + PORT + + LAYER met3 ( -15 -24 ) ( 15 24 ) + + LAYER met3 ( -41753 -24 ) ( -41723 24 ) + + LAYER met2 ( -777 102 ) ( -729 116 ) + + LAYER met2 ( -777 -700 ) ( -729 -686 ) + + LAYER met2 ( -1777 102 ) ( -1729 116 ) + + LAYER met2 ( -1777 -700 ) ( -1729 -686 ) + + LAYER met2 ( -2777 102 ) ( -2729 116 ) + + LAYER met2 ( -2777 -700 ) ( -2729 -686 ) + + LAYER met2 ( -3777 102 ) ( -3729 116 ) + + LAYER met2 ( -3777 -700 ) ( -3729 -686 ) + + LAYER met2 ( -4777 102 ) ( -4729 116 ) + + LAYER met2 ( -4777 -700 ) ( -4729 -686 ) + + LAYER met2 ( -5777 102 ) ( -5729 116 ) + + LAYER met2 ( -5777 -700 ) ( -5729 -686 ) + + LAYER met2 ( -6777 102 ) ( -6729 116 ) + + LAYER met2 ( -6777 -700 ) ( -6729 -686 ) + + LAYER met2 ( -7777 102 ) ( -7729 116 ) + + LAYER met2 ( -7777 -700 ) ( -7729 -686 ) + + LAYER met2 ( -8777 102 ) ( -8729 116 ) + + LAYER met2 ( -8777 -700 ) ( -8729 -686 ) + + LAYER met2 ( -9777 102 ) ( -9729 116 ) + + LAYER met2 ( -9777 -700 ) ( -9729 -686 ) + + LAYER met2 ( -10777 102 ) ( -10729 116 ) + + LAYER met2 ( -10777 -700 ) ( -10729 -686 ) + + LAYER met2 ( -11777 102 ) ( -11729 116 ) + + LAYER met2 ( -11777 -700 ) ( -11729 -686 ) + + LAYER met2 ( -12777 102 ) ( -12729 116 ) + + LAYER met2 ( -12777 -700 ) ( -12729 -686 ) + + LAYER met2 ( -13777 102 ) ( -13729 116 ) + + LAYER met2 ( -13777 -700 ) ( -13729 -686 ) + + LAYER met2 ( -14777 102 ) ( -14729 116 ) + + LAYER met2 ( -14777 -700 ) ( -14729 -686 ) + + LAYER met2 ( -15777 102 ) ( -15729 116 ) + + LAYER met2 ( -15777 -700 ) ( -15729 -686 ) + + LAYER met2 ( -16777 102 ) ( -16729 116 ) + + LAYER met2 ( -16777 -700 ) ( -16729 -686 ) + + LAYER met2 ( -17777 102 ) ( -17729 116 ) + + LAYER met2 ( -17777 -700 ) ( -17729 -686 ) + + LAYER met2 ( -18777 102 ) ( -18729 116 ) + + LAYER met2 ( -18777 -700 ) ( -18729 -686 ) + + LAYER met2 ( -19777 102 ) ( -19729 116 ) + + LAYER met2 ( -19777 -700 ) ( -19729 -686 ) + + LAYER met2 ( -20777 102 ) ( -20729 116 ) + + LAYER met2 ( -20777 -700 ) ( -20729 -686 ) + + LAYER met2 ( -21777 102 ) ( -21729 116 ) + + LAYER met2 ( -21777 -700 ) ( -21729 -686 ) + + LAYER met2 ( -22777 102 ) ( -22729 116 ) + + LAYER met2 ( -22777 -700 ) ( -22729 -686 ) + + LAYER met2 ( -23777 102 ) ( -23729 116 ) + + LAYER met2 ( -23777 -700 ) ( -23729 -686 ) + + LAYER met2 ( -24777 102 ) ( -24729 116 ) + + LAYER met2 ( -24777 -700 ) ( -24729 -686 ) + + LAYER met2 ( -25777 102 ) ( -25729 116 ) + + LAYER met2 ( -25777 -700 ) ( -25729 -686 ) + + LAYER met2 ( -26777 102 ) ( -26729 116 ) + + LAYER met2 ( -26777 -700 ) ( -26729 -686 ) + + LAYER met2 ( -27777 102 ) ( -27729 116 ) + + LAYER met2 ( -27777 -700 ) ( -27729 -686 ) + + LAYER met2 ( -28777 102 ) ( -28729 116 ) + + LAYER met2 ( -28777 -700 ) ( -28729 -686 ) + + LAYER met2 ( -29777 102 ) ( -29729 116 ) + + LAYER met2 ( -29777 -700 ) ( -29729 -686 ) + + LAYER met2 ( -30777 102 ) ( -30729 116 ) + + LAYER met2 ( -30777 -700 ) ( -30729 -686 ) + + LAYER met2 ( -31777 102 ) ( -31729 116 ) + + LAYER met2 ( -31777 -700 ) ( -31729 -686 ) + + LAYER met2 ( -32777 102 ) ( -32729 116 ) + + LAYER met2 ( -32777 -700 ) ( -32729 -686 ) + + LAYER met2 ( -33777 102 ) ( -33729 116 ) + + LAYER met2 ( -33777 -700 ) ( -33729 -686 ) + + LAYER met2 ( -34777 102 ) ( -34729 116 ) + + LAYER met2 ( -34777 -700 ) ( -34729 -686 ) + + LAYER met2 ( -35777 102 ) ( -35729 116 ) + + LAYER met2 ( -35777 -700 ) ( -35729 -686 ) + + LAYER met2 ( -36777 102 ) ( -36729 116 ) + + LAYER met2 ( -36777 -700 ) ( -36729 -686 ) + + LAYER met2 ( -37777 102 ) ( -37729 116 ) + + LAYER met2 ( -37777 -700 ) ( -37729 -686 ) + + LAYER met2 ( -38777 102 ) ( -38729 116 ) + + LAYER met2 ( -38777 -700 ) ( -38729 -686 ) + + LAYER met2 ( -39777 102 ) ( -39729 116 ) + + LAYER met2 ( -39777 -700 ) ( -39729 -686 ) + + LAYER met2 ( -40777 102 ) ( -40729 116 ) + + LAYER met2 ( -40777 -700 ) ( -40729 -686 ) + + LAYER met1 ( 1 -180 ) ( 15 -132 ) + + LAYER met1 ( -41753 -180 ) ( -41739 -132 ) + + LAYER met1 ( 1 -724 ) ( 15 -676 ) + + LAYER met1 ( -41753 -724 ) ( -41739 -676 ) + + FIXED ( 41753 700 ) N ; + - addr_rw[0] + NET addr_rw[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 41728 442 ) N ; + - addr_rw[1] + NET addr_rw[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 41728 578 ) N ; + - addr_rw[2] + NET addr_rw[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 41728 34 ) N ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 41728 170 ) N ; + - we[0] + NET we[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -40 -15 ) ( 40 15 ) + + PLACED ( 41728 306 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD ( PIN VDD ) ( tapcell.cell35_2 VPWR ) ( tapcell.cell35_1 VPWR ) ( tapcell.cell35_0 VPWR ) ( tapcell.cell34_2 VPWR ) ( tapcell.cell34_1 VPWR ) ( tapcell.cell34_0 VPWR ) + ( tapcell.cell33_2 VPWR ) ( tapcell.cell33_1 VPWR ) ( tapcell.cell33_0 VPWR ) ( tapcell.cell32_2 VPWR ) ( tapcell.cell32_1 VPWR ) ( tapcell.cell32_0 VPWR ) ( tapcell.cell31_2 VPWR ) ( tapcell.cell31_1 VPWR ) + ( tapcell.cell31_0 VPWR ) ( tapcell.cell30_2 VPWR ) ( tapcell.cell30_1 VPWR ) ( tapcell.cell30_0 VPWR ) ( tapcell.cell29_2 VPWR ) ( tapcell.cell29_1 VPWR ) ( tapcell.cell29_0 VPWR ) ( tapcell.cell28_2 VPWR ) + ( tapcell.cell28_1 VPWR ) ( tapcell.cell28_0 VPWR ) ( tapcell.cell27_2 VPWR ) ( tapcell.cell27_1 VPWR ) ( tapcell.cell27_0 VPWR ) ( tapcell.cell26_2 VPWR ) ( tapcell.cell26_1 VPWR ) ( tapcell.cell26_0 VPWR ) + ( tapcell.cell25_2 VPWR ) ( tapcell.cell25_1 VPWR ) ( tapcell.cell25_0 VPWR ) ( tapcell.cell24_2 VPWR ) ( tapcell.cell24_1 VPWR ) ( tapcell.cell24_0 VPWR ) ( tapcell.cell23_2 VPWR ) ( tapcell.cell23_1 VPWR ) + ( tapcell.cell23_0 VPWR ) ( tapcell.cell22_2 VPWR ) ( tapcell.cell22_1 VPWR ) ( tapcell.cell22_0 VPWR ) ( tapcell.cell21_2 VPWR ) ( tapcell.cell21_1 VPWR ) ( tapcell.cell21_0 VPWR ) ( tapcell.cell20_2 VPWR ) + ( tapcell.cell20_1 VPWR ) ( tapcell.cell20_0 VPWR ) ( tapcell.cell19_2 VPWR ) ( tapcell.cell19_1 VPWR ) ( tapcell.cell19_0 VPWR ) ( tapcell.cell18_2 VPWR ) ( tapcell.cell18_1 VPWR ) ( tapcell.cell18_0 VPWR ) + ( tapcell.cell17_2 VPWR ) ( tapcell.cell17_1 VPWR ) ( tapcell.cell17_0 VPWR ) ( tapcell.cell16_2 VPWR ) ( tapcell.cell16_1 VPWR ) ( tapcell.cell16_0 VPWR ) ( tapcell.cell15_2 VPWR ) ( tapcell.cell15_1 VPWR ) + ( tapcell.cell15_0 VPWR ) ( tapcell.cell14_2 VPWR ) ( tapcell.cell14_1 VPWR ) ( tapcell.cell14_0 VPWR ) ( tapcell.cell13_2 VPWR ) ( tapcell.cell13_1 VPWR ) ( tapcell.cell13_0 VPWR ) ( tapcell.cell12_2 VPWR ) + ( tapcell.cell12_1 VPWR ) ( tapcell.cell12_0 VPWR ) ( tapcell.cell11_2 VPWR ) ( tapcell.cell11_1 VPWR ) ( tapcell.cell11_0 VPWR ) ( tapcell.cell10_2 VPWR ) ( tapcell.cell10_1 VPWR ) ( tapcell.cell10_0 VPWR ) + ( tapcell.cell9_2 VPWR ) ( tapcell.cell9_1 VPWR ) ( tapcell.cell9_0 VPWR ) ( tapcell.cell8_2 VPWR ) ( tapcell.cell8_1 VPWR ) ( tapcell.cell8_0 VPWR ) ( tapcell.cell7_2 VPWR ) ( tapcell.cell7_1 VPWR ) + ( tapcell.cell7_0 VPWR ) ( tapcell.cell6_2 VPWR ) ( tapcell.cell6_1 VPWR ) ( tapcell.cell6_0 VPWR ) ( tapcell.cell5_2 VPWR ) ( tapcell.cell5_1 VPWR ) ( tapcell.cell5_0 VPWR ) ( tapcell.cell4_2 VPWR ) + ( tapcell.cell4_1 VPWR ) ( tapcell.cell4_0 VPWR ) ( tapcell.cell3_2 VPWR ) ( tapcell.cell3_1 VPWR ) ( tapcell.cell3_0 VPWR ) ( tapcell.cell2_2 VPWR ) ( tapcell.cell2_1 VPWR ) ( tapcell.cell2_0 VPWR ) + ( tapcell.cell1_2 VPWR ) ( tapcell.cell1_1 VPWR ) ( tapcell.cell1_0 VPWR ) ( tapcell.cell0_2 VPWR ) ( tapcell.cell0_1 VPWR ) ( tapcell.cell0_0 VPWR ) ( decoder.inv_2 VPWR ) ( buffer.in[7] VPWR ) + ( buffer.in[6] VPWR ) ( buffer.in[5] VPWR ) ( buffer.in[4] VPWR ) ( buffer.in[3] VPWR ) ( buffer.in[2] VPWR ) ( buffer.in[1] VPWR ) ( buffer.in[0] VPWR ) ( mux_slice0_bit7.s2_aoi VPWR ) + ( mux_slice0_bit7.s1_aoi_1 VPWR ) ( mux_slice0_bit7.s1_aoi_0 VPWR ) ( mux_slice0_bit6.s2_aoi VPWR ) ( mux_slice0_bit6.s1_aoi_1 VPWR ) ( mux_slice0_bit6.s1_aoi_0 VPWR ) ( mux_slice0_bit5.s2_aoi VPWR ) ( mux_slice0_bit5.s1_aoi_1 VPWR ) ( mux_slice0_bit5.s1_aoi_0 VPWR ) + ( mux_slice0_bit4.s2_aoi VPWR ) ( mux_slice0_bit4.s1_aoi_1 VPWR ) ( mux_slice0_bit4.s1_aoi_0 VPWR ) ( mux_slice0_bit3.s2_aoi VPWR ) ( mux_slice0_bit3.s1_aoi_1 VPWR ) ( mux_slice0_bit3.s1_aoi_0 VPWR ) ( mux_slice0_bit2.s2_aoi VPWR ) ( mux_slice0_bit2.s1_aoi_1 VPWR ) + ( mux_slice0_bit2.s1_aoi_0 VPWR ) ( mux_slice0_bit1.s2_aoi VPWR ) ( mux_slice0_bit1.s1_aoi_1 VPWR ) ( mux_slice0_bit1.s1_aoi_0 VPWR ) ( mux_slice0_bit0.s2_aoi VPWR ) ( mux_slice0_bit0.s1_aoi_1 VPWR ) ( mux_slice0_bit0.s1_aoi_0 VPWR ) ( storage_1_3_0.gcand VPWR ) + ( storage_1_3_0.word_and VPWR ) ( storage_1_3_0.cg VPWR ) ( storage_1_3_0.bit7.obuf0 VPWR ) ( storage_1_3_0.bit7.bit VPWR ) ( storage_1_3_0.bit6.obuf0 VPWR ) ( storage_1_3_0.bit6.bit VPWR ) ( storage_1_3_0.bit5.obuf0 VPWR ) ( storage_1_3_0.bit5.bit VPWR ) + ( storage_1_3_0.bit4.obuf0 VPWR ) ( storage_1_3_0.bit4.bit VPWR ) ( storage_1_3_0.bit3.obuf0 VPWR ) ( storage_1_3_0.bit3.bit VPWR ) ( storage_1_3_0.bit2.obuf0 VPWR ) ( storage_1_3_0.bit2.bit VPWR ) ( storage_1_3_0.bit1.obuf0 VPWR ) ( storage_1_3_0.bit1.bit VPWR ) + ( storage_1_3_0.bit0.obuf0 VPWR ) ( storage_1_3_0.bit0.bit VPWR ) ( storage_1_2_0.gcand VPWR ) ( storage_1_2_0.word_and VPWR ) ( storage_1_2_0.cg VPWR ) ( storage_1_2_0.bit7.obuf0 VPWR ) ( storage_1_2_0.bit7.bit VPWR ) ( storage_1_2_0.bit6.obuf0 VPWR ) + ( storage_1_2_0.bit6.bit VPWR ) ( storage_1_2_0.bit5.obuf0 VPWR ) ( storage_1_2_0.bit5.bit VPWR ) ( storage_1_2_0.bit4.obuf0 VPWR ) ( storage_1_2_0.bit4.bit VPWR ) ( storage_1_2_0.bit3.obuf0 VPWR ) ( storage_1_2_0.bit3.bit VPWR ) ( storage_1_2_0.bit2.obuf0 VPWR ) + ( storage_1_2_0.bit2.bit VPWR ) ( storage_1_2_0.bit1.obuf0 VPWR ) ( storage_1_2_0.bit1.bit VPWR ) ( storage_1_2_0.bit0.obuf0 VPWR ) ( storage_1_2_0.bit0.bit VPWR ) ( storage_1_1_0.gcand VPWR ) ( storage_1_1_0.word_and VPWR ) ( storage_1_1_0.cg VPWR ) + ( storage_1_1_0.bit7.obuf0 VPWR ) ( storage_1_1_0.bit7.bit VPWR ) ( storage_1_1_0.bit6.obuf0 VPWR ) ( storage_1_1_0.bit6.bit VPWR ) ( storage_1_1_0.bit5.obuf0 VPWR ) ( storage_1_1_0.bit5.bit VPWR ) ( storage_1_1_0.bit4.obuf0 VPWR ) ( storage_1_1_0.bit4.bit VPWR ) + ( storage_1_1_0.bit3.obuf0 VPWR ) ( storage_1_1_0.bit3.bit VPWR ) ( storage_1_1_0.bit2.obuf0 VPWR ) ( storage_1_1_0.bit2.bit VPWR ) ( storage_1_1_0.bit1.obuf0 VPWR ) ( storage_1_1_0.bit1.bit VPWR ) ( storage_1_1_0.bit0.obuf0 VPWR ) ( storage_1_1_0.bit0.bit VPWR ) + ( storage_1_0_0.select_inv_0 VPWR ) ( storage_1_0_0.gcand VPWR ) ( storage_1_0_0.word_and VPWR ) ( storage_1_0_0.cg VPWR ) ( storage_1_0_0.bit7.obuf0 VPWR ) ( storage_1_0_0.bit7.bit VPWR ) ( storage_1_0_0.bit6.obuf0 VPWR ) ( storage_1_0_0.bit6.bit VPWR ) + ( storage_1_0_0.bit5.obuf0 VPWR ) ( storage_1_0_0.bit5.bit VPWR ) ( storage_1_0_0.bit4.obuf0 VPWR ) ( storage_1_0_0.bit4.bit VPWR ) ( storage_1_0_0.bit3.obuf0 VPWR ) ( storage_1_0_0.bit3.bit VPWR ) ( storage_1_0_0.bit2.obuf0 VPWR ) ( storage_1_0_0.bit2.bit VPWR ) + ( storage_1_0_0.bit1.obuf0 VPWR ) ( storage_1_0_0.bit1.bit VPWR ) ( storage_1_0_0.bit0.obuf0 VPWR ) ( storage_1_0_0.bit0.bit VPWR ) ( storage_0_3_0.gcand VPWR ) ( storage_0_3_0.word_and VPWR ) ( storage_0_3_0.cg VPWR ) ( storage_0_3_0.bit7.obuf0 VPWR ) + ( storage_0_3_0.bit7.bit VPWR ) ( storage_0_3_0.bit6.obuf0 VPWR ) ( storage_0_3_0.bit6.bit VPWR ) ( storage_0_3_0.bit5.obuf0 VPWR ) ( storage_0_3_0.bit5.bit VPWR ) ( storage_0_3_0.bit4.obuf0 VPWR ) ( storage_0_3_0.bit4.bit VPWR ) ( storage_0_3_0.bit3.obuf0 VPWR ) + ( storage_0_3_0.bit3.bit VPWR ) ( storage_0_3_0.bit2.obuf0 VPWR ) ( storage_0_3_0.bit2.bit VPWR ) ( storage_0_3_0.bit1.obuf0 VPWR ) ( storage_0_3_0.bit1.bit VPWR ) ( storage_0_3_0.bit0.obuf0 VPWR ) ( storage_0_3_0.bit0.bit VPWR ) ( storage_0_2_0.gcand VPWR ) + ( storage_0_2_0.word_and VPWR ) ( storage_0_2_0.cg VPWR ) ( storage_0_2_0.bit7.obuf0 VPWR ) ( storage_0_2_0.bit7.bit VPWR ) ( storage_0_2_0.bit6.obuf0 VPWR ) ( storage_0_2_0.bit6.bit VPWR ) ( storage_0_2_0.bit5.obuf0 VPWR ) ( storage_0_2_0.bit5.bit VPWR ) + ( storage_0_2_0.bit4.obuf0 VPWR ) ( storage_0_2_0.bit4.bit VPWR ) ( storage_0_2_0.bit3.obuf0 VPWR ) ( storage_0_2_0.bit3.bit VPWR ) ( storage_0_2_0.bit2.obuf0 VPWR ) ( storage_0_2_0.bit2.bit VPWR ) ( storage_0_2_0.bit1.obuf0 VPWR ) ( storage_0_2_0.bit1.bit VPWR ) + ( storage_0_2_0.bit0.obuf0 VPWR ) ( storage_0_2_0.bit0.bit VPWR ) ( storage_0_1_0.gcand VPWR ) ( storage_0_1_0.word_and VPWR ) ( storage_0_1_0.cg VPWR ) ( storage_0_1_0.bit7.obuf0 VPWR ) ( storage_0_1_0.bit7.bit VPWR ) ( storage_0_1_0.bit6.obuf0 VPWR ) + ( storage_0_1_0.bit6.bit VPWR ) ( storage_0_1_0.bit5.obuf0 VPWR ) ( storage_0_1_0.bit5.bit VPWR ) ( storage_0_1_0.bit4.obuf0 VPWR ) ( storage_0_1_0.bit4.bit VPWR ) ( storage_0_1_0.bit3.obuf0 VPWR ) ( storage_0_1_0.bit3.bit VPWR ) ( storage_0_1_0.bit2.obuf0 VPWR ) + ( storage_0_1_0.bit2.bit VPWR ) ( storage_0_1_0.bit1.obuf0 VPWR ) ( storage_0_1_0.bit1.bit VPWR ) ( storage_0_1_0.bit0.obuf0 VPWR ) ( storage_0_1_0.bit0.bit VPWR ) ( storage_0_0_0.select_inv_0 VPWR ) ( storage_0_0_0.gcand VPWR ) ( storage_0_0_0.word_and VPWR ) + ( storage_0_0_0.cg VPWR ) ( storage_0_0_0.bit7.obuf0 VPWR ) ( storage_0_0_0.bit7.bit VPWR ) ( storage_0_0_0.bit6.obuf0 VPWR ) ( storage_0_0_0.bit6.bit VPWR ) ( storage_0_0_0.bit5.obuf0 VPWR ) ( storage_0_0_0.bit5.bit VPWR ) ( storage_0_0_0.bit4.obuf0 VPWR ) + ( storage_0_0_0.bit4.bit VPWR ) ( storage_0_0_0.bit3.obuf0 VPWR ) ( storage_0_0_0.bit3.bit VPWR ) ( storage_0_0_0.bit2.obuf0 VPWR ) ( storage_0_0_0.bit2.bit VPWR ) ( storage_0_0_0.bit1.obuf0 VPWR ) ( storage_0_0_0.bit1.bit VPWR ) ( storage_0_0_0.bit0.obuf0 VPWR ) + ( storage_0_0_0.bit0.bit VPWR ) ( word_sel.inv_addr_1 VPWR ) ( word_sel.inv_addr_0 VPWR ) ( word_sel.and_3 VPWR ) ( word_sel.and_2 VPWR ) ( word_sel.and_1 VPWR ) ( word_sel.and_0 VPWR ) + USE POWER + + ROUTED met3 48 + SHAPE STRIPE ( 0 350 ) ( 41768 350 ) + NEW met2 48 + SHAPE STRIPE ( 41500 0 ) ( 41500 840 ) + NEW met2 48 + SHAPE STRIPE ( 40500 0 ) ( 40500 840 ) + NEW met2 48 + SHAPE STRIPE ( 39500 0 ) ( 39500 840 ) + NEW met2 48 + SHAPE STRIPE ( 38500 0 ) ( 38500 840 ) + NEW met2 48 + SHAPE STRIPE ( 37500 0 ) ( 37500 840 ) + NEW met2 48 + SHAPE STRIPE ( 36500 0 ) ( 36500 840 ) + NEW met2 48 + SHAPE STRIPE ( 35500 0 ) ( 35500 840 ) + NEW met2 48 + SHAPE STRIPE ( 34500 0 ) ( 34500 840 ) + NEW met2 48 + SHAPE STRIPE ( 33500 0 ) ( 33500 840 ) + NEW met2 48 + SHAPE STRIPE ( 32500 0 ) ( 32500 840 ) + NEW met2 48 + SHAPE STRIPE ( 31500 0 ) ( 31500 840 ) + NEW met2 48 + SHAPE STRIPE ( 30500 0 ) ( 30500 840 ) + NEW met2 48 + SHAPE STRIPE ( 29500 0 ) ( 29500 840 ) + NEW met2 48 + SHAPE STRIPE ( 28500 0 ) ( 28500 840 ) + NEW met2 48 + SHAPE STRIPE ( 27500 0 ) ( 27500 840 ) + NEW met2 48 + SHAPE STRIPE ( 26500 0 ) ( 26500 840 ) + NEW met2 48 + SHAPE STRIPE ( 25500 0 ) ( 25500 840 ) + NEW met2 48 + SHAPE STRIPE ( 24500 0 ) ( 24500 840 ) + NEW met2 48 + SHAPE STRIPE ( 23500 0 ) ( 23500 840 ) + NEW met2 48 + SHAPE STRIPE ( 22500 0 ) ( 22500 840 ) + NEW met2 48 + SHAPE STRIPE ( 21500 0 ) ( 21500 840 ) + NEW met2 48 + SHAPE STRIPE ( 20500 0 ) ( 20500 840 ) + NEW met2 48 + SHAPE STRIPE ( 19500 0 ) ( 19500 840 ) + NEW met2 48 + SHAPE STRIPE ( 18500 0 ) ( 18500 840 ) + NEW met2 48 + SHAPE STRIPE ( 17500 0 ) ( 17500 840 ) + NEW met2 48 + SHAPE STRIPE ( 16500 0 ) ( 16500 840 ) + NEW met2 48 + SHAPE STRIPE ( 15500 0 ) ( 15500 840 ) + NEW met2 48 + SHAPE STRIPE ( 14500 0 ) ( 14500 840 ) + NEW met2 48 + SHAPE STRIPE ( 13500 0 ) ( 13500 840 ) + NEW met2 48 + SHAPE STRIPE ( 12500 0 ) ( 12500 840 ) + NEW met2 48 + SHAPE STRIPE ( 11500 0 ) ( 11500 840 ) + NEW met2 48 + SHAPE STRIPE ( 10500 0 ) ( 10500 840 ) + NEW met2 48 + SHAPE STRIPE ( 9500 0 ) ( 9500 840 ) + NEW met2 48 + SHAPE STRIPE ( 8500 0 ) ( 8500 840 ) + NEW met2 48 + SHAPE STRIPE ( 7500 0 ) ( 7500 840 ) + NEW met2 48 + SHAPE STRIPE ( 6500 0 ) ( 6500 840 ) + NEW met2 48 + SHAPE STRIPE ( 5500 0 ) ( 5500 840 ) + NEW met2 48 + SHAPE STRIPE ( 4500 0 ) ( 4500 840 ) + NEW met2 48 + SHAPE STRIPE ( 3500 0 ) ( 3500 840 ) + NEW met2 48 + SHAPE STRIPE ( 2500 0 ) ( 2500 840 ) + NEW met2 48 + SHAPE STRIPE ( 1500 0 ) ( 1500 840 ) + NEW met2 48 + SHAPE STRIPE ( 500 0 ) ( 500 840 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 816 ) ( 41768 816 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 272 ) ( 41768 272 ) + NEW met2 0 + SHAPE STRIPE ( 41500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 40500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 39500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 38500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 37500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 36500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 35500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 34500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 33500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 32500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 31500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 30500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 29500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 28500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 27500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 26500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 25500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 24500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 23500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 22500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 21500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 20500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 19500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 18500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 17500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 16500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 15500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 14500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 13500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 12500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 11500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 10500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 9500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 8500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 7500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 6500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 5500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 4500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 3500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 2500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 1500 350 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 500 350 ) via3_4_480_480_1_1_400_400 + NEW met1 0 + SHAPE STRIPE ( 41500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 41500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 40500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 40500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 39500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 39500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 38500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 38500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 37500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 37500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 36500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 36500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 35500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 35500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 34500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 34500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 33500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 33500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 32500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 32500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 31500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 31500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 30500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 30500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 29500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 29500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 28500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 28500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 27500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 27500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 26500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 26500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 25500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 25500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 24500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 24500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 23500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 23500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 22500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 22500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 21500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 21500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 20500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 20500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 19500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 19500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 18500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 18500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 17500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 17500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 16500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 16500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 15500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 15500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 14500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 14500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 13500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 13500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 12500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 12500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 11500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 11500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 9500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 9500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 7500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 7500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 5500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 5500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 3500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 3500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 1500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 1500 272 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 500 816 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 500 272 ) via2_3_480_480_1_1_320_320 ; + - VSS ( PIN VSS ) ( tapcell.cell35_2 VGND ) ( tapcell.cell35_1 VGND ) ( tapcell.cell35_0 VGND ) ( tapcell.cell34_2 VGND ) ( tapcell.cell34_1 VGND ) ( tapcell.cell34_0 VGND ) + ( tapcell.cell33_2 VGND ) ( tapcell.cell33_1 VGND ) ( tapcell.cell33_0 VGND ) ( tapcell.cell32_2 VGND ) ( tapcell.cell32_1 VGND ) ( tapcell.cell32_0 VGND ) ( tapcell.cell31_2 VGND ) ( tapcell.cell31_1 VGND ) + ( tapcell.cell31_0 VGND ) ( tapcell.cell30_2 VGND ) ( tapcell.cell30_1 VGND ) ( tapcell.cell30_0 VGND ) ( tapcell.cell29_2 VGND ) ( tapcell.cell29_1 VGND ) ( tapcell.cell29_0 VGND ) ( tapcell.cell28_2 VGND ) + ( tapcell.cell28_1 VGND ) ( tapcell.cell28_0 VGND ) ( tapcell.cell27_2 VGND ) ( tapcell.cell27_1 VGND ) ( tapcell.cell27_0 VGND ) ( tapcell.cell26_2 VGND ) ( tapcell.cell26_1 VGND ) ( tapcell.cell26_0 VGND ) + ( tapcell.cell25_2 VGND ) ( tapcell.cell25_1 VGND ) ( tapcell.cell25_0 VGND ) ( tapcell.cell24_2 VGND ) ( tapcell.cell24_1 VGND ) ( tapcell.cell24_0 VGND ) ( tapcell.cell23_2 VGND ) ( tapcell.cell23_1 VGND ) + ( tapcell.cell23_0 VGND ) ( tapcell.cell22_2 VGND ) ( tapcell.cell22_1 VGND ) ( tapcell.cell22_0 VGND ) ( tapcell.cell21_2 VGND ) ( tapcell.cell21_1 VGND ) ( tapcell.cell21_0 VGND ) ( tapcell.cell20_2 VGND ) + ( tapcell.cell20_1 VGND ) ( tapcell.cell20_0 VGND ) ( tapcell.cell19_2 VGND ) ( tapcell.cell19_1 VGND ) ( tapcell.cell19_0 VGND ) ( tapcell.cell18_2 VGND ) ( tapcell.cell18_1 VGND ) ( tapcell.cell18_0 VGND ) + ( tapcell.cell17_2 VGND ) ( tapcell.cell17_1 VGND ) ( tapcell.cell17_0 VGND ) ( tapcell.cell16_2 VGND ) ( tapcell.cell16_1 VGND ) ( tapcell.cell16_0 VGND ) ( tapcell.cell15_2 VGND ) ( tapcell.cell15_1 VGND ) + ( tapcell.cell15_0 VGND ) ( tapcell.cell14_2 VGND ) ( tapcell.cell14_1 VGND ) ( tapcell.cell14_0 VGND ) ( tapcell.cell13_2 VGND ) ( tapcell.cell13_1 VGND ) ( tapcell.cell13_0 VGND ) ( tapcell.cell12_2 VGND ) + ( tapcell.cell12_1 VGND ) ( tapcell.cell12_0 VGND ) ( tapcell.cell11_2 VGND ) ( tapcell.cell11_1 VGND ) ( tapcell.cell11_0 VGND ) ( tapcell.cell10_2 VGND ) ( tapcell.cell10_1 VGND ) ( tapcell.cell10_0 VGND ) + ( tapcell.cell9_2 VGND ) ( tapcell.cell9_1 VGND ) ( tapcell.cell9_0 VGND ) ( tapcell.cell8_2 VGND ) ( tapcell.cell8_1 VGND ) ( tapcell.cell8_0 VGND ) ( tapcell.cell7_2 VGND ) ( tapcell.cell7_1 VGND ) + ( tapcell.cell7_0 VGND ) ( tapcell.cell6_2 VGND ) ( tapcell.cell6_1 VGND ) ( tapcell.cell6_0 VGND ) ( tapcell.cell5_2 VGND ) ( tapcell.cell5_1 VGND ) ( tapcell.cell5_0 VGND ) ( tapcell.cell4_2 VGND ) + ( tapcell.cell4_1 VGND ) ( tapcell.cell4_0 VGND ) ( tapcell.cell3_2 VGND ) ( tapcell.cell3_1 VGND ) ( tapcell.cell3_0 VGND ) ( tapcell.cell2_2 VGND ) ( tapcell.cell2_1 VGND ) ( tapcell.cell2_0 VGND ) + ( tapcell.cell1_2 VGND ) ( tapcell.cell1_1 VGND ) ( tapcell.cell1_0 VGND ) ( tapcell.cell0_2 VGND ) ( tapcell.cell0_1 VGND ) ( tapcell.cell0_0 VGND ) ( decoder.inv_2 VGND ) ( buffer.in[7] VGND ) + ( buffer.in[6] VGND ) ( buffer.in[5] VGND ) ( buffer.in[4] VGND ) ( buffer.in[3] VGND ) ( buffer.in[2] VGND ) ( buffer.in[1] VGND ) ( buffer.in[0] VGND ) ( mux_slice0_bit7.s2_aoi VGND ) + ( mux_slice0_bit7.s1_aoi_1 VGND ) ( mux_slice0_bit7.s1_aoi_0 VGND ) ( mux_slice0_bit6.s2_aoi VGND ) ( mux_slice0_bit6.s1_aoi_1 VGND ) ( mux_slice0_bit6.s1_aoi_0 VGND ) ( mux_slice0_bit5.s2_aoi VGND ) ( mux_slice0_bit5.s1_aoi_1 VGND ) ( mux_slice0_bit5.s1_aoi_0 VGND ) + ( mux_slice0_bit4.s2_aoi VGND ) ( mux_slice0_bit4.s1_aoi_1 VGND ) ( mux_slice0_bit4.s1_aoi_0 VGND ) ( mux_slice0_bit3.s2_aoi VGND ) ( mux_slice0_bit3.s1_aoi_1 VGND ) ( mux_slice0_bit3.s1_aoi_0 VGND ) ( mux_slice0_bit2.s2_aoi VGND ) ( mux_slice0_bit2.s1_aoi_1 VGND ) + ( mux_slice0_bit2.s1_aoi_0 VGND ) ( mux_slice0_bit1.s2_aoi VGND ) ( mux_slice0_bit1.s1_aoi_1 VGND ) ( mux_slice0_bit1.s1_aoi_0 VGND ) ( mux_slice0_bit0.s2_aoi VGND ) ( mux_slice0_bit0.s1_aoi_1 VGND ) ( mux_slice0_bit0.s1_aoi_0 VGND ) ( storage_1_3_0.gcand VGND ) + ( storage_1_3_0.word_and VGND ) ( storage_1_3_0.cg VGND ) ( storage_1_3_0.bit7.obuf0 VGND ) ( storage_1_3_0.bit7.bit VGND ) ( storage_1_3_0.bit6.obuf0 VGND ) ( storage_1_3_0.bit6.bit VGND ) ( storage_1_3_0.bit5.obuf0 VGND ) ( storage_1_3_0.bit5.bit VGND ) + ( storage_1_3_0.bit4.obuf0 VGND ) ( storage_1_3_0.bit4.bit VGND ) ( storage_1_3_0.bit3.obuf0 VGND ) ( storage_1_3_0.bit3.bit VGND ) ( storage_1_3_0.bit2.obuf0 VGND ) ( storage_1_3_0.bit2.bit VGND ) ( storage_1_3_0.bit1.obuf0 VGND ) ( storage_1_3_0.bit1.bit VGND ) + ( storage_1_3_0.bit0.obuf0 VGND ) ( storage_1_3_0.bit0.bit VGND ) ( storage_1_2_0.gcand VGND ) ( storage_1_2_0.word_and VGND ) ( storage_1_2_0.cg VGND ) ( storage_1_2_0.bit7.obuf0 VGND ) ( storage_1_2_0.bit7.bit VGND ) ( storage_1_2_0.bit6.obuf0 VGND ) + ( storage_1_2_0.bit6.bit VGND ) ( storage_1_2_0.bit5.obuf0 VGND ) ( storage_1_2_0.bit5.bit VGND ) ( storage_1_2_0.bit4.obuf0 VGND ) ( storage_1_2_0.bit4.bit VGND ) ( storage_1_2_0.bit3.obuf0 VGND ) ( storage_1_2_0.bit3.bit VGND ) ( storage_1_2_0.bit2.obuf0 VGND ) + ( storage_1_2_0.bit2.bit VGND ) ( storage_1_2_0.bit1.obuf0 VGND ) ( storage_1_2_0.bit1.bit VGND ) ( storage_1_2_0.bit0.obuf0 VGND ) ( storage_1_2_0.bit0.bit VGND ) ( storage_1_1_0.gcand VGND ) ( storage_1_1_0.word_and VGND ) ( storage_1_1_0.cg VGND ) + ( storage_1_1_0.bit7.obuf0 VGND ) ( storage_1_1_0.bit7.bit VGND ) ( storage_1_1_0.bit6.obuf0 VGND ) ( storage_1_1_0.bit6.bit VGND ) ( storage_1_1_0.bit5.obuf0 VGND ) ( storage_1_1_0.bit5.bit VGND ) ( storage_1_1_0.bit4.obuf0 VGND ) ( storage_1_1_0.bit4.bit VGND ) + ( storage_1_1_0.bit3.obuf0 VGND ) ( storage_1_1_0.bit3.bit VGND ) ( storage_1_1_0.bit2.obuf0 VGND ) ( storage_1_1_0.bit2.bit VGND ) ( storage_1_1_0.bit1.obuf0 VGND ) ( storage_1_1_0.bit1.bit VGND ) ( storage_1_1_0.bit0.obuf0 VGND ) ( storage_1_1_0.bit0.bit VGND ) + ( storage_1_0_0.select_inv_0 VGND ) ( storage_1_0_0.gcand VGND ) ( storage_1_0_0.word_and VGND ) ( storage_1_0_0.cg VGND ) ( storage_1_0_0.bit7.obuf0 VGND ) ( storage_1_0_0.bit7.bit VGND ) ( storage_1_0_0.bit6.obuf0 VGND ) ( storage_1_0_0.bit6.bit VGND ) + ( storage_1_0_0.bit5.obuf0 VGND ) ( storage_1_0_0.bit5.bit VGND ) ( storage_1_0_0.bit4.obuf0 VGND ) ( storage_1_0_0.bit4.bit VGND ) ( storage_1_0_0.bit3.obuf0 VGND ) ( storage_1_0_0.bit3.bit VGND ) ( storage_1_0_0.bit2.obuf0 VGND ) ( storage_1_0_0.bit2.bit VGND ) + ( storage_1_0_0.bit1.obuf0 VGND ) ( storage_1_0_0.bit1.bit VGND ) ( storage_1_0_0.bit0.obuf0 VGND ) ( storage_1_0_0.bit0.bit VGND ) ( storage_0_3_0.gcand VGND ) ( storage_0_3_0.word_and VGND ) ( storage_0_3_0.cg VGND ) ( storage_0_3_0.bit7.obuf0 VGND ) + ( storage_0_3_0.bit7.bit VGND ) ( storage_0_3_0.bit6.obuf0 VGND ) ( storage_0_3_0.bit6.bit VGND ) ( storage_0_3_0.bit5.obuf0 VGND ) ( storage_0_3_0.bit5.bit VGND ) ( storage_0_3_0.bit4.obuf0 VGND ) ( storage_0_3_0.bit4.bit VGND ) ( storage_0_3_0.bit3.obuf0 VGND ) + ( storage_0_3_0.bit3.bit VGND ) ( storage_0_3_0.bit2.obuf0 VGND ) ( storage_0_3_0.bit2.bit VGND ) ( storage_0_3_0.bit1.obuf0 VGND ) ( storage_0_3_0.bit1.bit VGND ) ( storage_0_3_0.bit0.obuf0 VGND ) ( storage_0_3_0.bit0.bit VGND ) ( storage_0_2_0.gcand VGND ) + ( storage_0_2_0.word_and VGND ) ( storage_0_2_0.cg VGND ) ( storage_0_2_0.bit7.obuf0 VGND ) ( storage_0_2_0.bit7.bit VGND ) ( storage_0_2_0.bit6.obuf0 VGND ) ( storage_0_2_0.bit6.bit VGND ) ( storage_0_2_0.bit5.obuf0 VGND ) ( storage_0_2_0.bit5.bit VGND ) + ( storage_0_2_0.bit4.obuf0 VGND ) ( storage_0_2_0.bit4.bit VGND ) ( storage_0_2_0.bit3.obuf0 VGND ) ( storage_0_2_0.bit3.bit VGND ) ( storage_0_2_0.bit2.obuf0 VGND ) ( storage_0_2_0.bit2.bit VGND ) ( storage_0_2_0.bit1.obuf0 VGND ) ( storage_0_2_0.bit1.bit VGND ) + ( storage_0_2_0.bit0.obuf0 VGND ) ( storage_0_2_0.bit0.bit VGND ) ( storage_0_1_0.gcand VGND ) ( storage_0_1_0.word_and VGND ) ( storage_0_1_0.cg VGND ) ( storage_0_1_0.bit7.obuf0 VGND ) ( storage_0_1_0.bit7.bit VGND ) ( storage_0_1_0.bit6.obuf0 VGND ) + ( storage_0_1_0.bit6.bit VGND ) ( storage_0_1_0.bit5.obuf0 VGND ) ( storage_0_1_0.bit5.bit VGND ) ( storage_0_1_0.bit4.obuf0 VGND ) ( storage_0_1_0.bit4.bit VGND ) ( storage_0_1_0.bit3.obuf0 VGND ) ( storage_0_1_0.bit3.bit VGND ) ( storage_0_1_0.bit2.obuf0 VGND ) + ( storage_0_1_0.bit2.bit VGND ) ( storage_0_1_0.bit1.obuf0 VGND ) ( storage_0_1_0.bit1.bit VGND ) ( storage_0_1_0.bit0.obuf0 VGND ) ( storage_0_1_0.bit0.bit VGND ) ( storage_0_0_0.select_inv_0 VGND ) ( storage_0_0_0.gcand VGND ) ( storage_0_0_0.word_and VGND ) + ( storage_0_0_0.cg VGND ) ( storage_0_0_0.bit7.obuf0 VGND ) ( storage_0_0_0.bit7.bit VGND ) ( storage_0_0_0.bit6.obuf0 VGND ) ( storage_0_0_0.bit6.bit VGND ) ( storage_0_0_0.bit5.obuf0 VGND ) ( storage_0_0_0.bit5.bit VGND ) ( storage_0_0_0.bit4.obuf0 VGND ) + ( storage_0_0_0.bit4.bit VGND ) ( storage_0_0_0.bit3.obuf0 VGND ) ( storage_0_0_0.bit3.bit VGND ) ( storage_0_0_0.bit2.obuf0 VGND ) ( storage_0_0_0.bit2.bit VGND ) ( storage_0_0_0.bit1.obuf0 VGND ) ( storage_0_0_0.bit1.bit VGND ) ( storage_0_0_0.bit0.obuf0 VGND ) + ( storage_0_0_0.bit0.bit VGND ) ( word_sel.inv_addr_1 VGND ) ( word_sel.inv_addr_0 VGND ) ( word_sel.and_3 VGND ) ( word_sel.and_2 VGND ) ( word_sel.and_1 VGND ) ( word_sel.and_0 VGND ) + USE GROUND + + ROUTED met3 48 + SHAPE STRIPE ( 0 700 ) ( 41768 700 ) + NEW met2 48 + SHAPE STRIPE ( 41000 -24 ) ( 41000 816 ) + NEW met2 48 + SHAPE STRIPE ( 40000 -24 ) ( 40000 816 ) + NEW met2 48 + SHAPE STRIPE ( 39000 -24 ) ( 39000 816 ) + NEW met2 48 + SHAPE STRIPE ( 38000 -24 ) ( 38000 816 ) + NEW met2 48 + SHAPE STRIPE ( 37000 -24 ) ( 37000 816 ) + NEW met2 48 + SHAPE STRIPE ( 36000 -24 ) ( 36000 816 ) + NEW met2 48 + SHAPE STRIPE ( 35000 -24 ) ( 35000 816 ) + NEW met2 48 + SHAPE STRIPE ( 34000 -24 ) ( 34000 816 ) + NEW met2 48 + SHAPE STRIPE ( 33000 -24 ) ( 33000 816 ) + NEW met2 48 + SHAPE STRIPE ( 32000 -24 ) ( 32000 816 ) + NEW met2 48 + SHAPE STRIPE ( 31000 -24 ) ( 31000 816 ) + NEW met2 48 + SHAPE STRIPE ( 30000 -24 ) ( 30000 816 ) + NEW met2 48 + SHAPE STRIPE ( 29000 -24 ) ( 29000 816 ) + NEW met2 48 + SHAPE STRIPE ( 28000 -24 ) ( 28000 816 ) + NEW met2 48 + SHAPE STRIPE ( 27000 -24 ) ( 27000 816 ) + NEW met2 48 + SHAPE STRIPE ( 26000 -24 ) ( 26000 816 ) + NEW met2 48 + SHAPE STRIPE ( 25000 -24 ) ( 25000 816 ) + NEW met2 48 + SHAPE STRIPE ( 24000 -24 ) ( 24000 816 ) + NEW met2 48 + SHAPE STRIPE ( 23000 -24 ) ( 23000 816 ) + NEW met2 48 + SHAPE STRIPE ( 22000 -24 ) ( 22000 816 ) + NEW met2 48 + SHAPE STRIPE ( 21000 -24 ) ( 21000 816 ) + NEW met2 48 + SHAPE STRIPE ( 20000 -24 ) ( 20000 816 ) + NEW met2 48 + SHAPE STRIPE ( 19000 -24 ) ( 19000 816 ) + NEW met2 48 + SHAPE STRIPE ( 18000 -24 ) ( 18000 816 ) + NEW met2 48 + SHAPE STRIPE ( 17000 -24 ) ( 17000 816 ) + NEW met2 48 + SHAPE STRIPE ( 16000 -24 ) ( 16000 816 ) + NEW met2 48 + SHAPE STRIPE ( 15000 -24 ) ( 15000 816 ) + NEW met2 48 + SHAPE STRIPE ( 14000 -24 ) ( 14000 816 ) + NEW met2 48 + SHAPE STRIPE ( 13000 -24 ) ( 13000 816 ) + NEW met2 48 + SHAPE STRIPE ( 12000 -24 ) ( 12000 816 ) + NEW met2 48 + SHAPE STRIPE ( 11000 -24 ) ( 11000 816 ) + NEW met2 48 + SHAPE STRIPE ( 10000 -24 ) ( 10000 816 ) + NEW met2 48 + SHAPE STRIPE ( 9000 -24 ) ( 9000 816 ) + NEW met2 48 + SHAPE STRIPE ( 8000 -24 ) ( 8000 816 ) + NEW met2 48 + SHAPE STRIPE ( 7000 -24 ) ( 7000 816 ) + NEW met2 48 + SHAPE STRIPE ( 6000 -24 ) ( 6000 816 ) + NEW met2 48 + SHAPE STRIPE ( 5000 -24 ) ( 5000 816 ) + NEW met2 48 + SHAPE STRIPE ( 4000 -24 ) ( 4000 816 ) + NEW met2 48 + SHAPE STRIPE ( 3000 -24 ) ( 3000 816 ) + NEW met2 48 + SHAPE STRIPE ( 2000 -24 ) ( 2000 816 ) + NEW met2 48 + SHAPE STRIPE ( 1000 -24 ) ( 1000 816 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 544 ) ( 41768 544 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 0 ) ( 41768 0 ) + NEW met2 0 + SHAPE STRIPE ( 41000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 40000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 39000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 38000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 37000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 36000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 35000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 34000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 33000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 32000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 31000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 30000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 29000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 28000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 27000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 26000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 25000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 24000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 23000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 22000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 21000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 20000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 19000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 18000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 17000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 16000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 15000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 14000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 13000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 12000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 11000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 10000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 9000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 8000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 7000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 6000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 5000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 4000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 3000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 2000 700 ) via3_4_480_480_1_1_400_400 + NEW met2 0 + SHAPE STRIPE ( 1000 700 ) via3_4_480_480_1_1_400_400 + NEW met1 0 + SHAPE STRIPE ( 41000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 41000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 40000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 40000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 39000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 39000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 38000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 38000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 37000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 37000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 36000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 36000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 35000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 35000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 34000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 34000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 33000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 33000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 32000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 32000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 31000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 31000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 30000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 30000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 29000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 29000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 28000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 28000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 27000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 27000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 26000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 26000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 25000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 25000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 24000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 24000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 23000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 23000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 22000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 22000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 21000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 21000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 20000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 20000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 19000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 19000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 18000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 18000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 17000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 17000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 16000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 16000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 15000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 15000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 14000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 14000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 13000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 13000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 12000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 12000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 11000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 11000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 10000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 9000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 9000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 8000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 7000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 7000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 6000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 5000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 5000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 4000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 3000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 3000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 2000 0 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 1000 544 ) via2_3_480_480_1_1_320_320 + NEW met1 0 + SHAPE STRIPE ( 1000 0 ) via2_3_480_480_1_1_320_320 ; +END SPECIALNETS +NETS 174 ; + - D[0] ( PIN D[0] ) ( buffer.in[0] A ) + USE SIGNAL + + ROUTED met2 ( 115 663 ) ( * 782 0 ) + NEW met1 ( 69 663 ) ( 115 * ) + NEW met1 ( 115 663 ) M1M2_PR + NEW li1 ( 69 663 ) L1M1_PR_MR ; + - D[1] ( PIN D[1] ) ( buffer.in[1] A ) + USE SIGNAL + + ROUTED met2 ( 4715 663 ) ( * 782 0 ) + NEW met1 ( 4669 663 ) ( 4715 * ) + NEW met1 ( 4715 663 ) M1M2_PR + NEW li1 ( 4669 663 ) L1M1_PR_MR ; + - D[2] ( PIN D[2] ) ( buffer.in[2] A ) + USE SIGNAL + + ROUTED met2 ( 9315 663 ) ( * 782 0 ) + NEW met1 ( 9269 663 ) ( 9315 * ) + NEW met1 ( 9315 663 ) M1M2_PR + NEW li1 ( 9269 663 ) L1M1_PR_MR ; + - D[3] ( PIN D[3] ) ( buffer.in[3] A ) + USE SIGNAL + + ROUTED met2 ( 13915 663 ) ( * 782 0 ) + NEW met1 ( 13869 663 ) ( 13915 * ) + NEW met1 ( 13915 663 ) M1M2_PR + NEW li1 ( 13869 663 ) L1M1_PR_MR ; + - D[4] ( PIN D[4] ) ( buffer.in[4] A ) + USE SIGNAL + + ROUTED met2 ( 18423 663 ) ( * 782 0 ) + NEW met1 ( 18423 663 ) ( 18469 * ) + NEW met1 ( 18423 663 ) M1M2_PR + NEW li1 ( 18469 663 ) L1M1_PR_MR ; + - D[5] ( PIN D[5] ) ( buffer.in[5] A ) + USE SIGNAL + + ROUTED met2 ( 23115 663 ) ( * 782 0 ) + NEW met1 ( 23069 663 ) ( 23115 * ) + NEW met1 ( 23115 663 ) M1M2_PR + NEW li1 ( 23069 663 ) L1M1_PR_MR ; + - D[6] ( PIN D[6] ) ( buffer.in[6] A ) + USE SIGNAL + + ROUTED met2 ( 27715 663 ) ( * 782 0 ) + NEW met1 ( 27669 663 ) ( 27715 * ) + NEW met1 ( 27715 663 ) M1M2_PR + NEW li1 ( 27669 663 ) L1M1_PR_MR ; + - D[7] ( PIN D[7] ) ( buffer.in[7] A ) + USE SIGNAL + + ROUTED met2 ( 32315 663 ) ( * 782 0 ) + NEW met1 ( 32269 663 ) ( 32315 * ) + NEW met1 ( 32315 663 ) M1M2_PR + NEW li1 ( 32269 663 ) L1M1_PR_MR ; + - D_nets.b0 ( buffer.in[0] X ) ( storage_1_3_0.bit0.bit D ) ( storage_1_2_0.bit0.bit D ) ( storage_1_1_0.bit0.bit D ) ( storage_1_0_0.bit0.bit D ) ( storage_0_3_0.bit0.bit D ) ( storage_0_2_0.bit0.bit D ) + ( storage_0_1_0.bit0.bit D ) ( storage_0_0_0.bit0.bit D ) + USE SIGNAL + + ROUTED met1 ( 202 425 ) ( 207 * ) + NEW met2 ( 207 425 ) ( * 595 ) + NEW met1 ( 161 595 ) ( 207 * ) + NEW met1 ( 202 119 ) ( 207 * ) + NEW met2 ( 207 119 ) ( * 425 ) + NEW met1 ( 1265 425 ) ( 1347 * ) + NEW met1 ( 1265 391 ) ( * 425 ) + NEW met1 ( 851 391 ) ( 1265 * ) + NEW met1 ( 851 391 ) ( * 425 ) + NEW met1 ( 207 425 ) ( 851 * ) + NEW met2 ( 1357 85 ) ( * 425 ) + NEW met1 ( 1347 425 ) ( 1357 * ) + NEW met1 ( 1352 85 ) ( 1357 * ) + NEW met1 ( 2415 425 ) ( 2497 * ) + NEW met2 ( 2415 85 ) ( * 425 ) + NEW met1 ( 2491 85 ) ( 3641 * ) + NEW met1 ( 3652 459 ) ( 3749 * ) + NEW met2 ( 3749 85 ) ( * 459 ) + NEW met1 ( 3641 85 ) ( 3749 * ) + NEW met1 ( 1357 85 ) ( 2491 * ) + NEW li1 ( 202 425 ) L1M1_PR_MR + NEW met1 ( 207 425 ) M1M2_PR + NEW met1 ( 207 595 ) M1M2_PR + NEW li1 ( 161 595 ) L1M1_PR_MR + NEW li1 ( 202 119 ) L1M1_PR_MR + NEW met1 ( 207 119 ) M1M2_PR + NEW li1 ( 1347 425 ) L1M1_PR_MR + NEW met1 ( 1357 85 ) M1M2_PR + NEW met1 ( 1357 425 ) M1M2_PR + NEW li1 ( 1352 85 ) L1M1_PR_MR + NEW li1 ( 2491 85 ) L1M1_PR_MR + NEW li1 ( 2497 425 ) L1M1_PR_MR + NEW met1 ( 2415 425 ) M1M2_PR + NEW met1 ( 2415 85 ) M1M2_PR + NEW li1 ( 3641 85 ) L1M1_PR_MR + NEW li1 ( 3652 459 ) L1M1_PR_MR + NEW met1 ( 3749 459 ) M1M2_PR + NEW met1 ( 3749 85 ) M1M2_PR + NEW met1 ( 202 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 202 119 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 1352 85 ) RECT ( -55 -7 0 7 ) ; + - D_nets.b1 ( buffer.in[1] X ) ( storage_1_3_0.bit1.bit D ) ( storage_1_2_0.bit1.bit D ) ( storage_1_1_0.bit1.bit D ) ( storage_1_0_0.bit1.bit D ) ( storage_0_3_0.bit1.bit D ) ( storage_0_2_0.bit1.bit D ) + ( storage_0_1_0.bit1.bit D ) ( storage_0_0_0.bit1.bit D ) + USE SIGNAL + + ROUTED met1 ( 8252 459 ) ( 8257 * ) + NEW met2 ( 8257 85 ) ( * 459 ) + NEW met1 ( 8252 85 ) ( 8257 * ) + NEW met1 ( 5952 425 ) ( 6601 * ) + NEW met1 ( 6601 357 ) ( * 425 ) + NEW met1 ( 5865 85 ) ( 5941 * ) + NEW met2 ( 5865 85 ) ( * 425 ) + NEW met1 ( 5865 425 ) ( 5952 * ) + NEW met1 ( 4802 85 ) ( 5865 * ) + NEW met1 ( 4802 425 ) ( 4807 * ) + NEW met2 ( 4807 85 ) ( * 425 ) + NEW met1 ( 4761 595 ) ( 4807 * ) + NEW met2 ( 4807 425 ) ( * 595 ) + NEW met1 ( 6601 357 ) ( 6900 * ) + NEW met1 ( 7102 425 ) ( 7107 * ) + NEW met2 ( 7107 85 ) ( * 425 ) + NEW met1 ( 6900 357 ) ( * 391 ) + NEW met1 ( 6900 391 ) ( 7015 * ) + NEW met1 ( 7015 391 ) ( * 425 ) + NEW met1 ( 7015 425 ) ( 7102 * ) + NEW met1 ( 7102 85 ) ( 8252 * ) + NEW li1 ( 8252 459 ) L1M1_PR_MR + NEW met1 ( 8257 459 ) M1M2_PR + NEW met1 ( 8257 85 ) M1M2_PR + NEW li1 ( 8252 85 ) L1M1_PR_MR + NEW li1 ( 5952 425 ) L1M1_PR_MR + NEW li1 ( 5941 85 ) L1M1_PR_MR + NEW met1 ( 5865 85 ) M1M2_PR + NEW met1 ( 5865 425 ) M1M2_PR + NEW li1 ( 4802 85 ) L1M1_PR_MR + NEW li1 ( 4802 425 ) L1M1_PR_MR + NEW met1 ( 4807 425 ) M1M2_PR + NEW met1 ( 4807 85 ) M1M2_PR + NEW li1 ( 4761 595 ) L1M1_PR_MR + NEW met1 ( 4807 595 ) M1M2_PR + NEW li1 ( 7102 85 ) L1M1_PR_MR + NEW li1 ( 7102 425 ) L1M1_PR_MR + NEW met1 ( 7107 425 ) M1M2_PR + NEW met1 ( 7107 85 ) M1M2_PR + NEW met1 ( 8252 459 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 4802 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 7102 425 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b2 ( buffer.in[2] X ) ( storage_1_3_0.bit2.bit D ) ( storage_1_2_0.bit2.bit D ) ( storage_1_1_0.bit2.bit D ) ( storage_1_0_0.bit2.bit D ) ( storage_0_3_0.bit2.bit D ) ( storage_0_2_0.bit2.bit D ) + ( storage_0_1_0.bit2.bit D ) ( storage_0_0_0.bit2.bit D ) + USE SIGNAL + + ROUTED met1 ( 12852 425 ) ( 12857 * ) + NEW met2 ( 12857 85 ) ( * 425 ) + NEW met1 ( 12852 85 ) ( 12857 * ) + NEW met1 ( 11702 85 ) ( 12852 * ) + NEW met1 ( 11702 459 ) ( 11937 * ) + NEW met2 ( 11937 85 ) ( * 459 ) + NEW met1 ( 10552 85 ) ( 10695 * ) + NEW met2 ( 10695 85 ) ( * 102 ) + NEW met3 ( 10695 102 ) ( 11247 * ) + NEW met2 ( 11247 85 ) ( * 102 ) + NEW met1 ( 11247 85 ) ( 11702 * ) + NEW met1 ( 10552 459 ) ( 10695 * ) + NEW met2 ( 10695 102 ) ( * 459 ) + NEW met1 ( 9402 459 ) ( 10552 * ) + NEW met1 ( 9402 119 ) ( 9407 * ) + NEW met2 ( 9407 119 ) ( * 459 ) + NEW met1 ( 9361 595 ) ( 9407 * ) + NEW met2 ( 9407 459 ) ( * 595 ) + NEW li1 ( 12852 425 ) L1M1_PR_MR + NEW met1 ( 12857 425 ) M1M2_PR + NEW met1 ( 12857 85 ) M1M2_PR + NEW li1 ( 12852 85 ) L1M1_PR_MR + NEW li1 ( 11702 85 ) L1M1_PR_MR + NEW li1 ( 11702 459 ) L1M1_PR_MR + NEW met1 ( 11937 459 ) M1M2_PR + NEW met1 ( 11937 85 ) M1M2_PR + NEW li1 ( 10552 85 ) L1M1_PR_MR + NEW met1 ( 10695 85 ) M1M2_PR + NEW met2 ( 10695 102 ) M2M3_PR + NEW met2 ( 11247 102 ) M2M3_PR + NEW met1 ( 11247 85 ) M1M2_PR + NEW li1 ( 10552 459 ) L1M1_PR_MR + NEW met1 ( 10695 459 ) M1M2_PR + NEW li1 ( 9402 459 ) L1M1_PR_MR + NEW li1 ( 9402 119 ) L1M1_PR_MR + NEW met1 ( 9407 119 ) M1M2_PR + NEW met1 ( 9407 459 ) M1M2_PR + NEW li1 ( 9361 595 ) L1M1_PR_MR + NEW met1 ( 9407 595 ) M1M2_PR + NEW met1 ( 12852 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 9402 119 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b3 ( buffer.in[3] X ) ( storage_1_3_0.bit3.bit D ) ( storage_1_2_0.bit3.bit D ) ( storage_1_1_0.bit3.bit D ) ( storage_1_0_0.bit3.bit D ) ( storage_0_3_0.bit3.bit D ) ( storage_0_2_0.bit3.bit D ) + ( storage_0_1_0.bit3.bit D ) ( storage_0_0_0.bit3.bit D ) + USE SIGNAL + + ROUTED met1 ( 16302 85 ) ( 17441 * ) + NEW met1 ( 16302 425 ) ( 16307 * ) + NEW met2 ( 16307 85 ) ( * 425 ) + NEW met1 ( 17452 425 ) ( * 459 ) + NEW met1 ( 17365 459 ) ( 17452 * ) + NEW met1 ( 17365 425 ) ( * 459 ) + NEW met2 ( 17365 85 ) ( * 425 ) + NEW met1 ( 15152 85 ) ( 16302 * ) + NEW met1 ( 15152 425 ) ( 15157 * ) + NEW met2 ( 15157 85 ) ( * 425 ) + NEW met1 ( 14002 425 ) ( 14651 * ) + NEW met1 ( 14651 391 ) ( * 425 ) + NEW met1 ( 14651 391 ) ( 15065 * ) + NEW met1 ( 15065 391 ) ( * 425 ) + NEW met1 ( 15065 425 ) ( 15152 * ) + NEW met1 ( 14002 85 ) ( 14145 * ) + NEW met2 ( 14145 85 ) ( * 425 ) + NEW met1 ( 13961 595 ) ( 14145 * ) + NEW met2 ( 14145 425 ) ( * 595 ) + NEW li1 ( 16302 85 ) L1M1_PR_MR + NEW li1 ( 17441 85 ) L1M1_PR_MR + NEW li1 ( 16302 425 ) L1M1_PR_MR + NEW met1 ( 16307 425 ) M1M2_PR + NEW met1 ( 16307 85 ) M1M2_PR + NEW li1 ( 17452 425 ) L1M1_PR_MR + NEW met1 ( 17365 425 ) M1M2_PR + NEW met1 ( 17365 85 ) M1M2_PR + NEW li1 ( 15152 85 ) L1M1_PR_MR + NEW li1 ( 15152 425 ) L1M1_PR_MR + NEW met1 ( 15157 425 ) M1M2_PR + NEW met1 ( 15157 85 ) M1M2_PR + NEW li1 ( 14002 425 ) L1M1_PR_MR + NEW li1 ( 14002 85 ) L1M1_PR_MR + NEW met1 ( 14145 85 ) M1M2_PR + NEW met1 ( 14145 425 ) M1M2_PR + NEW li1 ( 13961 595 ) L1M1_PR_MR + NEW met1 ( 14145 595 ) M1M2_PR + NEW met1 ( 16302 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 15152 425 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b4 ( buffer.in[4] X ) ( storage_1_3_0.bit4.bit D ) ( storage_1_2_0.bit4.bit D ) ( storage_1_1_0.bit4.bit D ) ( storage_1_0_0.bit4.bit D ) ( storage_0_3_0.bit4.bit D ) ( storage_0_2_0.bit4.bit D ) + ( storage_0_1_0.bit4.bit D ) ( storage_0_0_0.bit4.bit D ) + USE SIGNAL + + ROUTED met1 ( 18602 425 ) ( 18607 * ) + NEW met2 ( 18607 85 ) ( * 425 ) + NEW met1 ( 18561 595 ) ( 18607 * ) + NEW met2 ( 18607 425 ) ( * 595 ) + NEW met1 ( 19752 459 ) ( 19757 * ) + NEW met2 ( 19757 85 ) ( * 459 ) + NEW met1 ( 19741 85 ) ( 19757 * ) + NEW met1 ( 19757 85 ) ( 20902 * ) + NEW met1 ( 20723 425 ) ( 20897 * ) + NEW met2 ( 20723 85 ) ( * 425 ) + NEW met1 ( 20902 85 ) ( 22041 * ) + NEW met1 ( 22052 459 ) ( 22057 * ) + NEW met2 ( 22057 85 ) ( * 459 ) + NEW met1 ( 22041 85 ) ( 22057 * ) + NEW met1 ( 18602 85 ) ( 19741 * ) + NEW li1 ( 18602 85 ) L1M1_PR_MR + NEW li1 ( 18602 425 ) L1M1_PR_MR + NEW met1 ( 18607 425 ) M1M2_PR + NEW met1 ( 18607 85 ) M1M2_PR + NEW li1 ( 18561 595 ) L1M1_PR_MR + NEW met1 ( 18607 595 ) M1M2_PR + NEW li1 ( 19741 85 ) L1M1_PR_MR + NEW li1 ( 19752 459 ) L1M1_PR_MR + NEW met1 ( 19757 459 ) M1M2_PR + NEW met1 ( 19757 85 ) M1M2_PR + NEW li1 ( 20902 85 ) L1M1_PR_MR + NEW li1 ( 20897 425 ) L1M1_PR_MR + NEW met1 ( 20723 425 ) M1M2_PR + NEW met1 ( 20723 85 ) M1M2_PR + NEW li1 ( 22041 85 ) L1M1_PR_MR + NEW li1 ( 22052 459 ) L1M1_PR_MR + NEW met1 ( 22057 459 ) M1M2_PR + NEW met1 ( 22057 85 ) M1M2_PR + NEW met1 ( 18602 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 19752 459 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 22052 459 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b5 ( buffer.in[5] X ) ( storage_1_3_0.bit5.bit D ) ( storage_1_2_0.bit5.bit D ) ( storage_1_1_0.bit5.bit D ) ( storage_1_0_0.bit5.bit D ) ( storage_0_3_0.bit5.bit D ) ( storage_0_2_0.bit5.bit D ) + ( storage_0_1_0.bit5.bit D ) ( storage_0_0_0.bit5.bit D ) + USE SIGNAL + + ROUTED met1 ( 23202 425 ) ( 23207 * ) + NEW met2 ( 23207 85 ) ( * 425 ) + NEW met1 ( 23161 595 ) ( 23207 * ) + NEW met2 ( 23207 425 ) ( * 595 ) + NEW met1 ( 24265 425 ) ( 24347 * ) + NEW met1 ( 24265 391 ) ( * 425 ) + NEW met1 ( 24127 391 ) ( 24265 * ) + NEW met1 ( 24127 391 ) ( * 425 ) + NEW met2 ( 24127 85 ) ( * 425 ) + NEW met1 ( 25415 85 ) ( 25491 * ) + NEW met2 ( 25415 34 ) ( * 85 ) + NEW met2 ( 25277 34 ) ( 25415 * ) + NEW met2 ( 25277 34 ) ( * 170 ) + NEW met3 ( 24127 170 ) ( 25277 * ) + NEW met1 ( 25415 425 ) ( 25502 * ) + NEW met1 ( 25415 391 ) ( * 425 ) + NEW met1 ( 25323 391 ) ( 25415 * ) + NEW met2 ( 25323 170 ) ( * 391 ) + NEW met2 ( 25277 170 ) ( 25323 * ) + NEW met1 ( 25491 85 ) ( 26641 * ) + NEW met1 ( 26652 459 ) ( 26657 * ) + NEW met2 ( 26657 85 ) ( * 459 ) + NEW met1 ( 26641 85 ) ( 26657 * ) + NEW met1 ( 23202 85 ) ( 24341 * ) + NEW li1 ( 23202 85 ) L1M1_PR_MR + NEW li1 ( 23202 425 ) L1M1_PR_MR + NEW met1 ( 23207 425 ) M1M2_PR + NEW met1 ( 23207 85 ) M1M2_PR + NEW li1 ( 23161 595 ) L1M1_PR_MR + NEW met1 ( 23207 595 ) M1M2_PR + NEW li1 ( 24341 85 ) L1M1_PR_MR + NEW li1 ( 24347 425 ) L1M1_PR_MR + NEW met1 ( 24127 425 ) M1M2_PR + NEW met1 ( 24127 85 ) M1M2_PR + NEW li1 ( 25491 85 ) L1M1_PR_MR + NEW met1 ( 25415 85 ) M1M2_PR + NEW met2 ( 25277 170 ) M2M3_PR + NEW met2 ( 24127 170 ) M2M3_PR + NEW li1 ( 25502 425 ) L1M1_PR_MR + NEW met1 ( 25323 391 ) M1M2_PR + NEW li1 ( 26641 85 ) L1M1_PR_MR + NEW li1 ( 26652 459 ) L1M1_PR_MR + NEW met1 ( 26657 459 ) M1M2_PR + NEW met1 ( 26657 85 ) M1M2_PR + NEW met1 ( 23202 425 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 26652 459 ) RECT ( -31 -7 0 7 ) ; + - D_nets.b6 ( buffer.in[6] X ) ( storage_1_3_0.bit6.bit D ) ( storage_1_2_0.bit6.bit D ) ( storage_1_1_0.bit6.bit D ) ( storage_1_0_0.bit6.bit D ) ( storage_0_3_0.bit6.bit D ) ( storage_0_2_0.bit6.bit D ) + ( storage_0_1_0.bit6.bit D ) ( storage_0_0_0.bit6.bit D ) + USE SIGNAL + + ROUTED met1 ( 27802 425 ) ( 27807 * ) + NEW met2 ( 27807 425 ) ( * 595 ) + NEW met1 ( 27761 595 ) ( 27807 * ) + NEW met1 ( 27802 85 ) ( 27807 * ) + NEW met2 ( 27807 85 ) ( * 425 ) + NEW met1 ( 27807 85 ) ( 28941 * ) + NEW met1 ( 27807 425 ) ( 28947 * ) + NEW met1 ( 30097 425 ) ( 31247 * ) + NEW met1 ( 31252 85 ) ( 31257 * ) + NEW met2 ( 31257 85 ) ( * 425 ) + NEW met1 ( 31247 425 ) ( 31257 * ) + NEW met1 ( 28941 85 ) ( 30091 * ) + NEW met1 ( 28947 425 ) ( 30097 * ) + NEW li1 ( 27802 425 ) L1M1_PR_MR + NEW met1 ( 27807 425 ) M1M2_PR + NEW met1 ( 27807 595 ) M1M2_PR + NEW li1 ( 27761 595 ) L1M1_PR_MR + NEW li1 ( 27802 85 ) L1M1_PR_MR + NEW met1 ( 27807 85 ) M1M2_PR + NEW li1 ( 28941 85 ) L1M1_PR_MR + NEW li1 ( 28947 425 ) L1M1_PR_MR + NEW li1 ( 30097 425 ) L1M1_PR_MR + NEW li1 ( 31247 425 ) L1M1_PR_MR + NEW li1 ( 31252 85 ) L1M1_PR_MR + NEW met1 ( 31257 85 ) M1M2_PR + NEW met1 ( 31257 425 ) M1M2_PR + NEW li1 ( 30091 85 ) L1M1_PR_MR + NEW met1 ( 27807 425 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 27802 85 ) RECT ( -31 -7 0 7 ) + NEW met1 ( 31257 85 ) RECT ( 0 -7 31 7 ) ; + - D_nets.b7 ( buffer.in[7] X ) ( storage_1_3_0.bit7.bit D ) ( storage_1_2_0.bit7.bit D ) ( storage_1_1_0.bit7.bit D ) ( storage_1_0_0.bit7.bit D ) ( storage_0_3_0.bit7.bit D ) ( storage_0_2_0.bit7.bit D ) + ( storage_0_1_0.bit7.bit D ) ( storage_0_0_0.bit7.bit D ) + USE SIGNAL + + ROUTED met1 ( 33281 85 ) ( 33541 * ) + NEW met2 ( 33281 85 ) ( * 425 ) + NEW met1 ( 33281 425 ) ( 33552 * ) + NEW met1 ( 32402 425 ) ( 33281 * ) + NEW met1 ( 32315 595 ) ( 32361 * ) + NEW met2 ( 32315 425 ) ( * 595 ) + NEW met1 ( 32315 425 ) ( 32402 * ) + NEW met1 ( 32402 85 ) ( 32407 * ) + NEW met2 ( 32407 85 ) ( * 425 ) + NEW met1 ( 34523 85 ) ( 34691 * ) + NEW met1 ( 34523 85 ) ( * 119 ) + NEW met1 ( 34431 119 ) ( 34523 * ) + NEW met2 ( 34431 119 ) ( * 425 ) + NEW met1 ( 34845 425 ) ( 35847 * ) + NEW met2 ( 34845 85 ) ( * 425 ) + NEW met2 ( 34707 85 ) ( 34845 * ) + NEW met1 ( 34691 85 ) ( 34707 * ) + NEW met1 ( 34702 459 ) ( 34845 * ) + NEW met1 ( 34845 425 ) ( * 459 ) + NEW met1 ( 35852 85 ) ( 35857 * ) + NEW met2 ( 35857 85 ) ( * 425 ) + NEW met1 ( 35847 425 ) ( 35857 * ) + NEW met1 ( 33552 425 ) ( 34431 * ) + NEW li1 ( 33552 425 ) L1M1_PR_MR + NEW li1 ( 33541 85 ) L1M1_PR_MR + NEW met1 ( 33281 85 ) M1M2_PR + NEW met1 ( 33281 425 ) M1M2_PR + NEW li1 ( 32402 425 ) L1M1_PR_MR + NEW li1 ( 32361 595 ) L1M1_PR_MR + NEW met1 ( 32315 595 ) M1M2_PR + NEW met1 ( 32315 425 ) M1M2_PR + NEW li1 ( 32402 85 ) L1M1_PR_MR + NEW met1 ( 32407 85 ) M1M2_PR + NEW met1 ( 32407 425 ) M1M2_PR + NEW li1 ( 34691 85 ) L1M1_PR_MR + NEW met1 ( 34431 119 ) M1M2_PR + NEW met1 ( 34431 425 ) M1M2_PR + NEW li1 ( 35847 425 ) L1M1_PR_MR + NEW met1 ( 34845 425 ) M1M2_PR + NEW met1 ( 34707 85 ) M1M2_PR + NEW li1 ( 34702 459 ) L1M1_PR_MR + NEW li1 ( 35852 85 ) L1M1_PR_MR + NEW met1 ( 35857 85 ) M1M2_PR + NEW met1 ( 35857 425 ) M1M2_PR + NEW met1 ( 32407 85 ) RECT ( 0 -7 31 7 ) + NEW met1 ( 35852 85 ) RECT ( -31 -7 0 7 ) ; + - Q[0] ( PIN Q[0] ) ( mux_slice0_bit0.s2_aoi Y ) + USE SIGNAL + + ROUTED met2 ( 2415 765 ) ( * 782 0 ) + NEW met1 ( 2369 765 ) ( 2415 * ) + NEW met1 ( 2415 765 ) M1M2_PR + NEW li1 ( 2369 765 ) L1M1_PR_MR ; + - Q[1] ( PIN Q[1] ) ( mux_slice0_bit1.s2_aoi Y ) + USE SIGNAL + + ROUTED met2 ( 4899 765 ) ( * 782 0 ) + NEW met1 ( 4899 765 ) ( 6831 * ) + NEW met2 ( 6831 765 ) ( 6923 * ) + NEW met1 ( 6923 765 ) ( 6969 * ) + NEW met1 ( 4899 765 ) M1M2_PR + NEW met1 ( 6831 765 ) M1M2_PR + NEW met1 ( 6923 765 ) M1M2_PR + NEW li1 ( 6969 765 ) L1M1_PR_MR ; + - Q[2] ( PIN Q[2] ) ( mux_slice0_bit2.s2_aoi Y ) + USE SIGNAL + + ROUTED met2 ( 11707 697 ) ( * 782 0 ) + NEW met2 ( 11702 697 ) ( 11707 * ) + NEW met1 ( 11702 697 ) ( 11707 * ) + NEW met1 ( 11702 697 ) M1M2_PR + NEW li1 ( 11707 697 ) L1M1_PR_MR ; + - Q[3] ( PIN Q[3] ) ( mux_slice0_bit3.s2_aoi Y ) + USE SIGNAL + + ROUTED met2 ( 16307 714 ) ( * 782 0 ) + NEW met2 ( 16261 714 ) ( 16307 * ) + NEW met2 ( 16261 697 ) ( * 714 ) + NEW li1 ( 16261 697 ) L1M1_PR_MR + NEW met1 ( 16261 697 ) M1M2_PR ; + - Q[4] ( PIN Q[4] ) ( mux_slice0_bit4.s2_aoi Y ) + USE SIGNAL + + ROUTED met2 ( 20907 765 ) ( * 782 0 ) + NEW met2 ( 20861 765 ) ( 20907 * ) + NEW met2 ( 20861 765 ) ( * 782 ) + NEW met2 ( 20815 782 ) ( 20861 * ) + NEW met2 ( 20815 697 ) ( * 782 ) + NEW li1 ( 20815 697 ) L1M1_PR_MR + NEW met1 ( 20815 697 ) M1M2_PR ; + - Q[5] ( PIN Q[5] ) ( mux_slice0_bit5.s2_aoi Y ) + USE SIGNAL + + ROUTED met2 ( 25415 765 ) ( * 782 0 ) + NEW met2 ( 25369 765 ) ( 25415 * ) + NEW li1 ( 25369 765 ) L1M1_PR_MR + NEW met1 ( 25369 765 ) M1M2_PR ; + - Q[6] ( PIN Q[6] ) ( mux_slice0_bit6.s2_aoi Y ) + USE SIGNAL + + ROUTED met2 ( 30107 697 ) ( * 782 0 ) + NEW li1 ( 30107 697 ) L1M1_PR_MR + NEW met1 ( 30107 697 ) M1M2_PR ; + - Q[7] ( PIN Q[7] ) ( mux_slice0_bit7.s2_aoi Y ) + USE SIGNAL + + ROUTED met2 ( 34707 765 ) ( * 782 0 ) + NEW met2 ( 34661 765 ) ( 34707 * ) + NEW met2 ( 34661 765 ) ( * 782 ) + NEW met2 ( 34569 782 ) ( 34661 * ) + NEW met2 ( 34569 731 ) ( * 782 ) + NEW li1 ( 34569 731 ) L1M1_PR_MR + NEW met1 ( 34569 731 ) M1M2_PR ; + - addr_rw[0] ( PIN addr_rw[0] ) ( mux_slice0_bit7.s1_aoi_1 B1 ) ( mux_slice0_bit7.s1_aoi_0 B1 ) ( mux_slice0_bit6.s1_aoi_1 B1 ) ( mux_slice0_bit6.s1_aoi_0 B1 ) ( mux_slice0_bit5.s1_aoi_1 B1 ) ( mux_slice0_bit5.s1_aoi_0 B1 ) + ( mux_slice0_bit4.s1_aoi_1 B1 ) ( mux_slice0_bit4.s1_aoi_0 B1 ) ( mux_slice0_bit3.s1_aoi_1 B1 ) ( mux_slice0_bit3.s1_aoi_0 B1 ) ( mux_slice0_bit2.s1_aoi_1 B1 ) ( mux_slice0_bit2.s1_aoi_0 B1 ) ( mux_slice0_bit1.s1_aoi_1 B1 ) ( mux_slice0_bit1.s1_aoi_0 B1 ) + ( mux_slice0_bit0.s1_aoi_1 B1 ) ( mux_slice0_bit0.s1_aoi_0 B1 ) ( word_sel.inv_addr_0 A ) ( word_sel.and_3 B ) ( word_sel.and_1 B ) + USE SIGNAL + + ROUTED met2 ( 3611 629 ) ( * 782 ) + NEW met3 ( 1311 782 ) ( 3611 * ) + NEW met2 ( 1311 629 ) ( * 782 ) + NEW met1 ( 9361 663 ) ( 10511 * ) + NEW met2 ( 9361 595 ) ( * 663 ) + NEW met2 ( 9315 595 ) ( 9361 * ) + NEW met1 ( 12811 663 ) ( * 765 ) + NEW met1 ( 11891 765 ) ( 12811 * ) + NEW met2 ( 11891 34 ) ( * 765 ) + NEW met2 ( 11753 34 ) ( 11891 * ) + NEW met2 ( 11753 34 ) ( * 102 ) + NEW met2 ( 11615 102 ) ( 11753 * ) + NEW met2 ( 11615 34 ) ( * 102 ) + NEW met2 ( 11569 34 ) ( 11615 * ) + NEW met3 ( 11385 34 ) ( 11569 * ) + NEW met2 ( 11385 34 ) ( * 697 ) + NEW met1 ( 10511 697 ) ( 11385 * ) + NEW met1 ( 10511 663 ) ( * 697 ) + NEW met1 ( 22011 595 ) ( * 629 ) + NEW met1 ( 22011 595 ) ( 22103 * ) + NEW met2 ( 22103 459 ) ( * 595 ) + NEW met1 ( 22103 459 ) ( 22241 * ) + NEW met2 ( 22241 459 ) ( * 697 ) + NEW met2 ( 19711 578 ) ( * 629 ) + NEW met2 ( 19711 578 ) ( 19803 * ) + NEW met2 ( 19803 578 ) ( * 697 ) + NEW met2 ( 19803 697 ) ( 19895 * ) + NEW met1 ( 19895 697 ) ( 20493 * ) + NEW met1 ( 20493 697 ) ( * 731 ) + NEW met1 ( 20493 731 ) ( 20815 * ) + NEW met1 ( 20815 731 ) ( * 765 ) + NEW met1 ( 20815 765 ) ( 21091 * ) + NEW met2 ( 21091 595 ) ( * 765 ) + NEW met1 ( 21091 595 ) ( 22011 * ) + NEW met1 ( 18699 629 ) ( * 697 ) + NEW met1 ( 18699 629 ) ( 19711 * ) + NEW met1 ( 5865 629 ) ( 5911 * ) + NEW met1 ( 5865 629 ) ( * 697 ) + NEW met1 ( 8211 595 ) ( * 629 ) + NEW met1 ( 7797 595 ) ( 8211 * ) + NEW met2 ( 7797 595 ) ( * 782 ) + NEW met3 ( 5911 782 ) ( 7797 * ) + NEW met2 ( 5911 697 ) ( * 782 ) + NEW met1 ( 5865 697 ) ( 5911 * ) + NEW met1 ( 3611 697 ) ( 5865 * ) + NEW met1 ( 8211 595 ) ( 9315 * ) + NEW met1 ( 12811 731 ) ( 13800 * ) + NEW met1 ( 13800 731 ) ( * 765 ) + NEW met2 ( 18377 595 ) ( * 697 ) + NEW met1 ( 18377 697 ) ( 18699 * ) + NEW met1 ( 24311 663 ) ( * 731 ) + NEW met1 ( 24311 731 ) ( 25323 * ) + NEW met2 ( 25323 629 ) ( * 731 ) + NEW met2 ( 25323 629 ) ( 25415 * ) + NEW met2 ( 25415 459 ) ( * 629 ) + NEW met1 ( 22241 697 ) ( 24311 * ) + NEW met1 ( 35811 595 ) ( * 629 ) + NEW met1 ( 33511 663 ) ( * 731 ) + NEW met1 ( 33511 731 ) ( 34109 * ) + NEW met1 ( 34109 595 ) ( * 731 ) + NEW met1 ( 34109 595 ) ( 35811 * ) + NEW met1 ( 31211 663 ) ( * 697 ) + NEW met1 ( 28888 663 ) ( 28911 * ) + NEW met2 ( 28911 510 ) ( * 663 ) + NEW met3 ( 28911 510 ) ( 30199 * ) + NEW met2 ( 30199 510 ) ( * 731 ) + NEW met1 ( 30199 731 ) ( 31211 * ) + NEW met1 ( 31211 697 ) ( * 731 ) + NEW met2 ( 26611 629 ) ( * 731 ) + NEW met1 ( 26611 731 ) ( 27669 * ) + NEW met1 ( 27669 697 ) ( * 731 ) + NEW met1 ( 27669 697 ) ( 28911 * ) + NEW met1 ( 28911 663 ) ( * 697 ) + NEW met1 ( 26565 425 ) ( * 459 ) + NEW met2 ( 26565 425 ) ( 26611 * ) + NEW met2 ( 26611 425 ) ( * 629 ) + NEW met1 ( 25415 459 ) ( 26565 * ) + NEW met1 ( 31211 697 ) ( 33511 * ) + NEW met1 ( 13800 765 ) ( 14490 * ) + NEW met1 ( 14490 731 ) ( * 765 ) + NEW met1 ( 14927 629 ) ( 15111 * ) + NEW met2 ( 14927 629 ) ( * 731 ) + NEW met1 ( 17411 595 ) ( * 629 ) + NEW met2 ( 17273 629 ) ( * 731 ) + NEW met1 ( 17273 629 ) ( 17411 * ) + NEW met1 ( 14490 731 ) ( 17273 * ) + NEW met1 ( 17411 595 ) ( 18377 * ) + NEW met2 ( 41377 442 ) ( * 595 ) + NEW met3 ( 41377 442 ) ( 41722 * 0 ) + NEW met1 ( 41239 663 ) ( 41377 * ) + NEW met2 ( 40779 442 ) ( * 663 ) + NEW met3 ( 40779 442 ) ( 41377 * ) + NEW met2 ( 40595 595 ) ( * 663 ) + NEW met1 ( 40595 663 ) ( 40779 * ) + NEW met1 ( 35811 595 ) ( 40595 * ) + NEW li1 ( 3611 629 ) L1M1_PR_MR + NEW met1 ( 3611 629 ) M1M2_PR + NEW met2 ( 3611 782 ) M2M3_PR + NEW met2 ( 1311 782 ) M2M3_PR + NEW li1 ( 1311 629 ) L1M1_PR_MR + NEW met1 ( 1311 629 ) M1M2_PR + NEW met1 ( 3611 697 ) M1M2_PR + NEW li1 ( 10511 663 ) L1M1_PR_MR + NEW met1 ( 9361 663 ) M1M2_PR + NEW met1 ( 9315 595 ) M1M2_PR + NEW li1 ( 12811 663 ) L1M1_PR_MR + NEW met1 ( 11891 765 ) M1M2_PR + NEW met2 ( 11569 34 ) M2M3_PR + NEW met2 ( 11385 34 ) M2M3_PR + NEW met1 ( 11385 697 ) M1M2_PR + NEW li1 ( 22011 629 ) L1M1_PR_MR + NEW met1 ( 22103 595 ) M1M2_PR + NEW met1 ( 22103 459 ) M1M2_PR + NEW met1 ( 22241 459 ) M1M2_PR + NEW met1 ( 22241 697 ) M1M2_PR + NEW li1 ( 19711 629 ) L1M1_PR_MR + NEW met1 ( 19711 629 ) M1M2_PR + NEW met1 ( 19895 697 ) M1M2_PR + NEW met1 ( 21091 765 ) M1M2_PR + NEW met1 ( 21091 595 ) M1M2_PR + NEW li1 ( 5911 629 ) L1M1_PR_MR + NEW li1 ( 8211 629 ) L1M1_PR_MR + NEW met1 ( 7797 595 ) M1M2_PR + NEW met2 ( 7797 782 ) M2M3_PR + NEW met2 ( 5911 782 ) M2M3_PR + NEW met1 ( 5911 697 ) M1M2_PR + NEW met1 ( 18377 697 ) M1M2_PR + NEW met1 ( 18377 595 ) M1M2_PR + NEW li1 ( 24311 663 ) L1M1_PR_MR + NEW met1 ( 25323 731 ) M1M2_PR + NEW met1 ( 25415 459 ) M1M2_PR + NEW li1 ( 35811 629 ) L1M1_PR_MR + NEW li1 ( 33511 663 ) L1M1_PR_MR + NEW li1 ( 31211 663 ) L1M1_PR_MR + NEW li1 ( 28888 663 ) L1M1_PR_MR + NEW met1 ( 28911 663 ) M1M2_PR + NEW met2 ( 28911 510 ) M2M3_PR + NEW met2 ( 30199 510 ) M2M3_PR + NEW met1 ( 30199 731 ) M1M2_PR + NEW li1 ( 26611 629 ) L1M1_PR_MR + NEW met1 ( 26611 629 ) M1M2_PR + NEW met1 ( 26611 731 ) M1M2_PR + NEW met1 ( 26565 425 ) M1M2_PR + NEW li1 ( 15111 629 ) L1M1_PR_MR + NEW met1 ( 14927 629 ) M1M2_PR + NEW met1 ( 14927 731 ) M1M2_PR + NEW li1 ( 17411 629 ) L1M1_PR_MR + NEW met1 ( 17273 731 ) M1M2_PR + NEW met1 ( 17273 629 ) M1M2_PR + NEW li1 ( 41377 595 ) L1M1_PR_MR + NEW met1 ( 41377 595 ) M1M2_PR + NEW met2 ( 41377 442 ) M2M3_PR + NEW li1 ( 41239 663 ) L1M1_PR_MR + NEW li1 ( 41377 663 ) L1M1_PR_MR + NEW li1 ( 40779 663 ) L1M1_PR_MR + NEW met1 ( 40779 663 ) M1M2_PR + NEW met2 ( 40779 442 ) M2M3_PR + NEW met1 ( 40595 595 ) M1M2_PR + NEW met1 ( 40595 663 ) M1M2_PR ; + - addr_rw[1] ( PIN addr_rw[1] ) ( mux_slice0_bit7.s2_aoi B1 ) ( mux_slice0_bit6.s2_aoi B1 ) ( mux_slice0_bit5.s2_aoi B1 ) ( mux_slice0_bit4.s2_aoi B1 ) ( mux_slice0_bit3.s2_aoi B1 ) ( mux_slice0_bit2.s2_aoi B1 ) + ( mux_slice0_bit1.s2_aoi B1 ) ( mux_slice0_bit0.s2_aoi B1 ) ( word_sel.inv_addr_1 A ) ( word_sel.and_3 A ) ( word_sel.and_2 A ) + USE SIGNAL + + ROUTED met1 ( 2461 663 ) ( * 765 ) + NEW met1 ( 10373 731 ) ( * 765 ) + NEW met1 ( 20861 629 ) ( * 731 ) + NEW met1 ( 20861 731 ) ( 21735 * ) + NEW met2 ( 21735 731 ) ( * 782 ) + NEW met1 ( 18653 595 ) ( * 629 ) + NEW met1 ( 18653 595 ) ( 20631 * ) + NEW met1 ( 20631 595 ) ( * 629 ) + NEW met1 ( 20631 629 ) ( 20861 * ) + NEW met2 ( 30061 442 ) ( * 629 ) + NEW met2 ( 28589 391 ) ( * 731 ) + NEW met1 ( 28589 391 ) ( 28773 * ) + NEW met2 ( 28773 391 ) ( * 493 ) + NEW met1 ( 28773 493 ) ( 30061 * ) + NEW met1 ( 16123 629 ) ( 16261 * ) + NEW met2 ( 16123 323 ) ( * 629 ) + NEW met2 ( 17595 629 ) ( * 782 ) + NEW met3 ( 17526 782 ) ( 17595 * ) + NEW met4 ( 17526 510 ) ( * 782 ) + NEW met4 ( 17342 510 ) ( 17526 * ) + NEW met4 ( 17342 510 ) ( * 578 ) + NEW met3 ( 16123 578 ) ( 17342 * ) + NEW met1 ( 17595 629 ) ( 18653 * ) + NEW met1 ( 25461 595 ) ( * 629 ) + NEW met1 ( 25139 595 ) ( 25461 * ) + NEW met2 ( 25139 595 ) ( * 782 ) + NEW met2 ( 28221 731 ) ( * 782 ) + NEW met3 ( 25898 782 ) ( 28221 * ) + NEW met4 ( 25898 510 ) ( * 782 ) + NEW met4 ( 25162 510 ) ( 25898 * ) + NEW met4 ( 25162 510 ) ( * 782 ) + NEW met3 ( 25139 782 ) ( 25162 * ) + NEW met3 ( 21735 782 ) ( 25139 * ) + NEW met1 ( 28221 731 ) ( 28589 * ) + NEW met1 ( 34661 629 ) ( 34937 * ) + NEW met1 ( 34937 629 ) ( * 663 ) + NEW met1 ( 34937 663 ) ( 35765 * ) + NEW met1 ( 35765 663 ) ( * 697 ) + NEW met1 ( 35765 697 ) ( 35949 * ) + NEW met2 ( 35949 697 ) ( * 765 ) + NEW met2 ( 33143 187 ) ( * 442 ) + NEW met1 ( 33143 187 ) ( 33373 * ) + NEW met1 ( 33373 187 ) ( * 221 ) + NEW met1 ( 33373 221 ) ( 34201 * ) + NEW met2 ( 34201 221 ) ( * 697 ) + NEW met1 ( 34201 697 ) ( 34661 * ) + NEW met1 ( 34661 629 ) ( * 697 ) + NEW met3 ( 30061 442 ) ( 33143 * ) + NEW met2 ( 11615 323 ) ( 11661 * ) + NEW met2 ( 11615 323 ) ( * 731 ) + NEW met1 ( 11661 663 ) ( * 668 ) + NEW met1 ( 11615 668 ) ( 11661 * ) + NEW met1 ( 11615 668 ) ( * 731 ) + NEW met1 ( 10373 731 ) ( 11615 * ) + NEW met1 ( 11661 323 ) ( 16123 * ) + NEW met2 ( 7429 493 ) ( * 765 ) + NEW met1 ( 6831 493 ) ( 7429 * ) + NEW met2 ( 6831 493 ) ( * 578 ) + NEW met2 ( 6785 578 ) ( 6831 * ) + NEW met2 ( 6785 578 ) ( * 731 ) + NEW met1 ( 4853 731 ) ( 6785 * ) + NEW met1 ( 4853 731 ) ( * 765 ) + NEW met1 ( 7061 652 ) ( * 663 ) + NEW met2 ( 7061 652 ) ( * 765 ) + NEW met2 ( 7061 765 ) ( 7107 * ) + NEW met1 ( 7107 765 ) ( 7429 * ) + NEW met1 ( 2461 765 ) ( 4853 * ) + NEW met1 ( 7429 765 ) ( 10373 * ) + NEW met1 ( 41515 595 ) ( 41561 * ) + NEW met2 ( 41561 578 ) ( * 595 ) + NEW met3 ( 41561 578 ) ( 41722 * 0 ) + NEW met1 ( 41147 731 ) ( * 765 ) + NEW met1 ( 41147 765 ) ( 41561 * ) + NEW met2 ( 41561 595 ) ( * 765 ) + NEW met2 ( 40917 697 ) ( * 765 ) + NEW met1 ( 40917 765 ) ( 41147 * ) + NEW met1 ( 35949 765 ) ( 40917 * ) + NEW li1 ( 2461 663 ) L1M1_PR_MR + NEW li1 ( 20861 629 ) L1M1_PR_MR + NEW met1 ( 21735 731 ) M1M2_PR + NEW met2 ( 21735 782 ) M2M3_PR + NEW li1 ( 30061 629 ) L1M1_PR_MR + NEW met1 ( 30061 629 ) M1M2_PR + NEW met2 ( 30061 442 ) M2M3_PR + NEW met1 ( 28589 731 ) M1M2_PR + NEW met1 ( 28589 391 ) M1M2_PR + NEW met1 ( 28773 391 ) M1M2_PR + NEW met1 ( 28773 493 ) M1M2_PR + NEW met1 ( 30061 493 ) M1M2_PR + NEW li1 ( 16261 629 ) L1M1_PR_MR + NEW met1 ( 16123 629 ) M1M2_PR + NEW met1 ( 16123 323 ) M1M2_PR + NEW met1 ( 17595 629 ) M1M2_PR + NEW met2 ( 17595 782 ) M2M3_PR + NEW met3 ( 17526 782 ) M3M4_PR + NEW met3 ( 17342 578 ) M3M4_PR + NEW met2 ( 16123 578 ) M2M3_PR + NEW li1 ( 25461 629 ) L1M1_PR_MR + NEW met1 ( 25139 595 ) M1M2_PR + NEW met2 ( 25139 782 ) M2M3_PR + NEW met1 ( 28221 731 ) M1M2_PR + NEW met2 ( 28221 782 ) M2M3_PR + NEW met3 ( 25898 782 ) M3M4_PR + NEW met3 ( 25162 782 ) M3M4_PR + NEW li1 ( 34661 629 ) L1M1_PR_MR + NEW met1 ( 35949 697 ) M1M2_PR + NEW met1 ( 35949 765 ) M1M2_PR + NEW met2 ( 33143 442 ) M2M3_PR + NEW met1 ( 33143 187 ) M1M2_PR + NEW met1 ( 34201 221 ) M1M2_PR + NEW met1 ( 34201 697 ) M1M2_PR + NEW met1 ( 11661 323 ) M1M2_PR + NEW met1 ( 11615 731 ) M1M2_PR + NEW li1 ( 11661 663 ) L1M1_PR_MR + NEW met1 ( 7429 765 ) M1M2_PR + NEW met1 ( 7429 493 ) M1M2_PR + NEW met1 ( 6831 493 ) M1M2_PR + NEW met1 ( 6785 731 ) M1M2_PR + NEW li1 ( 7061 663 ) L1M1_PR_MR + NEW met1 ( 7061 652 ) M1M2_PR + NEW met1 ( 7107 765 ) M1M2_PR + NEW li1 ( 41515 595 ) L1M1_PR_MR + NEW met1 ( 41561 595 ) M1M2_PR + NEW met2 ( 41561 578 ) M2M3_PR + NEW li1 ( 41147 731 ) L1M1_PR_MR + NEW met1 ( 41561 765 ) M1M2_PR + NEW li1 ( 40917 697 ) L1M1_PR_MR + NEW met1 ( 40917 697 ) M1M2_PR + NEW met1 ( 40917 765 ) M1M2_PR + NEW met3 ( 25139 782 ) RECT ( -57 -15 0 15 ) ; + - addr_rw[2] ( PIN addr_rw[2] ) ( decoder.inv_2 A ) ( storage_1_3_0.word_and A ) ( storage_1_2_0.word_and A ) ( storage_1_1_0.word_and A ) ( storage_1_0_0.select_inv_0 A ) ( storage_1_0_0.word_and A ) + USE SIGNAL + + ROUTED met1 ( 38801 357 ) ( 39951 * ) + NEW met1 ( 37973 425 ) ( 38111 * ) + NEW met2 ( 38111 357 ) ( * 425 ) + NEW met1 ( 38111 357 ) ( 38801 * ) + NEW met1 ( 37513 357 ) ( 37651 * ) + NEW met2 ( 37651 357 ) ( * 493 ) + NEW met1 ( 37651 493 ) ( 37973 * ) + NEW met1 ( 39951 357 ) ( 40020 * ) + NEW met1 ( 40227 357 ) ( 41101 * ) + NEW met1 ( 40227 357 ) ( * 391 ) + NEW met1 ( 40020 391 ) ( 40227 * ) + NEW met1 ( 40020 357 ) ( * 391 ) + NEW met2 ( 41653 119 ) ( * 323 ) + NEW met1 ( 41101 323 ) ( 41653 * ) + NEW met1 ( 41101 323 ) ( * 357 ) + NEW met3 ( 41653 34 ) ( 41722 * 0 ) + NEW met2 ( 41653 34 ) ( * 119 ) + NEW li1 ( 39951 357 ) L1M1_PR_MR + NEW li1 ( 38801 357 ) L1M1_PR_MR + NEW li1 ( 37973 425 ) L1M1_PR_MR + NEW met1 ( 38111 425 ) M1M2_PR + NEW met1 ( 38111 357 ) M1M2_PR + NEW li1 ( 37513 357 ) L1M1_PR_MR + NEW met1 ( 37651 357 ) M1M2_PR + NEW met1 ( 37651 493 ) M1M2_PR + NEW li1 ( 37973 493 ) L1M1_PR_MR + NEW li1 ( 41101 357 ) L1M1_PR_MR + NEW li1 ( 41653 119 ) L1M1_PR_MR + NEW met1 ( 41653 119 ) M1M2_PR + NEW met1 ( 41653 323 ) M1M2_PR + NEW met2 ( 41653 34 ) M2M3_PR ; + - clk ( PIN clk ) ( storage_1_3_0.cg CLK ) ( storage_1_2_0.cg CLK ) ( storage_1_1_0.cg CLK ) ( storage_1_0_0.cg CLK ) ( storage_0_3_0.cg CLK ) ( storage_0_2_0.cg CLK ) + ( storage_0_1_0.cg CLK ) ( storage_0_0_0.cg CLK ) + USE SIGNAL + + ROUTED met2 ( 39307 119 ) ( * 425 ) + NEW met1 ( 38663 119 0 ) ( 39307 * 0 ) + NEW met2 ( 38663 119 ) ( * 425 ) + NEW met1 ( 37375 119 0 ) ( 37559 * ) + NEW met2 ( 37559 119 ) ( * 459 ) + NEW met1 ( 37559 459 ) ( 38157 * ) + NEW met1 ( 38157 425 0 ) ( * 459 ) + NEW met2 ( 37283 119 ) ( * 425 ) + NEW met2 ( 40917 119 ) ( * 170 ) + NEW met3 ( 40917 170 ) ( 41722 * 0 ) + NEW met2 ( 40917 170 ) ( * 425 ) + NEW met1 ( 39813 119 0 ) ( 40457 * 0 ) + NEW met1 ( 39307 425 ) M1M2_PR_MR + NEW met1 ( 39307 119 ) M1M2_PR_MR + NEW met1 ( 38663 425 ) M1M2_PR_MR + NEW met1 ( 38663 119 ) M1M2_PR_MR + NEW met1 ( 37559 119 ) M1M2_PR + NEW met1 ( 37559 459 ) M1M2_PR + NEW met1 ( 37283 425 ) M1M2_PR + NEW met1 ( 37283 119 ) M1M2_PR + NEW met1 ( 40917 119 ) M1M2_PR + NEW met2 ( 40917 170 ) M2M3_PR + NEW met1 ( 40917 425 ) M1M2_PR ; + - inv.addr0 ( mux_slice0_bit7.s1_aoi_1 A1 ) ( mux_slice0_bit7.s1_aoi_0 A1 ) ( mux_slice0_bit6.s1_aoi_1 A1 ) ( mux_slice0_bit6.s1_aoi_0 A1 ) ( mux_slice0_bit5.s1_aoi_1 A1 ) ( mux_slice0_bit5.s1_aoi_0 A1 ) ( mux_slice0_bit4.s1_aoi_1 A1 ) + ( mux_slice0_bit4.s1_aoi_0 A1 ) ( mux_slice0_bit3.s1_aoi_1 A1 ) ( mux_slice0_bit3.s1_aoi_0 A1 ) ( mux_slice0_bit2.s1_aoi_1 A1 ) ( mux_slice0_bit2.s1_aoi_0 A1 ) ( mux_slice0_bit1.s1_aoi_1 A1 ) ( mux_slice0_bit1.s1_aoi_0 A1 ) ( mux_slice0_bit0.s1_aoi_1 A1 ) + ( mux_slice0_bit0.s1_aoi_0 A1 ) ( word_sel.inv_addr_0 Y ) ( word_sel.and_2 B ) ( word_sel.and_0 B ) + USE SIGNAL + + ROUTED met1 ( 3657 595 ) ( * 629 ) + NEW met1 ( 3381 595 ) ( 3657 * ) + NEW met2 ( 3381 493 ) ( * 595 ) + NEW met1 ( 2323 493 ) ( 3381 * ) + NEW met2 ( 2323 493 ) ( * 629 ) + NEW met1 ( 1357 629 ) ( 2323 * ) + NEW met1 ( 33557 595 ) ( * 629 ) + NEW met1 ( 33373 595 ) ( 33557 * ) + NEW met1 ( 33373 595 ) ( * 629 ) + NEW met2 ( 35857 663 ) ( * 731 ) + NEW met1 ( 35857 731 ) ( 35995 * ) + NEW met1 ( 35995 697 ) ( * 731 ) + NEW met2 ( 34063 578 ) ( * 629 ) + NEW met3 ( 34063 578 ) ( 35075 * ) + NEW met2 ( 35075 578 ) ( * 765 ) + NEW met1 ( 35075 765 ) ( 35857 * ) + NEW met1 ( 35857 731 ) ( * 765 ) + NEW met1 ( 33557 629 ) ( 34063 * ) + NEW met1 ( 10557 595 ) ( * 629 ) + NEW met1 ( 10373 595 ) ( 10557 * ) + NEW met1 ( 10373 595 ) ( * 629 ) + NEW met1 ( 12443 629 ) ( 12857 * ) + NEW met2 ( 12443 629 ) ( * 782 ) + NEW met3 ( 12006 782 ) ( 12443 * ) + NEW met4 ( 12006 510 ) ( * 782 ) + NEW met4 ( 11362 510 ) ( 12006 * ) + NEW met4 ( 11362 102 ) ( * 510 ) + NEW met3 ( 11362 102 ) ( 11431 * ) + NEW met2 ( 11431 102 ) ( * 595 ) + NEW met1 ( 10557 595 ) ( 11431 * ) + NEW met1 ( 12857 629 ) ( * 697 ) + NEW met2 ( 22057 629 ) ( * 714 ) + NEW met2 ( 22057 714 ) ( 22149 * ) + NEW met2 ( 22149 629 ) ( * 714 ) + NEW met1 ( 19757 629 ) ( 19849 * ) + NEW met2 ( 19849 170 ) ( * 629 ) + NEW met3 ( 19849 170 ) ( 22149 * ) + NEW met2 ( 22149 170 ) ( * 629 ) + NEW met1 ( 19481 731 ) ( * 765 ) + NEW met1 ( 19481 731 ) ( 19711 * ) + NEW met2 ( 19711 731 ) ( 19757 * ) + NEW met2 ( 19757 629 ) ( * 731 ) + NEW met1 ( 5957 595 ) ( * 629 ) + NEW met1 ( 5819 595 ) ( 5957 * ) + NEW met1 ( 5819 595 ) ( * 629 ) + NEW met2 ( 8257 663 ) ( * 782 ) + NEW met3 ( 8234 782 ) ( 8257 * ) + NEW met4 ( 8234 510 ) ( * 782 ) + NEW met5 ( 5842 510 ) ( 8234 * ) + NEW met4 ( 5842 510 ) ( * 782 ) + NEW met3 ( 5773 782 ) ( 5842 * ) + NEW met2 ( 5773 629 ) ( * 782 ) + NEW met1 ( 8257 629 ) ( * 663 ) + NEW met1 ( 3657 629 ) ( 5819 * ) + NEW met1 ( 8257 629 ) ( 10373 * ) + NEW met1 ( 17457 663 ) ( * 697 ) + NEW met1 ( 17411 697 ) ( 17457 * ) + NEW met1 ( 17411 697 ) ( * 731 ) + NEW met2 ( 17411 731 ) ( * 782 ) + NEW met2 ( 17227 782 ) ( 17411 * ) + NEW met2 ( 17227 765 ) ( * 782 ) + NEW met1 ( 18331 697 ) ( * 765 ) + NEW met1 ( 17457 697 ) ( 18331 * ) + NEW met1 ( 18331 765 ) ( 19481 * ) + NEW met1 ( 24357 629 ) ( 25231 * ) + NEW met2 ( 25231 629 ) ( * 782 ) + NEW met3 ( 25231 782 ) ( 25783 * ) + NEW met2 ( 25783 595 ) ( * 782 ) + NEW met1 ( 22149 629 ) ( 24357 * ) + NEW met1 ( 28957 629 ) ( * 629 ) + NEW met1 ( 28957 595 ) ( * 629 ) + NEW met1 ( 28957 595 ) ( 29785 * ) + NEW met1 ( 29785 595 ) ( * 731 ) + NEW met1 ( 29785 731 ) ( 30153 * ) + NEW met1 ( 30153 697 ) ( * 731 ) + NEW met1 ( 30153 697 ) ( 31073 * ) + NEW met2 ( 31073 629 ) ( * 697 ) + NEW met2 ( 31073 629 ) ( 31257 * ) + NEW met1 ( 26657 629 ) ( 27853 * ) + NEW met1 ( 27853 595 ) ( * 629 ) + NEW met1 ( 27853 595 ) ( 28957 * ) + NEW met1 ( 26657 595 ) ( * 629 ) + NEW met1 ( 25783 595 ) ( 26657 * ) + NEW met1 ( 31257 629 ) ( 33373 * ) + NEW met2 ( 14881 697 ) ( * 765 ) + NEW met2 ( 15157 629 ) ( * 765 ) + NEW met1 ( 12857 697 ) ( 14881 * ) + NEW met1 ( 14881 765 ) ( 17227 * ) + NEW met1 ( 35995 697 ) ( 36570 * ) + NEW met1 ( 36570 663 ) ( * 697 ) + NEW met1 ( 41009 629 ) ( * 663 ) + NEW met1 ( 40549 629 ) ( 41009 * ) + NEW met1 ( 40549 629 ) ( * 663 ) + NEW met1 ( 41009 629 ) ( 41423 * ) + NEW met1 ( 36570 663 ) ( 40549 * ) + NEW li1 ( 1357 629 ) L1M1_PR_MR + NEW li1 ( 3657 629 ) L1M1_PR_MR + NEW met1 ( 3381 595 ) M1M2_PR + NEW met1 ( 3381 493 ) M1M2_PR + NEW met1 ( 2323 493 ) M1M2_PR + NEW met1 ( 2323 629 ) M1M2_PR + NEW li1 ( 33557 629 ) L1M1_PR_MR + NEW li1 ( 35857 663 ) L1M1_PR_MR + NEW met1 ( 35857 663 ) M1M2_PR + NEW met1 ( 35857 731 ) M1M2_PR + NEW met1 ( 34063 629 ) M1M2_PR + NEW met2 ( 34063 578 ) M2M3_PR + NEW met2 ( 35075 578 ) M2M3_PR + NEW met1 ( 35075 765 ) M1M2_PR + NEW li1 ( 10557 629 ) L1M1_PR_MR + NEW li1 ( 12857 629 ) L1M1_PR_MR + NEW met1 ( 12443 629 ) M1M2_PR + NEW met2 ( 12443 782 ) M2M3_PR + NEW met3 ( 12006 782 ) M3M4_PR + NEW met3 ( 11362 102 ) M3M4_PR + NEW met2 ( 11431 102 ) M2M3_PR + NEW met1 ( 11431 595 ) M1M2_PR + NEW li1 ( 22057 629 ) L1M1_PR_MR + NEW met1 ( 22057 629 ) M1M2_PR + NEW met1 ( 22149 629 ) M1M2_PR + NEW li1 ( 19757 629 ) L1M1_PR_MR + NEW met1 ( 19849 629 ) M1M2_PR + NEW met2 ( 19849 170 ) M2M3_PR + NEW met2 ( 22149 170 ) M2M3_PR + NEW met1 ( 19711 731 ) M1M2_PR + NEW met1 ( 19757 629 ) M1M2_PR + NEW li1 ( 5957 629 ) L1M1_PR_MR + NEW li1 ( 8257 663 ) L1M1_PR_MR + NEW met1 ( 8257 663 ) M1M2_PR + NEW met2 ( 8257 782 ) M2M3_PR + NEW met3 ( 8234 782 ) M3M4_PR + NEW met4 ( 8234 510 ) M4M5_PR + NEW met4 ( 5842 510 ) M4M5_PR + NEW met3 ( 5842 782 ) M3M4_PR + NEW met2 ( 5773 782 ) M2M3_PR + NEW met1 ( 5773 629 ) M1M2_PR + NEW li1 ( 17457 663 ) L1M1_PR_MR + NEW met1 ( 17411 731 ) M1M2_PR + NEW met1 ( 17227 765 ) M1M2_PR + NEW li1 ( 24357 629 ) L1M1_PR_MR + NEW met1 ( 25231 629 ) M1M2_PR + NEW met2 ( 25231 782 ) M2M3_PR + NEW met2 ( 25783 782 ) M2M3_PR + NEW met1 ( 25783 595 ) M1M2_PR + NEW li1 ( 31257 629 ) L1M1_PR_MR + NEW li1 ( 28957 629 ) L1M1_PR_MR + NEW met1 ( 31073 697 ) M1M2_PR + NEW met1 ( 31257 629 ) M1M2_PR + NEW li1 ( 26657 629 ) L1M1_PR_MR + NEW met1 ( 14881 765 ) M1M2_PR + NEW met1 ( 14881 697 ) M1M2_PR + NEW li1 ( 15157 629 ) L1M1_PR_MR + NEW met1 ( 15157 629 ) M1M2_PR + NEW met1 ( 15157 765 ) M1M2_PR + NEW li1 ( 40549 663 ) L1M1_PR_MR + NEW li1 ( 41009 663 ) L1M1_PR_MR + NEW li1 ( 41423 629 ) L1M1_PR_MR + NEW met3 ( 8257 782 ) RECT ( 0 -15 39 15 ) ; + - inv.addr1 ( mux_slice0_bit7.s2_aoi A1 ) ( mux_slice0_bit6.s2_aoi A1 ) ( mux_slice0_bit5.s2_aoi A1 ) ( mux_slice0_bit4.s2_aoi A1 ) ( mux_slice0_bit3.s2_aoi A1 ) ( mux_slice0_bit2.s2_aoi A1 ) ( mux_slice0_bit1.s2_aoi A1 ) + ( mux_slice0_bit0.s2_aoi A1 ) ( word_sel.inv_addr_1 Y ) ( word_sel.and_1 A ) ( word_sel.and_0 A ) + USE SIGNAL + + ROUTED met1 ( 28819 187 ) ( * 221 ) + NEW met1 ( 28635 187 ) ( 28819 * ) + NEW met2 ( 28635 187 ) ( * 493 ) + NEW met1 ( 2521 668 ) ( * 697 ) + NEW met1 ( 2507 668 ) ( 2521 * ) + NEW met1 ( 2507 663 ) ( * 668 ) + NEW met2 ( 30107 493 ) ( * 629 ) + NEW met1 ( 30107 493 ) ( 30613 * ) + NEW met2 ( 30613 493 ) ( * 765 ) + NEW met1 ( 29601 187 ) ( * 221 ) + NEW met1 ( 29601 187 ) ( 29785 * ) + NEW met1 ( 29785 187 ) ( * 221 ) + NEW met1 ( 29785 221 ) ( 30107 * ) + NEW met2 ( 30107 221 ) ( * 493 ) + NEW met1 ( 28819 221 ) ( 29601 * ) + NEW met2 ( 11799 629 ) ( * 782 ) + NEW met2 ( 11799 782 ) ( 11845 * ) + NEW met2 ( 10327 731 ) ( * 782 ) + NEW met1 ( 11799 595 ) ( * 629 ) + NEW met1 ( 20907 663 ) ( * 668 ) + NEW met1 ( 20902 668 ) ( 20907 * ) + NEW met1 ( 20902 668 ) ( * 697 ) + NEW met1 ( 20902 697 ) ( 21965 * ) + NEW met1 ( 21965 697 ) ( * 765 ) + NEW met2 ( 21137 323 ) ( * 697 ) + NEW met1 ( 8970 731 ) ( 10327 * ) + NEW met1 ( 8970 697 ) ( * 731 ) + NEW met1 ( 11799 595 ) ( 13800 * ) + NEW met1 ( 18055 323 ) ( * 357 ) + NEW met1 ( 18055 357 ) ( 18285 * ) + NEW met1 ( 18285 323 ) ( * 357 ) + NEW met1 ( 13800 595 ) ( * 629 ) + NEW met1 ( 13800 629 ) ( 14881 * ) + NEW met2 ( 14881 493 ) ( * 629 ) + NEW met1 ( 18285 323 ) ( 21137 * ) + NEW met1 ( 25503 629 ) ( 25507 * ) + NEW met1 ( 25503 595 ) ( * 629 ) + NEW met1 ( 25503 595 ) ( 25645 * ) + NEW met1 ( 25645 595 ) ( * 731 ) + NEW met1 ( 25645 731 ) ( 26473 * ) + NEW met1 ( 26473 731 ) ( * 765 ) + NEW met1 ( 26473 765 ) ( 26565 * ) + NEW met2 ( 26565 697 ) ( * 765 ) + NEW met1 ( 26565 697 ) ( 27623 * ) + NEW met2 ( 27623 493 ) ( * 697 ) + NEW met2 ( 25093 323 ) ( * 765 ) + NEW met1 ( 25093 323 ) ( 25737 * ) + NEW met2 ( 25737 323 ) ( * 629 ) + NEW met1 ( 25645 629 ) ( 25737 * ) + NEW met1 ( 21965 765 ) ( 25093 * ) + NEW met1 ( 27623 493 ) ( 28635 * ) + NEW met2 ( 34707 663 ) ( 34753 * ) + NEW met2 ( 34753 663 ) ( * 782 ) + NEW met3 ( 34753 782 ) ( 36087 * ) + NEW met2 ( 36087 629 ) ( * 782 ) + NEW met2 ( 33327 765 ) ( * 782 ) + NEW met3 ( 33327 782 ) ( 34753 * ) + NEW met1 ( 30613 765 ) ( 33327 * ) + NEW met1 ( 11707 629 ) ( 11799 * ) + NEW met3 ( 10327 782 ) ( 11845 * ) + NEW met2 ( 16307 629 ) ( 16353 * ) + NEW met2 ( 16353 323 ) ( * 629 ) + NEW met1 ( 14881 493 ) ( 16353 * ) + NEW met1 ( 16353 323 ) ( 18055 * ) + NEW met2 ( 7567 119 ) ( * 697 ) + NEW met1 ( 7061 119 ) ( 7567 * ) + NEW met1 ( 7061 85 ) ( * 119 ) + NEW met1 ( 6877 85 ) ( 7061 * ) + NEW met1 ( 6877 51 ) ( * 85 ) + NEW met1 ( 5681 51 ) ( 6877 * ) + NEW met2 ( 5681 51 ) ( * 323 ) + NEW met1 ( 3335 323 ) ( 5681 * ) + NEW met2 ( 3335 323 ) ( * 697 ) + NEW met1 ( 7107 595 ) ( * 629 ) + NEW met1 ( 7107 595 ) ( 7567 * ) + NEW met1 ( 2521 697 ) ( 3335 * ) + NEW met1 ( 7567 697 ) ( 8970 * ) + NEW met1 ( 40687 697 ) ( 40825 * ) + NEW met1 ( 40825 663 ) ( * 697 ) + NEW met1 ( 40825 663 ) ( 40963 * ) + NEW met1 ( 40963 663 ) ( * 697 ) + NEW met1 ( 40963 697 ) ( 41055 * ) + NEW met1 ( 41055 663 ) ( * 697 ) + NEW met1 ( 41055 663 ) ( 41193 * ) + NEW met1 ( 41193 663 ) ( * 697 ) + NEW met1 ( 41193 697 ) ( 41561 * ) + NEW met1 ( 40457 697 ) ( 40687 * ) + NEW met2 ( 40135 629 ) ( * 697 ) + NEW met1 ( 40135 697 ) ( 40457 * ) + NEW met1 ( 36087 629 ) ( 40135 * ) + NEW met1 ( 28635 187 ) M1M2_PR + NEW met1 ( 28635 493 ) M1M2_PR + NEW li1 ( 2507 663 ) L1M1_PR_MR + NEW li1 ( 30107 629 ) L1M1_PR_MR + NEW met1 ( 30107 629 ) M1M2_PR + NEW met1 ( 30107 493 ) M1M2_PR + NEW met1 ( 30613 493 ) M1M2_PR + NEW met1 ( 30613 765 ) M1M2_PR + NEW met1 ( 30107 221 ) M1M2_PR + NEW met1 ( 11799 629 ) M1M2_PR + NEW met2 ( 11845 782 ) M2M3_PR + NEW met2 ( 10327 782 ) M2M3_PR + NEW met1 ( 10327 731 ) M1M2_PR + NEW li1 ( 20907 663 ) L1M1_PR_MR + NEW met1 ( 21137 323 ) M1M2_PR + NEW met1 ( 21137 697 ) M1M2_PR + NEW met1 ( 14881 629 ) M1M2_PR + NEW met1 ( 14881 493 ) M1M2_PR + NEW li1 ( 25507 629 ) L1M1_PR_MR + NEW met1 ( 26565 765 ) M1M2_PR + NEW met1 ( 26565 697 ) M1M2_PR + NEW met1 ( 27623 697 ) M1M2_PR + NEW met1 ( 27623 493 ) M1M2_PR + NEW met1 ( 25093 765 ) M1M2_PR + NEW met1 ( 25093 323 ) M1M2_PR + NEW met1 ( 25737 323 ) M1M2_PR + NEW met1 ( 25737 629 ) M1M2_PR + NEW li1 ( 34707 663 ) L1M1_PR_MR + NEW met1 ( 34707 663 ) M1M2_PR + NEW met2 ( 34753 782 ) M2M3_PR + NEW met2 ( 36087 782 ) M2M3_PR + NEW met1 ( 36087 629 ) M1M2_PR + NEW met1 ( 33327 765 ) M1M2_PR + NEW met2 ( 33327 782 ) M2M3_PR + NEW li1 ( 11707 629 ) L1M1_PR_MR + NEW li1 ( 16307 629 ) L1M1_PR_MR + NEW met1 ( 16307 629 ) M1M2_PR + NEW met1 ( 16353 323 ) M1M2_PR + NEW met1 ( 16353 493 ) M1M2_PR + NEW met1 ( 7567 697 ) M1M2_PR + NEW met1 ( 7567 119 ) M1M2_PR + NEW met1 ( 5681 51 ) M1M2_PR + NEW met1 ( 5681 323 ) M1M2_PR + NEW met1 ( 3335 323 ) M1M2_PR + NEW met1 ( 3335 697 ) M1M2_PR + NEW li1 ( 7107 629 ) L1M1_PR_MR + NEW met1 ( 7567 595 ) M1M2_PR + NEW li1 ( 40687 697 ) L1M1_PR_MR + NEW li1 ( 41561 697 ) L1M1_PR_MR + NEW li1 ( 40457 697 ) L1M1_PR_MR + NEW met1 ( 40135 629 ) M1M2_PR + NEW met1 ( 40135 697 ) M1M2_PR ; + - inv.addr2 ( decoder.inv_2 Y ) ( storage_0_3_0.word_and A ) ( storage_0_2_0.word_and A ) ( storage_0_1_0.word_and A ) ( storage_0_0_0.select_inv_0 A ) ( storage_0_0_0.word_and A ) + USE SIGNAL + + ROUTED met1 ( 38801 153 ) ( 38847 * ) + NEW met2 ( 38847 153 ) ( * 170 ) + NEW met3 ( 38847 170 ) ( 39353 * ) + NEW met2 ( 39353 153 ) ( * 170 ) + NEW met1 ( 39353 153 ) ( 39951 * ) + NEW met1 ( 39951 153 ) ( * 187 ) + NEW met1 ( 37973 119 ) ( 38111 * ) + NEW met2 ( 38111 119 ) ( * 238 ) + NEW met3 ( 38111 238 ) ( 38870 * ) + NEW met3 ( 38870 170 ) ( * 238 ) + NEW met1 ( 37513 187 ) ( 37789 * ) + NEW met1 ( 37789 153 ) ( * 187 ) + NEW met1 ( 37789 153 ) ( 37973 * ) + NEW met1 ( 37973 119 ) ( * 153 ) + NEW met1 ( 41101 187 ) ( 41699 * ) + NEW met1 ( 39951 187 ) ( 41101 * ) + NEW li1 ( 39951 187 ) L1M1_PR_MR + NEW li1 ( 38801 153 ) L1M1_PR_MR + NEW met1 ( 38847 153 ) M1M2_PR + NEW met2 ( 38847 170 ) M2M3_PR + NEW met2 ( 39353 170 ) M2M3_PR + NEW met1 ( 39353 153 ) M1M2_PR + NEW li1 ( 37973 119 ) L1M1_PR_MR + NEW met1 ( 38111 119 ) M1M2_PR + NEW met2 ( 38111 238 ) M2M3_PR + NEW li1 ( 37513 187 ) L1M1_PR_MR + NEW li1 ( 41101 187 ) L1M1_PR_MR + NEW li1 ( 41699 187 ) L1M1_PR_MR ; + - mux_slice0_bit0.s1_out_0 ( mux_slice0_bit0.s2_aoi A2 ) ( mux_slice0_bit0.s1_aoi_0 Y ) + USE SIGNAL + + ROUTED met1 ( 2555 652 ) ( 2563 * ) + NEW met1 ( 2555 629 ) ( * 652 ) + NEW met1 ( 2415 629 ) ( 2555 * ) + NEW met1 ( 2415 629 ) ( * 697 ) + NEW met1 ( 1357 697 ) ( 2415 * ) + NEW li1 ( 2563 652 ) L1M1_PR_MR + NEW li1 ( 1357 697 ) L1M1_PR_MR ; + - mux_slice0_bit0.s1_out_1 ( mux_slice0_bit0.s2_aoi B2 ) ( mux_slice0_bit0.s1_aoi_1 Y ) + USE SIGNAL + + ROUTED met1 ( 2369 595 ) ( * 629 ) + NEW met1 ( 2369 595 ) ( 2599 * ) + NEW met1 ( 2599 595 ) ( * 629 ) + NEW met1 ( 2599 629 ) ( 3565 * ) + NEW met1 ( 3565 629 ) ( * 697 ) + NEW li1 ( 2369 629 ) L1M1_PR_MR + NEW li1 ( 3565 697 ) L1M1_PR_MR ; + - mux_slice0_bit1.s1_out_0 ( mux_slice0_bit1.s2_aoi A2 ) ( mux_slice0_bit1.s1_aoi_0 Y ) + USE SIGNAL + + ROUTED met1 ( 7153 668 ) ( 7155 * ) + NEW met1 ( 7153 668 ) ( * 731 ) + NEW met1 ( 6992 731 ) ( 7153 * ) + NEW met1 ( 6992 697 ) ( * 731 ) + NEW met1 ( 6923 697 ) ( 6992 * ) + NEW met2 ( 6831 697 ) ( 6923 * ) + NEW met1 ( 5957 697 ) ( 6831 * ) + NEW li1 ( 7155 668 ) L1M1_PR_MR + NEW met1 ( 6923 697 ) M1M2_PR + NEW met1 ( 6831 697 ) M1M2_PR + NEW li1 ( 5957 697 ) L1M1_PR_MR ; + - mux_slice0_bit1.s1_out_1 ( mux_slice0_bit1.s2_aoi B2 ) ( mux_slice0_bit1.s1_aoi_1 Y ) + USE SIGNAL + + ROUTED met1 ( 6969 595 ) ( * 629 ) + NEW met1 ( 6969 595 ) ( 7061 * ) + NEW met2 ( 7061 595 ) ( 7107 * ) + NEW met2 ( 7107 595 ) ( * 629 ) + NEW met2 ( 7107 629 ) ( 7199 * ) + NEW met2 ( 7199 629 ) ( * 731 ) + NEW met1 ( 7199 731 ) ( 8119 * ) + NEW li1 ( 8119 731 ) L1M1_PR_MR + NEW li1 ( 6969 629 ) L1M1_PR_MR + NEW met1 ( 7061 595 ) M1M2_PR + NEW met1 ( 7199 731 ) M1M2_PR ; + - mux_slice0_bit2.s1_out_0 ( mux_slice0_bit2.s2_aoi A2 ) ( mux_slice0_bit2.s1_aoi_0 Y ) + USE SIGNAL + + ROUTED met1 ( 11755 668 ) ( * 671 ) + NEW met1 ( 11755 671 ) ( 11799 * ) + NEW met1 ( 11799 663 ) ( * 671 ) + NEW met1 ( 11799 663 ) ( 11845 * ) + NEW met2 ( 11845 442 ) ( * 663 ) + NEW met2 ( 11569 493 ) ( * 765 ) + NEW met1 ( 11569 493 ) ( 11661 * ) + NEW met2 ( 11661 493 ) ( 11707 * ) + NEW met2 ( 11707 442 ) ( * 493 ) + NEW met1 ( 10419 765 ) ( 11569 * ) + NEW met2 ( 11707 442 ) ( 11845 * ) + NEW li1 ( 11755 668 ) L1M1_PR_MR + NEW met1 ( 11845 663 ) M1M2_PR + NEW li1 ( 10419 765 ) L1M1_PR_MR + NEW met1 ( 11569 765 ) M1M2_PR + NEW met1 ( 11569 493 ) M1M2_PR + NEW met1 ( 11661 493 ) M1M2_PR ; + - mux_slice0_bit2.s1_out_1 ( mux_slice0_bit2.s2_aoi B2 ) ( mux_slice0_bit2.s1_aoi_1 Y ) + USE SIGNAL + + ROUTED met1 ( 11730 731 ) ( 12719 * ) + NEW met1 ( 11523 663 ) ( 11569 * ) + NEW met1 ( 11523 595 ) ( * 663 ) + NEW met1 ( 11523 595 ) ( 11661 * ) + NEW met2 ( 11661 595 ) ( * 765 ) + NEW met1 ( 11661 765 ) ( 11730 * ) + NEW met1 ( 11730 731 ) ( * 765 ) + NEW li1 ( 12719 731 ) L1M1_PR_MR + NEW li1 ( 11569 663 ) L1M1_PR_MR + NEW met1 ( 11661 595 ) M1M2_PR + NEW met1 ( 11661 765 ) M1M2_PR ; + - mux_slice0_bit3.s1_out_0 ( mux_slice0_bit3.s2_aoi A2 ) ( mux_slice0_bit3.s1_aoi_0 Y ) + USE SIGNAL + + ROUTED met1 ( 16215 663 ) ( * 697 ) + NEW met1 ( 16215 663 ) ( 16355 * ) + NEW met1 ( 15157 697 ) ( 16215 * ) + NEW li1 ( 15157 697 ) L1M1_PR_MR + NEW li1 ( 16355 663 ) L1M1_PR_MR ; + - mux_slice0_bit3.s1_out_1 ( mux_slice0_bit3.s2_aoi B2 ) ( mux_slice0_bit3.s1_aoi_1 Y ) + USE SIGNAL + + ROUTED met1 ( 16077 663 ) ( 16169 * ) + NEW met1 ( 16077 595 ) ( * 663 ) + NEW met1 ( 16077 595 ) ( 16445 * ) + NEW met1 ( 16445 595 ) ( * 697 ) + NEW met1 ( 16445 697 ) ( 17319 * ) + NEW met1 ( 17319 697 ) ( * 731 ) + NEW li1 ( 16169 663 ) L1M1_PR_MR + NEW li1 ( 17319 731 ) L1M1_PR_MR ; + - mux_slice0_bit4.s1_out_0 ( mux_slice0_bit4.s2_aoi A2 ) ( mux_slice0_bit4.s1_aoi_0 Y ) + USE SIGNAL + + ROUTED met1 ( 20955 595 ) ( * 652 ) + NEW met1 ( 20723 595 ) ( 20955 * ) + NEW met2 ( 20723 595 ) ( * 765 ) + NEW met1 ( 19619 765 ) ( 20723 * ) + NEW li1 ( 20955 652 ) L1M1_PR_MR + NEW met1 ( 20723 595 ) M1M2_PR + NEW met1 ( 20723 765 ) M1M2_PR + NEW li1 ( 19619 765 ) L1M1_PR_MR ; + - mux_slice0_bit4.s1_out_1 ( mux_slice0_bit4.s2_aoi B2 ) ( mux_slice0_bit4.s1_aoi_1 Y ) + USE SIGNAL + + ROUTED met2 ( 20769 646 ) ( * 663 ) + NEW met2 ( 20769 646 ) ( 20815 * ) + NEW met2 ( 20815 459 ) ( * 646 ) + NEW met1 ( 20815 459 ) ( 21781 * ) + NEW met2 ( 21781 459 ) ( * 731 ) + NEW met1 ( 21781 731 ) ( 21919 * ) + NEW li1 ( 20769 663 ) L1M1_PR_MR + NEW met1 ( 20769 663 ) M1M2_PR + NEW met1 ( 20815 459 ) M1M2_PR + NEW met1 ( 21781 459 ) M1M2_PR + NEW met1 ( 21781 731 ) M1M2_PR + NEW li1 ( 21919 731 ) L1M1_PR_MR ; + - mux_slice0_bit5.s1_out_0 ( mux_slice0_bit5.s2_aoi A2 ) ( mux_slice0_bit5.s1_aoi_0 Y ) + USE SIGNAL + + ROUTED met1 ( 25553 663 ) ( 25555 * ) + NEW met2 ( 25553 493 ) ( * 663 ) + NEW met1 ( 25369 493 ) ( 25553 * ) + NEW met2 ( 25369 493 ) ( * 578 ) + NEW met2 ( 25185 578 ) ( 25369 * ) + NEW met2 ( 25185 578 ) ( * 697 ) + NEW met1 ( 24357 697 ) ( 25185 * ) + NEW li1 ( 25555 663 ) L1M1_PR_MR + NEW met1 ( 25553 663 ) M1M2_PR + NEW met1 ( 25553 493 ) M1M2_PR + NEW met1 ( 25369 493 ) M1M2_PR + NEW met1 ( 25185 697 ) M1M2_PR + NEW li1 ( 24357 697 ) L1M1_PR_MR + NEW met1 ( 25555 663 ) RECT ( 0 -7 33 7 ) ; + - mux_slice0_bit5.s1_out_1 ( mux_slice0_bit5.s2_aoi B2 ) ( mux_slice0_bit5.s1_aoi_1 Y ) + USE SIGNAL + + ROUTED met1 ( 25369 661 ) ( * 663 ) + NEW met1 ( 25369 661 ) ( 25415 * ) + NEW met1 ( 25415 661 ) ( * 697 ) + NEW met1 ( 25415 697 ) ( 25530 * ) + NEW met1 ( 25530 697 ) ( * 731 ) + NEW met1 ( 25530 731 ) ( 25553 * ) + NEW met1 ( 25553 731 ) ( * 765 ) + NEW met1 ( 25553 765 ) ( 25691 * ) + NEW met2 ( 25691 697 ) ( * 765 ) + NEW met1 ( 25691 697 ) ( 26519 * ) + NEW li1 ( 25369 663 ) L1M1_PR_MR + NEW met1 ( 25691 765 ) M1M2_PR + NEW met1 ( 25691 697 ) M1M2_PR + NEW li1 ( 26519 697 ) L1M1_PR_MR ; + - mux_slice0_bit6.s1_out_0 ( mux_slice0_bit6.s2_aoi A2 ) ( mux_slice0_bit6.s1_aoi_0 Y ) + USE SIGNAL + + ROUTED met1 ( 30153 663 ) ( 30155 * ) + NEW met2 ( 30153 663 ) ( * 765 ) + NEW met1 ( 28819 765 ) ( 30153 * ) + NEW li1 ( 30155 663 ) L1M1_PR_MR + NEW met1 ( 30153 663 ) M1M2_PR + NEW met1 ( 30153 765 ) M1M2_PR + NEW li1 ( 28819 765 ) L1M1_PR_MR + NEW met1 ( 30155 663 ) RECT ( 0 -7 33 7 ) ; + - mux_slice0_bit6.s1_out_1 ( mux_slice0_bit6.s2_aoi B2 ) ( mux_slice0_bit6.s1_aoi_1 Y ) + USE SIGNAL + + ROUTED met1 ( 29969 595 ) ( * 629 ) + NEW met1 ( 29969 595 ) ( 30245 * ) + NEW met1 ( 30245 595 ) ( * 663 ) + NEW met1 ( 30245 663 ) ( 31119 * ) + NEW met1 ( 31119 663 ) ( * 697 ) + NEW li1 ( 29969 629 ) L1M1_PR_MR + NEW li1 ( 31119 697 ) L1M1_PR_MR ; + - mux_slice0_bit7.s1_out_0 ( mux_slice0_bit7.s2_aoi A2 ) ( mux_slice0_bit7.s1_aoi_0 Y ) + USE SIGNAL + + ROUTED met1 ( 34771 663 ) ( * 668 ) + NEW met1 ( 34771 668 ) ( 34799 * ) + NEW met1 ( 34799 663 ) ( * 668 ) + NEW met2 ( 34799 663 ) ( * 765 ) + NEW met1 ( 33419 765 ) ( 34799 * ) + NEW li1 ( 34771 663 ) L1M1_PR_MR + NEW met1 ( 34799 663 ) M1M2_PR + NEW met1 ( 34799 765 ) M1M2_PR + NEW li1 ( 33419 765 ) L1M1_PR_MR ; + - mux_slice0_bit7.s1_out_1 ( mux_slice0_bit7.s2_aoi B2 ) ( mux_slice0_bit7.s1_aoi_1 Y ) + USE SIGNAL + + ROUTED met1 ( 34569 663 ) ( 34615 * ) + NEW met2 ( 34615 663 ) ( * 731 ) + NEW met1 ( 34615 731 ) ( 35719 * ) + NEW li1 ( 34569 663 ) L1M1_PR_MR + NEW met1 ( 34615 663 ) M1M2_PR + NEW met1 ( 34615 731 ) M1M2_PR + NEW li1 ( 35719 731 ) L1M1_PR_MR ; + - row0.select0_b ( storage_0_3_0.bit7.obuf0 TE_B ) ( storage_0_3_0.bit6.obuf0 TE_B ) ( storage_0_3_0.bit5.obuf0 TE_B ) ( storage_0_3_0.bit4.obuf0 TE_B ) ( storage_0_3_0.bit3.obuf0 TE_B ) ( storage_0_3_0.bit2.obuf0 TE_B ) ( storage_0_3_0.bit1.obuf0 TE_B ) + ( storage_0_3_0.bit0.obuf0 TE_B ) ( storage_0_2_0.bit7.obuf0 TE_B ) ( storage_0_2_0.bit6.obuf0 TE_B ) ( storage_0_2_0.bit5.obuf0 TE_B ) ( storage_0_2_0.bit4.obuf0 TE_B ) ( storage_0_2_0.bit3.obuf0 TE_B ) ( storage_0_2_0.bit2.obuf0 TE_B ) ( storage_0_2_0.bit1.obuf0 TE_B ) + ( storage_0_2_0.bit0.obuf0 TE_B ) ( storage_0_1_0.bit7.obuf0 TE_B ) ( storage_0_1_0.bit6.obuf0 TE_B ) ( storage_0_1_0.bit5.obuf0 TE_B ) ( storage_0_1_0.bit4.obuf0 TE_B ) ( storage_0_1_0.bit3.obuf0 TE_B ) ( storage_0_1_0.bit2.obuf0 TE_B ) ( storage_0_1_0.bit1.obuf0 TE_B ) + ( storage_0_1_0.bit0.obuf0 TE_B ) ( storage_0_0_0.select_inv_0 Y ) ( storage_0_0_0.bit7.obuf0 TE_B ) ( storage_0_0_0.bit6.obuf0 TE_B ) ( storage_0_0_0.bit5.obuf0 TE_B ) ( storage_0_0_0.bit4.obuf0 TE_B ) ( storage_0_0_0.bit3.obuf0 TE_B ) ( storage_0_0_0.bit2.obuf0 TE_B ) + ( storage_0_0_0.bit1.obuf0 TE_B ) ( storage_0_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 1265 119 ) ( * 153 ) + NEW met1 ( 897 153 ) ( 1265 * ) + NEW met1 ( 16215 119 ) ( 16997 * ) + NEW met1 ( 16215 119 ) ( * 153 ) + NEW met1 ( 18101 153 ) ( 18147 * ) + NEW met1 ( 18101 119 ) ( * 153 ) + NEW met1 ( 16997 119 ) ( 18101 * ) + NEW met1 ( 18515 119 ) ( 19297 * ) + NEW met1 ( 18515 119 ) ( * 153 ) + NEW met1 ( 18147 153 ) ( 18515 * ) + NEW met1 ( 28497 153 ) ( 28865 * ) + NEW met1 ( 28865 119 ) ( * 153 ) + NEW met1 ( 28497 119 ) ( * 153 ) + NEW met1 ( 35397 153 ) ( 35673 * ) + NEW met1 ( 35673 153 ) ( * 221 ) + NEW met1 ( 35673 221 ) ( 36501 * ) + NEW met1 ( 36501 187 ) ( * 221 ) + NEW met1 ( 35397 119 ) ( * 153 ) + NEW met1 ( 3197 153 ) ( 3473 * ) + NEW met1 ( 3473 153 ) ( * 221 ) + NEW met1 ( 2047 153 ) ( 2415 * ) + NEW met1 ( 2415 119 ) ( * 153 ) + NEW met1 ( 2415 119 ) ( 3197 * ) + NEW met1 ( 3197 119 ) ( * 153 ) + NEW met1 ( 2047 119 ) ( * 153 ) + NEW met1 ( 1265 119 ) ( 2047 * ) + NEW met1 ( 15111 119 ) ( 15847 * ) + NEW met1 ( 15111 85 ) ( * 119 ) + NEW met1 ( 14697 85 ) ( 15111 * ) + NEW met1 ( 14697 85 ) ( * 119 ) + NEW met1 ( 15847 119 ) ( * 153 ) + NEW met1 ( 15847 153 ) ( 16215 * ) + NEW met1 ( 34247 153 ) ( 34615 * ) + NEW met1 ( 34615 119 ) ( * 153 ) + NEW met1 ( 34247 119 ) ( * 153 ) + NEW met1 ( 34615 119 ) ( 35397 * ) + NEW met1 ( 20447 119 ) ( 21597 * ) + NEW met1 ( 21597 119 ) ( 22747 * ) + NEW met1 ( 19297 119 ) ( 20447 * ) + NEW met1 ( 33097 153 ) ( 33465 * ) + NEW met1 ( 33465 119 ) ( * 153 ) + NEW met1 ( 31947 153 ) ( 32315 * ) + NEW met1 ( 32315 119 ) ( * 153 ) + NEW met1 ( 32315 119 ) ( 33097 * ) + NEW met1 ( 33097 119 ) ( * 153 ) + NEW met1 ( 30797 153 ) ( * 187 ) + NEW met1 ( 30797 187 ) ( 30981 * ) + NEW met1 ( 30981 187 ) ( * 221 ) + NEW met1 ( 30981 221 ) ( 31947 * ) + NEW met1 ( 31947 153 ) ( * 221 ) + NEW met1 ( 29647 153 ) ( 30015 * ) + NEW met1 ( 30015 119 ) ( * 153 ) + NEW met1 ( 30015 119 ) ( 30797 * ) + NEW met1 ( 30797 119 ) ( * 153 ) + NEW met1 ( 29647 119 ) ( * 153 ) + NEW met1 ( 28865 119 ) ( 29647 * ) + NEW met1 ( 33465 119 ) ( 34247 * ) + NEW met2 ( 10097 102 ) ( * 119 ) + NEW met3 ( 9315 102 ) ( 10097 * ) + NEW met2 ( 9315 102 ) ( * 119 ) + NEW met1 ( 11247 119 ) ( * 153 ) + NEW met1 ( 10465 119 ) ( 11247 * ) + NEW met1 ( 10465 119 ) ( * 153 ) + NEW met1 ( 10097 153 ) ( 10465 * ) + NEW met1 ( 10097 119 ) ( * 153 ) + NEW met1 ( 11615 119 ) ( 12397 * ) + NEW met1 ( 11615 119 ) ( * 153 ) + NEW met1 ( 11247 153 ) ( 11615 * ) + NEW met1 ( 12397 119 ) ( 13547 * ) + NEW met1 ( 13547 119 ) ( 14697 * ) + NEW met1 ( 4347 153 ) ( * 221 ) + NEW met1 ( 4715 119 ) ( 5497 * ) + NEW met1 ( 4715 119 ) ( * 153 ) + NEW met1 ( 4347 153 ) ( 4715 * ) + NEW met1 ( 5865 119 ) ( 6647 * ) + NEW met1 ( 5865 119 ) ( * 153 ) + NEW met1 ( 5497 153 ) ( 5865 * ) + NEW met1 ( 5497 119 ) ( * 153 ) + NEW met2 ( 7797 102 ) ( * 119 ) + NEW met3 ( 7314 102 ) ( 7797 * ) + NEW met4 ( 7314 102 ) ( * 510 ) + NEW met4 ( 6578 510 ) ( 7314 * ) + NEW met4 ( 6578 34 ) ( * 510 ) + NEW met3 ( 6578 34 ) ( 6601 * ) + NEW met2 ( 6601 34 ) ( * 119 ) + NEW met1 ( 8165 119 ) ( 8947 * ) + NEW met1 ( 8165 119 ) ( * 153 ) + NEW met1 ( 7797 153 ) ( 8165 * ) + NEW met1 ( 7797 119 ) ( * 153 ) + NEW met1 ( 3473 221 ) ( 4347 * ) + NEW met1 ( 8947 119 ) ( 9315 * ) + NEW met1 ( 27347 153 ) ( 27715 * ) + NEW met1 ( 27715 119 ) ( * 153 ) + NEW met1 ( 26197 153 ) ( 26565 * ) + NEW met1 ( 26565 119 ) ( * 153 ) + NEW met1 ( 26565 119 ) ( 27347 * ) + NEW met1 ( 27347 119 ) ( * 153 ) + NEW met1 ( 25047 153 ) ( 25415 * ) + NEW met1 ( 25415 119 ) ( * 153 ) + NEW met1 ( 25415 119 ) ( 26197 * ) + NEW met1 ( 26197 119 ) ( * 153 ) + NEW met1 ( 23897 119 ) ( 24403 * ) + NEW met1 ( 24403 85 ) ( * 119 ) + NEW met1 ( 24403 85 ) ( 25047 * ) + NEW met1 ( 25047 85 ) ( * 153 ) + NEW met1 ( 22747 119 ) ( 23897 * ) + NEW met1 ( 27715 119 ) ( 28497 * ) + NEW met1 ( 36731 187 ) ( * 221 ) + NEW met1 ( 36731 221 ) ( 38019 * ) + NEW met2 ( 36593 119 ) ( * 187 ) + NEW met1 ( 36547 119 ) ( 36593 * ) + NEW met1 ( 36501 187 ) ( 36731 * ) + NEW li1 ( 897 153 ) L1M1_PR_MR + NEW li1 ( 16997 119 ) L1M1_PR_MR + NEW li1 ( 18147 153 ) L1M1_PR_MR + NEW li1 ( 19297 119 ) L1M1_PR_MR + NEW li1 ( 28497 153 ) L1M1_PR_MR + NEW li1 ( 36547 119 ) L1M1_PR_MR + NEW li1 ( 35397 153 ) L1M1_PR_MR + NEW li1 ( 3197 153 ) L1M1_PR_MR + NEW li1 ( 2047 153 ) L1M1_PR_MR + NEW li1 ( 14697 119 ) L1M1_PR_MR + NEW li1 ( 15847 119 ) L1M1_PR_MR + NEW li1 ( 34247 153 ) L1M1_PR_MR + NEW li1 ( 20447 119 ) L1M1_PR_MR + NEW li1 ( 21597 119 ) L1M1_PR_MR + NEW li1 ( 22747 119 ) L1M1_PR_MR + NEW li1 ( 33097 153 ) L1M1_PR_MR + NEW li1 ( 31947 153 ) L1M1_PR_MR + NEW li1 ( 30797 153 ) L1M1_PR_MR + NEW li1 ( 29647 153 ) L1M1_PR_MR + NEW li1 ( 10097 119 ) L1M1_PR_MR + NEW met1 ( 10097 119 ) M1M2_PR + NEW met2 ( 10097 102 ) M2M3_PR + NEW met2 ( 9315 102 ) M2M3_PR + NEW met1 ( 9315 119 ) M1M2_PR + NEW li1 ( 11247 153 ) L1M1_PR_MR + NEW li1 ( 12397 119 ) L1M1_PR_MR + NEW li1 ( 13547 119 ) L1M1_PR_MR + NEW li1 ( 4347 153 ) L1M1_PR_MR + NEW li1 ( 5497 119 ) L1M1_PR_MR + NEW li1 ( 6647 119 ) L1M1_PR_MR + NEW li1 ( 7797 119 ) L1M1_PR_MR + NEW met1 ( 7797 119 ) M1M2_PR + NEW met2 ( 7797 102 ) M2M3_PR + NEW met3 ( 7314 102 ) M3M4_PR + NEW met3 ( 6578 34 ) M3M4_PR + NEW met2 ( 6601 34 ) M2M3_PR + NEW met1 ( 6601 119 ) M1M2_PR + NEW li1 ( 8947 119 ) L1M1_PR_MR + NEW li1 ( 27347 153 ) L1M1_PR_MR + NEW li1 ( 26197 153 ) L1M1_PR_MR + NEW li1 ( 25047 153 ) L1M1_PR_MR + NEW li1 ( 23897 119 ) L1M1_PR_MR + NEW li1 ( 38019 221 ) L1M1_PR_MR + NEW met1 ( 36593 119 ) M1M2_PR + NEW met1 ( 36593 187 ) M1M2_PR + NEW met3 ( 6578 34 ) RECT ( -39 -15 0 15 ) ; + - row1.select0_b ( storage_1_3_0.bit7.obuf0 TE_B ) ( storage_1_3_0.bit6.obuf0 TE_B ) ( storage_1_3_0.bit5.obuf0 TE_B ) ( storage_1_3_0.bit4.obuf0 TE_B ) ( storage_1_3_0.bit3.obuf0 TE_B ) ( storage_1_3_0.bit2.obuf0 TE_B ) ( storage_1_3_0.bit1.obuf0 TE_B ) + ( storage_1_3_0.bit0.obuf0 TE_B ) ( storage_1_2_0.bit7.obuf0 TE_B ) ( storage_1_2_0.bit6.obuf0 TE_B ) ( storage_1_2_0.bit5.obuf0 TE_B ) ( storage_1_2_0.bit4.obuf0 TE_B ) ( storage_1_2_0.bit3.obuf0 TE_B ) ( storage_1_2_0.bit2.obuf0 TE_B ) ( storage_1_2_0.bit1.obuf0 TE_B ) + ( storage_1_2_0.bit0.obuf0 TE_B ) ( storage_1_1_0.bit7.obuf0 TE_B ) ( storage_1_1_0.bit6.obuf0 TE_B ) ( storage_1_1_0.bit5.obuf0 TE_B ) ( storage_1_1_0.bit4.obuf0 TE_B ) ( storage_1_1_0.bit3.obuf0 TE_B ) ( storage_1_1_0.bit2.obuf0 TE_B ) ( storage_1_1_0.bit1.obuf0 TE_B ) + ( storage_1_1_0.bit0.obuf0 TE_B ) ( storage_1_0_0.select_inv_0 Y ) ( storage_1_0_0.bit7.obuf0 TE_B ) ( storage_1_0_0.bit6.obuf0 TE_B ) ( storage_1_0_0.bit5.obuf0 TE_B ) ( storage_1_0_0.bit4.obuf0 TE_B ) ( storage_1_0_0.bit3.obuf0 TE_B ) ( storage_1_0_0.bit2.obuf0 TE_B ) + ( storage_1_0_0.bit1.obuf0 TE_B ) ( storage_1_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 19297 425 ) ( * 459 ) + NEW met1 ( 20447 425 ) ( * 493 ) + NEW met1 ( 20355 493 ) ( 20447 * ) + NEW met1 ( 20355 425 ) ( * 493 ) + NEW met1 ( 19297 425 ) ( 20355 * ) + NEW met1 ( 29647 391 ) ( 29785 * ) + NEW met1 ( 29785 323 ) ( * 391 ) + NEW met1 ( 28497 323 ) ( * 391 ) + NEW met1 ( 28497 323 ) ( 29647 * ) + NEW met1 ( 29647 323 ) ( * 391 ) + NEW met1 ( 35397 323 ) ( * 391 ) + NEW met1 ( 35397 323 ) ( 36547 * ) + NEW met1 ( 36547 323 ) ( * 391 ) + NEW met2 ( 21597 391 ) ( * 493 ) + NEW met1 ( 22747 323 ) ( * 391 ) + NEW met1 ( 21873 323 ) ( 22747 * ) + NEW met1 ( 21873 323 ) ( * 391 ) + NEW met1 ( 21597 391 ) ( 21873 * ) + NEW met1 ( 23069 323 ) ( * 357 ) + NEW met1 ( 22747 357 ) ( 23069 * ) + NEW met1 ( 20447 493 ) ( 21597 * ) + NEW met1 ( 34247 391 ) ( 34385 * ) + NEW met1 ( 34385 323 ) ( * 391 ) + NEW met1 ( 34385 323 ) ( 35029 * ) + NEW met1 ( 35029 323 ) ( * 357 ) + NEW met1 ( 33097 323 ) ( * 391 ) + NEW met1 ( 33097 323 ) ( 34247 * ) + NEW met1 ( 34247 323 ) ( * 391 ) + NEW met1 ( 31947 323 ) ( * 391 ) + NEW met1 ( 31947 323 ) ( 33097 * ) + NEW met1 ( 30797 391 ) ( 30981 * ) + NEW met1 ( 30981 323 ) ( * 391 ) + NEW met1 ( 30981 323 ) ( 31947 * ) + NEW met1 ( 30797 323 ) ( * 391 ) + NEW met1 ( 29785 323 ) ( 30797 * ) + NEW met1 ( 35029 357 ) ( 35397 * ) + NEW met1 ( 2047 425 ) ( * 459 ) + NEW met1 ( 897 459 ) ( 2047 * ) + NEW met1 ( 897 425 ) ( * 459 ) + NEW met1 ( 3197 425 ) ( * 459 ) + NEW met1 ( 2047 459 ) ( 3197 * ) + NEW met1 ( 3611 459 ) ( * 493 ) + NEW met1 ( 3519 459 ) ( 3611 * ) + NEW met1 ( 3519 425 ) ( * 459 ) + NEW met1 ( 3197 425 ) ( 3519 * ) + NEW met1 ( 10097 323 ) ( * 391 ) + NEW met1 ( 9223 323 ) ( 10097 * ) + NEW met2 ( 9223 323 ) ( * 391 ) + NEW met1 ( 11247 323 ) ( * 391 ) + NEW met1 ( 10097 323 ) ( 11247 * ) + NEW met1 ( 12121 425 ) ( 12397 * ) + NEW met2 ( 12121 238 ) ( * 425 ) + NEW met3 ( 11569 238 ) ( 12121 * ) + NEW met2 ( 11569 238 ) ( * 357 ) + NEW met1 ( 11569 357 ) ( * 391 ) + NEW met1 ( 11247 391 ) ( 11569 * ) + NEW met1 ( 13547 425 ) ( * 459 ) + NEW met1 ( 12397 459 ) ( 13547 * ) + NEW met1 ( 12397 425 ) ( * 459 ) + NEW met1 ( 3611 493 ) ( 4140 * ) + NEW met1 ( 4347 425 ) ( * 459 ) + NEW met1 ( 4140 459 ) ( 4347 * ) + NEW met1 ( 4140 459 ) ( * 493 ) + NEW met1 ( 5497 425 ) ( * 459 ) + NEW met1 ( 4347 459 ) ( 5497 * ) + NEW met1 ( 6647 425 ) ( * 459 ) + NEW met1 ( 5497 459 ) ( 6647 * ) + NEW met1 ( 7751 391 ) ( 7797 * ) + NEW met2 ( 7751 51 ) ( * 391 ) + NEW met1 ( 6923 51 ) ( 7751 * ) + NEW met2 ( 6877 51 ) ( 6923 * ) + NEW met2 ( 6877 51 ) ( * 425 ) + NEW met1 ( 6647 425 ) ( 6877 * ) + NEW met1 ( 8165 425 ) ( 8947 * ) + NEW met1 ( 8165 391 ) ( * 425 ) + NEW met1 ( 7797 391 ) ( 8165 * ) + NEW met1 ( 8947 391 ) ( * 425 ) + NEW met1 ( 8947 391 ) ( 9223 * ) + NEW met1 ( 14697 425 ) ( * 459 ) + NEW met1 ( 15847 425 ) ( * 459 ) + NEW met1 ( 14697 459 ) ( 15847 * ) + NEW met1 ( 16997 425 ) ( * 459 ) + NEW met1 ( 15847 459 ) ( 16997 * ) + NEW met1 ( 18147 425 ) ( * 459 ) + NEW met1 ( 17503 459 ) ( 18147 * ) + NEW met1 ( 17503 459 ) ( * 493 ) + NEW met1 ( 17319 493 ) ( 17503 * ) + NEW met1 ( 17319 459 ) ( * 493 ) + NEW met1 ( 16997 459 ) ( 17319 * ) + NEW met1 ( 13547 459 ) ( 14697 * ) + NEW met1 ( 18147 459 ) ( 19297 * ) + NEW met1 ( 27347 391 ) ( 27485 * ) + NEW met1 ( 27485 323 ) ( * 391 ) + NEW met1 ( 26197 323 ) ( * 391 ) + NEW met1 ( 26197 323 ) ( 27347 * ) + NEW met1 ( 27347 323 ) ( * 391 ) + NEW met1 ( 25047 357 ) ( * 391 ) + NEW met1 ( 25047 357 ) ( 25369 * ) + NEW met2 ( 25369 357 ) ( 25415 * ) + NEW met2 ( 25415 170 ) ( * 357 ) + NEW met3 ( 25415 170 ) ( 26197 * ) + NEW met2 ( 26197 170 ) ( * 323 ) + NEW met1 ( 23897 323 ) ( * 391 ) + NEW met1 ( 23897 323 ) ( 25047 * ) + NEW met1 ( 25047 323 ) ( * 357 ) + NEW met1 ( 23069 323 ) ( 23897 * ) + NEW met1 ( 27485 323 ) ( 28497 * ) + NEW met1 ( 36823 323 ) ( * 391 ) + NEW met1 ( 36823 323 ) ( 38019 * ) + NEW met1 ( 36547 391 ) ( 36823 * ) + NEW li1 ( 19297 425 ) L1M1_PR_MR + NEW li1 ( 20447 425 ) L1M1_PR_MR + NEW li1 ( 29647 391 ) L1M1_PR_MR + NEW li1 ( 28497 391 ) L1M1_PR_MR + NEW li1 ( 36547 391 ) L1M1_PR_MR + NEW li1 ( 35397 391 ) L1M1_PR_MR + NEW li1 ( 21597 391 ) L1M1_PR_MR + NEW met1 ( 21597 391 ) M1M2_PR + NEW met1 ( 21597 493 ) M1M2_PR + NEW li1 ( 22747 391 ) L1M1_PR_MR + NEW li1 ( 34247 391 ) L1M1_PR_MR + NEW li1 ( 33097 391 ) L1M1_PR_MR + NEW li1 ( 31947 391 ) L1M1_PR_MR + NEW li1 ( 30797 391 ) L1M1_PR_MR + NEW li1 ( 2047 425 ) L1M1_PR_MR + NEW li1 ( 897 425 ) L1M1_PR_MR + NEW li1 ( 3197 425 ) L1M1_PR_MR + NEW li1 ( 10097 391 ) L1M1_PR_MR + NEW met1 ( 9223 323 ) M1M2_PR + NEW met1 ( 9223 391 ) M1M2_PR + NEW li1 ( 11247 391 ) L1M1_PR_MR + NEW li1 ( 12397 425 ) L1M1_PR_MR + NEW met1 ( 12121 425 ) M1M2_PR + NEW met2 ( 12121 238 ) M2M3_PR + NEW met2 ( 11569 238 ) M2M3_PR + NEW met1 ( 11569 357 ) M1M2_PR + NEW li1 ( 13547 425 ) L1M1_PR_MR + NEW li1 ( 4347 425 ) L1M1_PR_MR + NEW li1 ( 5497 425 ) L1M1_PR_MR + NEW li1 ( 6647 425 ) L1M1_PR_MR + NEW li1 ( 7797 391 ) L1M1_PR_MR + NEW met1 ( 7751 391 ) M1M2_PR + NEW met1 ( 7751 51 ) M1M2_PR + NEW met1 ( 6923 51 ) M1M2_PR + NEW met1 ( 6877 425 ) M1M2_PR + NEW li1 ( 8947 425 ) L1M1_PR_MR + NEW li1 ( 14697 425 ) L1M1_PR_MR + NEW li1 ( 15847 425 ) L1M1_PR_MR + NEW li1 ( 16997 425 ) L1M1_PR_MR + NEW li1 ( 18147 425 ) L1M1_PR_MR + NEW li1 ( 27347 391 ) L1M1_PR_MR + NEW li1 ( 26197 391 ) L1M1_PR_MR + NEW li1 ( 25047 391 ) L1M1_PR_MR + NEW met1 ( 25369 357 ) M1M2_PR + NEW met2 ( 25415 170 ) M2M3_PR + NEW met2 ( 26197 170 ) M2M3_PR + NEW met1 ( 26197 323 ) M1M2_PR + NEW li1 ( 23897 391 ) L1M1_PR_MR + NEW li1 ( 38019 323 ) L1M1_PR_MR ; + - storage_0_0_0.bit0.storage ( storage_0_0_0.bit0.obuf0 A ) ( storage_0_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 805 153 ) ( * 187 ) + NEW met1 ( 759 187 ) ( 805 * ) + NEW li1 ( 805 153 ) L1M1_PR_MR + NEW li1 ( 759 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit1.storage ( storage_0_0_0.bit1.obuf0 A ) ( storage_0_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5405 153 ) ( * 187 ) + NEW met1 ( 5359 187 ) ( 5405 * ) + NEW li1 ( 5405 153 ) L1M1_PR_MR + NEW li1 ( 5359 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit2.storage ( storage_0_0_0.bit2.obuf0 A ) ( storage_0_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 10005 153 ) ( * 187 ) + NEW met1 ( 9959 187 ) ( 10005 * ) + NEW li1 ( 10005 153 ) L1M1_PR_MR + NEW li1 ( 9959 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit3.storage ( storage_0_0_0.bit3.obuf0 A ) ( storage_0_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 14605 153 ) ( * 187 ) + NEW met1 ( 14559 187 ) ( 14605 * ) + NEW li1 ( 14605 153 ) L1M1_PR_MR + NEW li1 ( 14559 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit4.storage ( storage_0_0_0.bit4.obuf0 A ) ( storage_0_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 19205 153 ) ( * 187 ) + NEW met1 ( 19159 187 ) ( 19205 * ) + NEW li1 ( 19205 153 ) L1M1_PR_MR + NEW li1 ( 19159 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit5.storage ( storage_0_0_0.bit5.obuf0 A ) ( storage_0_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 23805 153 ) ( * 187 ) + NEW met1 ( 23759 187 ) ( 23805 * ) + NEW li1 ( 23805 153 ) L1M1_PR_MR + NEW li1 ( 23759 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit6.storage ( storage_0_0_0.bit6.obuf0 A ) ( storage_0_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 28405 153 ) ( * 187 ) + NEW met1 ( 28359 187 ) ( 28405 * ) + NEW li1 ( 28405 153 ) L1M1_PR_MR + NEW li1 ( 28359 187 ) L1M1_PR_MR ; + - storage_0_0_0.bit7.storage ( storage_0_0_0.bit7.obuf0 A ) ( storage_0_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 33005 153 ) ( * 187 ) + NEW met1 ( 32959 187 ) ( 33005 * ) + NEW li1 ( 33005 153 ) L1M1_PR_MR + NEW li1 ( 32959 187 ) L1M1_PR_MR ; + - storage_0_0_0.gclock ( storage_0_0_0.cg GCLK ) ( storage_0_0_0.bit7.bit CLK ) ( storage_0_0_0.bit6.bit CLK ) ( storage_0_0_0.bit5.bit CLK ) ( storage_0_0_0.bit4.bit CLK ) ( storage_0_0_0.bit3.bit CLK ) ( storage_0_0_0.bit2.bit CLK ) + ( storage_0_0_0.bit1.bit CLK ) ( storage_0_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 69 153 ) ( * 221 ) + NEW met1 ( 9039 153 ) ( 9269 * ) + NEW met1 ( 9039 153 ) ( * 221 ) + NEW met1 ( 9269 153 ) ( * 221 ) + NEW met1 ( 27669 51 ) ( * 119 ) + NEW met1 ( 35765 85 ) ( * 119 ) + NEW met1 ( 35765 119 ) ( 36501 * ) + NEW met1 ( 36501 119 ) ( * 153 ) + NEW met2 ( 2093 51 ) ( * 221 ) + NEW met1 ( 69 221 ) ( 2093 * ) + NEW met1 ( 34431 51 ) ( * 85 ) + NEW met1 ( 34431 51 ) ( 34753 * ) + NEW met1 ( 34753 51 ) ( * 85 ) + NEW met1 ( 34753 85 ) ( 35765 * ) + NEW met1 ( 13593 153 ) ( * 221 ) + NEW met1 ( 12719 221 ) ( 13593 * ) + NEW met1 ( 12719 187 ) ( * 221 ) + NEW met1 ( 12581 187 ) ( 12719 * ) + NEW met1 ( 12581 187 ) ( * 221 ) + NEW met1 ( 11569 221 ) ( 12581 * ) + NEW met1 ( 11569 187 ) ( * 221 ) + NEW met1 ( 11201 187 ) ( 11569 * ) + NEW met2 ( 11201 85 ) ( * 187 ) + NEW met1 ( 10879 85 ) ( 11201 * ) + NEW met1 ( 10879 51 ) ( * 85 ) + NEW met1 ( 10465 51 ) ( 10879 * ) + NEW met1 ( 10465 51 ) ( * 85 ) + NEW met1 ( 10281 85 ) ( 10465 * ) + NEW met2 ( 10281 85 ) ( * 221 ) + NEW met1 ( 9269 221 ) ( 10281 * ) + NEW met1 ( 22793 153 ) ( 23069 * ) + NEW met1 ( 22793 153 ) ( * 221 ) + NEW met1 ( 21919 221 ) ( 22793 * ) + NEW met1 ( 21919 187 ) ( * 221 ) + NEW met1 ( 21781 187 ) ( 21919 * ) + NEW met1 ( 21781 187 ) ( * 221 ) + NEW met1 ( 20769 221 ) ( 21781 * ) + NEW met1 ( 20769 187 ) ( * 221 ) + NEW met1 ( 20585 187 ) ( 20769 * ) + NEW met2 ( 20585 51 ) ( * 187 ) + NEW met2 ( 23069 51 ) ( * 153 ) + NEW met1 ( 23069 51 ) ( 27669 * ) + NEW met1 ( 31349 119 ) ( 32269 * ) + NEW met1 ( 31349 85 ) ( * 119 ) + NEW met2 ( 31349 34 ) ( * 85 ) + NEW met2 ( 31211 34 ) ( 31349 * ) + NEW met2 ( 31211 34 ) ( * 85 ) + NEW met2 ( 31165 85 ) ( 31211 * ) + NEW met1 ( 31027 85 ) ( 31165 * ) + NEW met1 ( 31027 51 ) ( * 85 ) + NEW met2 ( 33787 85 ) ( * 102 ) + NEW met3 ( 32269 102 ) ( 33787 * ) + NEW met2 ( 32269 102 ) ( * 119 ) + NEW met1 ( 27669 51 ) ( 31027 * ) + NEW met1 ( 33787 85 ) ( 34431 * ) + NEW met2 ( 4669 34 ) ( * 119 ) + NEW met3 ( 4669 34 ) ( 4738 * ) + NEW met4 ( 4738 34 ) ( * 170 ) + NEW met5 ( 4738 170 ) ( 7866 * ) + NEW met4 ( 7866 102 ) ( * 170 ) + NEW met3 ( 7866 102 ) ( 8211 * ) + NEW met2 ( 8211 102 ) ( * 221 ) + NEW met1 ( 2093 51 ) ( 4669 * ) + NEW met1 ( 8211 221 ) ( 9039 * ) + NEW met1 ( 18469 51 ) ( * 119 ) + NEW met1 ( 13869 153 ) ( * 221 ) + NEW met1 ( 13869 221 ) ( 14651 * ) + NEW met1 ( 14651 187 ) ( * 221 ) + NEW met1 ( 14651 187 ) ( 14973 * ) + NEW met1 ( 14973 187 ) ( * 221 ) + NEW met1 ( 14973 221 ) ( 15939 * ) + NEW met2 ( 15939 34 ) ( * 221 ) + NEW met3 ( 15939 34 ) ( 17595 * ) + NEW met2 ( 17595 34 ) ( * 51 ) + NEW met1 ( 17595 51 ) ( 18469 * ) + NEW met1 ( 13593 153 ) ( 13869 * ) + NEW met1 ( 18469 51 ) ( 20585 * ) + NEW met1 ( 36777 153 ) ( * 187 ) + NEW met1 ( 36777 187 ) ( 37467 * ) + NEW met1 ( 36501 153 ) ( 36777 * ) + NEW li1 ( 69 153 ) L1M1_PR_MR + NEW li1 ( 9269 153 ) L1M1_PR_MR + NEW li1 ( 27669 119 ) L1M1_PR_MR + NEW met1 ( 2093 51 ) M1M2_PR + NEW met1 ( 2093 221 ) M1M2_PR + NEW met1 ( 11201 187 ) M1M2_PR + NEW met1 ( 11201 85 ) M1M2_PR + NEW met1 ( 10281 85 ) M1M2_PR + NEW met1 ( 10281 221 ) M1M2_PR + NEW li1 ( 23069 153 ) L1M1_PR_MR + NEW met1 ( 20585 187 ) M1M2_PR + NEW met1 ( 20585 51 ) M1M2_PR + NEW met1 ( 23069 51 ) M1M2_PR + NEW met1 ( 23069 153 ) M1M2_PR + NEW li1 ( 32269 119 ) L1M1_PR_MR + NEW met1 ( 31349 85 ) M1M2_PR + NEW met1 ( 31165 85 ) M1M2_PR + NEW met1 ( 33787 85 ) M1M2_PR + NEW met2 ( 33787 102 ) M2M3_PR + NEW met2 ( 32269 102 ) M2M3_PR + NEW met1 ( 32269 119 ) M1M2_PR + NEW li1 ( 4669 119 ) L1M1_PR_MR + NEW met1 ( 4669 119 ) M1M2_PR + NEW met2 ( 4669 34 ) M2M3_PR + NEW met3 ( 4738 34 ) M3M4_PR + NEW met4 ( 4738 170 ) M4M5_PR + NEW met4 ( 7866 170 ) M4M5_PR + NEW met3 ( 7866 102 ) M3M4_PR + NEW met2 ( 8211 102 ) M2M3_PR + NEW met1 ( 8211 221 ) M1M2_PR + NEW met1 ( 4669 51 ) M1M2_PR + NEW li1 ( 18469 119 ) L1M1_PR_MR + NEW li1 ( 13869 153 ) L1M1_PR_MR + NEW met1 ( 15939 221 ) M1M2_PR + NEW met2 ( 15939 34 ) M2M3_PR + NEW met2 ( 17595 34 ) M2M3_PR + NEW met1 ( 17595 51 ) M1M2_PR + NEW li1 ( 37467 187 ) L1M1_PR_MR ; + - storage_0_0_0.we0 ( storage_0_0_0.gcand X ) ( storage_0_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 37053 85 ) ( 37329 * ) + NEW met2 ( 37329 34 ) ( * 85 ) + NEW met2 ( 37329 34 ) ( 37421 * ) + NEW met2 ( 37421 34 ) ( * 85 ) + NEW met1 ( 37421 85 ) ( 37927 * ) + NEW li1 ( 37053 85 ) L1M1_PR_MR + NEW met1 ( 37329 85 ) M1M2_PR + NEW met1 ( 37421 85 ) M1M2_PR + NEW li1 ( 37927 85 ) L1M1_PR_MR ; + - storage_0_0_0.write_sel ( storage_0_0_0.gcand A ) ( storage_0_0_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 37697 153 ) ( 37743 * ) + NEW li1 ( 37743 153 ) L1M1_PR_MR + NEW li1 ( 37697 153 ) L1M1_PR_MR ; + - storage_0_1_0.bit0.storage ( storage_0_1_0.bit0.obuf0 A ) ( storage_0_1_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1955 153 ) ( * 187 ) + NEW met1 ( 1909 187 ) ( 1955 * ) + NEW li1 ( 1955 153 ) L1M1_PR_MR + NEW li1 ( 1909 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit1.storage ( storage_0_1_0.bit1.obuf0 A ) ( storage_0_1_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6555 153 ) ( * 187 ) + NEW met1 ( 6509 187 ) ( 6555 * ) + NEW li1 ( 6555 153 ) L1M1_PR_MR + NEW li1 ( 6509 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit2.storage ( storage_0_1_0.bit2.obuf0 A ) ( storage_0_1_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 11155 153 ) ( * 187 ) + NEW met1 ( 11109 187 ) ( 11155 * ) + NEW li1 ( 11155 153 ) L1M1_PR_MR + NEW li1 ( 11109 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit3.storage ( storage_0_1_0.bit3.obuf0 A ) ( storage_0_1_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 15755 153 ) ( * 187 ) + NEW met1 ( 15709 187 ) ( 15755 * ) + NEW li1 ( 15755 153 ) L1M1_PR_MR + NEW li1 ( 15709 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit4.storage ( storage_0_1_0.bit4.obuf0 A ) ( storage_0_1_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 20355 153 ) ( * 187 ) + NEW met1 ( 20309 187 ) ( 20355 * ) + NEW li1 ( 20355 153 ) L1M1_PR_MR + NEW li1 ( 20309 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit5.storage ( storage_0_1_0.bit5.obuf0 A ) ( storage_0_1_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 24954 153 ) ( 24955 * ) + NEW met1 ( 24955 153 ) ( * 187 ) + NEW met1 ( 24909 187 ) ( 24955 * ) + NEW li1 ( 24954 153 ) L1M1_PR_MR + NEW li1 ( 24909 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit6.storage ( storage_0_1_0.bit6.obuf0 A ) ( storage_0_1_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 29555 153 ) ( * 187 ) + NEW met1 ( 29509 187 ) ( 29555 * ) + NEW li1 ( 29555 153 ) L1M1_PR_MR + NEW li1 ( 29509 187 ) L1M1_PR_MR ; + - storage_0_1_0.bit7.storage ( storage_0_1_0.bit7.obuf0 A ) ( storage_0_1_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 34155 153 ) ( * 187 ) + NEW met1 ( 34109 187 ) ( 34155 * ) + NEW li1 ( 34155 153 ) L1M1_PR_MR + NEW li1 ( 34109 187 ) L1M1_PR_MR ; + - storage_0_1_0.gclock ( storage_0_1_0.cg GCLK ) ( storage_0_1_0.bit7.bit CLK ) ( storage_0_1_0.bit6.bit CLK ) ( storage_0_1_0.bit5.bit CLK ) ( storage_0_1_0.bit4.bit CLK ) ( storage_0_1_0.bit3.bit CLK ) ( storage_0_1_0.bit2.bit CLK ) + ( storage_0_1_0.bit1.bit CLK ) ( storage_0_1_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met2 ( 1219 119 ) ( * 170 ) + NEW met2 ( 10419 119 ) ( * 170 ) + NEW met2 ( 10925 51 ) ( * 170 ) + NEW met3 ( 10419 170 ) ( 10925 * ) + NEW met2 ( 19619 153 ) ( * 238 ) + NEW met1 ( 28681 119 ) ( 28819 * ) + NEW met2 ( 28681 119 ) ( * 221 ) + NEW met1 ( 27669 221 ) ( 28681 * ) + NEW met1 ( 27669 187 ) ( * 221 ) + NEW met1 ( 27393 187 ) ( 27669 * ) + NEW met1 ( 27393 187 ) ( * 221 ) + NEW met1 ( 26519 221 ) ( 27393 * ) + NEW met1 ( 26519 187 ) ( * 221 ) + NEW met1 ( 26381 187 ) ( 26519 * ) + NEW met1 ( 26381 187 ) ( * 221 ) + NEW met2 ( 5819 119 ) ( * 170 ) + NEW met3 ( 1219 170 ) ( 10419 * ) + NEW met3 ( 15870 238 ) ( 19619 * ) + NEW met1 ( 14881 119 ) ( 15019 * ) + NEW met2 ( 14881 51 ) ( * 119 ) + NEW met1 ( 12903 51 ) ( 14881 * ) + NEW met2 ( 12903 34 ) ( * 51 ) + NEW met3 ( 11661 34 ) ( 12903 * ) + NEW met2 ( 11661 34 ) ( * 51 ) + NEW met4 ( 15870 34 ) ( * 238 ) + NEW met3 ( 14881 34 ) ( 15870 * ) + NEW met2 ( 14881 34 ) ( * 51 ) + NEW met1 ( 10925 51 ) ( 11661 * ) + NEW met2 ( 24219 153 ) ( * 238 ) + NEW met1 ( 25369 187 ) ( * 221 ) + NEW met1 ( 25093 187 ) ( 25369 * ) + NEW met1 ( 25093 187 ) ( * 221 ) + NEW met1 ( 24219 221 ) ( 25093 * ) + NEW met3 ( 19619 238 ) ( 24219 * ) + NEW met1 ( 25369 221 ) ( 26381 * ) + NEW met2 ( 33419 119 ) ( * 170 ) + NEW met3 ( 28681 170 ) ( 33419 * ) + NEW met2 ( 38755 153 ) ( * 170 ) + NEW met3 ( 33419 170 ) ( 38755 * ) + NEW met2 ( 1219 170 ) M2M3_PR + NEW li1 ( 1219 119 ) L1M1_PR_MR + NEW met1 ( 1219 119 ) M1M2_PR + NEW li1 ( 10419 119 ) L1M1_PR_MR + NEW met1 ( 10419 119 ) M1M2_PR + NEW met2 ( 10419 170 ) M2M3_PR + NEW met1 ( 10925 51 ) M1M2_PR + NEW met2 ( 10925 170 ) M2M3_PR + NEW li1 ( 19619 153 ) L1M1_PR_MR + NEW met1 ( 19619 153 ) M1M2_PR + NEW met2 ( 19619 238 ) M2M3_PR + NEW li1 ( 28819 119 ) L1M1_PR_MR + NEW met1 ( 28681 119 ) M1M2_PR + NEW met1 ( 28681 221 ) M1M2_PR + NEW met2 ( 28681 170 ) M2M3_PR + NEW li1 ( 5819 119 ) L1M1_PR_MR + NEW met1 ( 5819 119 ) M1M2_PR + NEW met2 ( 5819 170 ) M2M3_PR + NEW li1 ( 15019 119 ) L1M1_PR_MR + NEW met1 ( 14881 119 ) M1M2_PR + NEW met1 ( 14881 51 ) M1M2_PR + NEW met1 ( 12903 51 ) M1M2_PR + NEW met2 ( 12903 34 ) M2M3_PR + NEW met2 ( 11661 34 ) M2M3_PR + NEW met1 ( 11661 51 ) M1M2_PR + NEW met3 ( 15870 238 ) M3M4_PR + NEW met3 ( 15870 34 ) M3M4_PR + NEW met2 ( 14881 34 ) M2M3_PR + NEW li1 ( 24219 153 ) L1M1_PR_MR + NEW met1 ( 24219 153 ) M1M2_PR + NEW met2 ( 24219 238 ) M2M3_PR + NEW met1 ( 24219 221 ) M1M2_PR + NEW li1 ( 33419 119 ) L1M1_PR_MR + NEW met1 ( 33419 119 ) M1M2_PR + NEW met2 ( 33419 170 ) M2M3_PR + NEW met2 ( 38755 170 ) M2M3_PR + NEW li1 ( 38755 153 ) L1M1_PR_MR + NEW met1 ( 38755 153 ) M1M2_PR + NEW met3 ( 5819 170 ) RECT ( -62 -15 0 15 ) ; + - storage_0_1_0.we0 ( storage_0_1_0.gcand X ) ( storage_0_1_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 38341 51 ) ( 38617 * ) + NEW met2 ( 38617 34 ) ( * 51 ) + NEW met2 ( 38617 34 ) ( 38755 * ) + NEW met2 ( 38755 34 ) ( * 51 ) + NEW met1 ( 38755 51 ) ( 39215 * ) + NEW li1 ( 38341 51 ) L1M1_PR_MR + NEW met1 ( 38617 51 ) M1M2_PR + NEW met1 ( 38755 51 ) M1M2_PR + NEW li1 ( 39215 51 ) L1M1_PR_MR ; + - storage_0_1_0.write_sel ( storage_0_1_0.gcand A ) ( storage_0_1_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 38985 153 ) ( 39031 * ) + NEW li1 ( 39031 153 ) L1M1_PR_MR + NEW li1 ( 38985 153 ) L1M1_PR_MR ; + - storage_0_2_0.bit0.storage ( storage_0_2_0.bit0.obuf0 A ) ( storage_0_2_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3105 153 ) ( * 187 ) + NEW met1 ( 3059 187 ) ( 3105 * ) + NEW li1 ( 3105 153 ) L1M1_PR_MR + NEW li1 ( 3059 187 ) L1M1_PR_MR ; + - storage_0_2_0.bit1.storage ( storage_0_2_0.bit1.obuf0 A ) ( storage_0_2_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7705 153 ) ( * 187 ) + NEW met1 ( 7659 187 ) ( 7705 * ) + NEW li1 ( 7705 153 ) L1M1_PR_MR + NEW li1 ( 7659 187 ) L1M1_PR_MR ; + - storage_0_2_0.bit2.storage ( storage_0_2_0.bit2.obuf0 A ) ( storage_0_2_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 12305 153 ) ( * 187 ) + NEW met1 ( 12259 187 ) ( 12305 * ) + NEW li1 ( 12305 153 ) L1M1_PR_MR + NEW li1 ( 12259 187 ) L1M1_PR_MR ; + - storage_0_2_0.bit3.storage ( storage_0_2_0.bit3.obuf0 A ) ( storage_0_2_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 16905 153 ) ( * 187 ) + NEW met1 ( 16859 187 ) ( 16905 * ) + NEW li1 ( 16905 153 ) L1M1_PR_MR + NEW li1 ( 16859 187 ) L1M1_PR_MR ; + - storage_0_2_0.bit4.storage ( storage_0_2_0.bit4.obuf0 A ) ( storage_0_2_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 21505 153 ) ( * 187 ) + NEW met1 ( 21459 187 ) ( 21505 * ) + NEW li1 ( 21505 153 ) L1M1_PR_MR + NEW li1 ( 21459 187 ) L1M1_PR_MR ; + - storage_0_2_0.bit5.storage ( storage_0_2_0.bit5.obuf0 A ) ( storage_0_2_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 26105 153 ) ( * 187 ) + NEW met1 ( 26059 187 ) ( 26105 * ) + NEW li1 ( 26105 153 ) L1M1_PR_MR + NEW li1 ( 26059 187 ) L1M1_PR_MR ; + - storage_0_2_0.bit6.storage ( storage_0_2_0.bit6.obuf0 A ) ( storage_0_2_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 30705 153 ) ( * 187 ) + NEW met1 ( 30659 187 ) ( 30705 * ) + NEW li1 ( 30705 153 ) L1M1_PR_MR + NEW li1 ( 30659 187 ) L1M1_PR_MR ; + - storage_0_2_0.bit7.storage ( storage_0_2_0.bit7.obuf0 A ) ( storage_0_2_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 35305 153 ) ( * 187 ) + NEW met1 ( 35259 187 ) ( 35305 * ) + NEW li1 ( 35305 153 ) L1M1_PR_MR + NEW li1 ( 35259 187 ) L1M1_PR_MR ; + - storage_0_2_0.gclock ( storage_0_2_0.cg GCLK ) ( storage_0_2_0.bit7.bit CLK ) ( storage_0_2_0.bit6.bit CLK ) ( storage_0_2_0.bit5.bit CLK ) ( storage_0_2_0.bit4.bit CLK ) ( storage_0_2_0.bit3.bit CLK ) ( storage_0_2_0.bit2.bit CLK ) + ( storage_0_2_0.bit1.bit CLK ) ( storage_0_2_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met2 ( 10373 51 ) ( * 221 ) + NEW met2 ( 16169 102 ) ( * 119 ) + NEW met1 ( 29923 119 ) ( 29969 * ) + NEW met2 ( 29923 119 ) ( * 238 ) + NEW met2 ( 2369 102 ) ( * 119 ) + NEW met2 ( 11569 102 ) ( * 119 ) + NEW met2 ( 11293 119 ) ( * 221 ) + NEW met1 ( 11293 119 ) ( 11569 * ) + NEW met1 ( 10373 221 ) ( 11293 * ) + NEW met2 ( 34569 119 ) ( * 238 ) + NEW met2 ( 35167 51 ) ( * 238 ) + NEW met3 ( 34569 238 ) ( 35167 * ) + NEW met2 ( 20769 153 ) ( 20861 * ) + NEW met2 ( 20861 51 ) ( * 153 ) + NEW met1 ( 20861 51 ) ( 22287 * ) + NEW met2 ( 22287 51 ) ( * 493 ) + NEW met2 ( 20401 102 ) ( * 153 ) + NEW met1 ( 20401 153 ) ( 20769 * ) + NEW met3 ( 11569 102 ) ( 20401 * ) + NEW met1 ( 6923 119 ) ( 6969 * ) + NEW met2 ( 6923 102 ) ( * 119 ) + NEW met2 ( 8947 34 ) ( * 51 ) + NEW met3 ( 7222 34 ) ( 8947 * ) + NEW met3 ( 7222 34 ) ( * 85 ) + NEW met3 ( 6946 85 ) ( 7222 * ) + NEW met3 ( 6946 85 ) ( * 102 ) + NEW met3 ( 6923 102 ) ( 6946 * ) + NEW met3 ( 2369 102 ) ( 6923 * ) + NEW met1 ( 8947 51 ) ( 10373 * ) + NEW met2 ( 25369 119 ) ( * 238 ) + NEW met2 ( 23851 153 ) ( * 493 ) + NEW met1 ( 23851 153 ) ( 24173 * ) + NEW met2 ( 24173 102 ) ( * 153 ) + NEW met2 ( 24173 102 ) ( 24265 * ) + NEW met2 ( 24265 102 ) ( * 238 ) + NEW met2 ( 24265 238 ) ( 24311 * ) + NEW met3 ( 24311 238 ) ( 25369 * ) + NEW met1 ( 22287 493 ) ( 23851 * ) + NEW met3 ( 25369 238 ) ( 34569 * ) + NEW met2 ( 37881 51 ) ( * 187 ) + NEW met1 ( 37881 187 ) ( 39905 * ) + NEW met1 ( 35167 51 ) ( 37881 * ) + NEW met1 ( 10373 51 ) M1M2_PR + NEW met1 ( 10373 221 ) M1M2_PR + NEW li1 ( 16169 119 ) L1M1_PR_MR + NEW met1 ( 16169 119 ) M1M2_PR + NEW met2 ( 16169 102 ) M2M3_PR + NEW li1 ( 29969 119 ) L1M1_PR_MR + NEW met1 ( 29923 119 ) M1M2_PR + NEW met2 ( 29923 238 ) M2M3_PR + NEW met2 ( 2369 102 ) M2M3_PR + NEW li1 ( 2369 119 ) L1M1_PR_MR + NEW met1 ( 2369 119 ) M1M2_PR + NEW li1 ( 11569 119 ) L1M1_PR_MR + NEW met1 ( 11569 119 ) M1M2_PR + NEW met2 ( 11569 102 ) M2M3_PR + NEW met1 ( 11293 221 ) M1M2_PR + NEW met1 ( 11293 119 ) M1M2_PR + NEW li1 ( 34569 119 ) L1M1_PR_MR + NEW met1 ( 34569 119 ) M1M2_PR + NEW met2 ( 34569 238 ) M2M3_PR + NEW met1 ( 35167 51 ) M1M2_PR + NEW met2 ( 35167 238 ) M2M3_PR + NEW li1 ( 20769 153 ) L1M1_PR_MR + NEW met1 ( 20769 153 ) M1M2_PR + NEW met1 ( 20861 51 ) M1M2_PR + NEW met1 ( 22287 51 ) M1M2_PR + NEW met1 ( 22287 493 ) M1M2_PR + NEW met2 ( 20401 102 ) M2M3_PR + NEW met1 ( 20401 153 ) M1M2_PR + NEW li1 ( 6969 119 ) L1M1_PR_MR + NEW met1 ( 6923 119 ) M1M2_PR + NEW met2 ( 6923 102 ) M2M3_PR + NEW met1 ( 8947 51 ) M1M2_PR + NEW met2 ( 8947 34 ) M2M3_PR + NEW li1 ( 25369 119 ) L1M1_PR_MR + NEW met1 ( 25369 119 ) M1M2_PR + NEW met2 ( 25369 238 ) M2M3_PR + NEW met1 ( 23851 493 ) M1M2_PR + NEW met1 ( 23851 153 ) M1M2_PR + NEW met1 ( 24173 153 ) M1M2_PR + NEW met2 ( 24311 238 ) M2M3_PR + NEW met1 ( 37881 51 ) M1M2_PR + NEW met1 ( 37881 187 ) M1M2_PR + NEW li1 ( 39905 187 ) L1M1_PR_MR + NEW met3 ( 16169 102 ) RECT ( -62 -15 0 15 ) + NEW met3 ( 29923 238 ) RECT ( -62 -15 0 15 ) ; + - storage_0_2_0.we0 ( storage_0_2_0.gcand X ) ( storage_0_2_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 39491 85 ) ( 40365 * ) + NEW li1 ( 39491 85 ) L1M1_PR_MR + NEW li1 ( 40365 85 ) L1M1_PR_MR ; + - storage_0_2_0.write_sel ( storage_0_2_0.gcand A ) ( storage_0_2_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 40135 153 ) ( 40181 * ) + NEW li1 ( 40181 153 ) L1M1_PR_MR + NEW li1 ( 40135 153 ) L1M1_PR_MR ; + - storage_0_3_0.bit0.storage ( storage_0_3_0.bit0.obuf0 A ) ( storage_0_3_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4255 153 ) ( * 187 ) + NEW met1 ( 4209 187 ) ( 4255 * ) + NEW li1 ( 4255 153 ) L1M1_PR_MR + NEW li1 ( 4209 187 ) L1M1_PR_MR ; + - storage_0_3_0.bit1.storage ( storage_0_3_0.bit1.obuf0 A ) ( storage_0_3_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8855 153 ) ( * 187 ) + NEW met1 ( 8809 187 ) ( 8855 * ) + NEW li1 ( 8855 153 ) L1M1_PR_MR + NEW li1 ( 8809 187 ) L1M1_PR_MR ; + - storage_0_3_0.bit2.storage ( storage_0_3_0.bit2.obuf0 A ) ( storage_0_3_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 13455 153 ) ( * 187 ) + NEW met1 ( 13409 187 ) ( 13455 * ) + NEW li1 ( 13455 153 ) L1M1_PR_MR + NEW li1 ( 13409 187 ) L1M1_PR_MR ; + - storage_0_3_0.bit3.storage ( storage_0_3_0.bit3.obuf0 A ) ( storage_0_3_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 18055 153 ) ( * 187 ) + NEW met1 ( 18009 187 ) ( 18055 * ) + NEW li1 ( 18055 153 ) L1M1_PR_MR + NEW li1 ( 18009 187 ) L1M1_PR_MR ; + - storage_0_3_0.bit4.storage ( storage_0_3_0.bit4.obuf0 A ) ( storage_0_3_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 22655 153 ) ( * 187 ) + NEW met1 ( 22609 187 ) ( 22655 * ) + NEW li1 ( 22655 153 ) L1M1_PR_MR + NEW li1 ( 22609 187 ) L1M1_PR_MR ; + - storage_0_3_0.bit5.storage ( storage_0_3_0.bit5.obuf0 A ) ( storage_0_3_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 27255 153 ) ( * 187 ) + NEW met1 ( 27209 187 ) ( 27255 * ) + NEW li1 ( 27255 153 ) L1M1_PR_MR + NEW li1 ( 27209 187 ) L1M1_PR_MR ; + - storage_0_3_0.bit6.storage ( storage_0_3_0.bit6.obuf0 A ) ( storage_0_3_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 31855 153 ) ( * 187 ) + NEW met1 ( 31809 187 ) ( 31855 * ) + NEW li1 ( 31855 153 ) L1M1_PR_MR + NEW li1 ( 31809 187 ) L1M1_PR_MR ; + - storage_0_3_0.bit7.storage ( storage_0_3_0.bit7.obuf0 A ) ( storage_0_3_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 36455 153 ) ( * 187 ) + NEW met1 ( 36409 187 ) ( 36455 * ) + NEW li1 ( 36455 153 ) L1M1_PR_MR + NEW li1 ( 36409 187 ) L1M1_PR_MR ; + - storage_0_3_0.gclock ( storage_0_3_0.cg GCLK ) ( storage_0_3_0.bit7.bit CLK ) ( storage_0_3_0.bit6.bit CLK ) ( storage_0_3_0.bit5.bit CLK ) ( storage_0_3_0.bit4.bit CLK ) ( storage_0_3_0.bit3.bit CLK ) ( storage_0_3_0.bit2.bit CLK ) + ( storage_0_3_0.bit1.bit CLK ) ( storage_0_3_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met2 ( 8119 119 ) ( * 238 ) + NEW met2 ( 19435 731 ) ( * 782 ) + NEW met1 ( 26427 119 ) ( 26519 * ) + NEW met2 ( 26427 102 ) ( * 119 ) + NEW met2 ( 35719 102 ) ( * 119 ) + NEW met2 ( 35443 119 ) ( * 221 ) + NEW met1 ( 35443 119 ) ( 35719 * ) + NEW met2 ( 4117 119 ) ( * 238 ) + NEW met1 ( 3519 119 ) ( 4117 * ) + NEW met3 ( 4117 238 ) ( 8119 * ) + NEW met3 ( 8119 238 ) ( 11040 * ) + NEW met2 ( 12719 153 ) ( * 170 ) + NEW met3 ( 11040 170 ) ( * 238 ) + NEW met3 ( 11040 170 ) ( 12719 * ) + NEW met2 ( 21919 102 ) ( * 153 ) + NEW met2 ( 21643 153 ) ( * 782 ) + NEW met1 ( 21643 153 ) ( 21919 * ) + NEW met3 ( 19435 782 ) ( 21643 * ) + NEW met3 ( 21919 102 ) ( 26427 * ) + NEW met2 ( 34385 51 ) ( * 221 ) + NEW met1 ( 34385 221 ) ( 35443 * ) + NEW met2 ( 31119 102 ) ( * 119 ) + NEW met1 ( 31211 51 ) ( * 119 ) + NEW met1 ( 31119 119 ) ( 31211 * ) + NEW met3 ( 26427 102 ) ( 31119 * ) + NEW met1 ( 31211 51 ) ( 34385 * ) + NEW met2 ( 17319 153 ) ( * 170 ) + NEW met2 ( 18561 170 ) ( * 731 ) + NEW met3 ( 17319 170 ) ( 18561 * ) + NEW met3 ( 12719 170 ) ( 17319 * ) + NEW met1 ( 18561 731 ) ( 19435 * ) + NEW met2 ( 41055 51 ) ( * 102 ) + NEW met3 ( 35719 102 ) ( 41055 * ) + NEW li1 ( 8119 119 ) L1M1_PR_MR + NEW met1 ( 8119 119 ) M1M2_PR + NEW met2 ( 8119 238 ) M2M3_PR + NEW met1 ( 19435 731 ) M1M2_PR + NEW met2 ( 19435 782 ) M2M3_PR + NEW li1 ( 26519 119 ) L1M1_PR_MR + NEW met1 ( 26427 119 ) M1M2_PR + NEW met2 ( 26427 102 ) M2M3_PR + NEW li1 ( 35719 119 ) L1M1_PR_MR + NEW met1 ( 35719 119 ) M1M2_PR + NEW met2 ( 35719 102 ) M2M3_PR + NEW met1 ( 35443 221 ) M1M2_PR + NEW met1 ( 35443 119 ) M1M2_PR + NEW met2 ( 4117 238 ) M2M3_PR + NEW met1 ( 4117 119 ) M1M2_PR + NEW li1 ( 3519 119 ) L1M1_PR_MR + NEW li1 ( 12719 153 ) L1M1_PR_MR + NEW met1 ( 12719 153 ) M1M2_PR + NEW met2 ( 12719 170 ) M2M3_PR + NEW li1 ( 21919 153 ) L1M1_PR_MR + NEW met1 ( 21919 153 ) M1M2_PR + NEW met2 ( 21919 102 ) M2M3_PR + NEW met2 ( 21643 782 ) M2M3_PR + NEW met1 ( 21643 153 ) M1M2_PR + NEW met1 ( 34385 51 ) M1M2_PR + NEW met1 ( 34385 221 ) M1M2_PR + NEW li1 ( 31119 119 ) L1M1_PR_MR + NEW met1 ( 31119 119 ) M1M2_PR + NEW met2 ( 31119 102 ) M2M3_PR + NEW li1 ( 17319 153 ) L1M1_PR_MR + NEW met1 ( 17319 153 ) M1M2_PR + NEW met2 ( 17319 170 ) M2M3_PR + NEW met1 ( 18561 731 ) M1M2_PR + NEW met2 ( 18561 170 ) M2M3_PR + NEW met2 ( 41055 102 ) M2M3_PR + NEW li1 ( 41055 51 ) L1M1_PR_MR + NEW met1 ( 41055 51 ) M1M2_PR ; + - storage_0_3_0.we0 ( storage_0_3_0.gcand X ) ( storage_0_3_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 40641 85 ) ( 41515 * ) + NEW li1 ( 40641 85 ) L1M1_PR_MR + NEW li1 ( 41515 85 ) L1M1_PR_MR ; + - storage_0_3_0.write_sel ( storage_0_3_0.gcand A ) ( storage_0_3_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 41285 153 ) ( 41331 * ) + NEW li1 ( 41331 153 ) L1M1_PR_MR + NEW li1 ( 41285 153 ) L1M1_PR_MR ; + - storage_1_0_0.bit0.storage ( storage_1_0_0.bit0.obuf0 A ) ( storage_1_0_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 759 391 ) ( 805 * ) + NEW met1 ( 759 357 ) ( * 391 ) + NEW li1 ( 805 391 ) L1M1_PR_MR + NEW li1 ( 759 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit1.storage ( storage_1_0_0.bit1.obuf0 A ) ( storage_1_0_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 5359 391 ) ( 5405 * ) + NEW met1 ( 5359 357 ) ( * 391 ) + NEW li1 ( 5405 391 ) L1M1_PR_MR + NEW li1 ( 5359 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit2.storage ( storage_1_0_0.bit2.obuf0 A ) ( storage_1_0_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 9959 391 ) ( 10005 * ) + NEW met1 ( 9959 357 ) ( * 391 ) + NEW li1 ( 10005 391 ) L1M1_PR_MR + NEW li1 ( 9959 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit3.storage ( storage_1_0_0.bit3.obuf0 A ) ( storage_1_0_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 14559 391 ) ( 14605 * ) + NEW met1 ( 14559 357 ) ( * 391 ) + NEW li1 ( 14605 391 ) L1M1_PR_MR + NEW li1 ( 14559 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit4.storage ( storage_1_0_0.bit4.obuf0 A ) ( storage_1_0_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 19159 391 ) ( 19205 * ) + NEW met1 ( 19159 357 ) ( * 391 ) + NEW li1 ( 19205 391 ) L1M1_PR_MR + NEW li1 ( 19159 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit5.storage ( storage_1_0_0.bit5.obuf0 A ) ( storage_1_0_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 23759 391 ) ( 23805 * ) + NEW met1 ( 23759 357 ) ( * 391 ) + NEW li1 ( 23805 391 ) L1M1_PR_MR + NEW li1 ( 23759 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit6.storage ( storage_1_0_0.bit6.obuf0 A ) ( storage_1_0_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 28359 391 ) ( 28405 * ) + NEW met1 ( 28359 357 ) ( * 391 ) + NEW li1 ( 28405 391 ) L1M1_PR_MR + NEW li1 ( 28359 357 ) L1M1_PR_MR ; + - storage_1_0_0.bit7.storage ( storage_1_0_0.bit7.obuf0 A ) ( storage_1_0_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 32959 391 ) ( 33005 * ) + NEW met1 ( 32959 357 ) ( * 391 ) + NEW li1 ( 33005 391 ) L1M1_PR_MR + NEW li1 ( 32959 357 ) L1M1_PR_MR ; + - storage_1_0_0.gclock ( storage_1_0_0.cg GCLK ) ( storage_1_0_0.bit7.bit CLK ) ( storage_1_0_0.bit6.bit CLK ) ( storage_1_0_0.bit5.bit CLK ) ( storage_1_0_0.bit4.bit CLK ) ( storage_1_0_0.bit3.bit CLK ) ( storage_1_0_0.bit2.bit CLK ) + ( storage_1_0_0.bit1.bit CLK ) ( storage_1_0_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 18193 391 ) ( 18469 * ) + NEW met2 ( 18193 221 ) ( * 391 ) + NEW met1 ( 17319 221 ) ( 18193 * ) + NEW met1 ( 17319 187 ) ( * 221 ) + NEW met1 ( 17181 187 ) ( 17319 * ) + NEW met1 ( 17181 187 ) ( * 221 ) + NEW met1 ( 16169 221 ) ( 17181 * ) + NEW met1 ( 16169 187 ) ( * 221 ) + NEW met1 ( 18469 187 ) ( * 221 ) + NEW met1 ( 18193 187 ) ( 18469 * ) + NEW met1 ( 18193 187 ) ( * 221 ) + NEW met2 ( 15801 187 ) ( * 238 ) + NEW met3 ( 14835 238 ) ( 15801 * ) + NEW met2 ( 14835 238 ) ( * 493 ) + NEW met1 ( 15801 187 ) ( 16169 * ) + NEW met1 ( 32269 425 ) ( * 459 ) + NEW met2 ( 3933 238 ) ( * 425 ) + NEW met3 ( 69 238 ) ( 3933 * ) + NEW met2 ( 69 238 ) ( * 391 ) + NEW met2 ( 13869 391 ) ( * 493 ) + NEW met1 ( 13869 493 ) ( 14835 * ) + NEW met1 ( 22931 391 ) ( 23069 * ) + NEW met2 ( 22931 34 ) ( * 391 ) + NEW met3 ( 20447 34 ) ( 22931 * ) + NEW met2 ( 20447 34 ) ( * 221 ) + NEW met1 ( 18469 221 ) ( 20447 * ) + NEW met2 ( 34155 102 ) ( * 459 ) + NEW met3 ( 34155 102 ) ( 34178 * ) + NEW met4 ( 34178 102 ) ( * 170 ) + NEW met4 ( 34178 170 ) ( 35006 * ) + NEW met4 ( 35006 102 ) ( * 170 ) + NEW met3 ( 35006 102 ) ( 35075 * ) + NEW met2 ( 35075 102 ) ( * 459 ) + NEW met1 ( 32269 459 ) ( 34155 * ) + NEW met1 ( 9269 425 ) ( 10143 * ) + NEW met1 ( 10143 391 ) ( * 425 ) + NEW met1 ( 10143 391 ) ( 10465 * ) + NEW met1 ( 10465 391 ) ( * 425 ) + NEW met1 ( 10465 425 ) ( 11109 * ) + NEW met2 ( 11109 238 ) ( * 425 ) + NEW met3 ( 11109 238 ) ( 11454 * ) + NEW met4 ( 11454 170 ) ( * 238 ) + NEW met4 ( 11454 170 ) ( 12190 * ) + NEW met4 ( 12190 170 ) ( * 238 ) + NEW met3 ( 12190 238 ) ( 13593 * ) + NEW met2 ( 13593 238 ) ( * 391 ) + NEW met1 ( 9269 357 ) ( * 425 ) + NEW met1 ( 13593 391 ) ( 13869 * ) + NEW met1 ( 8970 357 ) ( 9269 * ) + NEW met2 ( 4669 425 ) ( * 493 ) + NEW met1 ( 4669 493 ) ( 5773 * ) + NEW met2 ( 5773 323 ) ( * 493 ) + NEW met1 ( 5773 323 ) ( 6601 * ) + NEW met2 ( 6601 187 ) ( * 323 ) + NEW met1 ( 6601 187 ) ( 6969 * ) + NEW met1 ( 6969 187 ) ( * 221 ) + NEW met1 ( 6969 221 ) ( 7061 * ) + NEW met2 ( 7061 221 ) ( * 323 ) + NEW met1 ( 7061 323 ) ( 8970 * ) + NEW met1 ( 8970 323 ) ( * 357 ) + NEW met1 ( 4301 391 ) ( * 425 ) + NEW met1 ( 4301 391 ) ( 4669 * ) + NEW met1 ( 4669 391 ) ( * 425 ) + NEW met1 ( 3933 425 ) ( 4301 * ) + NEW met2 ( 27669 34 ) ( * 391 ) + NEW met3 ( 24081 34 ) ( 27669 * ) + NEW met2 ( 24081 34 ) ( * 221 ) + NEW met1 ( 27669 391 ) ( * 459 ) + NEW met1 ( 22931 221 ) ( 24081 * ) + NEW met1 ( 27669 459 ) ( 32269 * ) + NEW met1 ( 36823 459 ) ( * 493 ) + NEW met1 ( 36823 493 ) ( 37467 * ) + NEW met1 ( 35075 459 ) ( 36823 * ) + NEW li1 ( 18469 391 ) L1M1_PR_MR + NEW met1 ( 18193 391 ) M1M2_PR + NEW met1 ( 18193 221 ) M1M2_PR + NEW met1 ( 15801 187 ) M1M2_PR + NEW met2 ( 15801 238 ) M2M3_PR + NEW met2 ( 14835 238 ) M2M3_PR + NEW met1 ( 14835 493 ) M1M2_PR + NEW li1 ( 32269 425 ) L1M1_PR_MR + NEW met1 ( 3933 425 ) M1M2_PR + NEW met2 ( 3933 238 ) M2M3_PR + NEW met2 ( 69 238 ) M2M3_PR + NEW li1 ( 69 391 ) L1M1_PR_MR + NEW met1 ( 69 391 ) M1M2_PR + NEW li1 ( 13869 391 ) L1M1_PR_MR + NEW met1 ( 13869 493 ) M1M2_PR + NEW met1 ( 13869 391 ) M1M2_PR + NEW li1 ( 23069 391 ) L1M1_PR_MR + NEW met1 ( 22931 391 ) M1M2_PR + NEW met2 ( 22931 34 ) M2M3_PR + NEW met2 ( 20447 34 ) M2M3_PR + NEW met1 ( 20447 221 ) M1M2_PR + NEW met1 ( 22931 221 ) M1M2_PR + NEW met1 ( 34155 459 ) M1M2_PR + NEW met2 ( 34155 102 ) M2M3_PR + NEW met3 ( 34178 102 ) M3M4_PR + NEW met3 ( 35006 102 ) M3M4_PR + NEW met2 ( 35075 102 ) M2M3_PR + NEW met1 ( 35075 459 ) M1M2_PR + NEW li1 ( 9269 425 ) L1M1_PR_MR + NEW met1 ( 11109 425 ) M1M2_PR + NEW met2 ( 11109 238 ) M2M3_PR + NEW met3 ( 11454 238 ) M3M4_PR + NEW met3 ( 12190 238 ) M3M4_PR + NEW met2 ( 13593 238 ) M2M3_PR + NEW met1 ( 13593 391 ) M1M2_PR + NEW li1 ( 4669 425 ) L1M1_PR_MR + NEW met1 ( 4669 425 ) M1M2_PR + NEW met1 ( 4669 493 ) M1M2_PR + NEW met1 ( 5773 493 ) M1M2_PR + NEW met1 ( 5773 323 ) M1M2_PR + NEW met1 ( 6601 323 ) M1M2_PR + NEW met1 ( 6601 187 ) M1M2_PR + NEW met1 ( 7061 221 ) M1M2_PR + NEW met1 ( 7061 323 ) M1M2_PR + NEW li1 ( 27669 391 ) L1M1_PR_MR + NEW met1 ( 27669 391 ) M1M2_PR + NEW met2 ( 27669 34 ) M2M3_PR + NEW met2 ( 24081 34 ) M2M3_PR + NEW met1 ( 24081 221 ) M1M2_PR + NEW li1 ( 37467 493 ) L1M1_PR_MR + NEW met3 ( 34155 102 ) RECT ( -39 -15 0 15 ) ; + - storage_1_0_0.we0 ( storage_1_0_0.gcand X ) ( storage_1_0_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 37053 357 ) ( * 391 ) + NEW met1 ( 37053 357 ) ( 37421 * ) + NEW met1 ( 37421 357 ) ( * 425 ) + NEW met1 ( 37421 425 ) ( 37927 * ) + NEW li1 ( 37053 391 ) L1M1_PR_MR + NEW li1 ( 37927 425 ) L1M1_PR_MR ; + - storage_1_0_0.write_sel ( storage_1_0_0.gcand A ) ( storage_1_0_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 37697 357 ) ( 37743 * ) + NEW li1 ( 37743 357 ) L1M1_PR_MR + NEW li1 ( 37697 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit0.storage ( storage_1_1_0.bit0.obuf0 A ) ( storage_1_1_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 1909 391 ) ( 1955 * ) + NEW met1 ( 1909 357 ) ( * 391 ) + NEW li1 ( 1955 391 ) L1M1_PR_MR + NEW li1 ( 1909 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit1.storage ( storage_1_1_0.bit1.obuf0 A ) ( storage_1_1_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 6509 391 ) ( 6555 * ) + NEW met1 ( 6509 357 ) ( * 391 ) + NEW li1 ( 6555 391 ) L1M1_PR_MR + NEW li1 ( 6509 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit2.storage ( storage_1_1_0.bit2.obuf0 A ) ( storage_1_1_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 11109 391 ) ( 11155 * ) + NEW met1 ( 11109 357 ) ( * 391 ) + NEW li1 ( 11155 391 ) L1M1_PR_MR + NEW li1 ( 11109 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit3.storage ( storage_1_1_0.bit3.obuf0 A ) ( storage_1_1_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 15709 391 ) ( 15755 * ) + NEW met1 ( 15709 357 ) ( * 391 ) + NEW li1 ( 15755 391 ) L1M1_PR_MR + NEW li1 ( 15709 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit4.storage ( storage_1_1_0.bit4.obuf0 A ) ( storage_1_1_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 20309 391 ) ( 20355 * ) + NEW met1 ( 20309 357 ) ( * 391 ) + NEW li1 ( 20355 391 ) L1M1_PR_MR + NEW li1 ( 20309 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit5.storage ( storage_1_1_0.bit5.obuf0 A ) ( storage_1_1_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 24909 391 ) ( 24955 * ) + NEW met1 ( 24909 357 ) ( * 391 ) + NEW li1 ( 24955 391 ) L1M1_PR_MR + NEW li1 ( 24909 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit6.storage ( storage_1_1_0.bit6.obuf0 A ) ( storage_1_1_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 29509 391 ) ( 29555 * ) + NEW met1 ( 29509 357 ) ( * 391 ) + NEW li1 ( 29555 391 ) L1M1_PR_MR + NEW li1 ( 29509 357 ) L1M1_PR_MR ; + - storage_1_1_0.bit7.storage ( storage_1_1_0.bit7.obuf0 A ) ( storage_1_1_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 34109 391 ) ( 34155 * ) + NEW met1 ( 34109 357 ) ( * 391 ) + NEW li1 ( 34155 391 ) L1M1_PR_MR + NEW li1 ( 34109 357 ) L1M1_PR_MR ; + - storage_1_1_0.gclock ( storage_1_1_0.cg GCLK ) ( storage_1_1_0.bit7.bit CLK ) ( storage_1_1_0.bit6.bit CLK ) ( storage_1_1_0.bit5.bit CLK ) ( storage_1_1_0.bit4.bit CLK ) ( storage_1_1_0.bit3.bit CLK ) ( storage_1_1_0.bit2.bit CLK ) + ( storage_1_1_0.bit1.bit CLK ) ( storage_1_1_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met2 ( 1219 425 ) ( * 442 ) + NEW met2 ( 10419 425 ) ( * 442 ) + NEW met1 ( 19435 391 ) ( 19619 * ) + NEW met2 ( 19435 391 ) ( * 510 ) + NEW met2 ( 5819 425 ) ( * 442 ) + NEW met3 ( 1219 442 ) ( 10419 * ) + NEW met1 ( 14881 425 ) ( 15019 * ) + NEW met2 ( 14881 425 ) ( * 442 ) + NEW met3 ( 15778 442 ) ( * 510 ) + NEW met3 ( 14881 442 ) ( 15778 * ) + NEW met3 ( 10419 442 ) ( 14881 * ) + NEW met3 ( 15778 510 ) ( 19435 * ) + NEW met1 ( 24173 425 ) ( 24219 * ) + NEW met2 ( 24173 425 ) ( * 510 ) + NEW met3 ( 19435 510 ) ( 24173 * ) + NEW met2 ( 33235 442 ) ( * 782 ) + NEW met1 ( 33235 391 ) ( 33419 * ) + NEW met2 ( 33235 391 ) ( * 442 ) + NEW met2 ( 28405 510 ) ( * 782 ) + NEW met1 ( 28819 357 ) ( * 391 ) + NEW met1 ( 28681 357 ) ( 28819 * ) + NEW met2 ( 28681 357 ) ( * 510 ) + NEW met3 ( 28405 510 ) ( 28681 * ) + NEW met3 ( 24173 510 ) ( 28405 * ) + NEW met3 ( 28405 782 ) ( 33235 * ) + NEW met2 ( 38755 391 ) ( * 442 ) + NEW met3 ( 33235 442 ) ( 38755 * ) + NEW met2 ( 1219 442 ) M2M3_PR + NEW li1 ( 1219 425 ) L1M1_PR_MR + NEW met1 ( 1219 425 ) M1M2_PR + NEW li1 ( 10419 425 ) L1M1_PR_MR + NEW met1 ( 10419 425 ) M1M2_PR + NEW met2 ( 10419 442 ) M2M3_PR + NEW li1 ( 19619 391 ) L1M1_PR_MR + NEW met1 ( 19435 391 ) M1M2_PR + NEW met2 ( 19435 510 ) M2M3_PR + NEW li1 ( 5819 425 ) L1M1_PR_MR + NEW met1 ( 5819 425 ) M1M2_PR + NEW met2 ( 5819 442 ) M2M3_PR + NEW li1 ( 15019 425 ) L1M1_PR_MR + NEW met1 ( 14881 425 ) M1M2_PR + NEW met2 ( 14881 442 ) M2M3_PR + NEW li1 ( 24219 425 ) L1M1_PR_MR + NEW met1 ( 24173 425 ) M1M2_PR + NEW met2 ( 24173 510 ) M2M3_PR + NEW met2 ( 33235 442 ) M2M3_PR + NEW met2 ( 33235 782 ) M2M3_PR + NEW li1 ( 33419 391 ) L1M1_PR_MR + NEW met1 ( 33235 391 ) M1M2_PR + NEW met2 ( 28405 510 ) M2M3_PR + NEW met2 ( 28405 782 ) M2M3_PR + NEW li1 ( 28819 391 ) L1M1_PR_MR + NEW met1 ( 28681 357 ) M1M2_PR + NEW met2 ( 28681 510 ) M2M3_PR + NEW met2 ( 38755 442 ) M2M3_PR + NEW li1 ( 38755 391 ) L1M1_PR_MR + NEW met1 ( 38755 391 ) M1M2_PR + NEW met3 ( 5819 442 ) RECT ( -62 -15 0 15 ) ; + - storage_1_1_0.we0 ( storage_1_1_0.gcand X ) ( storage_1_1_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 38341 493 ) ( 39215 * ) + NEW li1 ( 38341 493 ) L1M1_PR_MR + NEW li1 ( 39215 493 ) L1M1_PR_MR ; + - storage_1_1_0.write_sel ( storage_1_1_0.gcand A ) ( storage_1_1_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 38985 391 ) ( 39031 * ) + NEW li1 ( 39031 391 ) L1M1_PR_MR + NEW li1 ( 38985 391 ) L1M1_PR_MR ; + - storage_1_2_0.bit0.storage ( storage_1_2_0.bit0.obuf0 A ) ( storage_1_2_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 3059 391 ) ( 3105 * ) + NEW met1 ( 3059 357 ) ( * 391 ) + NEW li1 ( 3105 391 ) L1M1_PR_MR + NEW li1 ( 3059 357 ) L1M1_PR_MR ; + - storage_1_2_0.bit1.storage ( storage_1_2_0.bit1.obuf0 A ) ( storage_1_2_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 7659 391 ) ( 7705 * ) + NEW met1 ( 7659 357 ) ( * 391 ) + NEW li1 ( 7705 391 ) L1M1_PR_MR + NEW li1 ( 7659 357 ) L1M1_PR_MR ; + - storage_1_2_0.bit2.storage ( storage_1_2_0.bit2.obuf0 A ) ( storage_1_2_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 12259 391 ) ( 12305 * ) + NEW met1 ( 12259 357 ) ( * 391 ) + NEW li1 ( 12305 391 ) L1M1_PR_MR + NEW li1 ( 12259 357 ) L1M1_PR_MR ; + - storage_1_2_0.bit3.storage ( storage_1_2_0.bit3.obuf0 A ) ( storage_1_2_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 16859 391 ) ( 16905 * ) + NEW met1 ( 16859 357 ) ( * 391 ) + NEW li1 ( 16905 391 ) L1M1_PR_MR + NEW li1 ( 16859 357 ) L1M1_PR_MR ; + - storage_1_2_0.bit4.storage ( storage_1_2_0.bit4.obuf0 A ) ( storage_1_2_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 21459 391 ) ( 21505 * ) + NEW met1 ( 21459 357 ) ( * 391 ) + NEW li1 ( 21505 391 ) L1M1_PR_MR + NEW li1 ( 21459 357 ) L1M1_PR_MR ; + - storage_1_2_0.bit5.storage ( storage_1_2_0.bit5.obuf0 A ) ( storage_1_2_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 26059 391 ) ( 26105 * ) + NEW met1 ( 26059 357 ) ( * 391 ) + NEW li1 ( 26105 391 ) L1M1_PR_MR + NEW li1 ( 26059 357 ) L1M1_PR_MR ; + - storage_1_2_0.bit6.storage ( storage_1_2_0.bit6.obuf0 A ) ( storage_1_2_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 30659 391 ) ( 30705 * ) + NEW met1 ( 30659 357 ) ( * 391 ) + NEW li1 ( 30705 391 ) L1M1_PR_MR + NEW li1 ( 30659 357 ) L1M1_PR_MR ; + - storage_1_2_0.bit7.storage ( storage_1_2_0.bit7.obuf0 A ) ( storage_1_2_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met2 ( 35305 391 ) ( * 493 ) + NEW met1 ( 35259 493 ) ( 35305 * ) + NEW li1 ( 35305 391 ) L1M1_PR_MR + NEW met1 ( 35305 391 ) M1M2_PR + NEW met1 ( 35305 493 ) M1M2_PR + NEW li1 ( 35259 493 ) L1M1_PR_MR ; + - storage_1_2_0.gclock ( storage_1_2_0.cg GCLK ) ( storage_1_2_0.bit7.bit CLK ) ( storage_1_2_0.bit6.bit CLK ) ( storage_1_2_0.bit5.bit CLK ) ( storage_1_2_0.bit4.bit CLK ) ( storage_1_2_0.bit3.bit CLK ) ( storage_1_2_0.bit2.bit CLK ) + ( storage_1_2_0.bit1.bit CLK ) ( storage_1_2_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met2 ( 15893 442 ) ( * 578 ) + NEW met2 ( 16169 425 ) ( * 442 ) + NEW met1 ( 29923 391 ) ( 29969 * ) + NEW met2 ( 29923 391 ) ( * 442 ) + NEW met2 ( 29877 34 ) ( * 306 ) + NEW met2 ( 29877 306 ) ( 29923 * ) + NEW met2 ( 29923 306 ) ( * 391 ) + NEW met2 ( 2369 425 ) ( * 578 ) + NEW met2 ( 25369 425 ) ( * 442 ) + NEW met2 ( 20769 391 ) ( * 442 ) + NEW met3 ( 20769 442 ) ( 25369 * ) + NEW met3 ( 15893 442 ) ( 20769 * ) + NEW met3 ( 25369 442 ) ( 29923 * ) + NEW met2 ( 34569 391 ) ( 34615 * ) + NEW met2 ( 34615 34 ) ( * 391 ) + NEW met3 ( 34615 34 ) ( 35259 * ) + NEW met2 ( 35259 34 ) ( * 238 ) + NEW met3 ( 35259 238 ) ( 36133 * ) + NEW met2 ( 36133 238 ) ( * 731 ) + NEW met3 ( 29877 34 ) ( 34615 * ) + NEW met1 ( 11293 425 ) ( 11569 * ) + NEW met2 ( 11293 425 ) ( * 578 ) + NEW met3 ( 11293 578 ) ( 15893 * ) + NEW met2 ( 7153 459 ) ( * 578 ) + NEW met1 ( 6969 459 ) ( 7153 * ) + NEW met1 ( 6969 425 ) ( * 459 ) + NEW met3 ( 2369 578 ) ( 7153 * ) + NEW met3 ( 7153 578 ) ( 11293 * ) + NEW met2 ( 39905 391 ) ( * 731 ) + NEW met1 ( 36133 731 ) ( 39905 * ) + NEW met2 ( 15893 578 ) M2M3_PR + NEW met2 ( 15893 442 ) M2M3_PR + NEW li1 ( 16169 425 ) L1M1_PR_MR + NEW met1 ( 16169 425 ) M1M2_PR + NEW met2 ( 16169 442 ) M2M3_PR + NEW li1 ( 29969 391 ) L1M1_PR_MR + NEW met1 ( 29923 391 ) M1M2_PR + NEW met2 ( 29923 442 ) M2M3_PR + NEW met2 ( 29877 34 ) M2M3_PR + NEW met2 ( 2369 578 ) M2M3_PR + NEW li1 ( 2369 425 ) L1M1_PR_MR + NEW met1 ( 2369 425 ) M1M2_PR + NEW li1 ( 25369 425 ) L1M1_PR_MR + NEW met1 ( 25369 425 ) M1M2_PR + NEW met2 ( 25369 442 ) M2M3_PR + NEW li1 ( 20769 391 ) L1M1_PR_MR + NEW met1 ( 20769 391 ) M1M2_PR + NEW met2 ( 20769 442 ) M2M3_PR + NEW li1 ( 34569 391 ) L1M1_PR_MR + NEW met1 ( 34569 391 ) M1M2_PR + NEW met2 ( 34615 34 ) M2M3_PR + NEW met2 ( 35259 34 ) M2M3_PR + NEW met2 ( 35259 238 ) M2M3_PR + NEW met2 ( 36133 238 ) M2M3_PR + NEW met1 ( 36133 731 ) M1M2_PR + NEW li1 ( 11569 425 ) L1M1_PR_MR + NEW met1 ( 11293 425 ) M1M2_PR + NEW met2 ( 11293 578 ) M2M3_PR + NEW met2 ( 7153 578 ) M2M3_PR + NEW met1 ( 7153 459 ) M1M2_PR + NEW li1 ( 6969 425 ) L1M1_PR_MR + NEW li1 ( 39905 391 ) L1M1_PR_MR + NEW met1 ( 39905 391 ) M1M2_PR + NEW met1 ( 39905 731 ) M1M2_PR + NEW met3 ( 16169 442 ) RECT ( -62 -15 0 15 ) ; + - storage_1_2_0.we0 ( storage_1_2_0.gcand X ) ( storage_1_2_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 39491 459 ) ( 40365 * ) + NEW li1 ( 39491 459 ) L1M1_PR_MR + NEW li1 ( 40365 459 ) L1M1_PR_MR ; + - storage_1_2_0.write_sel ( storage_1_2_0.gcand A ) ( storage_1_2_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 40135 357 ) ( 40181 * ) + NEW li1 ( 40181 357 ) L1M1_PR_MR + NEW li1 ( 40135 357 ) L1M1_PR_MR ; + - storage_1_3_0.bit0.storage ( storage_1_3_0.bit0.obuf0 A ) ( storage_1_3_0.bit0.bit Q ) + USE SIGNAL + + ROUTED met1 ( 4209 391 ) ( 4255 * ) + NEW met1 ( 4209 357 ) ( * 391 ) + NEW li1 ( 4255 391 ) L1M1_PR_MR + NEW li1 ( 4209 357 ) L1M1_PR_MR ; + - storage_1_3_0.bit1.storage ( storage_1_3_0.bit1.obuf0 A ) ( storage_1_3_0.bit1.bit Q ) + USE SIGNAL + + ROUTED met1 ( 8809 391 ) ( 8855 * ) + NEW met1 ( 8809 357 ) ( * 391 ) + NEW li1 ( 8855 391 ) L1M1_PR_MR + NEW li1 ( 8809 357 ) L1M1_PR_MR ; + - storage_1_3_0.bit2.storage ( storage_1_3_0.bit2.obuf0 A ) ( storage_1_3_0.bit2.bit Q ) + USE SIGNAL + + ROUTED met1 ( 13409 391 ) ( 13455 * ) + NEW met1 ( 13409 357 ) ( * 391 ) + NEW li1 ( 13455 391 ) L1M1_PR_MR + NEW li1 ( 13409 357 ) L1M1_PR_MR ; + - storage_1_3_0.bit3.storage ( storage_1_3_0.bit3.obuf0 A ) ( storage_1_3_0.bit3.bit Q ) + USE SIGNAL + + ROUTED met1 ( 18009 391 ) ( 18055 * ) + NEW met1 ( 18009 357 ) ( * 391 ) + NEW li1 ( 18055 391 ) L1M1_PR_MR + NEW li1 ( 18009 357 ) L1M1_PR_MR ; + - storage_1_3_0.bit4.storage ( storage_1_3_0.bit4.obuf0 A ) ( storage_1_3_0.bit4.bit Q ) + USE SIGNAL + + ROUTED met1 ( 22609 391 ) ( 22655 * ) + NEW met1 ( 22609 357 ) ( * 391 ) + NEW li1 ( 22655 391 ) L1M1_PR_MR + NEW li1 ( 22609 357 ) L1M1_PR_MR ; + - storage_1_3_0.bit5.storage ( storage_1_3_0.bit5.obuf0 A ) ( storage_1_3_0.bit5.bit Q ) + USE SIGNAL + + ROUTED met1 ( 27209 391 ) ( 27255 * ) + NEW met1 ( 27209 357 ) ( * 391 ) + NEW li1 ( 27255 391 ) L1M1_PR_MR + NEW li1 ( 27209 357 ) L1M1_PR_MR ; + - storage_1_3_0.bit6.storage ( storage_1_3_0.bit6.obuf0 A ) ( storage_1_3_0.bit6.bit Q ) + USE SIGNAL + + ROUTED met1 ( 31809 391 ) ( 31855 * ) + NEW met1 ( 31809 357 ) ( * 391 ) + NEW li1 ( 31855 391 ) L1M1_PR_MR + NEW li1 ( 31809 357 ) L1M1_PR_MR ; + - storage_1_3_0.bit7.storage ( storage_1_3_0.bit7.obuf0 A ) ( storage_1_3_0.bit7.bit Q ) + USE SIGNAL + + ROUTED met1 ( 36409 391 ) ( 36455 * ) + NEW met1 ( 36409 357 ) ( * 391 ) + NEW li1 ( 36455 391 ) L1M1_PR_MR + NEW li1 ( 36409 357 ) L1M1_PR_MR ; + - storage_1_3_0.gclock ( storage_1_3_0.cg GCLK ) ( storage_1_3_0.bit7.bit CLK ) ( storage_1_3_0.bit6.bit CLK ) ( storage_1_3_0.bit5.bit CLK ) ( storage_1_3_0.bit4.bit CLK ) ( storage_1_3_0.bit3.bit CLK ) ( storage_1_3_0.bit2.bit CLK ) + ( storage_1_3_0.bit1.bit CLK ) ( storage_1_3_0.bit0.bit CLK ) + USE SIGNAL + + ROUTED met1 ( 8119 425 ) ( * 459 ) + NEW met1 ( 8119 459 ) ( 8165 * ) + NEW met2 ( 8165 459 ) ( * 510 ) + NEW met1 ( 26381 425 ) ( 26519 * ) + NEW met2 ( 26381 425 ) ( * 578 ) + NEW met1 ( 35673 391 ) ( 35719 * ) + NEW met2 ( 35673 391 ) ( * 510 ) + NEW met2 ( 21919 391 ) ( * 442 ) + NEW met2 ( 21873 442 ) ( 21919 * ) + NEW met2 ( 21873 442 ) ( * 578 ) + NEW met3 ( 21873 578 ) ( 26381 * ) + NEW met3 ( 26381 578 ) ( 30360 * ) + NEW met2 ( 31119 391 ) ( * 510 ) + NEW met3 ( 30360 510 ) ( * 578 ) + NEW met3 ( 30360 510 ) ( 31119 * ) + NEW met2 ( 3289 238 ) ( * 510 ) + NEW met2 ( 3289 238 ) ( 3381 * ) + NEW met2 ( 3381 238 ) ( * 357 ) + NEW met1 ( 3381 357 ) ( 3519 * ) + NEW met1 ( 3519 357 ) ( * 391 ) + NEW met3 ( 3289 510 ) ( 8165 * ) + NEW met1 ( 12627 391 ) ( 12719 * ) + NEW met2 ( 12627 391 ) ( * 510 ) + NEW met2 ( 12627 510 ) ( * 782 ) + NEW met3 ( 8165 510 ) ( 12627 * ) + NEW met1 ( 17273 425 ) ( 17319 * ) + NEW met1 ( 17273 391 ) ( * 425 ) + NEW met1 ( 17181 391 ) ( 17273 * ) + NEW met2 ( 17181 391 ) ( * 782 ) + NEW met4 ( 17434 578 ) ( * 782 ) + NEW met3 ( 17181 782 ) ( 17434 * ) + NEW met3 ( 12627 782 ) ( 17181 * ) + NEW met3 ( 17434 578 ) ( 21873 * ) + NEW met2 ( 41055 493 ) ( * 510 ) + NEW met3 ( 31119 510 ) ( 41055 * ) + NEW li1 ( 8119 425 ) L1M1_PR_MR + NEW met1 ( 8165 459 ) M1M2_PR + NEW met2 ( 8165 510 ) M2M3_PR + NEW li1 ( 26519 425 ) L1M1_PR_MR + NEW met1 ( 26381 425 ) M1M2_PR + NEW met2 ( 26381 578 ) M2M3_PR + NEW li1 ( 35719 391 ) L1M1_PR_MR + NEW met1 ( 35673 391 ) M1M2_PR + NEW met2 ( 35673 510 ) M2M3_PR + NEW li1 ( 21919 391 ) L1M1_PR_MR + NEW met1 ( 21919 391 ) M1M2_PR + NEW met2 ( 21873 578 ) M2M3_PR + NEW li1 ( 31119 391 ) L1M1_PR_MR + NEW met1 ( 31119 391 ) M1M2_PR + NEW met2 ( 31119 510 ) M2M3_PR + NEW met2 ( 3289 510 ) M2M3_PR + NEW met1 ( 3381 357 ) M1M2_PR + NEW li1 ( 3519 391 ) L1M1_PR_MR + NEW li1 ( 12719 391 ) L1M1_PR_MR + NEW met1 ( 12627 391 ) M1M2_PR + NEW met2 ( 12627 510 ) M2M3_PR + NEW met2 ( 12627 782 ) M2M3_PR + NEW li1 ( 17319 425 ) L1M1_PR_MR + NEW met1 ( 17181 391 ) M1M2_PR + NEW met2 ( 17181 782 ) M2M3_PR + NEW met3 ( 17434 578 ) M3M4_PR + NEW met3 ( 17434 782 ) M3M4_PR + NEW li1 ( 41055 493 ) L1M1_PR_MR + NEW met1 ( 41055 493 ) M1M2_PR + NEW met2 ( 41055 510 ) M2M3_PR + NEW met3 ( 35673 510 ) RECT ( -62 -15 0 15 ) ; + - storage_1_3_0.we0 ( storage_1_3_0.gcand X ) ( storage_1_3_0.cg GATE ) + USE SIGNAL + + ROUTED met1 ( 40641 459 ) ( 41515 * ) + NEW li1 ( 40641 459 ) L1M1_PR_MR + NEW li1 ( 41515 459 ) L1M1_PR_MR ; + - storage_1_3_0.write_sel ( storage_1_3_0.gcand A ) ( storage_1_3_0.word_and X ) + USE SIGNAL + + ROUTED met1 ( 41285 357 ) ( 41331 * ) + NEW li1 ( 41331 357 ) L1M1_PR_MR + NEW li1 ( 41285 357 ) L1M1_PR_MR ; + - we[0] ( PIN we[0] ) ( storage_1_3_0.gcand B ) ( storage_1_2_0.gcand B ) ( storage_1_1_0.gcand B ) ( storage_1_0_0.gcand B ) ( storage_0_3_0.gcand B ) ( storage_0_2_0.gcand B ) + ( storage_0_1_0.gcand B ) ( storage_0_0_0.gcand B ) + USE SIGNAL + + ROUTED met2 ( 39123 153 ) ( * 221 ) + NEW met2 ( 39123 221 ) ( * 391 ) + NEW met1 ( 37835 391 ) ( 38065 * ) + NEW met2 ( 38065 221 ) ( * 391 ) + NEW met1 ( 38065 221 ) ( 39123 * ) + NEW met2 ( 37835 119 ) ( * 391 ) + NEW met1 ( 41423 425 ) ( 41561 * ) + NEW met2 ( 41561 238 ) ( * 425 ) + NEW met3 ( 41561 238 ) ( 41722 * ) + NEW met3 ( 41722 238 ) ( * 306 0 ) + NEW met1 ( 41423 153 ) ( 41561 * ) + NEW met2 ( 41561 153 ) ( * 238 ) + NEW met1 ( 40273 153 ) ( 40319 * ) + NEW met2 ( 40319 153 ) ( * 221 ) + NEW met1 ( 40273 425 ) ( 40319 * ) + NEW met2 ( 40319 221 ) ( * 425 ) + NEW met1 ( 39123 221 ) ( 41561 * ) + NEW li1 ( 39123 153 ) L1M1_PR_MR + NEW met1 ( 39123 153 ) M1M2_PR + NEW met1 ( 39123 221 ) M1M2_PR + NEW li1 ( 39123 391 ) L1M1_PR_MR + NEW met1 ( 39123 391 ) M1M2_PR + NEW li1 ( 37835 391 ) L1M1_PR_MR + NEW met1 ( 38065 391 ) M1M2_PR + NEW met1 ( 38065 221 ) M1M2_PR + NEW li1 ( 37835 119 ) L1M1_PR_MR + NEW met1 ( 37835 119 ) M1M2_PR + NEW met1 ( 37835 391 ) M1M2_PR + NEW li1 ( 41423 425 ) L1M1_PR_MR + NEW met1 ( 41561 425 ) M1M2_PR + NEW met2 ( 41561 238 ) M2M3_PR + NEW li1 ( 41423 153 ) L1M1_PR_MR + NEW met1 ( 41561 153 ) M1M2_PR + NEW met1 ( 41561 221 ) M1M2_PR + NEW li1 ( 40273 153 ) L1M1_PR_MR + NEW met1 ( 40319 153 ) M1M2_PR + NEW met1 ( 40319 221 ) M1M2_PR + NEW li1 ( 40273 425 ) L1M1_PR_MR + NEW met1 ( 40319 425 ) M1M2_PR ; + - word_q.w0_b0 ( mux_slice0_bit0.s1_aoi_0 A2 ) ( storage_1_0_0.bit0.obuf0 Z ) ( storage_0_0_0.bit0.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 1127 493 ) ( * 663 ) + NEW met2 ( 1127 187 ) ( * 493 ) + NEW met1 ( 1127 663 ) ( 1405 * ) + NEW li1 ( 1127 493 ) L1M1_PR_MR + NEW met1 ( 1127 493 ) M1M2_PR + NEW met1 ( 1127 663 ) M1M2_PR + NEW li1 ( 1127 187 ) L1M1_PR_MR + NEW met1 ( 1127 187 ) M1M2_PR + NEW li1 ( 1405 663 ) L1M1_PR_MR ; + - word_q.w0_b1 ( mux_slice0_bit1.s1_aoi_0 A2 ) ( storage_1_0_0.bit1.obuf0 Z ) ( storage_0_0_0.bit1.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 5727 34 ) ( * 323 ) + NEW met3 ( 5727 34 ) ( 6095 * ) + NEW met2 ( 6095 34 ) ( * 663 ) + NEW met1 ( 6021 663 ) ( 6095 * ) + NEW li1 ( 5727 323 ) L1M1_PR_MR + NEW met1 ( 5727 323 ) M1M2_PR + NEW met2 ( 5727 34 ) M2M3_PR + NEW met2 ( 6095 34 ) M2M3_PR + NEW met1 ( 6095 663 ) M1M2_PR + NEW li1 ( 6021 663 ) L1M1_PR_MR + NEW li1 ( 5727 221 ) L1M1_PR_MR + NEW met1 ( 5727 221 ) M1M2_PR ; + - word_q.w0_b2 ( mux_slice0_bit2.s1_aoi_0 A2 ) ( storage_1_0_0.bit2.obuf0 Z ) ( storage_0_0_0.bit2.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 10327 102 ) ( * 221 ) + NEW met3 ( 10327 102 ) ( 10603 * ) + NEW met2 ( 10603 102 ) ( * 663 ) + NEW met1 ( 10603 663 ) ( 10605 * ) + NEW met2 ( 10327 221 ) ( * 357 ) + NEW li1 ( 10327 221 ) L1M1_PR_MR + NEW met1 ( 10327 221 ) M1M2_PR + NEW met2 ( 10327 102 ) M2M3_PR + NEW met2 ( 10603 102 ) M2M3_PR + NEW met1 ( 10603 663 ) M1M2_PR + NEW li1 ( 10605 663 ) L1M1_PR_MR + NEW li1 ( 10327 357 ) L1M1_PR_MR + NEW met1 ( 10327 357 ) M1M2_PR ; + - word_q.w0_b3 ( mux_slice0_bit3.s1_aoi_0 A2 ) ( storage_1_0_0.bit3.obuf0 Z ) ( storage_0_0_0.bit3.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 14927 51 ) ( 15203 * ) + NEW met2 ( 15203 51 ) ( * 663 ) + NEW met1 ( 15203 663 ) ( 15205 * ) + NEW met2 ( 14927 221 ) ( * 357 ) + NEW li1 ( 14927 51 ) L1M1_PR_MR + NEW met1 ( 15203 51 ) M1M2_PR + NEW met1 ( 15203 663 ) M1M2_PR + NEW li1 ( 15205 663 ) L1M1_PR_MR + NEW li1 ( 14927 357 ) L1M1_PR_MR + NEW met1 ( 14927 357 ) M1M2_PR + NEW li1 ( 14927 221 ) L1M1_PR_MR + NEW met1 ( 14927 221 ) M1M2_PR ; + - word_q.w0_b4 ( mux_slice0_bit4.s1_aoi_0 A2 ) ( storage_1_0_0.bit4.obuf0 Z ) ( storage_0_0_0.bit4.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 19527 493 ) ( 19665 * ) + NEW met2 ( 19665 493 ) ( * 663 ) + NEW met1 ( 19665 663 ) ( * 668 ) + NEW met1 ( 19665 668 ) ( 19805 * ) + NEW met2 ( 19389 187 ) ( * 357 ) + NEW li1 ( 19527 493 ) L1M1_PR_MR + NEW met1 ( 19665 493 ) M1M2_PR + NEW met1 ( 19665 663 ) M1M2_PR + NEW li1 ( 19805 668 ) L1M1_PR_MR + NEW li1 ( 19389 187 ) L1M1_PR_MR + NEW met1 ( 19389 187 ) M1M2_PR + NEW li1 ( 19389 357 ) L1M1_PR_MR + NEW met1 ( 19389 357 ) M1M2_PR ; + - word_q.w0_b5 ( mux_slice0_bit5.s1_aoi_0 A2 ) ( storage_1_0_0.bit5.obuf0 Z ) ( storage_0_0_0.bit5.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 24127 357 ) ( 24219 * ) + NEW met2 ( 24219 357 ) ( * 374 ) + NEW met2 ( 24219 374 ) ( 24265 * ) + NEW met2 ( 24265 374 ) ( * 510 ) + NEW met2 ( 24265 510 ) ( 24403 * ) + NEW met2 ( 24403 510 ) ( * 663 ) + NEW met1 ( 24403 663 ) ( 24405 * ) + NEW met1 ( 24127 221 ) ( 24173 * ) + NEW met2 ( 24173 221 ) ( * 306 ) + NEW met2 ( 24173 306 ) ( 24219 * ) + NEW met2 ( 24219 306 ) ( * 357 ) + NEW li1 ( 24127 357 ) L1M1_PR_MR + NEW met1 ( 24219 357 ) M1M2_PR + NEW met1 ( 24403 663 ) M1M2_PR + NEW li1 ( 24405 663 ) L1M1_PR_MR + NEW li1 ( 24127 221 ) L1M1_PR_MR + NEW met1 ( 24173 221 ) M1M2_PR ; + - word_q.w0_b6 ( mux_slice0_bit6.s1_aoi_0 A2 ) ( storage_1_0_0.bit6.obuf0 Z ) ( storage_0_0_0.bit6.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 28727 34 ) ( * 221 ) + NEW met3 ( 28727 34 ) ( 29095 * ) + NEW met2 ( 29095 34 ) ( * 663 ) + NEW met1 ( 29049 663 ) ( 29095 * ) + NEW met1 ( 29049 661 ) ( * 663 ) + NEW met1 ( 29013 661 ) ( 29049 * ) + NEW met1 ( 29013 660 ) ( * 661 ) + NEW met2 ( 28727 221 ) ( * 493 ) + NEW li1 ( 28727 221 ) L1M1_PR_MR + NEW met1 ( 28727 221 ) M1M2_PR + NEW met2 ( 28727 34 ) M2M3_PR + NEW met2 ( 29095 34 ) M2M3_PR + NEW met1 ( 29095 663 ) M1M2_PR + NEW li1 ( 29013 660 ) L1M1_PR_MR + NEW li1 ( 28727 493 ) L1M1_PR_MR + NEW met1 ( 28727 493 ) M1M2_PR ; + - word_q.w0_b7 ( mux_slice0_bit7.s1_aoi_0 A2 ) ( storage_1_0_0.bit7.obuf0 Z ) ( storage_0_0_0.bit7.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 33327 493 ) ( * 578 ) + NEW met3 ( 33327 578 ) ( 33603 * ) + NEW met2 ( 33603 578 ) ( * 663 ) + NEW met1 ( 33603 663 ) ( 33605 * ) + NEW met2 ( 33327 221 ) ( * 493 ) + NEW li1 ( 33327 493 ) L1M1_PR_MR + NEW met1 ( 33327 493 ) M1M2_PR + NEW met2 ( 33327 578 ) M2M3_PR + NEW met2 ( 33603 578 ) M2M3_PR + NEW met1 ( 33603 663 ) M1M2_PR + NEW li1 ( 33605 663 ) L1M1_PR_MR + NEW li1 ( 33327 221 ) L1M1_PR_MR + NEW met1 ( 33327 221 ) M1M2_PR ; + - word_q.w1_b0 ( mux_slice0_bit0.s1_aoi_0 B2 ) ( storage_1_1_0.bit0.obuf0 Z ) ( storage_0_1_0.bit0.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 1173 323 ) ( * 629 ) + NEW met1 ( 1173 629 ) ( 1219 * ) + NEW met2 ( 2139 221 ) ( * 323 ) + NEW met1 ( 1173 323 ) ( 2139 * ) + NEW met1 ( 1173 323 ) M1M2_PR + NEW met1 ( 1173 629 ) M1M2_PR + NEW li1 ( 1219 629 ) L1M1_PR_MR + NEW li1 ( 2139 323 ) L1M1_PR_MR + NEW li1 ( 2139 221 ) L1M1_PR_MR + NEW met1 ( 2139 221 ) M1M2_PR + NEW met1 ( 2139 323 ) M1M2_PR ; + - word_q.w1_b1 ( mux_slice0_bit1.s1_aoi_0 B2 ) ( storage_1_1_0.bit1.obuf0 Z ) ( storage_0_1_0.bit1.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 6785 323 ) ( * 493 ) + NEW met1 ( 5819 493 ) ( 6785 * ) + NEW met2 ( 5819 493 ) ( * 663 ) + NEW met2 ( 6785 221 ) ( * 323 ) + NEW li1 ( 6785 323 ) L1M1_PR_MR + NEW met1 ( 6785 323 ) M1M2_PR + NEW met1 ( 6785 493 ) M1M2_PR + NEW met1 ( 5819 493 ) M1M2_PR + NEW li1 ( 5819 663 ) L1M1_PR_MR + NEW met1 ( 5819 663 ) M1M2_PR + NEW li1 ( 6785 221 ) L1M1_PR_MR + NEW met1 ( 6785 221 ) M1M2_PR ; + - word_q.w1_b2 ( mux_slice0_bit2.s1_aoi_0 B2 ) ( storage_1_1_0.bit2.obuf0 Z ) ( storage_0_1_0.bit2.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 11339 357 ) ( * 493 ) + NEW met1 ( 10419 493 ) ( 11339 * ) + NEW met2 ( 10419 493 ) ( * 629 ) + NEW met2 ( 11339 221 ) ( * 357 ) + NEW li1 ( 11339 357 ) L1M1_PR_MR + NEW met1 ( 11339 357 ) M1M2_PR + NEW met1 ( 11339 493 ) M1M2_PR + NEW met1 ( 10419 493 ) M1M2_PR + NEW li1 ( 10419 629 ) L1M1_PR_MR + NEW met1 ( 10419 629 ) M1M2_PR + NEW li1 ( 11339 221 ) L1M1_PR_MR + NEW met1 ( 11339 221 ) M1M2_PR ; + - word_q.w1_b3 ( mux_slice0_bit3.s1_aoi_0 B2 ) ( storage_1_1_0.bit3.obuf0 Z ) ( storage_0_1_0.bit3.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 15939 357 ) ( * 595 ) + NEW met2 ( 16077 221 ) ( * 357 ) + NEW met2 ( 15065 595 ) ( * 663 ) + NEW met1 ( 15019 663 ) ( 15065 * ) + NEW met1 ( 15065 595 ) ( 15939 * ) + NEW li1 ( 15939 357 ) L1M1_PR_MR + NEW met1 ( 15939 357 ) M1M2_PR + NEW met1 ( 15939 595 ) M1M2_PR + NEW li1 ( 16077 221 ) L1M1_PR_MR + NEW met1 ( 16077 221 ) M1M2_PR + NEW li1 ( 16077 357 ) L1M1_PR_MR + NEW met1 ( 16077 357 ) M1M2_PR + NEW met1 ( 15065 595 ) M1M2_PR + NEW met1 ( 15065 663 ) M1M2_PR + NEW li1 ( 15019 663 ) L1M1_PR_MR ; + - word_q.w1_b4 ( mux_slice0_bit4.s1_aoi_0 B2 ) ( storage_1_1_0.bit4.obuf0 Z ) ( storage_0_1_0.bit4.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 20447 357 ) ( 20539 * ) + NEW met2 ( 20447 357 ) ( * 731 ) + NEW met1 ( 19757 731 ) ( 20447 * ) + NEW met1 ( 19757 697 ) ( * 731 ) + NEW met1 ( 19619 697 ) ( 19757 * ) + NEW met1 ( 19619 663 ) ( * 697 ) + NEW met2 ( 20631 221 ) ( * 357 ) + NEW met1 ( 20539 357 ) ( 20631 * ) + NEW li1 ( 20539 357 ) L1M1_PR_MR + NEW met1 ( 20447 357 ) M1M2_PR + NEW met1 ( 20447 731 ) M1M2_PR + NEW li1 ( 19619 663 ) L1M1_PR_MR + NEW li1 ( 20631 221 ) L1M1_PR_MR + NEW met1 ( 20631 221 ) M1M2_PR + NEW met1 ( 20631 357 ) M1M2_PR ; + - word_q.w1_b5 ( mux_slice0_bit5.s1_aoi_0 B2 ) ( storage_1_1_0.bit5.obuf0 Z ) ( storage_0_1_0.bit5.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 24449 425 ) ( 25277 * ) + NEW met1 ( 24449 425 ) ( * 459 ) + NEW met2 ( 24449 459 ) ( * 714 ) + NEW met2 ( 24357 714 ) ( 24449 * ) + NEW met2 ( 24357 663 ) ( * 714 ) + NEW met2 ( 24265 663 ) ( 24357 * ) + NEW met1 ( 24219 663 ) ( 24265 * ) + NEW met2 ( 25139 221 ) ( * 425 ) + NEW li1 ( 25277 425 ) L1M1_PR_MR + NEW met1 ( 24449 459 ) M1M2_PR + NEW met1 ( 24265 663 ) M1M2_PR + NEW li1 ( 24219 663 ) L1M1_PR_MR + NEW li1 ( 25139 221 ) L1M1_PR_MR + NEW met1 ( 25139 221 ) M1M2_PR + NEW met1 ( 25139 425 ) M1M2_PR ; + - word_q.w1_b6 ( mux_slice0_bit6.s1_aoi_0 B2 ) ( storage_1_1_0.bit6.obuf0 Z ) ( storage_0_1_0.bit6.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 29739 357 ) ( * 731 ) + NEW met1 ( 28773 731 ) ( 29739 * ) + NEW met2 ( 28773 663 ) ( * 731 ) + NEW met1 ( 28773 663 ) ( 28819 * ) + NEW met2 ( 29739 221 ) ( * 357 ) + NEW li1 ( 29739 357 ) L1M1_PR_MR + NEW met1 ( 29739 357 ) M1M2_PR + NEW met1 ( 29739 731 ) M1M2_PR + NEW met1 ( 28773 731 ) M1M2_PR + NEW met1 ( 28773 663 ) M1M2_PR + NEW li1 ( 28819 663 ) L1M1_PR_MR + NEW li1 ( 29739 221 ) L1M1_PR_MR + NEW met1 ( 29739 221 ) M1M2_PR ; + - word_q.w1_b7 ( mux_slice0_bit7.s1_aoi_0 B2 ) ( storage_1_1_0.bit7.obuf0 Z ) ( storage_0_1_0.bit7.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 34339 221 ) ( * 323 ) + NEW met2 ( 33419 493 ) ( * 629 ) + NEW met1 ( 33419 493 ) ( 34477 * ) + NEW li1 ( 34477 493 ) L1M1_PR_MR + NEW li1 ( 34339 221 ) L1M1_PR_MR + NEW met1 ( 34339 221 ) M1M2_PR + NEW li1 ( 34339 323 ) L1M1_PR_MR + NEW met1 ( 34339 323 ) M1M2_PR + NEW met1 ( 33419 493 ) M1M2_PR + NEW li1 ( 33419 629 ) L1M1_PR_MR + NEW met1 ( 33419 629 ) M1M2_PR ; + - word_q.w2_b0 ( mux_slice0_bit0.s1_aoi_1 A2 ) ( storage_1_2_0.bit0.obuf0 Z ) ( storage_0_2_0.bit0.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 3427 493 ) ( 3565 * ) + NEW met2 ( 3565 493 ) ( 3703 * ) + NEW met2 ( 3703 493 ) ( * 663 ) + NEW met1 ( 3703 663 ) ( 3705 * ) + NEW met2 ( 3427 221 ) ( * 493 ) + NEW li1 ( 3427 493 ) L1M1_PR_MR + NEW met1 ( 3565 493 ) M1M2_PR + NEW met1 ( 3703 663 ) M1M2_PR + NEW li1 ( 3705 663 ) L1M1_PR_MR + NEW li1 ( 3427 221 ) L1M1_PR_MR + NEW met1 ( 3427 221 ) M1M2_PR + NEW met1 ( 3427 493 ) M1M2_PR ; + - word_q.w2_b1 ( mux_slice0_bit1.s1_aoi_1 A2 ) ( storage_1_2_0.bit1.obuf0 Z ) ( storage_0_2_0.bit1.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 8027 357 ) ( 8119 * ) + NEW met2 ( 8119 357 ) ( * 374 ) + NEW met2 ( 8119 374 ) ( 8211 * ) + NEW met2 ( 8211 374 ) ( * 510 ) + NEW met2 ( 8211 510 ) ( 8303 * ) + NEW met2 ( 8303 510 ) ( * 663 ) + NEW met1 ( 8303 663 ) ( 8305 * ) + NEW met1 ( 8027 221 ) ( 8073 * ) + NEW met2 ( 8073 221 ) ( * 306 ) + NEW met2 ( 8073 306 ) ( 8119 * ) + NEW met2 ( 8119 306 ) ( * 357 ) + NEW li1 ( 8027 357 ) L1M1_PR_MR + NEW met1 ( 8119 357 ) M1M2_PR + NEW met1 ( 8303 663 ) M1M2_PR + NEW li1 ( 8305 663 ) L1M1_PR_MR + NEW li1 ( 8027 221 ) L1M1_PR_MR + NEW met1 ( 8073 221 ) M1M2_PR ; + - word_q.w2_b2 ( mux_slice0_bit2.s1_aoi_1 A2 ) ( storage_1_2_0.bit2.obuf0 Z ) ( storage_0_2_0.bit2.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 12627 493 ) ( 12673 * ) + NEW met2 ( 12673 442 ) ( * 493 ) + NEW met2 ( 12673 442 ) ( 12765 * ) + NEW met2 ( 12765 442 ) ( * 510 ) + NEW met2 ( 12765 510 ) ( 12903 * ) + NEW met2 ( 12903 510 ) ( * 663 ) + NEW met1 ( 12903 663 ) ( 12905 * ) + NEW met1 ( 12627 221 ) ( 12673 * ) + NEW met2 ( 12673 221 ) ( * 442 ) + NEW li1 ( 12627 493 ) L1M1_PR_MR + NEW met1 ( 12673 493 ) M1M2_PR + NEW met1 ( 12903 663 ) M1M2_PR + NEW li1 ( 12905 663 ) L1M1_PR_MR + NEW li1 ( 12627 221 ) L1M1_PR_MR + NEW met1 ( 12673 221 ) M1M2_PR ; + - word_q.w2_b3 ( mux_slice0_bit3.s1_aoi_1 A2 ) ( storage_1_2_0.bit3.obuf0 Z ) ( storage_0_2_0.bit3.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 17227 51 ) ( 17503 * ) + NEW met1 ( 17503 51 ) ( * 85 ) + NEW met1 ( 17503 85 ) ( 17641 * ) + NEW met2 ( 17641 85 ) ( * 663 ) + NEW met1 ( 17521 663 ) ( 17641 * ) + NEW met2 ( 17227 221 ) ( * 357 ) + NEW li1 ( 17227 51 ) L1M1_PR_MR + NEW met1 ( 17641 85 ) M1M2_PR + NEW met1 ( 17641 663 ) M1M2_PR + NEW li1 ( 17521 663 ) L1M1_PR_MR + NEW li1 ( 17227 357 ) L1M1_PR_MR + NEW met1 ( 17227 357 ) M1M2_PR + NEW li1 ( 17227 221 ) L1M1_PR_MR + NEW met1 ( 17227 221 ) M1M2_PR ; + - word_q.w2_b4 ( mux_slice0_bit4.s1_aoi_1 A2 ) ( storage_1_2_0.bit4.obuf0 Z ) ( storage_0_2_0.bit4.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 21827 493 ) ( 22195 * ) + NEW met2 ( 22195 493 ) ( * 663 ) + NEW met1 ( 22195 663 ) ( * 668 ) + NEW met1 ( 22121 668 ) ( 22195 * ) + NEW met2 ( 21827 221 ) ( * 323 ) + NEW li1 ( 21827 493 ) L1M1_PR_MR + NEW met1 ( 22195 493 ) M1M2_PR + NEW met1 ( 22195 663 ) M1M2_PR + NEW li1 ( 22121 668 ) L1M1_PR_MR + NEW li1 ( 21827 221 ) L1M1_PR_MR + NEW met1 ( 21827 221 ) M1M2_PR + NEW li1 ( 21827 323 ) L1M1_PR_MR + NEW met1 ( 21827 323 ) M1M2_PR ; + - word_q.w2_b5 ( mux_slice0_bit5.s1_aoi_1 A2 ) ( storage_1_2_0.bit5.obuf0 Z ) ( storage_0_2_0.bit5.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 26427 493 ) ( * 663 ) + NEW met1 ( 26427 663 ) ( 26705 * ) + NEW met2 ( 26427 221 ) ( * 493 ) + NEW li1 ( 26427 493 ) L1M1_PR_MR + NEW met1 ( 26427 493 ) M1M2_PR + NEW met1 ( 26427 663 ) M1M2_PR + NEW li1 ( 26705 663 ) L1M1_PR_MR + NEW li1 ( 26427 221 ) L1M1_PR_MR + NEW met1 ( 26427 221 ) M1M2_PR ; + - word_q.w2_b6 ( mux_slice0_bit6.s1_aoi_1 A2 ) ( storage_1_2_0.bit6.obuf0 Z ) ( storage_0_2_0.bit6.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 31027 493 ) ( 31303 * ) + NEW met2 ( 31303 493 ) ( * 663 ) + NEW met1 ( 31303 663 ) ( 31305 * ) + NEW met2 ( 30935 221 ) ( * 323 ) + NEW li1 ( 31027 493 ) L1M1_PR_MR + NEW met1 ( 31303 493 ) M1M2_PR + NEW met1 ( 31303 663 ) M1M2_PR + NEW li1 ( 31305 663 ) L1M1_PR_MR + NEW li1 ( 30935 221 ) L1M1_PR_MR + NEW met1 ( 30935 221 ) M1M2_PR + NEW li1 ( 30935 323 ) L1M1_PR_MR + NEW met1 ( 30935 323 ) M1M2_PR ; + - word_q.w2_b7 ( mux_slice0_bit7.s1_aoi_1 A2 ) ( storage_1_2_0.bit7.obuf0 Z ) ( storage_0_2_0.bit7.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 35627 493 ) ( * 578 ) + NEW met3 ( 35627 578 ) ( 35903 * ) + NEW met2 ( 35903 578 ) ( * 663 ) + NEW met1 ( 35903 663 ) ( 35905 * ) + NEW met2 ( 35627 221 ) ( * 493 ) + NEW li1 ( 35627 493 ) L1M1_PR_MR + NEW met1 ( 35627 493 ) M1M2_PR + NEW met2 ( 35627 578 ) M2M3_PR + NEW met2 ( 35903 578 ) M2M3_PR + NEW met1 ( 35903 663 ) M1M2_PR + NEW li1 ( 35905 663 ) L1M1_PR_MR + NEW li1 ( 35627 221 ) L1M1_PR_MR + NEW met1 ( 35627 221 ) M1M2_PR ; + - word_q.w3_b0 ( mux_slice0_bit0.s1_aoi_1 B2 ) ( storage_1_3_0.bit0.obuf0 Z ) ( storage_0_3_0.bit0.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 4439 357 ) ( * 731 ) + NEW met1 ( 3519 731 ) ( 4439 * ) + NEW met1 ( 3519 663 ) ( * 731 ) + NEW met2 ( 4439 221 ) ( * 357 ) + NEW li1 ( 4439 357 ) L1M1_PR_MR + NEW met1 ( 4439 357 ) M1M2_PR + NEW met1 ( 4439 731 ) M1M2_PR + NEW li1 ( 3519 663 ) L1M1_PR_MR + NEW li1 ( 4439 221 ) L1M1_PR_MR + NEW met1 ( 4439 221 ) M1M2_PR ; + - word_q.w3_b1 ( mux_slice0_bit1.s1_aoi_1 B2 ) ( storage_1_3_0.bit1.obuf0 Z ) ( storage_0_3_0.bit1.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 9085 221 ) ( * 323 ) + NEW met2 ( 8119 493 ) ( * 663 ) + NEW met1 ( 8119 493 ) ( 9177 * ) + NEW li1 ( 9177 493 ) L1M1_PR_MR + NEW li1 ( 9085 221 ) L1M1_PR_MR + NEW met1 ( 9085 221 ) M1M2_PR + NEW li1 ( 9085 323 ) L1M1_PR_MR + NEW met1 ( 9085 323 ) M1M2_PR + NEW met1 ( 8119 493 ) M1M2_PR + NEW li1 ( 8119 663 ) L1M1_PR_MR + NEW met1 ( 8119 663 ) M1M2_PR ; + - word_q.w3_b2 ( mux_slice0_bit2.s1_aoi_1 B2 ) ( storage_1_3_0.bit2.obuf0 Z ) ( storage_0_3_0.bit2.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 12719 493 ) ( 13777 * ) + NEW met2 ( 12719 493 ) ( * 663 ) + NEW met2 ( 13639 221 ) ( * 357 ) + NEW li1 ( 13777 493 ) L1M1_PR_MR + NEW met1 ( 12719 493 ) M1M2_PR + NEW li1 ( 12719 663 ) L1M1_PR_MR + NEW met1 ( 12719 663 ) M1M2_PR + NEW li1 ( 13639 221 ) L1M1_PR_MR + NEW met1 ( 13639 221 ) M1M2_PR + NEW li1 ( 13639 357 ) L1M1_PR_MR + NEW met1 ( 13639 357 ) M1M2_PR ; + - word_q.w3_b3 ( mux_slice0_bit3.s1_aoi_1 B2 ) ( storage_1_3_0.bit3.obuf0 Z ) ( storage_0_3_0.bit3.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 18285 493 ) ( 18377 * ) + NEW met2 ( 18285 493 ) ( * 765 ) + NEW met1 ( 17365 765 ) ( 18285 * ) + NEW met1 ( 17365 663 ) ( * 765 ) + NEW met1 ( 17319 663 ) ( 17365 * ) + NEW met2 ( 18285 221 ) ( * 493 ) + NEW li1 ( 18377 493 ) L1M1_PR_MR + NEW met1 ( 18285 493 ) M1M2_PR + NEW met1 ( 18285 765 ) M1M2_PR + NEW li1 ( 17319 663 ) L1M1_PR_MR + NEW li1 ( 18285 221 ) L1M1_PR_MR + NEW met1 ( 18285 221 ) M1M2_PR ; + - word_q.w3_b4 ( mux_slice0_bit4.s1_aoi_1 B2 ) ( storage_1_3_0.bit4.obuf0 Z ) ( storage_0_3_0.bit4.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 21827 425 ) ( 22977 * ) + NEW met2 ( 21827 425 ) ( * 629 ) + NEW met2 ( 21827 629 ) ( 21873 * ) + NEW met1 ( 21873 629 ) ( 21919 * ) + NEW met2 ( 22839 221 ) ( * 425 ) + NEW li1 ( 22977 425 ) L1M1_PR_MR + NEW met1 ( 21827 425 ) M1M2_PR + NEW met1 ( 21873 629 ) M1M2_PR + NEW li1 ( 21919 629 ) L1M1_PR_MR + NEW li1 ( 22839 221 ) L1M1_PR_MR + NEW met1 ( 22839 221 ) M1M2_PR + NEW met1 ( 22839 425 ) M1M2_PR ; + - word_q.w3_b5 ( mux_slice0_bit5.s1_aoi_1 B2 ) ( storage_1_3_0.bit5.obuf0 Z ) ( storage_0_3_0.bit5.obuf0 Z ) + USE SIGNAL + + ROUTED met1 ( 26565 493 ) ( 27577 * ) + NEW met2 ( 26565 493 ) ( * 629 ) + NEW met1 ( 26519 629 ) ( 26565 * ) + NEW met2 ( 27439 221 ) ( * 323 ) + NEW li1 ( 27577 493 ) L1M1_PR_MR + NEW met1 ( 26565 493 ) M1M2_PR + NEW met1 ( 26565 629 ) M1M2_PR + NEW li1 ( 26519 629 ) L1M1_PR_MR + NEW li1 ( 27439 221 ) L1M1_PR_MR + NEW met1 ( 27439 221 ) M1M2_PR + NEW li1 ( 27439 323 ) L1M1_PR_MR + NEW met1 ( 27439 323 ) M1M2_PR ; + - word_q.w3_b6 ( mux_slice0_bit6.s1_aoi_1 B2 ) ( storage_1_3_0.bit6.obuf0 Z ) ( storage_0_3_0.bit6.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 32177 493 ) ( * 595 ) + NEW met1 ( 31165 595 ) ( 32177 * ) + NEW met1 ( 31165 595 ) ( * 629 ) + NEW met1 ( 31119 629 ) ( 31165 * ) + NEW met2 ( 32177 221 ) ( * 493 ) + NEW li1 ( 32177 493 ) L1M1_PR_MR + NEW met1 ( 32177 493 ) M1M2_PR + NEW met1 ( 32177 595 ) M1M2_PR + NEW li1 ( 31119 629 ) L1M1_PR_MR + NEW li1 ( 32177 221 ) L1M1_PR_MR + NEW met1 ( 32177 221 ) M1M2_PR ; + - word_q.w3_b7 ( mux_slice0_bit7.s1_aoi_1 B2 ) ( storage_1_3_0.bit7.obuf0 Z ) ( storage_0_3_0.bit7.obuf0 Z ) + USE SIGNAL + + ROUTED met2 ( 35719 493 ) ( * 629 ) + NEW met2 ( 36685 221 ) ( * 323 ) + NEW met1 ( 35719 493 ) ( 36777 * ) + NEW met1 ( 35719 493 ) M1M2_PR + NEW li1 ( 35719 629 ) L1M1_PR_MR + NEW met1 ( 35719 629 ) M1M2_PR + NEW li1 ( 36777 493 ) L1M1_PR_MR + NEW li1 ( 36685 221 ) L1M1_PR_MR + NEW met1 ( 36685 221 ) M1M2_PR + NEW li1 ( 36685 323 ) L1M1_PR_MR + NEW met1 ( 36685 323 ) M1M2_PR ; + - word_sel.0 ( storage_1_0_0.word_and B ) ( storage_0_0_0.word_and B ) ( word_sel.and_0 X ) + USE SIGNAL + + ROUTED met1 ( 37605 391 ) ( 37789 * ) + NEW met1 ( 37789 357 ) ( * 391 ) + NEW met1 ( 37789 357 ) ( 38065 * ) + NEW met1 ( 38065 323 ) ( * 357 ) + NEW met2 ( 37605 153 ) ( * 391 ) + NEW met2 ( 40641 323 ) ( * 595 ) + NEW met1 ( 38065 323 ) ( 40641 * ) + NEW li1 ( 37605 391 ) L1M1_PR_MR + NEW li1 ( 37605 153 ) L1M1_PR_MR + NEW met1 ( 37605 153 ) M1M2_PR + NEW met1 ( 37605 391 ) M1M2_PR + NEW met1 ( 40641 323 ) M1M2_PR + NEW li1 ( 40641 595 ) L1M1_PR_MR + NEW met1 ( 40641 595 ) M1M2_PR ; + - word_sel.1 ( storage_1_1_0.word_and B ) ( storage_0_1_0.word_and B ) ( word_sel.and_1 X ) + USE SIGNAL + + ROUTED met1 ( 38893 425 ) ( 39261 * ) + NEW met1 ( 39261 425 ) ( * 493 ) + NEW met2 ( 38893 153 ) ( * 425 ) + NEW met2 ( 40871 493 ) ( * 595 ) + NEW met1 ( 39261 493 ) ( 40871 * ) + NEW li1 ( 38893 425 ) L1M1_PR_MR + NEW li1 ( 38893 153 ) L1M1_PR_MR + NEW met1 ( 38893 153 ) M1M2_PR + NEW met1 ( 38893 425 ) M1M2_PR + NEW met1 ( 40871 493 ) M1M2_PR + NEW li1 ( 40871 595 ) L1M1_PR_MR + NEW met1 ( 40871 595 ) M1M2_PR ; + - word_sel.2 ( storage_1_2_0.word_and B ) ( storage_0_2_0.word_and B ) ( word_sel.and_2 X ) + USE SIGNAL + + ROUTED met1 ( 40043 425 ) ( 40089 * ) + NEW met2 ( 40089 425 ) ( * 731 ) + NEW met1 ( 40089 731 ) ( 41101 * ) + NEW met1 ( 40043 153 ) ( 40089 * ) + NEW met2 ( 40089 153 ) ( * 425 ) + NEW li1 ( 40043 425 ) L1M1_PR_MR + NEW met1 ( 40089 425 ) M1M2_PR + NEW met1 ( 40089 731 ) M1M2_PR + NEW li1 ( 41101 731 ) L1M1_PR_MR + NEW li1 ( 40043 153 ) L1M1_PR_MR + NEW met1 ( 40089 153 ) M1M2_PR ; + - word_sel.3 ( storage_1_3_0.word_and B ) ( storage_0_3_0.word_and B ) ( word_sel.and_3 X ) + USE SIGNAL + + ROUTED met1 ( 41193 425 ) ( 41331 * ) + NEW met2 ( 41331 425 ) ( * 595 ) + NEW met2 ( 41193 153 ) ( * 425 ) + NEW li1 ( 41193 425 ) L1M1_PR_MR + NEW met1 ( 41331 425 ) M1M2_PR + NEW li1 ( 41331 595 ) L1M1_PR_MR + NEW met1 ( 41331 595 ) M1M2_PR + NEW li1 ( 41193 153 ) L1M1_PR_MR + NEW met1 ( 41193 153 ) M1M2_PR + NEW met1 ( 41193 425 ) M1M2_PR ; +END NETS +END DESIGN diff --git a/src/ram/test/make_8x8_mux4_sky130.lefok b/src/ram/test/make_8x8_mux4_sky130.lefok new file mode 100644 index 00000000000..801bab69318 --- /dev/null +++ b/src/ram/test/make_8x8_mux4_sky130.lefok @@ -0,0 +1,565 @@ +VERSION 5.8 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MACRO RAM8x8 + FOREIGN RAM8x8 0 0 ; + CLASS BLOCK ; + SIZE 417.68 BY 8.16 ; + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 416.88 1.55 417.68 1.85 ; + END + END clk + PIN we[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 416.88 2.91 417.68 3.21 ; + END + END we[0] + PIN addr_rw[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 416.88 4.27 417.68 4.57 ; + END + END addr_rw[0] + PIN addr_rw[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 416.88 5.63 417.68 5.93 ; + END + END addr_rw[1] + PIN addr_rw[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 416.88 0.19 417.68 0.49 ; + END + END addr_rw[2] + PIN D[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 1.08 7.675 1.22 8.16 ; + END + END D[0] + PIN Q[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 7.675 24.22 8.16 ; + END + END Q[0] + PIN D[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 7.675 47.22 8.16 ; + END + END D[1] + PIN Q[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.92 7.675 49.06 8.16 ; + END + END Q[1] + PIN D[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.08 7.675 93.22 8.16 ; + END + END D[2] + PIN Q[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 117 7.675 117.14 8.16 ; + END + END Q[2] + PIN D[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 139.08 7.675 139.22 8.16 ; + END + END D[3] + PIN Q[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 163 7.675 163.14 8.16 ; + END + END Q[3] + PIN D[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 184.16 7.675 184.3 8.16 ; + END + END D[4] + PIN Q[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 209 7.675 209.14 8.16 ; + END + END Q[4] + PIN D[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 231.08 7.675 231.22 8.16 ; + END + END D[5] + PIN Q[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 254.08 7.675 254.22 8.16 ; + END + END Q[5] + PIN D[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 277.08 7.675 277.22 8.16 ; + END + END D[6] + PIN Q[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 301 7.675 301.14 8.16 ; + END + END Q[6] + PIN D[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 323.08 7.675 323.22 8.16 ; + END + END D[7] + PIN Q[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 347 7.675 347.14 8.16 ; + END + END Q[7] + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met3 ; + RECT 417.38 6.76 417.68 7.24 ; + RECT 0 6.76 0.3 7.24 ; + LAYER met2 ; + RECT 409.76 8.02 410.24 8.16 ; + RECT 409.76 0 410.24 0.14 ; + RECT 399.76 8.02 400.24 8.16 ; + RECT 399.76 0 400.24 0.14 ; + RECT 389.76 8.02 390.24 8.16 ; + RECT 389.76 0 390.24 0.14 ; + RECT 379.76 8.02 380.24 8.16 ; + RECT 379.76 0 380.24 0.14 ; + RECT 369.76 8.02 370.24 8.16 ; + RECT 369.76 0 370.24 0.14 ; + RECT 359.76 8.02 360.24 8.16 ; + RECT 359.76 0 360.24 0.14 ; + RECT 349.76 8.02 350.24 8.16 ; + RECT 349.76 0 350.24 0.14 ; + RECT 339.76 8.02 340.24 8.16 ; + RECT 339.76 0 340.24 0.14 ; + RECT 329.76 8.02 330.24 8.16 ; + RECT 329.76 0 330.24 0.14 ; + RECT 319.76 8.02 320.24 8.16 ; + RECT 319.76 0 320.24 0.14 ; + RECT 309.76 8.02 310.24 8.16 ; + RECT 309.76 0 310.24 0.14 ; + RECT 299.76 8.02 300.24 8.16 ; + RECT 299.76 0 300.24 0.14 ; + RECT 289.76 8.02 290.24 8.16 ; + RECT 289.76 0 290.24 0.14 ; + RECT 279.76 8.02 280.24 8.16 ; + RECT 279.76 0 280.24 0.14 ; + RECT 269.76 8.02 270.24 8.16 ; + RECT 269.76 0 270.24 0.14 ; + RECT 259.76 8.02 260.24 8.16 ; + RECT 259.76 0 260.24 0.14 ; + RECT 249.76 8.02 250.24 8.16 ; + RECT 249.76 0 250.24 0.14 ; + RECT 239.76 8.02 240.24 8.16 ; + RECT 239.76 0 240.24 0.14 ; + RECT 229.76 8.02 230.24 8.16 ; + RECT 229.76 0 230.24 0.14 ; + RECT 219.76 8.02 220.24 8.16 ; + RECT 219.76 0 220.24 0.14 ; + RECT 209.76 8.02 210.24 8.16 ; + RECT 209.76 0 210.24 0.14 ; + RECT 199.76 8.02 200.24 8.16 ; + RECT 199.76 0 200.24 0.14 ; + RECT 189.76 8.02 190.24 8.16 ; + RECT 189.76 0 190.24 0.14 ; + RECT 179.76 8.02 180.24 8.16 ; + RECT 179.76 0 180.24 0.14 ; + RECT 169.76 8.02 170.24 8.16 ; + RECT 169.76 0 170.24 0.14 ; + RECT 159.76 8.02 160.24 8.16 ; + RECT 159.76 0 160.24 0.14 ; + RECT 149.76 8.02 150.24 8.16 ; + RECT 149.76 0 150.24 0.14 ; + RECT 139.76 8.02 140.24 8.16 ; + RECT 139.76 0 140.24 0.14 ; + RECT 129.76 8.02 130.24 8.16 ; + RECT 129.76 0 130.24 0.14 ; + RECT 119.76 8.02 120.24 8.16 ; + RECT 119.76 0 120.24 0.14 ; + RECT 109.76 8.02 110.24 8.16 ; + RECT 109.76 0 110.24 0.14 ; + RECT 99.76 8.02 100.24 8.16 ; + RECT 99.76 0 100.24 0.14 ; + RECT 89.76 8.02 90.24 8.16 ; + RECT 89.76 0 90.24 0.14 ; + RECT 79.76 8.02 80.24 8.16 ; + RECT 79.76 0 80.24 0.14 ; + RECT 69.76 8.02 70.24 8.16 ; + RECT 69.76 0 70.24 0.14 ; + RECT 59.76 8.02 60.24 8.16 ; + RECT 59.76 0 60.24 0.14 ; + RECT 49.76 8.02 50.24 8.16 ; + RECT 49.76 0 50.24 0.14 ; + RECT 39.76 8.02 40.24 8.16 ; + RECT 39.76 0 40.24 0.14 ; + RECT 29.76 8.02 30.24 8.16 ; + RECT 29.76 0 30.24 0.14 ; + RECT 19.76 8.02 20.24 8.16 ; + RECT 19.76 0 20.24 0.14 ; + RECT 9.76 8.02 10.24 8.16 ; + RECT 9.76 0 10.24 0.14 ; + LAYER met1 ; + RECT 417.54 5.2 417.68 5.68 ; + RECT 0 5.2 0.14 5.68 ; + RECT 417.54 -0.24 417.68 0.24 ; + RECT 0 -0.24 0.14 0.24 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met3 ; + RECT 417.38 3.26 417.68 3.74 ; + RECT 0 3.26 0.3 3.74 ; + LAYER met2 ; + RECT 414.76 8.02 415.24 8.16 ; + RECT 414.76 0 415.24 0.14 ; + RECT 404.76 8.02 405.24 8.16 ; + RECT 404.76 0 405.24 0.14 ; + RECT 394.76 8.02 395.24 8.16 ; + RECT 394.76 0 395.24 0.14 ; + RECT 384.76 8.02 385.24 8.16 ; + RECT 384.76 0 385.24 0.14 ; + RECT 374.76 8.02 375.24 8.16 ; + RECT 374.76 0 375.24 0.14 ; + RECT 364.76 8.02 365.24 8.16 ; + RECT 364.76 0 365.24 0.14 ; + RECT 354.76 8.02 355.24 8.16 ; + RECT 354.76 0 355.24 0.14 ; + RECT 344.76 8.02 345.24 8.16 ; + RECT 344.76 0 345.24 0.14 ; + RECT 334.76 8.02 335.24 8.16 ; + RECT 334.76 0 335.24 0.14 ; + RECT 324.76 8.02 325.24 8.16 ; + RECT 324.76 0 325.24 0.14 ; + RECT 314.76 8.02 315.24 8.16 ; + RECT 314.76 0 315.24 0.14 ; + RECT 304.76 8.02 305.24 8.16 ; + RECT 304.76 0 305.24 0.14 ; + RECT 294.76 8.02 295.24 8.16 ; + RECT 294.76 0 295.24 0.14 ; + RECT 284.76 8.02 285.24 8.16 ; + RECT 284.76 0 285.24 0.14 ; + RECT 274.76 8.02 275.24 8.16 ; + RECT 274.76 0 275.24 0.14 ; + RECT 264.76 8.02 265.24 8.16 ; + RECT 264.76 0 265.24 0.14 ; + RECT 254.76 8.02 255.24 8.16 ; + RECT 254.76 0 255.24 0.14 ; + RECT 244.76 8.02 245.24 8.16 ; + RECT 244.76 0 245.24 0.14 ; + RECT 234.76 8.02 235.24 8.16 ; + RECT 234.76 0 235.24 0.14 ; + RECT 224.76 8.02 225.24 8.16 ; + RECT 224.76 0 225.24 0.14 ; + RECT 214.76 8.02 215.24 8.16 ; + RECT 214.76 0 215.24 0.14 ; + RECT 204.76 8.02 205.24 8.16 ; + RECT 204.76 0 205.24 0.14 ; + RECT 194.76 8.02 195.24 8.16 ; + RECT 194.76 0 195.24 0.14 ; + RECT 184.76 8.02 185.24 8.16 ; + RECT 184.76 0 185.24 0.14 ; + RECT 174.76 8.02 175.24 8.16 ; + RECT 174.76 0 175.24 0.14 ; + RECT 164.76 8.02 165.24 8.16 ; + RECT 164.76 0 165.24 0.14 ; + RECT 154.76 8.02 155.24 8.16 ; + RECT 154.76 0 155.24 0.14 ; + RECT 144.76 8.02 145.24 8.16 ; + RECT 144.76 0 145.24 0.14 ; + RECT 134.76 8.02 135.24 8.16 ; + RECT 134.76 0 135.24 0.14 ; + RECT 124.76 8.02 125.24 8.16 ; + RECT 124.76 0 125.24 0.14 ; + RECT 114.76 8.02 115.24 8.16 ; + RECT 114.76 0 115.24 0.14 ; + RECT 104.76 8.02 105.24 8.16 ; + RECT 104.76 0 105.24 0.14 ; + RECT 94.76 8.02 95.24 8.16 ; + RECT 94.76 0 95.24 0.14 ; + RECT 84.76 8.02 85.24 8.16 ; + RECT 84.76 0 85.24 0.14 ; + RECT 74.76 8.02 75.24 8.16 ; + RECT 74.76 0 75.24 0.14 ; + RECT 64.76 8.02 65.24 8.16 ; + RECT 64.76 0 65.24 0.14 ; + RECT 54.76 8.02 55.24 8.16 ; + RECT 54.76 0 55.24 0.14 ; + RECT 44.76 8.02 45.24 8.16 ; + RECT 44.76 0 45.24 0.14 ; + RECT 34.76 8.02 35.24 8.16 ; + RECT 34.76 0 35.24 0.14 ; + RECT 24.76 8.02 25.24 8.16 ; + RECT 24.76 0 25.24 0.14 ; + RECT 14.76 8.02 15.24 8.16 ; + RECT 14.76 0 15.24 0.14 ; + RECT 4.76 8.02 5.24 8.16 ; + RECT 4.76 0 5.24 0.14 ; + LAYER met1 ; + RECT 417.54 7.92 417.68 8.4 ; + RECT 0 7.92 0.14 8.4 ; + RECT 417.54 2.48 417.68 2.96 ; + RECT 0 2.48 0.14 2.96 ; + END + END VDD + OBS + LAYER li1 ; + RECT 0 -0.085 417.68 8.245 ; + LAYER met1 ; + RECT 0 -0.24 417.68 8.4 ; + LAYER met2 ; + RECT 9.76 -0.24 10.24 0 ; + RECT 19.76 -0.24 20.24 0 ; + RECT 29.76 -0.24 30.24 0 ; + RECT 39.76 -0.24 40.24 0 ; + RECT 49.76 -0.24 50.24 0 ; + RECT 59.76 -0.24 60.24 0 ; + RECT 69.76 -0.24 70.24 0 ; + RECT 79.76 -0.24 80.24 0 ; + RECT 89.76 -0.24 90.24 0 ; + RECT 99.76 -0.24 100.24 0 ; + RECT 109.76 -0.24 110.24 0 ; + RECT 119.76 -0.24 120.24 0 ; + RECT 129.76 -0.24 130.24 0 ; + RECT 139.76 -0.24 140.24 0 ; + RECT 149.76 -0.24 150.24 0 ; + RECT 159.76 -0.24 160.24 0 ; + RECT 169.76 -0.24 170.24 0 ; + RECT 179.76 -0.24 180.24 0 ; + RECT 189.76 -0.24 190.24 0 ; + RECT 199.76 -0.24 200.24 0 ; + RECT 209.76 -0.24 210.24 0 ; + RECT 219.76 -0.24 220.24 0 ; + RECT 229.76 -0.24 230.24 0 ; + RECT 239.76 -0.24 240.24 0 ; + RECT 249.76 -0.24 250.24 0 ; + RECT 259.76 -0.24 260.24 0 ; + RECT 269.76 -0.24 270.24 0 ; + RECT 279.76 -0.24 280.24 0 ; + RECT 289.76 -0.24 290.24 0 ; + RECT 299.76 -0.24 300.24 0 ; + RECT 309.76 -0.24 310.24 0 ; + RECT 319.76 -0.24 320.24 0 ; + RECT 329.76 -0.24 330.24 0 ; + RECT 339.76 -0.24 340.24 0 ; + RECT 349.76 -0.24 350.24 0 ; + RECT 359.76 -0.24 360.24 0 ; + RECT 369.76 -0.24 370.24 0 ; + RECT 379.76 -0.24 380.24 0 ; + RECT 389.76 -0.24 390.24 0 ; + RECT 399.76 -0.24 400.24 0 ; + RECT 409.76 -0.24 410.24 0 ; + RECT 4.76 0 415.24 0.155 ; + RECT 4.76 0.155 416.67 0.525 ; + RECT 4.76 0.525 416.66 1.03 ; + RECT 1.94 1.03 416.66 2.195 ; + RECT 0.55 2.195 416.66 2.565 ; + RECT 0.56 2.565 416.66 3.39 ; + RECT 0.56 3.39 415.75 4.07 ; + RECT 1.02 4.07 415.75 5.965 ; + RECT 1.02 5.965 415.74 6.79 ; + RECT 1.08 6.79 415.74 7.81 ; + RECT 1.08 7.81 415.24 7.82 ; + RECT 4.76 7.82 415.24 8.16 ; + RECT 4.76 8.16 5.24 8.4 ; + RECT 14.76 8.16 15.24 8.4 ; + RECT 24.76 8.16 25.24 8.4 ; + RECT 34.76 8.16 35.24 8.4 ; + RECT 44.76 8.16 45.24 8.4 ; + RECT 54.76 8.16 55.24 8.4 ; + RECT 64.76 8.16 65.24 8.4 ; + RECT 74.76 8.16 75.24 8.4 ; + RECT 84.76 8.16 85.24 8.4 ; + RECT 94.76 8.16 95.24 8.4 ; + RECT 104.76 8.16 105.24 8.4 ; + RECT 114.76 8.16 115.24 8.4 ; + RECT 124.76 8.16 125.24 8.4 ; + RECT 134.76 8.16 135.24 8.4 ; + RECT 144.76 8.16 145.24 8.4 ; + RECT 154.76 8.16 155.24 8.4 ; + RECT 164.76 8.16 165.24 8.4 ; + RECT 174.76 8.16 175.24 8.4 ; + RECT 184.76 8.16 185.24 8.4 ; + RECT 194.76 8.16 195.24 8.4 ; + RECT 204.76 8.16 205.24 8.4 ; + RECT 214.76 8.16 215.24 8.4 ; + RECT 224.76 8.16 225.24 8.4 ; + RECT 234.76 8.16 235.24 8.4 ; + RECT 244.76 8.16 245.24 8.4 ; + RECT 254.76 8.16 255.24 8.4 ; + RECT 264.76 8.16 265.24 8.4 ; + RECT 274.76 8.16 275.24 8.4 ; + RECT 284.76 8.16 285.24 8.4 ; + RECT 294.76 8.16 295.24 8.4 ; + RECT 304.76 8.16 305.24 8.4 ; + RECT 314.76 8.16 315.24 8.4 ; + RECT 324.76 8.16 325.24 8.4 ; + RECT 334.76 8.16 335.24 8.4 ; + RECT 344.76 8.16 345.24 8.4 ; + RECT 354.76 8.16 355.24 8.4 ; + RECT 364.76 8.16 365.24 8.4 ; + RECT 374.76 8.16 375.24 8.4 ; + RECT 384.76 8.16 385.24 8.4 ; + RECT 394.76 8.16 395.24 8.4 ; + RECT 404.76 8.16 405.24 8.4 ; + RECT 414.76 8.16 415.24 8.4 ; + LAYER met3 ; + RECT 0 3.26 0.525 7.24 ; + RECT 0.525 2.215 12.025 7.24 ; + RECT 12.025 1.535 12.945 7.24 ; + RECT 12.945 1.535 13.275 7.985 ; + RECT 13.275 1.535 23.525 7.97 ; + RECT 23.525 0.855 23.855 7.97 ; + RECT 23.855 0.87 35.945 7.97 ; + RECT 35.945 0.87 36.275 7.985 ; + RECT 36.275 0.87 46.525 7.24 ; + RECT 46.525 0.175 57.565 7.24 ; + RECT 57.565 0.175 59.275 7.985 ; + RECT 59.275 0.175 66.175 7.97 ; + RECT 66.175 0.19 77.805 7.97 ; + RECT 77.805 0.19 82.735 7.985 ; + RECT 82.735 0.19 82.96 7.97 ; + RECT 82.96 0.19 89.305 7.24 ; + RECT 89.305 0.175 89.635 7.24 ; + RECT 89.635 0.855 103.105 7.24 ; + RECT 103.105 0.855 103.435 7.985 ; + RECT 103.435 0.855 113.685 7.97 ; + RECT 113.685 0.175 118.285 7.97 ; + RECT 118.285 0.175 126.435 7.985 ; + RECT 126.435 0.175 129.195 7.97 ; + RECT 129.195 0.87 148.645 7.97 ; + RECT 148.645 0.175 159.555 7.97 ; + RECT 159.555 0.19 171.645 7.97 ; + RECT 171.645 0.19 175.785 7.985 ; + RECT 175.785 0.175 176.115 7.985 ; + RECT 176.115 0.87 194.185 7.24 ; + RECT 194.185 0.87 194.515 7.985 ; + RECT 194.515 0.87 203.845 7.97 ; + RECT 203.845 0.855 204.305 7.97 ; + RECT 204.305 0.175 204.635 7.97 ; + RECT 204.635 0.19 216.265 7.97 ; + RECT 216.265 0.19 217.515 7.985 ; + RECT 217.515 0.19 229.145 7.97 ; + RECT 229.145 0.175 240.975 7.97 ; + RECT 240.975 0.19 251.225 7.97 ; + RECT 251.225 0.19 257.995 7.985 ; + RECT 257.995 0.19 259.17 7.98 ; + RECT 259.17 0.19 276.525 7.97 ; + RECT 276.525 0.175 282.045 7.97 ; + RECT 282.045 0.175 284.215 7.985 ; + RECT 284.215 0.175 298.935 7.97 ; + RECT 298.935 0.19 332.185 7.97 ; + RECT 332.185 0.19 333.435 7.985 ; + RECT 333.435 0.19 345.985 7.97 ; + RECT 345.985 0.175 347.365 7.97 ; + RECT 347.365 0.175 352.755 7.985 ; + RECT 352.755 0.855 357.355 7.985 ; + RECT 357.355 0.87 361.035 7.985 ; + RECT 361.035 0.87 410.385 7.24 ; + RECT 410.385 0.855 416.365 7.24 ; + RECT 416.365 0.175 416.695 7.24 ; + RECT 416.695 0.19 417.22 7.24 ; + RECT 417.22 2.23 417.37 7.24 ; + RECT 417.37 3.26 417.68 7.24 ; + LAYER met4 ; + RECT 47.215 0.175 65.945 0.855 ; + RECT 47.215 0.855 78.825 1.11 ; + RECT 113.455 0.855 113.785 1.185 ; + RECT 341.615 0.855 350.225 1.185 ; + RECT 113.47 1.185 113.785 1.55 ; + RECT 341.63 1.185 350.21 1.85 ; + RECT 113.47 1.55 122.05 2.215 ; + RECT 46.79 1.11 79.25 2.29 ; + RECT 113.47 2.215 122.065 2.545 ; + RECT 158.535 0.175 158.865 2.545 ; + RECT 57.83 2.29 79.25 4.51 ; + RECT 57.83 4.51 82.93 5.25 ; + RECT 113.47 2.545 120.225 5.25 ; + RECT 57.83 5.25 59.01 5.69 ; + RECT 81.75 5.25 82.93 5.69 ; + RECT 173.255 4.95 175.41 5.945 ; + RECT 174.175 5.945 175.41 7.655 ; + RECT 251.47 4.95 259.13 7.655 ; + RECT 58.255 5.69 58.585 7.985 ; + RECT 82.175 5.69 82.505 7.985 ; + RECT 119.895 5.25 120.225 7.985 ; + RECT 174.175 7.655 175.425 7.985 ; + RECT 251.455 7.655 259.145 7.985 ; + LAYER met5 ; + RECT 46.58 0.9 57.62 2.5 ; + RECT 57.62 0.9 79.46 5.9 ; + RECT 79.46 4.3 83.14 5.9 ; + END +END RAM8x8 +END LIBRARY diff --git a/src/ram/test/make_8x8_mux4_sky130.ok b/src/ram/test/make_8x8_mux4_sky130.ok new file mode 100644 index 00000000000..e7b78bbc993 --- /dev/null +++ b/src/ram/test/make_8x8_mux4_sky130.ok @@ -0,0 +1,78 @@ +[INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells +[INFO RAM-0003] Generating RAM8x8 +[INFO RAM-0016] Selected inverter cell sky130_fd_sc_hd__clkinv_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__clkinv_1: Y +[INFO RAM-0016] Selected tristate cell sky130_fd_sc_hd__ebufn_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__ebufn_1: Z +[INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__and2_0: X +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__dfxtp_1: Q +[INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__dlclkp_1: GCLK +[INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__buf_1: X +[INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 +[INFO RAM-0024] Behavioral Verilog written for RAM8x8 +[INFO PDN-0001] Inserting grid: ram_grid +[INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-417.68u at the TOP edge. +[INFO PPL-0067] Restrict pins [ clk we[0] addr_rw[0] addr_rw[1] addr_rw[2] ... ] to region 0.00u-8.16u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 830 +[INFO PPL-0002] Number of I/O 21 +[INFO PPL-0003] Number of I/O w/sink 21 +[INFO PPL-0004] Number of I/O w/o sink 0 +[INFO PPL-0005] Slots per section 200 +[INFO PPL-0008] Successfully assigned pins to sections. +[INFO PPL-0012] I/O nets HPWL: 990.17 um. +[INFO DPL-0001] Placed 120 filler instances. +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[INFO DRT-0167] List of default vias: + Layer via + default via: M1M2_PR + Layer via2 + default via: M2M3_PR + Layer via3 + default via: M3M4_PR + Layer via4 + default via: M4M5_PR +[INFO DRT-0168] Init region query. +[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. +[INFO DRT-0033] FR_VIA shape region query size = 0. +[INFO DRT-0033] li1 shape region query size = 8229. +[INFO DRT-0033] mcon shape region query size = 600. +[INFO DRT-0033] met1 shape region query size = 1572. +[INFO DRT-0033] via shape region query size = 166. +[INFO DRT-0033] met2 shape region query size = 514. +[INFO DRT-0033] via2 shape region query size = 83. +[INFO DRT-0033] met3 shape region query size = 94. +[INFO DRT-0033] via3 shape region query size = 0. +[INFO DRT-0033] met4 shape region query size = 0. +[INFO DRT-0033] via4 shape region query size = 0. +[INFO DRT-0033] met5 shape region query size = 0. +[INFO DRT-0178] Init guide query. +[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. +[INFO DRT-0036] FR_VIA guide region query size = 0. +[INFO DRT-0036] li1 guide region query size = 440. +[INFO DRT-0036] mcon guide region query size = 0. +[INFO DRT-0036] met1 guide region query size = 293. +[INFO DRT-0036] via guide region query size = 0. +[INFO DRT-0036] met2 guide region query size = 73. +[INFO DRT-0036] via2 guide region query size = 0. +[INFO DRT-0036] met3 guide region query size = 45. +[INFO DRT-0036] via3 guide region query size = 0. +[INFO DRT-0036] met4 guide region query size = 0. +[INFO DRT-0036] via4 guide region query size = 0. +[INFO DRT-0036] met5 guide region query size = 0. +[INFO DRT-0179] Init gr pin query. +No differences found. +No differences found. +No differences found. diff --git a/src/ram/test/make_8x8_mux4_sky130.tcl b/src/ram/test/make_8x8_mux4_sky130.tcl new file mode 100644 index 00000000000..a4467f35034 --- /dev/null +++ b/src/ram/test/make_8x8_mux4_sky130.tcl @@ -0,0 +1,40 @@ +source "helpers.tcl" + +set_thread_count [expr [cpu_count]] + +read_liberty sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib + +read_lef sky130hd/sky130hd.tlef +read_lef sky130hd/sky130_fd_sc_hd_merged.lef + +set behavioral_file [make_result_file make_8x8_mux4_behavioral.v] + +generate_ram \ + -mask_size 8 \ + -word_size 8 \ + -num_words 8 \ + -column_mux_ratio 4 \ + -read_ports 1 \ + -storage_cell sky130_fd_sc_hd__dfxtp_1 \ + -power_pin VPWR \ + -ground_pin VGND \ + -routing_layer {met1 0.48} \ + -ver_layer {met2 0.48 10} \ + -hor_layer {met3 0.48 7} \ + -filler_cells {sky130_fd_sc_hd__fill_1 sky130_fd_sc_hd__fill_2 \ + sky130_fd_sc_hd__fill_4 sky130_fd_sc_hd__fill_8} \ + -tapcell sky130_fd_sc_hd__tap_1 \ + -max_tap_dist 15 \ + -write_behavioral_verilog $behavioral_file + +write_verilog [make_result_file make_8x8_mux4_sky130.v] + +set lef_file [make_result_file make_8x8_mux4_sky130.lef] +write_abstract_lef $lef_file +diff_files make_8x8_mux4_sky130.lefok $lef_file + +set def_file [make_result_file make_8x8_mux4_sky130.def] +write_def $def_file +diff_files make_8x8_mux4_sky130.defok $def_file + +diff_files make_8x8_behavioral.vok $behavioral_file diff --git a/src/ram/test/make_8x8_sky130.defok b/src/ram/test/make_8x8_sky130.defok index 6bcee0b5908..db5c5e5456b 100644 --- a/src/ram/test/make_8x8_sky130.defok +++ b/src/ram/test/make_8x8_sky130.defok @@ -115,158 +115,158 @@ COMPONENTS 325 ; - decoder_7.and_layer0 sky130_fd_sc_hd__and2_0 + PLACED ( 10304 1904 ) FS ; - decoder_7.and_layer1 sky130_fd_sc_hd__and2_0 + PLACED ( 10534 1904 ) FS ; - decoder_7.buf_port0 sky130_fd_sc_hd__buf_1 + PLACED ( 10764 1904 ) FS ; - - storage_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 0 ) N ; - - storage_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 0 ) N ; - - storage_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 0 ) N ; - - storage_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 0 ) N ; - - storage_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 0 ) N ; - - storage_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 0 ) N ; - - storage_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 0 ) N ; - - storage_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 0 ) N ; - - storage_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 0 ) N ; - - storage_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 0 ) N ; - - storage_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 0 ) N ; - - storage_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 0 ) N ; - - storage_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 0 ) N ; - - storage_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 0 ) N ; - - storage_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 0 ) N ; - - storage_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 0 ) N ; - - storage_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 0 ) N ; - - storage_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 0 ) N ; - - storage_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 0 ) N ; - - storage_1_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 272 ) FS ; - - storage_1_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 272 ) FS ; - - storage_1_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 272 ) FS ; - - storage_1_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 272 ) FS ; - - storage_1_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 272 ) FS ; - - storage_1_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 272 ) FS ; - - storage_1_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 272 ) FS ; - - storage_1_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 272 ) FS ; - - storage_1_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 272 ) FS ; - - storage_1_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 272 ) FS ; - - storage_1_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 272 ) FS ; - - storage_1_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 272 ) FS ; - - storage_1_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 272 ) FS ; - - storage_1_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 272 ) FS ; - - storage_1_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 272 ) FS ; - - storage_1_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 272 ) FS ; - - storage_1_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 272 ) FS ; - - storage_1_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 272 ) FS ; - - storage_1_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 272 ) FS ; - - storage_2_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 544 ) N ; - - storage_2_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 544 ) N ; - - storage_2_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 544 ) N ; - - storage_2_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 544 ) N ; - - storage_2_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 544 ) N ; - - storage_2_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 544 ) N ; - - storage_2_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 544 ) N ; - - storage_2_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 544 ) N ; - - storage_2_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 544 ) N ; - - storage_2_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 544 ) N ; - - storage_2_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 544 ) N ; - - storage_2_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 544 ) N ; - - storage_2_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 544 ) N ; - - storage_2_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 544 ) N ; - - storage_2_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 544 ) N ; - - storage_2_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 544 ) N ; - - storage_2_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 544 ) N ; - - storage_2_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 544 ) N ; - - storage_2_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 544 ) N ; - - storage_3_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 816 ) FS ; - - storage_3_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 816 ) FS ; - - storage_3_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 816 ) FS ; - - storage_3_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 816 ) FS ; - - storage_3_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 816 ) FS ; - - storage_3_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 816 ) FS ; - - storage_3_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 816 ) FS ; - - storage_3_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 816 ) FS ; - - storage_3_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 816 ) FS ; - - storage_3_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 816 ) FS ; - - storage_3_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 816 ) FS ; - - storage_3_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 816 ) FS ; - - storage_3_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 816 ) FS ; - - storage_3_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 816 ) FS ; - - storage_3_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 816 ) FS ; - - storage_3_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 816 ) FS ; - - storage_3_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 816 ) FS ; - - storage_3_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 816 ) FS ; - - storage_3_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 816 ) FS ; - - storage_4_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1088 ) N ; - - storage_4_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1088 ) N ; - - storage_4_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1088 ) N ; - - storage_4_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1088 ) N ; - - storage_4_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1088 ) N ; - - storage_4_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1088 ) N ; - - storage_4_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1088 ) N ; - - storage_4_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1088 ) N ; - - storage_4_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1088 ) N ; - - storage_4_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1088 ) N ; - - storage_4_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1088 ) N ; - - storage_4_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1088 ) N ; - - storage_4_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1088 ) N ; - - storage_4_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1088 ) N ; - - storage_4_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1088 ) N ; - - storage_4_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1088 ) N ; - - storage_4_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1088 ) N ; - - storage_4_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1088 ) N ; - - storage_4_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1088 ) N ; - - storage_5_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1360 ) FS ; - - storage_5_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1360 ) FS ; - - storage_5_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1360 ) FS ; - - storage_5_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1360 ) FS ; - - storage_5_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1360 ) FS ; - - storage_5_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1360 ) FS ; - - storage_5_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1360 ) FS ; - - storage_5_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1360 ) FS ; - - storage_5_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1360 ) FS ; - - storage_5_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1360 ) FS ; - - storage_5_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1360 ) FS ; - - storage_5_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1360 ) FS ; - - storage_5_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1360 ) FS ; - - storage_5_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1360 ) FS ; - - storage_5_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1360 ) FS ; - - storage_5_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1360 ) FS ; - - storage_5_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1360 ) FS ; - - storage_5_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1360 ) FS ; - - storage_5_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1360 ) FS ; - - storage_6_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1632 ) N ; - - storage_6_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1632 ) N ; - - storage_6_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1632 ) N ; - - storage_6_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1632 ) N ; - - storage_6_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1632 ) N ; - - storage_6_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1632 ) N ; - - storage_6_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1632 ) N ; - - storage_6_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1632 ) N ; - - storage_6_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1632 ) N ; - - storage_6_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1632 ) N ; - - storage_6_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1632 ) N ; - - storage_6_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1632 ) N ; - - storage_6_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1632 ) N ; - - storage_6_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1632 ) N ; - - storage_6_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1632 ) N ; - - storage_6_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1632 ) N ; - - storage_6_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1632 ) N ; - - storage_6_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1632 ) N ; - - storage_6_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1632 ) N ; - - storage_7_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1904 ) FS ; - - storage_7_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1904 ) FS ; - - storage_7_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1904 ) FS ; - - storage_7_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1904 ) FS ; - - storage_7_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1904 ) FS ; - - storage_7_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1904 ) FS ; - - storage_7_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1904 ) FS ; - - storage_7_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1904 ) FS ; - - storage_7_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1904 ) FS ; - - storage_7_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1904 ) FS ; - - storage_7_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1904 ) FS ; - - storage_7_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1904 ) FS ; - - storage_7_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1904 ) FS ; - - storage_7_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1904 ) FS ; - - storage_7_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1904 ) FS ; - - storage_7_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1904 ) FS ; - - storage_7_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1904 ) FS ; - - storage_7_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1904 ) FS ; - - storage_7_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1904 ) FS ; + - storage_0_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 0 ) N ; + - storage_0_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 0 ) N ; + - storage_0_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 0 ) N ; + - storage_0_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 0 ) N ; + - storage_0_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 0 ) N ; + - storage_0_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 0 ) N ; + - storage_0_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 0 ) N ; + - storage_0_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 0 ) N ; + - storage_0_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 0 ) N ; + - storage_0_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 0 ) N ; + - storage_0_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 0 ) N ; + - storage_0_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 0 ) N ; + - storage_0_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 0 ) N ; + - storage_0_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 0 ) N ; + - storage_0_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 0 ) N ; + - storage_0_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 0 ) N ; + - storage_0_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 0 ) N ; + - storage_0_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 0 ) N ; + - storage_0_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 0 ) N ; + - storage_1_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 272 ) FS ; + - storage_1_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 272 ) FS ; + - storage_1_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 272 ) FS ; + - storage_1_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 272 ) FS ; + - storage_1_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 272 ) FS ; + - storage_1_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 272 ) FS ; + - storage_1_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 272 ) FS ; + - storage_1_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 272 ) FS ; + - storage_1_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 272 ) FS ; + - storage_1_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 272 ) FS ; + - storage_1_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 272 ) FS ; + - storage_1_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 272 ) FS ; + - storage_1_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 272 ) FS ; + - storage_1_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 272 ) FS ; + - storage_1_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 272 ) FS ; + - storage_1_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 272 ) FS ; + - storage_1_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 272 ) FS ; + - storage_1_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 272 ) FS ; + - storage_1_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 272 ) FS ; + - storage_2_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 544 ) N ; + - storage_2_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 544 ) N ; + - storage_2_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 544 ) N ; + - storage_2_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 544 ) N ; + - storage_2_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 544 ) N ; + - storage_2_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 544 ) N ; + - storage_2_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 544 ) N ; + - storage_2_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 544 ) N ; + - storage_2_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 544 ) N ; + - storage_2_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 544 ) N ; + - storage_2_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 544 ) N ; + - storage_2_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 544 ) N ; + - storage_2_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 544 ) N ; + - storage_2_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 544 ) N ; + - storage_2_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 544 ) N ; + - storage_2_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 544 ) N ; + - storage_2_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 544 ) N ; + - storage_2_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 544 ) N ; + - storage_2_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 544 ) N ; + - storage_3_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 816 ) FS ; + - storage_3_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 816 ) FS ; + - storage_3_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 816 ) FS ; + - storage_3_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 816 ) FS ; + - storage_3_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 816 ) FS ; + - storage_3_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 816 ) FS ; + - storage_3_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 816 ) FS ; + - storage_3_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 816 ) FS ; + - storage_3_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 816 ) FS ; + - storage_3_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 816 ) FS ; + - storage_3_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 816 ) FS ; + - storage_3_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 816 ) FS ; + - storage_3_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 816 ) FS ; + - storage_3_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 816 ) FS ; + - storage_3_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 816 ) FS ; + - storage_3_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 816 ) FS ; + - storage_3_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 816 ) FS ; + - storage_3_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 816 ) FS ; + - storage_3_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 816 ) FS ; + - storage_4_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1088 ) N ; + - storage_4_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1088 ) N ; + - storage_4_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1088 ) N ; + - storage_4_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1088 ) N ; + - storage_4_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1088 ) N ; + - storage_4_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1088 ) N ; + - storage_4_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1088 ) N ; + - storage_4_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1088 ) N ; + - storage_4_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1088 ) N ; + - storage_4_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1088 ) N ; + - storage_4_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1088 ) N ; + - storage_4_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1088 ) N ; + - storage_4_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1088 ) N ; + - storage_4_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1088 ) N ; + - storage_4_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1088 ) N ; + - storage_4_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1088 ) N ; + - storage_4_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1088 ) N ; + - storage_4_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1088 ) N ; + - storage_4_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1088 ) N ; + - storage_5_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1360 ) FS ; + - storage_5_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1360 ) FS ; + - storage_5_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1360 ) FS ; + - storage_5_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1360 ) FS ; + - storage_5_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1360 ) FS ; + - storage_5_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1360 ) FS ; + - storage_5_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1360 ) FS ; + - storage_5_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1360 ) FS ; + - storage_5_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1360 ) FS ; + - storage_5_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1360 ) FS ; + - storage_5_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1360 ) FS ; + - storage_5_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1360 ) FS ; + - storage_5_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1360 ) FS ; + - storage_5_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1360 ) FS ; + - storage_5_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1360 ) FS ; + - storage_5_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1360 ) FS ; + - storage_5_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1360 ) FS ; + - storage_5_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1360 ) FS ; + - storage_5_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1360 ) FS ; + - storage_6_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1632 ) N ; + - storage_6_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1632 ) N ; + - storage_6_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1632 ) N ; + - storage_6_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1632 ) N ; + - storage_6_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1632 ) N ; + - storage_6_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1632 ) N ; + - storage_6_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1632 ) N ; + - storage_6_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1632 ) N ; + - storage_6_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1632 ) N ; + - storage_6_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1632 ) N ; + - storage_6_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1632 ) N ; + - storage_6_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1632 ) N ; + - storage_6_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1632 ) N ; + - storage_6_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1632 ) N ; + - storage_6_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1632 ) N ; + - storage_6_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1632 ) N ; + - storage_6_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1632 ) N ; + - storage_6_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1632 ) N ; + - storage_6_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1632 ) N ; + - storage_7_0_0.bit0.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46 1904 ) FS ; + - storage_7_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 782 1904 ) FS ; + - storage_7_0_0.bit1.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 1196 1904 ) FS ; + - storage_7_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1932 1904 ) FS ; + - storage_7_0_0.bit2.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 2346 1904 ) FS ; + - storage_7_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3082 1904 ) FS ; + - storage_7_0_0.bit3.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3496 1904 ) FS ; + - storage_7_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1904 ) FS ; + - storage_7_0_0.bit4.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 4646 1904 ) FS ; + - storage_7_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5382 1904 ) FS ; + - storage_7_0_0.bit5.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 5796 1904 ) FS ; + - storage_7_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6532 1904 ) FS ; + - storage_7_0_0.bit6.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 6946 1904 ) FS ; + - storage_7_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7682 1904 ) FS ; + - storage_7_0_0.bit7.bit sky130_fd_sc_hd__dfxtp_1 + PLACED ( 8096 1904 ) FS ; + - storage_7_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 8832 1904 ) FS ; + - storage_7_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 9246 1904 ) FS ; + - storage_7_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 9890 1904 ) FS ; + - storage_7_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 10120 1904 ) FS ; - tapcell.cell0_0 sky130_fd_sc_hd__tap_1 + PLACED ( 0 0 ) N ; - tapcell.cell0_1 sky130_fd_sc_hd__tap_1 + PLACED ( 0 272 ) FS ; - tapcell.cell0_2 sky130_fd_sc_hd__tap_1 + PLACED ( 0 544 ) N ; @@ -362,7 +362,7 @@ PINS 23 ; - D[0] + NET D[0] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 207 2423 ) N ; + + PLACED ( 115 2423 ) N ; - D[1] + NET D[1] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) @@ -463,15 +463,15 @@ PINS 23 ; + LAYER met1 ( 1 -2024 ) ( 15 -1976 ) + LAYER met1 ( -11025 -2024 ) ( -11011 -1976 ) + FIXED ( 11025 2000 ) N ; - - addr[0] + NET addr[0] + DIRECTION INPUT + USE SIGNAL + - addr_rw[0] + NET addr_rw[0] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met3 ( -40 -15 ) ( 40 15 ) + PLACED ( 11000 442 ) N ; - - addr[1] + NET addr[1] + DIRECTION INPUT + USE SIGNAL + - addr_rw[1] + NET addr_rw[1] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met3 ( -40 -15 ) ( 40 15 ) + PLACED ( 11000 714 ) N ; - - addr[2] + NET addr[2] + DIRECTION INPUT + USE SIGNAL + - addr_rw[2] + NET addr_rw[2] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met3 ( -40 -15 ) ( 40 15 ) + PLACED ( 11000 578 ) N ; @@ -497,26 +497,26 @@ SPECIALNETS 2 ; ( tapcell.cell2_1 VPWR ) ( tapcell.cell2_0 VPWR ) ( tapcell.cell1_8 VPWR ) ( tapcell.cell1_7 VPWR ) ( tapcell.cell1_6 VPWR ) ( tapcell.cell1_5 VPWR ) ( tapcell.cell1_4 VPWR ) ( tapcell.cell1_3 VPWR ) ( tapcell.cell1_2 VPWR ) ( tapcell.cell1_1 VPWR ) ( tapcell.cell1_0 VPWR ) ( tapcell.cell0_8 VPWR ) ( tapcell.cell0_7 VPWR ) ( tapcell.cell0_6 VPWR ) ( tapcell.cell0_5 VPWR ) ( tapcell.cell0_4 VPWR ) ( tapcell.cell0_3 VPWR ) ( tapcell.cell0_2 VPWR ) ( tapcell.cell0_1 VPWR ) ( tapcell.cell0_0 VPWR ) ( decoder.inv_0 VPWR ) ( decoder.inv_1 VPWR ) ( decoder.inv_2 VPWR ) ( buffer.in[7] VPWR ) - ( buffer.in[6] VPWR ) ( buffer.in[5] VPWR ) ( buffer.in[4] VPWR ) ( buffer.in[3] VPWR ) ( buffer.in[2] VPWR ) ( buffer.in[1] VPWR ) ( buffer.in[0] VPWR ) ( storage_7_0.select_inv_0 VPWR ) - ( storage_7_0.gcand VPWR ) ( storage_7_0.cg VPWR ) ( storage_7_0.bit7.obuf0 VPWR ) ( storage_7_0.bit7.bit VPWR ) ( storage_7_0.bit6.obuf0 VPWR ) ( storage_7_0.bit6.bit VPWR ) ( storage_7_0.bit5.obuf0 VPWR ) ( storage_7_0.bit5.bit VPWR ) - ( storage_7_0.bit4.obuf0 VPWR ) ( storage_7_0.bit4.bit VPWR ) ( storage_7_0.bit3.obuf0 VPWR ) ( storage_7_0.bit3.bit VPWR ) ( storage_7_0.bit2.obuf0 VPWR ) ( storage_7_0.bit2.bit VPWR ) ( storage_7_0.bit1.obuf0 VPWR ) ( storage_7_0.bit1.bit VPWR ) - ( storage_7_0.bit0.obuf0 VPWR ) ( storage_7_0.bit0.bit VPWR ) ( storage_6_0.select_inv_0 VPWR ) ( storage_6_0.gcand VPWR ) ( storage_6_0.cg VPWR ) ( storage_6_0.bit7.obuf0 VPWR ) ( storage_6_0.bit7.bit VPWR ) ( storage_6_0.bit6.obuf0 VPWR ) - ( storage_6_0.bit6.bit VPWR ) ( storage_6_0.bit5.obuf0 VPWR ) ( storage_6_0.bit5.bit VPWR ) ( storage_6_0.bit4.obuf0 VPWR ) ( storage_6_0.bit4.bit VPWR ) ( storage_6_0.bit3.obuf0 VPWR ) ( storage_6_0.bit3.bit VPWR ) ( storage_6_0.bit2.obuf0 VPWR ) - ( storage_6_0.bit2.bit VPWR ) ( storage_6_0.bit1.obuf0 VPWR ) ( storage_6_0.bit1.bit VPWR ) ( storage_6_0.bit0.obuf0 VPWR ) ( storage_6_0.bit0.bit VPWR ) ( storage_5_0.select_inv_0 VPWR ) ( storage_5_0.gcand VPWR ) ( storage_5_0.cg VPWR ) - ( storage_5_0.bit7.obuf0 VPWR ) ( storage_5_0.bit7.bit VPWR ) ( storage_5_0.bit6.obuf0 VPWR ) ( storage_5_0.bit6.bit VPWR ) ( storage_5_0.bit5.obuf0 VPWR ) ( storage_5_0.bit5.bit VPWR ) ( storage_5_0.bit4.obuf0 VPWR ) ( storage_5_0.bit4.bit VPWR ) - ( storage_5_0.bit3.obuf0 VPWR ) ( storage_5_0.bit3.bit VPWR ) ( storage_5_0.bit2.obuf0 VPWR ) ( storage_5_0.bit2.bit VPWR ) ( storage_5_0.bit1.obuf0 VPWR ) ( storage_5_0.bit1.bit VPWR ) ( storage_5_0.bit0.obuf0 VPWR ) ( storage_5_0.bit0.bit VPWR ) - ( storage_4_0.select_inv_0 VPWR ) ( storage_4_0.gcand VPWR ) ( storage_4_0.cg VPWR ) ( storage_4_0.bit7.obuf0 VPWR ) ( storage_4_0.bit7.bit VPWR ) ( storage_4_0.bit6.obuf0 VPWR ) ( storage_4_0.bit6.bit VPWR ) ( storage_4_0.bit5.obuf0 VPWR ) - ( storage_4_0.bit5.bit VPWR ) ( storage_4_0.bit4.obuf0 VPWR ) ( storage_4_0.bit4.bit VPWR ) ( storage_4_0.bit3.obuf0 VPWR ) ( storage_4_0.bit3.bit VPWR ) ( storage_4_0.bit2.obuf0 VPWR ) ( storage_4_0.bit2.bit VPWR ) ( storage_4_0.bit1.obuf0 VPWR ) - ( storage_4_0.bit1.bit VPWR ) ( storage_4_0.bit0.obuf0 VPWR ) ( storage_4_0.bit0.bit VPWR ) ( storage_3_0.select_inv_0 VPWR ) ( storage_3_0.gcand VPWR ) ( storage_3_0.cg VPWR ) ( storage_3_0.bit7.obuf0 VPWR ) ( storage_3_0.bit7.bit VPWR ) - ( storage_3_0.bit6.obuf0 VPWR ) ( storage_3_0.bit6.bit VPWR ) ( storage_3_0.bit5.obuf0 VPWR ) ( storage_3_0.bit5.bit VPWR ) ( storage_3_0.bit4.obuf0 VPWR ) ( storage_3_0.bit4.bit VPWR ) ( storage_3_0.bit3.obuf0 VPWR ) ( storage_3_0.bit3.bit VPWR ) - ( storage_3_0.bit2.obuf0 VPWR ) ( storage_3_0.bit2.bit VPWR ) ( storage_3_0.bit1.obuf0 VPWR ) ( storage_3_0.bit1.bit VPWR ) ( storage_3_0.bit0.obuf0 VPWR ) ( storage_3_0.bit0.bit VPWR ) ( storage_2_0.select_inv_0 VPWR ) ( storage_2_0.gcand VPWR ) - ( storage_2_0.cg VPWR ) ( storage_2_0.bit7.obuf0 VPWR ) ( storage_2_0.bit7.bit VPWR ) ( storage_2_0.bit6.obuf0 VPWR ) ( storage_2_0.bit6.bit VPWR ) ( storage_2_0.bit5.obuf0 VPWR ) ( storage_2_0.bit5.bit VPWR ) ( storage_2_0.bit4.obuf0 VPWR ) - ( storage_2_0.bit4.bit VPWR ) ( storage_2_0.bit3.obuf0 VPWR ) ( storage_2_0.bit3.bit VPWR ) ( storage_2_0.bit2.obuf0 VPWR ) ( storage_2_0.bit2.bit VPWR ) ( storage_2_0.bit1.obuf0 VPWR ) ( storage_2_0.bit1.bit VPWR ) ( storage_2_0.bit0.obuf0 VPWR ) - ( storage_2_0.bit0.bit VPWR ) ( storage_1_0.select_inv_0 VPWR ) ( storage_1_0.gcand VPWR ) ( storage_1_0.cg VPWR ) ( storage_1_0.bit7.obuf0 VPWR ) ( storage_1_0.bit7.bit VPWR ) ( storage_1_0.bit6.obuf0 VPWR ) ( storage_1_0.bit6.bit VPWR ) - ( storage_1_0.bit5.obuf0 VPWR ) ( storage_1_0.bit5.bit VPWR ) ( storage_1_0.bit4.obuf0 VPWR ) ( storage_1_0.bit4.bit VPWR ) ( storage_1_0.bit3.obuf0 VPWR ) ( storage_1_0.bit3.bit VPWR ) ( storage_1_0.bit2.obuf0 VPWR ) ( storage_1_0.bit2.bit VPWR ) - ( storage_1_0.bit1.obuf0 VPWR ) ( storage_1_0.bit1.bit VPWR ) ( storage_1_0.bit0.obuf0 VPWR ) ( storage_1_0.bit0.bit VPWR ) ( storage_0_0.select_inv_0 VPWR ) ( storage_0_0.gcand VPWR ) ( storage_0_0.cg VPWR ) ( storage_0_0.bit7.obuf0 VPWR ) - ( storage_0_0.bit7.bit VPWR ) ( storage_0_0.bit6.obuf0 VPWR ) ( storage_0_0.bit6.bit VPWR ) ( storage_0_0.bit5.obuf0 VPWR ) ( storage_0_0.bit5.bit VPWR ) ( storage_0_0.bit4.obuf0 VPWR ) ( storage_0_0.bit4.bit VPWR ) ( storage_0_0.bit3.obuf0 VPWR ) - ( storage_0_0.bit3.bit VPWR ) ( storage_0_0.bit2.obuf0 VPWR ) ( storage_0_0.bit2.bit VPWR ) ( storage_0_0.bit1.obuf0 VPWR ) ( storage_0_0.bit1.bit VPWR ) ( storage_0_0.bit0.obuf0 VPWR ) ( storage_0_0.bit0.bit VPWR ) ( decoder_7.buf_port0 VPWR ) + ( buffer.in[6] VPWR ) ( buffer.in[5] VPWR ) ( buffer.in[4] VPWR ) ( buffer.in[3] VPWR ) ( buffer.in[2] VPWR ) ( buffer.in[1] VPWR ) ( buffer.in[0] VPWR ) ( storage_7_0_0.select_inv_0 VPWR ) + ( storage_7_0_0.gcand VPWR ) ( storage_7_0_0.cg VPWR ) ( storage_7_0_0.bit7.obuf0 VPWR ) ( storage_7_0_0.bit7.bit VPWR ) ( storage_7_0_0.bit6.obuf0 VPWR ) ( storage_7_0_0.bit6.bit VPWR ) ( storage_7_0_0.bit5.obuf0 VPWR ) ( storage_7_0_0.bit5.bit VPWR ) + ( storage_7_0_0.bit4.obuf0 VPWR ) ( storage_7_0_0.bit4.bit VPWR ) ( storage_7_0_0.bit3.obuf0 VPWR ) ( storage_7_0_0.bit3.bit VPWR ) ( storage_7_0_0.bit2.obuf0 VPWR ) ( storage_7_0_0.bit2.bit VPWR ) ( storage_7_0_0.bit1.obuf0 VPWR ) ( storage_7_0_0.bit1.bit VPWR ) + ( storage_7_0_0.bit0.obuf0 VPWR ) ( storage_7_0_0.bit0.bit VPWR ) ( storage_6_0_0.select_inv_0 VPWR ) ( storage_6_0_0.gcand VPWR ) ( storage_6_0_0.cg VPWR ) ( storage_6_0_0.bit7.obuf0 VPWR ) ( storage_6_0_0.bit7.bit VPWR ) ( storage_6_0_0.bit6.obuf0 VPWR ) + ( storage_6_0_0.bit6.bit VPWR ) ( storage_6_0_0.bit5.obuf0 VPWR ) ( storage_6_0_0.bit5.bit VPWR ) ( storage_6_0_0.bit4.obuf0 VPWR ) ( storage_6_0_0.bit4.bit VPWR ) ( storage_6_0_0.bit3.obuf0 VPWR ) ( storage_6_0_0.bit3.bit VPWR ) ( storage_6_0_0.bit2.obuf0 VPWR ) + ( storage_6_0_0.bit2.bit VPWR ) ( storage_6_0_0.bit1.obuf0 VPWR ) ( storage_6_0_0.bit1.bit VPWR ) ( storage_6_0_0.bit0.obuf0 VPWR ) ( storage_6_0_0.bit0.bit VPWR ) ( storage_5_0_0.select_inv_0 VPWR ) ( storage_5_0_0.gcand VPWR ) ( storage_5_0_0.cg VPWR ) + ( storage_5_0_0.bit7.obuf0 VPWR ) ( storage_5_0_0.bit7.bit VPWR ) ( storage_5_0_0.bit6.obuf0 VPWR ) ( storage_5_0_0.bit6.bit VPWR ) ( storage_5_0_0.bit5.obuf0 VPWR ) ( storage_5_0_0.bit5.bit VPWR ) ( storage_5_0_0.bit4.obuf0 VPWR ) ( storage_5_0_0.bit4.bit VPWR ) + ( storage_5_0_0.bit3.obuf0 VPWR ) ( storage_5_0_0.bit3.bit VPWR ) ( storage_5_0_0.bit2.obuf0 VPWR ) ( storage_5_0_0.bit2.bit VPWR ) ( storage_5_0_0.bit1.obuf0 VPWR ) ( storage_5_0_0.bit1.bit VPWR ) ( storage_5_0_0.bit0.obuf0 VPWR ) ( storage_5_0_0.bit0.bit VPWR ) + ( storage_4_0_0.select_inv_0 VPWR ) ( storage_4_0_0.gcand VPWR ) ( storage_4_0_0.cg VPWR ) ( storage_4_0_0.bit7.obuf0 VPWR ) ( storage_4_0_0.bit7.bit VPWR ) ( storage_4_0_0.bit6.obuf0 VPWR ) ( storage_4_0_0.bit6.bit VPWR ) ( storage_4_0_0.bit5.obuf0 VPWR ) + ( storage_4_0_0.bit5.bit VPWR ) ( storage_4_0_0.bit4.obuf0 VPWR ) ( storage_4_0_0.bit4.bit VPWR ) ( storage_4_0_0.bit3.obuf0 VPWR ) ( storage_4_0_0.bit3.bit VPWR ) ( storage_4_0_0.bit2.obuf0 VPWR ) ( storage_4_0_0.bit2.bit VPWR ) ( storage_4_0_0.bit1.obuf0 VPWR ) + ( storage_4_0_0.bit1.bit VPWR ) ( storage_4_0_0.bit0.obuf0 VPWR ) ( storage_4_0_0.bit0.bit VPWR ) ( storage_3_0_0.select_inv_0 VPWR ) ( storage_3_0_0.gcand VPWR ) ( storage_3_0_0.cg VPWR ) ( storage_3_0_0.bit7.obuf0 VPWR ) ( storage_3_0_0.bit7.bit VPWR ) + ( storage_3_0_0.bit6.obuf0 VPWR ) ( storage_3_0_0.bit6.bit VPWR ) ( storage_3_0_0.bit5.obuf0 VPWR ) ( storage_3_0_0.bit5.bit VPWR ) ( storage_3_0_0.bit4.obuf0 VPWR ) ( storage_3_0_0.bit4.bit VPWR ) ( storage_3_0_0.bit3.obuf0 VPWR ) ( storage_3_0_0.bit3.bit VPWR ) + ( storage_3_0_0.bit2.obuf0 VPWR ) ( storage_3_0_0.bit2.bit VPWR ) ( storage_3_0_0.bit1.obuf0 VPWR ) ( storage_3_0_0.bit1.bit VPWR ) ( storage_3_0_0.bit0.obuf0 VPWR ) ( storage_3_0_0.bit0.bit VPWR ) ( storage_2_0_0.select_inv_0 VPWR ) ( storage_2_0_0.gcand VPWR ) + ( storage_2_0_0.cg VPWR ) ( storage_2_0_0.bit7.obuf0 VPWR ) ( storage_2_0_0.bit7.bit VPWR ) ( storage_2_0_0.bit6.obuf0 VPWR ) ( storage_2_0_0.bit6.bit VPWR ) ( storage_2_0_0.bit5.obuf0 VPWR ) ( storage_2_0_0.bit5.bit VPWR ) ( storage_2_0_0.bit4.obuf0 VPWR ) + ( storage_2_0_0.bit4.bit VPWR ) ( storage_2_0_0.bit3.obuf0 VPWR ) ( storage_2_0_0.bit3.bit VPWR ) ( storage_2_0_0.bit2.obuf0 VPWR ) ( storage_2_0_0.bit2.bit VPWR ) ( storage_2_0_0.bit1.obuf0 VPWR ) ( storage_2_0_0.bit1.bit VPWR ) ( storage_2_0_0.bit0.obuf0 VPWR ) + ( storage_2_0_0.bit0.bit VPWR ) ( storage_1_0_0.select_inv_0 VPWR ) ( storage_1_0_0.gcand VPWR ) ( storage_1_0_0.cg VPWR ) ( storage_1_0_0.bit7.obuf0 VPWR ) ( storage_1_0_0.bit7.bit VPWR ) ( storage_1_0_0.bit6.obuf0 VPWR ) ( storage_1_0_0.bit6.bit VPWR ) + ( storage_1_0_0.bit5.obuf0 VPWR ) ( storage_1_0_0.bit5.bit VPWR ) ( storage_1_0_0.bit4.obuf0 VPWR ) ( storage_1_0_0.bit4.bit VPWR ) ( storage_1_0_0.bit3.obuf0 VPWR ) ( storage_1_0_0.bit3.bit VPWR ) ( storage_1_0_0.bit2.obuf0 VPWR ) ( storage_1_0_0.bit2.bit VPWR ) + ( storage_1_0_0.bit1.obuf0 VPWR ) ( storage_1_0_0.bit1.bit VPWR ) ( storage_1_0_0.bit0.obuf0 VPWR ) ( storage_1_0_0.bit0.bit VPWR ) ( storage_0_0_0.select_inv_0 VPWR ) ( storage_0_0_0.gcand VPWR ) ( storage_0_0_0.cg VPWR ) ( storage_0_0_0.bit7.obuf0 VPWR ) + ( storage_0_0_0.bit7.bit VPWR ) ( storage_0_0_0.bit6.obuf0 VPWR ) ( storage_0_0_0.bit6.bit VPWR ) ( storage_0_0_0.bit5.obuf0 VPWR ) ( storage_0_0_0.bit5.bit VPWR ) ( storage_0_0_0.bit4.obuf0 VPWR ) ( storage_0_0_0.bit4.bit VPWR ) ( storage_0_0_0.bit3.obuf0 VPWR ) + ( storage_0_0_0.bit3.bit VPWR ) ( storage_0_0_0.bit2.obuf0 VPWR ) ( storage_0_0_0.bit2.bit VPWR ) ( storage_0_0_0.bit1.obuf0 VPWR ) ( storage_0_0_0.bit1.bit VPWR ) ( storage_0_0_0.bit0.obuf0 VPWR ) ( storage_0_0_0.bit0.bit VPWR ) ( decoder_7.buf_port0 VPWR ) ( decoder_7.and_layer1 VPWR ) ( decoder_7.and_layer0 VPWR ) ( decoder_6.buf_port0 VPWR ) ( decoder_6.and_layer1 VPWR ) ( decoder_6.and_layer0 VPWR ) ( decoder_5.buf_port0 VPWR ) ( decoder_5.and_layer1 VPWR ) ( decoder_5.and_layer0 VPWR ) ( decoder_4.buf_port0 VPWR ) ( decoder_4.and_layer1 VPWR ) ( decoder_4.and_layer0 VPWR ) ( decoder_3.buf_port0 VPWR ) ( decoder_3.and_layer1 VPWR ) ( decoder_3.and_layer0 VPWR ) ( decoder_2.buf_port0 VPWR ) ( decoder_2.and_layer1 VPWR ) ( decoder_2.and_layer0 VPWR ) ( decoder_1.buf_port0 VPWR ) ( decoder_1.and_layer1 VPWR ) ( decoder_1.and_layer0 VPWR ) ( decoder_0.buf_port0 VPWR ) ( decoder_0.and_layer1 VPWR ) ( decoder_0.and_layer0 VPWR ) + USE POWER @@ -559,26 +559,26 @@ SPECIALNETS 2 ; ( tapcell.cell2_1 VGND ) ( tapcell.cell2_0 VGND ) ( tapcell.cell1_8 VGND ) ( tapcell.cell1_7 VGND ) ( tapcell.cell1_6 VGND ) ( tapcell.cell1_5 VGND ) ( tapcell.cell1_4 VGND ) ( tapcell.cell1_3 VGND ) ( tapcell.cell1_2 VGND ) ( tapcell.cell1_1 VGND ) ( tapcell.cell1_0 VGND ) ( tapcell.cell0_8 VGND ) ( tapcell.cell0_7 VGND ) ( tapcell.cell0_6 VGND ) ( tapcell.cell0_5 VGND ) ( tapcell.cell0_4 VGND ) ( tapcell.cell0_3 VGND ) ( tapcell.cell0_2 VGND ) ( tapcell.cell0_1 VGND ) ( tapcell.cell0_0 VGND ) ( decoder.inv_0 VGND ) ( decoder.inv_1 VGND ) ( decoder.inv_2 VGND ) ( buffer.in[7] VGND ) - ( buffer.in[6] VGND ) ( buffer.in[5] VGND ) ( buffer.in[4] VGND ) ( buffer.in[3] VGND ) ( buffer.in[2] VGND ) ( buffer.in[1] VGND ) ( buffer.in[0] VGND ) ( storage_7_0.select_inv_0 VGND ) - ( storage_7_0.gcand VGND ) ( storage_7_0.cg VGND ) ( storage_7_0.bit7.obuf0 VGND ) ( storage_7_0.bit7.bit VGND ) ( storage_7_0.bit6.obuf0 VGND ) ( storage_7_0.bit6.bit VGND ) ( storage_7_0.bit5.obuf0 VGND ) ( storage_7_0.bit5.bit VGND ) - ( storage_7_0.bit4.obuf0 VGND ) ( storage_7_0.bit4.bit VGND ) ( storage_7_0.bit3.obuf0 VGND ) ( storage_7_0.bit3.bit VGND ) ( storage_7_0.bit2.obuf0 VGND ) ( storage_7_0.bit2.bit VGND ) ( storage_7_0.bit1.obuf0 VGND ) ( storage_7_0.bit1.bit VGND ) - ( storage_7_0.bit0.obuf0 VGND ) ( storage_7_0.bit0.bit VGND ) ( storage_6_0.select_inv_0 VGND ) ( storage_6_0.gcand VGND ) ( storage_6_0.cg VGND ) ( storage_6_0.bit7.obuf0 VGND ) ( storage_6_0.bit7.bit VGND ) ( storage_6_0.bit6.obuf0 VGND ) - ( storage_6_0.bit6.bit VGND ) ( storage_6_0.bit5.obuf0 VGND ) ( storage_6_0.bit5.bit VGND ) ( storage_6_0.bit4.obuf0 VGND ) ( storage_6_0.bit4.bit VGND ) ( storage_6_0.bit3.obuf0 VGND ) ( storage_6_0.bit3.bit VGND ) ( storage_6_0.bit2.obuf0 VGND ) - ( storage_6_0.bit2.bit VGND ) ( storage_6_0.bit1.obuf0 VGND ) ( storage_6_0.bit1.bit VGND ) ( storage_6_0.bit0.obuf0 VGND ) ( storage_6_0.bit0.bit VGND ) ( storage_5_0.select_inv_0 VGND ) ( storage_5_0.gcand VGND ) ( storage_5_0.cg VGND ) - ( storage_5_0.bit7.obuf0 VGND ) ( storage_5_0.bit7.bit VGND ) ( storage_5_0.bit6.obuf0 VGND ) ( storage_5_0.bit6.bit VGND ) ( storage_5_0.bit5.obuf0 VGND ) ( storage_5_0.bit5.bit VGND ) ( storage_5_0.bit4.obuf0 VGND ) ( storage_5_0.bit4.bit VGND ) - ( storage_5_0.bit3.obuf0 VGND ) ( storage_5_0.bit3.bit VGND ) ( storage_5_0.bit2.obuf0 VGND ) ( storage_5_0.bit2.bit VGND ) ( storage_5_0.bit1.obuf0 VGND ) ( storage_5_0.bit1.bit VGND ) ( storage_5_0.bit0.obuf0 VGND ) ( storage_5_0.bit0.bit VGND ) - ( storage_4_0.select_inv_0 VGND ) ( storage_4_0.gcand VGND ) ( storage_4_0.cg VGND ) ( storage_4_0.bit7.obuf0 VGND ) ( storage_4_0.bit7.bit VGND ) ( storage_4_0.bit6.obuf0 VGND ) ( storage_4_0.bit6.bit VGND ) ( storage_4_0.bit5.obuf0 VGND ) - ( storage_4_0.bit5.bit VGND ) ( storage_4_0.bit4.obuf0 VGND ) ( storage_4_0.bit4.bit VGND ) ( storage_4_0.bit3.obuf0 VGND ) ( storage_4_0.bit3.bit VGND ) ( storage_4_0.bit2.obuf0 VGND ) ( storage_4_0.bit2.bit VGND ) ( storage_4_0.bit1.obuf0 VGND ) - ( storage_4_0.bit1.bit VGND ) ( storage_4_0.bit0.obuf0 VGND ) ( storage_4_0.bit0.bit VGND ) ( storage_3_0.select_inv_0 VGND ) ( storage_3_0.gcand VGND ) ( storage_3_0.cg VGND ) ( storage_3_0.bit7.obuf0 VGND ) ( storage_3_0.bit7.bit VGND ) - ( storage_3_0.bit6.obuf0 VGND ) ( storage_3_0.bit6.bit VGND ) ( storage_3_0.bit5.obuf0 VGND ) ( storage_3_0.bit5.bit VGND ) ( storage_3_0.bit4.obuf0 VGND ) ( storage_3_0.bit4.bit VGND ) ( storage_3_0.bit3.obuf0 VGND ) ( storage_3_0.bit3.bit VGND ) - ( storage_3_0.bit2.obuf0 VGND ) ( storage_3_0.bit2.bit VGND ) ( storage_3_0.bit1.obuf0 VGND ) ( storage_3_0.bit1.bit VGND ) ( storage_3_0.bit0.obuf0 VGND ) ( storage_3_0.bit0.bit VGND ) ( storage_2_0.select_inv_0 VGND ) ( storage_2_0.gcand VGND ) - ( storage_2_0.cg VGND ) ( storage_2_0.bit7.obuf0 VGND ) ( storage_2_0.bit7.bit VGND ) ( storage_2_0.bit6.obuf0 VGND ) ( storage_2_0.bit6.bit VGND ) ( storage_2_0.bit5.obuf0 VGND ) ( storage_2_0.bit5.bit VGND ) ( storage_2_0.bit4.obuf0 VGND ) - ( storage_2_0.bit4.bit VGND ) ( storage_2_0.bit3.obuf0 VGND ) ( storage_2_0.bit3.bit VGND ) ( storage_2_0.bit2.obuf0 VGND ) ( storage_2_0.bit2.bit VGND ) ( storage_2_0.bit1.obuf0 VGND ) ( storage_2_0.bit1.bit VGND ) ( storage_2_0.bit0.obuf0 VGND ) - ( storage_2_0.bit0.bit VGND ) ( storage_1_0.select_inv_0 VGND ) ( storage_1_0.gcand VGND ) ( storage_1_0.cg VGND ) ( storage_1_0.bit7.obuf0 VGND ) ( storage_1_0.bit7.bit VGND ) ( storage_1_0.bit6.obuf0 VGND ) ( storage_1_0.bit6.bit VGND ) - ( storage_1_0.bit5.obuf0 VGND ) ( storage_1_0.bit5.bit VGND ) ( storage_1_0.bit4.obuf0 VGND ) ( storage_1_0.bit4.bit VGND ) ( storage_1_0.bit3.obuf0 VGND ) ( storage_1_0.bit3.bit VGND ) ( storage_1_0.bit2.obuf0 VGND ) ( storage_1_0.bit2.bit VGND ) - ( storage_1_0.bit1.obuf0 VGND ) ( storage_1_0.bit1.bit VGND ) ( storage_1_0.bit0.obuf0 VGND ) ( storage_1_0.bit0.bit VGND ) ( storage_0_0.select_inv_0 VGND ) ( storage_0_0.gcand VGND ) ( storage_0_0.cg VGND ) ( storage_0_0.bit7.obuf0 VGND ) - ( storage_0_0.bit7.bit VGND ) ( storage_0_0.bit6.obuf0 VGND ) ( storage_0_0.bit6.bit VGND ) ( storage_0_0.bit5.obuf0 VGND ) ( storage_0_0.bit5.bit VGND ) ( storage_0_0.bit4.obuf0 VGND ) ( storage_0_0.bit4.bit VGND ) ( storage_0_0.bit3.obuf0 VGND ) - ( storage_0_0.bit3.bit VGND ) ( storage_0_0.bit2.obuf0 VGND ) ( storage_0_0.bit2.bit VGND ) ( storage_0_0.bit1.obuf0 VGND ) ( storage_0_0.bit1.bit VGND ) ( storage_0_0.bit0.obuf0 VGND ) ( storage_0_0.bit0.bit VGND ) ( decoder_7.buf_port0 VGND ) + ( buffer.in[6] VGND ) ( buffer.in[5] VGND ) ( buffer.in[4] VGND ) ( buffer.in[3] VGND ) ( buffer.in[2] VGND ) ( buffer.in[1] VGND ) ( buffer.in[0] VGND ) ( storage_7_0_0.select_inv_0 VGND ) + ( storage_7_0_0.gcand VGND ) ( storage_7_0_0.cg VGND ) ( storage_7_0_0.bit7.obuf0 VGND ) ( storage_7_0_0.bit7.bit VGND ) ( storage_7_0_0.bit6.obuf0 VGND ) ( storage_7_0_0.bit6.bit VGND ) ( storage_7_0_0.bit5.obuf0 VGND ) ( storage_7_0_0.bit5.bit VGND ) + ( storage_7_0_0.bit4.obuf0 VGND ) ( storage_7_0_0.bit4.bit VGND ) ( storage_7_0_0.bit3.obuf0 VGND ) ( storage_7_0_0.bit3.bit VGND ) ( storage_7_0_0.bit2.obuf0 VGND ) ( storage_7_0_0.bit2.bit VGND ) ( storage_7_0_0.bit1.obuf0 VGND ) ( storage_7_0_0.bit1.bit VGND ) + ( storage_7_0_0.bit0.obuf0 VGND ) ( storage_7_0_0.bit0.bit VGND ) ( storage_6_0_0.select_inv_0 VGND ) ( storage_6_0_0.gcand VGND ) ( storage_6_0_0.cg VGND ) ( storage_6_0_0.bit7.obuf0 VGND ) ( storage_6_0_0.bit7.bit VGND ) ( storage_6_0_0.bit6.obuf0 VGND ) + ( storage_6_0_0.bit6.bit VGND ) ( storage_6_0_0.bit5.obuf0 VGND ) ( storage_6_0_0.bit5.bit VGND ) ( storage_6_0_0.bit4.obuf0 VGND ) ( storage_6_0_0.bit4.bit VGND ) ( storage_6_0_0.bit3.obuf0 VGND ) ( storage_6_0_0.bit3.bit VGND ) ( storage_6_0_0.bit2.obuf0 VGND ) + ( storage_6_0_0.bit2.bit VGND ) ( storage_6_0_0.bit1.obuf0 VGND ) ( storage_6_0_0.bit1.bit VGND ) ( storage_6_0_0.bit0.obuf0 VGND ) ( storage_6_0_0.bit0.bit VGND ) ( storage_5_0_0.select_inv_0 VGND ) ( storage_5_0_0.gcand VGND ) ( storage_5_0_0.cg VGND ) + ( storage_5_0_0.bit7.obuf0 VGND ) ( storage_5_0_0.bit7.bit VGND ) ( storage_5_0_0.bit6.obuf0 VGND ) ( storage_5_0_0.bit6.bit VGND ) ( storage_5_0_0.bit5.obuf0 VGND ) ( storage_5_0_0.bit5.bit VGND ) ( storage_5_0_0.bit4.obuf0 VGND ) ( storage_5_0_0.bit4.bit VGND ) + ( storage_5_0_0.bit3.obuf0 VGND ) ( storage_5_0_0.bit3.bit VGND ) ( storage_5_0_0.bit2.obuf0 VGND ) ( storage_5_0_0.bit2.bit VGND ) ( storage_5_0_0.bit1.obuf0 VGND ) ( storage_5_0_0.bit1.bit VGND ) ( storage_5_0_0.bit0.obuf0 VGND ) ( storage_5_0_0.bit0.bit VGND ) + ( storage_4_0_0.select_inv_0 VGND ) ( storage_4_0_0.gcand VGND ) ( storage_4_0_0.cg VGND ) ( storage_4_0_0.bit7.obuf0 VGND ) ( storage_4_0_0.bit7.bit VGND ) ( storage_4_0_0.bit6.obuf0 VGND ) ( storage_4_0_0.bit6.bit VGND ) ( storage_4_0_0.bit5.obuf0 VGND ) + ( storage_4_0_0.bit5.bit VGND ) ( storage_4_0_0.bit4.obuf0 VGND ) ( storage_4_0_0.bit4.bit VGND ) ( storage_4_0_0.bit3.obuf0 VGND ) ( storage_4_0_0.bit3.bit VGND ) ( storage_4_0_0.bit2.obuf0 VGND ) ( storage_4_0_0.bit2.bit VGND ) ( storage_4_0_0.bit1.obuf0 VGND ) + ( storage_4_0_0.bit1.bit VGND ) ( storage_4_0_0.bit0.obuf0 VGND ) ( storage_4_0_0.bit0.bit VGND ) ( storage_3_0_0.select_inv_0 VGND ) ( storage_3_0_0.gcand VGND ) ( storage_3_0_0.cg VGND ) ( storage_3_0_0.bit7.obuf0 VGND ) ( storage_3_0_0.bit7.bit VGND ) + ( storage_3_0_0.bit6.obuf0 VGND ) ( storage_3_0_0.bit6.bit VGND ) ( storage_3_0_0.bit5.obuf0 VGND ) ( storage_3_0_0.bit5.bit VGND ) ( storage_3_0_0.bit4.obuf0 VGND ) ( storage_3_0_0.bit4.bit VGND ) ( storage_3_0_0.bit3.obuf0 VGND ) ( storage_3_0_0.bit3.bit VGND ) + ( storage_3_0_0.bit2.obuf0 VGND ) ( storage_3_0_0.bit2.bit VGND ) ( storage_3_0_0.bit1.obuf0 VGND ) ( storage_3_0_0.bit1.bit VGND ) ( storage_3_0_0.bit0.obuf0 VGND ) ( storage_3_0_0.bit0.bit VGND ) ( storage_2_0_0.select_inv_0 VGND ) ( storage_2_0_0.gcand VGND ) + ( storage_2_0_0.cg VGND ) ( storage_2_0_0.bit7.obuf0 VGND ) ( storage_2_0_0.bit7.bit VGND ) ( storage_2_0_0.bit6.obuf0 VGND ) ( storage_2_0_0.bit6.bit VGND ) ( storage_2_0_0.bit5.obuf0 VGND ) ( storage_2_0_0.bit5.bit VGND ) ( storage_2_0_0.bit4.obuf0 VGND ) + ( storage_2_0_0.bit4.bit VGND ) ( storage_2_0_0.bit3.obuf0 VGND ) ( storage_2_0_0.bit3.bit VGND ) ( storage_2_0_0.bit2.obuf0 VGND ) ( storage_2_0_0.bit2.bit VGND ) ( storage_2_0_0.bit1.obuf0 VGND ) ( storage_2_0_0.bit1.bit VGND ) ( storage_2_0_0.bit0.obuf0 VGND ) + ( storage_2_0_0.bit0.bit VGND ) ( storage_1_0_0.select_inv_0 VGND ) ( storage_1_0_0.gcand VGND ) ( storage_1_0_0.cg VGND ) ( storage_1_0_0.bit7.obuf0 VGND ) ( storage_1_0_0.bit7.bit VGND ) ( storage_1_0_0.bit6.obuf0 VGND ) ( storage_1_0_0.bit6.bit VGND ) + ( storage_1_0_0.bit5.obuf0 VGND ) ( storage_1_0_0.bit5.bit VGND ) ( storage_1_0_0.bit4.obuf0 VGND ) ( storage_1_0_0.bit4.bit VGND ) ( storage_1_0_0.bit3.obuf0 VGND ) ( storage_1_0_0.bit3.bit VGND ) ( storage_1_0_0.bit2.obuf0 VGND ) ( storage_1_0_0.bit2.bit VGND ) + ( storage_1_0_0.bit1.obuf0 VGND ) ( storage_1_0_0.bit1.bit VGND ) ( storage_1_0_0.bit0.obuf0 VGND ) ( storage_1_0_0.bit0.bit VGND ) ( storage_0_0_0.select_inv_0 VGND ) ( storage_0_0_0.gcand VGND ) ( storage_0_0_0.cg VGND ) ( storage_0_0_0.bit7.obuf0 VGND ) + ( storage_0_0_0.bit7.bit VGND ) ( storage_0_0_0.bit6.obuf0 VGND ) ( storage_0_0_0.bit6.bit VGND ) ( storage_0_0_0.bit5.obuf0 VGND ) ( storage_0_0_0.bit5.bit VGND ) ( storage_0_0_0.bit4.obuf0 VGND ) ( storage_0_0_0.bit4.bit VGND ) ( storage_0_0_0.bit3.obuf0 VGND ) + ( storage_0_0_0.bit3.bit VGND ) ( storage_0_0_0.bit2.obuf0 VGND ) ( storage_0_0_0.bit2.bit VGND ) ( storage_0_0_0.bit1.obuf0 VGND ) ( storage_0_0_0.bit1.bit VGND ) ( storage_0_0_0.bit0.obuf0 VGND ) ( storage_0_0_0.bit0.bit VGND ) ( decoder_7.buf_port0 VGND ) ( decoder_7.and_layer1 VGND ) ( decoder_7.and_layer0 VGND ) ( decoder_6.buf_port0 VGND ) ( decoder_6.and_layer1 VGND ) ( decoder_6.and_layer0 VGND ) ( decoder_5.buf_port0 VGND ) ( decoder_5.and_layer1 VGND ) ( decoder_5.and_layer0 VGND ) ( decoder_4.buf_port0 VGND ) ( decoder_4.and_layer1 VGND ) ( decoder_4.and_layer0 VGND ) ( decoder_3.buf_port0 VGND ) ( decoder_3.and_layer1 VGND ) ( decoder_3.and_layer0 VGND ) ( decoder_2.buf_port0 VGND ) ( decoder_2.and_layer1 VGND ) ( decoder_2.and_layer0 VGND ) ( decoder_1.buf_port0 VGND ) ( decoder_1.and_layer1 VGND ) ( decoder_1.and_layer0 VGND ) ( decoder_0.buf_port0 VGND ) ( decoder_0.and_layer1 VGND ) ( decoder_0.and_layer0 VGND ) + USE GROUND @@ -605,9 +605,9 @@ SPECIALNETS 2 ; END SPECIALNETS NETS 152 ; - D[0] ( PIN D[0] ) ( buffer.in[0] A ) + USE SIGNAL - + ROUTED met2 ( 207 2295 ) ( * 2414 0 ) - NEW met1 ( 69 2295 ) ( 207 * ) - NEW met1 ( 207 2295 ) M1M2_PR + + ROUTED met2 ( 115 2295 ) ( * 2414 0 ) + NEW met1 ( 69 2295 ) ( 115 * ) + NEW met1 ( 115 2295 ) M1M2_PR NEW li1 ( 69 2295 ) L1M1_PR_MR ; - D[1] ( PIN D[1] ) ( buffer.in[1] A ) + USE SIGNAL + ROUTED met2 ( 1219 2295 ) ( * 2414 0 ) @@ -640,8 +640,8 @@ NETS 152 ; + ROUTED met2 ( 8119 2295 ) ( * 2414 0 ) NEW li1 ( 8119 2295 ) L1M1_PR_MR NEW met1 ( 8119 2295 ) M1M2_PR ; - - D_nets[0].net ( buffer.in[0] X ) ( storage_7_0.bit0.bit D ) ( storage_6_0.bit0.bit D ) ( storage_5_0.bit0.bit D ) ( storage_4_0.bit0.bit D ) ( storage_3_0.bit0.bit D ) ( storage_2_0.bit0.bit D ) - ( storage_1_0.bit0.bit D ) ( storage_0_0.bit0.bit D ) + USE SIGNAL + - D_nets.b0 ( buffer.in[0] X ) ( storage_7_0_0.bit0.bit D ) ( storage_6_0_0.bit0.bit D ) ( storage_5_0_0.bit0.bit D ) ( storage_4_0_0.bit0.bit D ) ( storage_3_0_0.bit0.bit D ) ( storage_2_0_0.bit0.bit D ) + ( storage_1_0_0.bit0.bit D ) ( storage_0_0_0.bit0.bit D ) + USE SIGNAL + ROUTED met1 ( 202 2057 ) ( 207 * ) NEW met2 ( 207 2057 ) ( * 2227 ) NEW met1 ( 161 2227 ) ( 207 * ) @@ -685,8 +685,8 @@ NETS 152 ; NEW met1 ( 202 663 ) RECT ( -31 -7 0 7 ) NEW met1 ( 202 459 ) RECT ( -31 -7 0 7 ) NEW met1 ( 202 119 ) RECT ( -31 -7 0 7 ) ; - - D_nets[1].net ( buffer.in[1] X ) ( storage_7_0.bit1.bit D ) ( storage_6_0.bit1.bit D ) ( storage_5_0.bit1.bit D ) ( storage_4_0.bit1.bit D ) ( storage_3_0.bit1.bit D ) ( storage_2_0.bit1.bit D ) - ( storage_1_0.bit1.bit D ) ( storage_0_0.bit1.bit D ) + USE SIGNAL + - D_nets.b1 ( buffer.in[1] X ) ( storage_7_0_0.bit1.bit D ) ( storage_6_0_0.bit1.bit D ) ( storage_5_0_0.bit1.bit D ) ( storage_4_0_0.bit1.bit D ) ( storage_3_0_0.bit1.bit D ) ( storage_2_0_0.bit1.bit D ) + ( storage_1_0_0.bit1.bit D ) ( storage_0_0_0.bit1.bit D ) + USE SIGNAL + ROUTED met1 ( 1352 2057 ) ( 1357 * ) NEW met2 ( 1357 2057 ) ( * 2227 ) NEW met1 ( 1311 2227 ) ( 1357 * ) @@ -730,8 +730,8 @@ NETS 152 ; NEW met1 ( 1352 663 ) RECT ( -31 -7 0 7 ) NEW met1 ( 1352 459 ) RECT ( -31 -7 0 7 ) NEW met1 ( 1352 119 ) RECT ( -31 -7 0 7 ) ; - - D_nets[2].net ( buffer.in[2] X ) ( storage_7_0.bit2.bit D ) ( storage_6_0.bit2.bit D ) ( storage_5_0.bit2.bit D ) ( storage_4_0.bit2.bit D ) ( storage_3_0.bit2.bit D ) ( storage_2_0.bit2.bit D ) - ( storage_1_0.bit2.bit D ) ( storage_0_0.bit2.bit D ) + USE SIGNAL + - D_nets.b2 ( buffer.in[2] X ) ( storage_7_0_0.bit2.bit D ) ( storage_6_0_0.bit2.bit D ) ( storage_5_0_0.bit2.bit D ) ( storage_4_0_0.bit2.bit D ) ( storage_3_0_0.bit2.bit D ) ( storage_2_0_0.bit2.bit D ) + ( storage_1_0_0.bit2.bit D ) ( storage_0_0_0.bit2.bit D ) + USE SIGNAL + ROUTED met1 ( 2502 1207 ) ( 2507 * ) NEW met1 ( 2502 1003 ) ( 2507 * ) NEW met2 ( 2507 1003 ) ( * 1207 ) @@ -775,8 +775,8 @@ NETS 152 ; NEW met1 ( 2502 2057 ) RECT ( -31 -7 0 7 ) NEW met1 ( 2502 1751 ) RECT ( -31 -7 0 7 ) NEW met1 ( 2502 1547 ) RECT ( -31 -7 0 7 ) ; - - D_nets[3].net ( buffer.in[3] X ) ( storage_7_0.bit3.bit D ) ( storage_6_0.bit3.bit D ) ( storage_5_0.bit3.bit D ) ( storage_4_0.bit3.bit D ) ( storage_3_0.bit3.bit D ) ( storage_2_0.bit3.bit D ) - ( storage_1_0.bit3.bit D ) ( storage_0_0.bit3.bit D ) + USE SIGNAL + - D_nets.b3 ( buffer.in[3] X ) ( storage_7_0_0.bit3.bit D ) ( storage_6_0_0.bit3.bit D ) ( storage_5_0_0.bit3.bit D ) ( storage_4_0_0.bit3.bit D ) ( storage_3_0_0.bit3.bit D ) ( storage_2_0_0.bit3.bit D ) + ( storage_1_0_0.bit3.bit D ) ( storage_0_0_0.bit3.bit D ) + USE SIGNAL + ROUTED met1 ( 3652 1207 ) ( 3657 * ) NEW met1 ( 3652 1003 ) ( 3657 * ) NEW met2 ( 3657 1003 ) ( * 1207 ) @@ -820,8 +820,8 @@ NETS 152 ; NEW met1 ( 3652 2057 ) RECT ( -31 -7 0 7 ) NEW met1 ( 3652 1751 ) RECT ( -31 -7 0 7 ) NEW met1 ( 3652 1547 ) RECT ( -31 -7 0 7 ) ; - - D_nets[4].net ( buffer.in[4] X ) ( storage_7_0.bit4.bit D ) ( storage_6_0.bit4.bit D ) ( storage_5_0.bit4.bit D ) ( storage_4_0.bit4.bit D ) ( storage_3_0.bit4.bit D ) ( storage_2_0.bit4.bit D ) - ( storage_1_0.bit4.bit D ) ( storage_0_0.bit4.bit D ) + USE SIGNAL + - D_nets.b4 ( buffer.in[4] X ) ( storage_7_0_0.bit4.bit D ) ( storage_6_0_0.bit4.bit D ) ( storage_5_0_0.bit4.bit D ) ( storage_4_0_0.bit4.bit D ) ( storage_3_0_0.bit4.bit D ) ( storage_2_0_0.bit4.bit D ) + ( storage_1_0_0.bit4.bit D ) ( storage_0_0_0.bit4.bit D ) + USE SIGNAL + ROUTED met1 ( 4802 1207 ) ( 4807 * ) NEW met1 ( 4802 1003 ) ( 4807 * ) NEW met2 ( 4807 1003 ) ( * 1207 ) @@ -865,8 +865,8 @@ NETS 152 ; NEW met1 ( 4802 2057 ) RECT ( -31 -7 0 7 ) NEW met1 ( 4802 1751 ) RECT ( -31 -7 0 7 ) NEW met1 ( 4802 1547 ) RECT ( -31 -7 0 7 ) ; - - D_nets[5].net ( buffer.in[5] X ) ( storage_7_0.bit5.bit D ) ( storage_6_0.bit5.bit D ) ( storage_5_0.bit5.bit D ) ( storage_4_0.bit5.bit D ) ( storage_3_0.bit5.bit D ) ( storage_2_0.bit5.bit D ) - ( storage_1_0.bit5.bit D ) ( storage_0_0.bit5.bit D ) + USE SIGNAL + - D_nets.b5 ( buffer.in[5] X ) ( storage_7_0_0.bit5.bit D ) ( storage_6_0_0.bit5.bit D ) ( storage_5_0_0.bit5.bit D ) ( storage_4_0_0.bit5.bit D ) ( storage_3_0_0.bit5.bit D ) ( storage_2_0_0.bit5.bit D ) + ( storage_1_0_0.bit5.bit D ) ( storage_0_0_0.bit5.bit D ) + USE SIGNAL + ROUTED met1 ( 5865 1207 ) ( 5947 * ) NEW met1 ( 5865 1003 ) ( 5941 * ) NEW met2 ( 5865 1003 ) ( * 1207 ) @@ -902,8 +902,8 @@ NETS 152 ; NEW met1 ( 5865 2057 ) M1M2_PR NEW li1 ( 5911 2227 ) L1M1_PR_MR NEW met1 ( 5865 2227 ) M1M2_PR ; - - D_nets[6].net ( buffer.in[6] X ) ( storage_7_0.bit6.bit D ) ( storage_6_0.bit6.bit D ) ( storage_5_0.bit6.bit D ) ( storage_4_0.bit6.bit D ) ( storage_3_0.bit6.bit D ) ( storage_2_0.bit6.bit D ) - ( storage_1_0.bit6.bit D ) ( storage_0_0.bit6.bit D ) + USE SIGNAL + - D_nets.b6 ( buffer.in[6] X ) ( storage_7_0_0.bit6.bit D ) ( storage_6_0_0.bit6.bit D ) ( storage_5_0_0.bit6.bit D ) ( storage_4_0_0.bit6.bit D ) ( storage_3_0_0.bit6.bit D ) ( storage_2_0_0.bit6.bit D ) + ( storage_1_0_0.bit6.bit D ) ( storage_0_0_0.bit6.bit D ) + USE SIGNAL + ROUTED met1 ( 7102 1207 ) ( 7107 * ) NEW met1 ( 7102 1003 ) ( 7107 * ) NEW met2 ( 7107 1003 ) ( * 1207 ) @@ -947,8 +947,8 @@ NETS 152 ; NEW met1 ( 7102 2057 ) RECT ( -31 -7 0 7 ) NEW met1 ( 7102 1751 ) RECT ( -31 -7 0 7 ) NEW met1 ( 7102 1547 ) RECT ( -31 -7 0 7 ) ; - - D_nets[7].net ( buffer.in[7] X ) ( storage_7_0.bit7.bit D ) ( storage_6_0.bit7.bit D ) ( storage_5_0.bit7.bit D ) ( storage_4_0.bit7.bit D ) ( storage_3_0.bit7.bit D ) ( storage_2_0.bit7.bit D ) - ( storage_1_0.bit7.bit D ) ( storage_0_0.bit7.bit D ) + USE SIGNAL + - D_nets.b7 ( buffer.in[7] X ) ( storage_7_0_0.bit7.bit D ) ( storage_6_0_0.bit7.bit D ) ( storage_5_0_0.bit7.bit D ) ( storage_4_0_0.bit7.bit D ) ( storage_3_0_0.bit7.bit D ) ( storage_2_0_0.bit7.bit D ) + ( storage_1_0_0.bit7.bit D ) ( storage_0_0_0.bit7.bit D ) + USE SIGNAL + ROUTED met1 ( 8252 2057 ) ( 8257 * ) NEW met2 ( 8257 2057 ) ( * 2227 ) NEW met1 ( 8211 2227 ) ( 8257 * ) @@ -992,8 +992,8 @@ NETS 152 ; NEW met1 ( 8252 663 ) RECT ( -31 -7 0 7 ) NEW met1 ( 8252 459 ) RECT ( -31 -7 0 7 ) NEW met1 ( 8252 119 ) RECT ( -31 -7 0 7 ) ; - - Q[0] ( PIN Q[0] ) ( storage_7_0.bit0.obuf0 Z ) ( storage_6_0.bit0.obuf0 Z ) ( storage_5_0.bit0.obuf0 Z ) ( storage_4_0.bit0.obuf0 Z ) ( storage_3_0.bit0.obuf0 Z ) ( storage_2_0.bit0.obuf0 Z ) - ( storage_1_0.bit0.obuf0 Z ) ( storage_0_0.bit0.obuf0 Z ) + USE SIGNAL + - Q[0] ( PIN Q[0] ) ( storage_7_0_0.bit0.obuf0 Z ) ( storage_6_0_0.bit0.obuf0 Z ) ( storage_5_0_0.bit0.obuf0 Z ) ( storage_4_0_0.bit0.obuf0 Z ) ( storage_3_0_0.bit0.obuf0 Z ) ( storage_2_0_0.bit0.obuf0 Z ) + ( storage_1_0_0.bit0.obuf0 Z ) ( storage_0_0_0.bit0.obuf0 Z ) + USE SIGNAL + ROUTED met2 ( 1127 2125 ) ( * 2414 0 ) NEW met2 ( 1127 1853 ) ( * 2125 ) NEW met2 ( 1127 1581 ) ( * 1853 ) @@ -1018,8 +1018,8 @@ NETS 152 ; NEW met1 ( 1127 493 ) M1M2_PR NEW li1 ( 1127 221 ) L1M1_PR_MR NEW met1 ( 1127 221 ) M1M2_PR ; - - Q[1] ( PIN Q[1] ) ( storage_7_0.bit1.obuf0 Z ) ( storage_6_0.bit1.obuf0 Z ) ( storage_5_0.bit1.obuf0 Z ) ( storage_4_0.bit1.obuf0 Z ) ( storage_3_0.bit1.obuf0 Z ) ( storage_2_0.bit1.obuf0 Z ) - ( storage_1_0.bit1.obuf0 Z ) ( storage_0_0.bit1.obuf0 Z ) + USE SIGNAL + - Q[1] ( PIN Q[1] ) ( storage_7_0_0.bit1.obuf0 Z ) ( storage_6_0_0.bit1.obuf0 Z ) ( storage_5_0_0.bit1.obuf0 Z ) ( storage_4_0_0.bit1.obuf0 Z ) ( storage_3_0_0.bit1.obuf0 Z ) ( storage_2_0_0.bit1.obuf0 Z ) + ( storage_1_0_0.bit1.obuf0 Z ) ( storage_0_0_0.bit1.obuf0 Z ) + USE SIGNAL + ROUTED met1 ( 2231 1037 ) ( 2277 * ) NEW met2 ( 2231 1037 ) ( * 1309 ) NEW met2 ( 2231 765 ) ( * 1037 ) @@ -1048,8 +1048,8 @@ NETS 152 ; NEW met1 ( 2231 1853 ) M1M2_PR NEW li1 ( 2277 1581 ) L1M1_PR_MR NEW met1 ( 2231 1581 ) M1M2_PR ; - - Q[2] ( PIN Q[2] ) ( storage_7_0.bit2.obuf0 Z ) ( storage_6_0.bit2.obuf0 Z ) ( storage_5_0.bit2.obuf0 Z ) ( storage_4_0.bit2.obuf0 Z ) ( storage_3_0.bit2.obuf0 Z ) ( storage_2_0.bit2.obuf0 Z ) - ( storage_1_0.bit2.obuf0 Z ) ( storage_0_0.bit2.obuf0 Z ) + USE SIGNAL + - Q[2] ( PIN Q[2] ) ( storage_7_0_0.bit2.obuf0 Z ) ( storage_6_0_0.bit2.obuf0 Z ) ( storage_5_0_0.bit2.obuf0 Z ) ( storage_4_0_0.bit2.obuf0 Z ) ( storage_3_0_0.bit2.obuf0 Z ) ( storage_2_0_0.bit2.obuf0 Z ) + ( storage_1_0_0.bit2.obuf0 Z ) ( storage_0_0_0.bit2.obuf0 Z ) + USE SIGNAL + ROUTED met2 ( 3427 1037 ) ( * 1309 ) NEW met2 ( 3427 765 ) ( * 1037 ) NEW met2 ( 3427 493 ) ( * 765 ) @@ -1074,8 +1074,8 @@ NETS 152 ; NEW met1 ( 3427 1853 ) M1M2_PR NEW li1 ( 3427 1581 ) L1M1_PR_MR NEW met1 ( 3427 1581 ) M1M2_PR ; - - Q[3] ( PIN Q[3] ) ( storage_7_0.bit3.obuf0 Z ) ( storage_6_0.bit3.obuf0 Z ) ( storage_5_0.bit3.obuf0 Z ) ( storage_4_0.bit3.obuf0 Z ) ( storage_3_0.bit3.obuf0 Z ) ( storage_2_0.bit3.obuf0 Z ) - ( storage_1_0.bit3.obuf0 Z ) ( storage_0_0.bit3.obuf0 Z ) + USE SIGNAL + - Q[3] ( PIN Q[3] ) ( storage_7_0_0.bit3.obuf0 Z ) ( storage_6_0_0.bit3.obuf0 Z ) ( storage_5_0_0.bit3.obuf0 Z ) ( storage_4_0_0.bit3.obuf0 Z ) ( storage_3_0_0.bit3.obuf0 Z ) ( storage_2_0_0.bit3.obuf0 Z ) + ( storage_1_0_0.bit3.obuf0 Z ) ( storage_0_0_0.bit3.obuf0 Z ) + USE SIGNAL + ROUTED met1 ( 4531 1037 ) ( 4577 * ) NEW met2 ( 4531 1037 ) ( * 1309 ) NEW met2 ( 4531 765 ) ( * 1037 ) @@ -1104,8 +1104,8 @@ NETS 152 ; NEW met1 ( 4531 1853 ) M1M2_PR NEW li1 ( 4577 1581 ) L1M1_PR_MR NEW met1 ( 4531 1581 ) M1M2_PR ; - - Q[4] ( PIN Q[4] ) ( storage_7_0.bit4.obuf0 Z ) ( storage_6_0.bit4.obuf0 Z ) ( storage_5_0.bit4.obuf0 Z ) ( storage_4_0.bit4.obuf0 Z ) ( storage_3_0.bit4.obuf0 Z ) ( storage_2_0.bit4.obuf0 Z ) - ( storage_1_0.bit4.obuf0 Z ) ( storage_0_0.bit4.obuf0 Z ) + USE SIGNAL + - Q[4] ( PIN Q[4] ) ( storage_7_0_0.bit4.obuf0 Z ) ( storage_6_0_0.bit4.obuf0 Z ) ( storage_5_0_0.bit4.obuf0 Z ) ( storage_4_0_0.bit4.obuf0 Z ) ( storage_3_0_0.bit4.obuf0 Z ) ( storage_2_0_0.bit4.obuf0 Z ) + ( storage_1_0_0.bit4.obuf0 Z ) ( storage_0_0_0.bit4.obuf0 Z ) + USE SIGNAL + ROUTED met2 ( 5727 1037 ) ( * 1309 ) NEW met2 ( 5727 765 ) ( * 1037 ) NEW met2 ( 5727 493 ) ( * 765 ) @@ -1130,8 +1130,8 @@ NETS 152 ; NEW met1 ( 5727 1853 ) M1M2_PR NEW li1 ( 5727 1581 ) L1M1_PR_MR NEW met1 ( 5727 1581 ) M1M2_PR ; - - Q[5] ( PIN Q[5] ) ( storage_7_0.bit5.obuf0 Z ) ( storage_6_0.bit5.obuf0 Z ) ( storage_5_0.bit5.obuf0 Z ) ( storage_4_0.bit5.obuf0 Z ) ( storage_3_0.bit5.obuf0 Z ) ( storage_2_0.bit5.obuf0 Z ) - ( storage_1_0.bit5.obuf0 Z ) ( storage_0_0.bit5.obuf0 Z ) + USE SIGNAL + - Q[5] ( PIN Q[5] ) ( storage_7_0_0.bit5.obuf0 Z ) ( storage_6_0_0.bit5.obuf0 Z ) ( storage_5_0_0.bit5.obuf0 Z ) ( storage_4_0_0.bit5.obuf0 Z ) ( storage_3_0_0.bit5.obuf0 Z ) ( storage_2_0_0.bit5.obuf0 Z ) + ( storage_1_0_0.bit5.obuf0 Z ) ( storage_0_0_0.bit5.obuf0 Z ) + USE SIGNAL + ROUTED met1 ( 6831 1037 ) ( 6877 * ) NEW met2 ( 6831 1037 ) ( * 1309 ) NEW met2 ( 6831 765 ) ( * 1037 ) @@ -1160,8 +1160,8 @@ NETS 152 ; NEW met1 ( 6831 1853 ) M1M2_PR NEW li1 ( 6877 1581 ) L1M1_PR_MR NEW met1 ( 6831 1581 ) M1M2_PR ; - - Q[6] ( PIN Q[6] ) ( storage_7_0.bit6.obuf0 Z ) ( storage_6_0.bit6.obuf0 Z ) ( storage_5_0.bit6.obuf0 Z ) ( storage_4_0.bit6.obuf0 Z ) ( storage_3_0.bit6.obuf0 Z ) ( storage_2_0.bit6.obuf0 Z ) - ( storage_1_0.bit6.obuf0 Z ) ( storage_0_0.bit6.obuf0 Z ) + USE SIGNAL + - Q[6] ( PIN Q[6] ) ( storage_7_0_0.bit6.obuf0 Z ) ( storage_6_0_0.bit6.obuf0 Z ) ( storage_5_0_0.bit6.obuf0 Z ) ( storage_4_0_0.bit6.obuf0 Z ) ( storage_3_0_0.bit6.obuf0 Z ) ( storage_2_0_0.bit6.obuf0 Z ) + ( storage_1_0_0.bit6.obuf0 Z ) ( storage_0_0_0.bit6.obuf0 Z ) + USE SIGNAL + ROUTED met1 ( 8027 2125 ) ( 8073 * ) NEW met2 ( 8073 2125 ) ( * 2414 ) NEW met2 ( 8027 2414 0 ) ( 8073 * ) @@ -1195,8 +1195,8 @@ NETS 152 ; NEW met1 ( 8073 493 ) M1M2_PR NEW li1 ( 8027 221 ) L1M1_PR_MR NEW met1 ( 8073 221 ) M1M2_PR ; - - Q[7] ( PIN Q[7] ) ( storage_7_0.bit7.obuf0 Z ) ( storage_6_0.bit7.obuf0 Z ) ( storage_5_0.bit7.obuf0 Z ) ( storage_4_0.bit7.obuf0 Z ) ( storage_3_0.bit7.obuf0 Z ) ( storage_2_0.bit7.obuf0 Z ) - ( storage_1_0.bit7.obuf0 Z ) ( storage_0_0.bit7.obuf0 Z ) + USE SIGNAL + - Q[7] ( PIN Q[7] ) ( storage_7_0_0.bit7.obuf0 Z ) ( storage_6_0_0.bit7.obuf0 Z ) ( storage_5_0_0.bit7.obuf0 Z ) ( storage_4_0_0.bit7.obuf0 Z ) ( storage_3_0_0.bit7.obuf0 Z ) ( storage_2_0_0.bit7.obuf0 Z ) + ( storage_1_0_0.bit7.obuf0 Z ) ( storage_0_0_0.bit7.obuf0 Z ) + USE SIGNAL + ROUTED met1 ( 9131 2125 ) ( 9177 * ) NEW met2 ( 9131 2125 ) ( * 2414 0 ) NEW met2 ( 9131 1853 ) ( * 2125 ) @@ -1225,7 +1225,7 @@ NETS 152 ; NEW met1 ( 9131 493 ) M1M2_PR NEW li1 ( 9131 221 ) L1M1_PR_MR NEW met1 ( 9131 221 ) M1M2_PR ; - - addr[0] ( PIN addr[0] ) ( decoder.inv_0 A ) ( decoder_7.and_layer0 A ) ( decoder_5.and_layer0 A ) ( decoder_3.and_layer0 A ) ( decoder_1.and_layer0 A ) + USE SIGNAL + - addr_rw[0] ( PIN addr_rw[0] ) ( decoder.inv_0 A ) ( decoder_7.and_layer0 A ) ( decoder_5.and_layer0 A ) ( decoder_3.and_layer0 A ) ( decoder_1.and_layer0 A ) + USE SIGNAL + ROUTED met1 ( 10327 391 ) ( 10373 * ) NEW met2 ( 10373 391 ) ( * 442 ) NEW met3 ( 10373 442 ) ( 10994 * 0 ) @@ -1250,7 +1250,7 @@ NETS 152 ; NEW met1 ( 10925 1411 ) M1M2_PR NEW li1 ( 10327 1989 ) L1M1_PR_MR NEW met1 ( 10373 1989 ) M1M2_PR ; - - addr[1] ( PIN addr[1] ) ( decoder.inv_1 A ) ( decoder_7.and_layer1 A ) ( decoder_6.and_layer1 A ) ( decoder_3.and_layer1 A ) ( decoder_2.and_layer1 A ) + USE SIGNAL + - addr_rw[1] ( PIN addr_rw[1] ) ( decoder.inv_1 A ) ( decoder_7.and_layer1 A ) ( decoder_6.and_layer1 A ) ( decoder_3.and_layer1 A ) ( decoder_2.and_layer1 A ) + USE SIGNAL + ROUTED met2 ( 10925 714 ) ( * 969 ) NEW met3 ( 10925 714 ) ( 10994 * 0 ) NEW met1 ( 10557 697 ) ( 10925 * ) @@ -1272,7 +1272,7 @@ NETS 152 ; NEW met1 ( 10603 901 ) M1M2_PR NEW li1 ( 10557 1989 ) L1M1_PR_MR NEW met1 ( 10603 1989 ) M1M2_PR ; - - addr[2] ( PIN addr[2] ) ( decoder.inv_2 A ) ( decoder_7.and_layer1 B ) ( decoder_6.and_layer1 B ) ( decoder_5.and_layer1 B ) ( decoder_4.and_layer1 B ) + USE SIGNAL + - addr_rw[2] ( PIN addr_rw[2] ) ( decoder.inv_2 A ) ( decoder_7.and_layer1 B ) ( decoder_6.and_layer1 B ) ( decoder_5.and_layer1 B ) ( decoder_4.and_layer1 B ) + USE SIGNAL + ROUTED met3 ( 10925 578 ) ( 10994 * 0 ) NEW met2 ( 10925 119 ) ( * 578 ) NEW met1 ( 10649 1207 ) ( 10695 * ) @@ -1296,8 +1296,8 @@ NETS 152 ; NEW met1 ( 10695 1751 ) M1M2_PR NEW li1 ( 10649 2023 ) L1M1_PR_MR NEW met1 ( 10695 2023 ) M1M2_PR ; - - clk ( PIN clk ) ( storage_7_0.cg CLK ) ( storage_6_0.cg CLK ) ( storage_5_0.cg CLK ) ( storage_4_0.cg CLK ) ( storage_3_0.cg CLK ) ( storage_2_0.cg CLK ) - ( storage_1_0.cg CLK ) ( storage_0_0.cg CLK ) + USE SIGNAL + - clk ( PIN clk ) ( storage_7_0_0.cg CLK ) ( storage_6_0_0.cg CLK ) ( storage_5_0_0.cg CLK ) ( storage_4_0_0.cg CLK ) ( storage_3_0_0.cg CLK ) ( storage_2_0_0.cg CLK ) + ( storage_1_0_0.cg CLK ) ( storage_0_0_0.cg CLK ) + USE SIGNAL + ROUTED met2 ( 9775 119 ) ( * 170 ) NEW met3 ( 9775 170 ) ( 10994 * 0 ) NEW met2 ( 9775 170 ) ( * 425 ) @@ -1318,7 +1318,7 @@ NETS 152 ; NEW met1 ( 9775 1513 ) M1M2_PR_MR NEW met1 ( 9729 1751 ) M1M2_PR NEW met1 ( 9729 2057 ) M1M2_PR ; - - decoder_0.decoder0 ( storage_0_0.select_inv_0 A ) ( storage_0_0.gcand A ) ( decoder_0.buf_port0 X ) + USE SIGNAL + - decoder_0.decoder0 ( storage_0_0_0.select_inv_0 A ) ( storage_0_0_0.gcand A ) ( decoder_0.buf_port0 X ) + USE SIGNAL + ROUTED met1 ( 10143 85 ) ( 10235 * ) NEW met1 ( 10235 51 ) ( * 85 ) NEW met1 ( 10235 51 ) ( 10879 * ) @@ -1338,7 +1338,7 @@ NETS 152 ; NEW li1 ( 10419 153 ) L1M1_PR_MR NEW li1 ( 10741 187 ) L1M1_PR_MR ; - decoder_0.layer_in1 + USE SIGNAL ; - - decoder_1.decoder0 ( storage_1_0.select_inv_0 A ) ( storage_1_0.gcand A ) ( decoder_1.buf_port0 X ) + USE SIGNAL + - decoder_1.decoder0 ( storage_1_0_0.select_inv_0 A ) ( storage_1_0_0.gcand A ) ( decoder_1.buf_port0 X ) + USE SIGNAL + ROUTED met1 ( 10143 493 ) ( 10879 * ) NEW met1 ( 9913 391 ) ( * 425 ) NEW met1 ( 9913 425 ) ( 10143 * ) @@ -1356,7 +1356,7 @@ NETS 152 ; NEW li1 ( 10419 425 ) L1M1_PR_MR NEW li1 ( 10741 425 ) L1M1_PR_MR ; - decoder_1.layer_in1 + USE SIGNAL ; - - decoder_2.decoder0 ( storage_2_0.select_inv_0 A ) ( storage_2_0.gcand A ) ( decoder_2.buf_port0 X ) + USE SIGNAL + - decoder_2.decoder0 ( storage_2_0_0.select_inv_0 A ) ( storage_2_0_0.gcand A ) ( decoder_2.buf_port0 X ) + USE SIGNAL + ROUTED met1 ( 10143 629 ) ( 10235 * ) NEW met1 ( 10235 595 ) ( * 629 ) NEW met1 ( 10235 595 ) ( 10879 * ) @@ -1376,7 +1376,7 @@ NETS 152 ; NEW li1 ( 10419 697 ) L1M1_PR_MR NEW li1 ( 10741 731 ) L1M1_PR_MR ; - decoder_2.layer_in1 + USE SIGNAL ; - - decoder_3.decoder0 ( storage_3_0.select_inv_0 A ) ( storage_3_0.gcand A ) ( decoder_3.buf_port0 X ) + USE SIGNAL + - decoder_3.decoder0 ( storage_3_0_0.select_inv_0 A ) ( storage_3_0_0.gcand A ) ( decoder_3.buf_port0 X ) + USE SIGNAL + ROUTED met1 ( 10143 1037 ) ( 10879 * ) NEW met1 ( 9913 935 ) ( * 969 ) NEW met1 ( 9913 969 ) ( 10143 * ) @@ -1394,7 +1394,7 @@ NETS 152 ; NEW li1 ( 10419 969 ) L1M1_PR_MR NEW li1 ( 10741 969 ) L1M1_PR_MR ; - decoder_3.layer_in1 + USE SIGNAL ; - - decoder_4.decoder0 ( storage_4_0.select_inv_0 A ) ( storage_4_0.gcand A ) ( decoder_4.buf_port0 X ) + USE SIGNAL + - decoder_4.decoder0 ( storage_4_0_0.select_inv_0 A ) ( storage_4_0_0.gcand A ) ( decoder_4.buf_port0 X ) + USE SIGNAL + ROUTED met1 ( 10143 1173 ) ( 10235 * ) NEW met1 ( 10235 1139 ) ( * 1173 ) NEW met1 ( 10235 1139 ) ( 10879 * ) @@ -1414,7 +1414,7 @@ NETS 152 ; NEW li1 ( 10419 1241 ) L1M1_PR_MR NEW li1 ( 10741 1275 ) L1M1_PR_MR ; - decoder_4.layer_in1 + USE SIGNAL ; - - decoder_5.decoder0 ( storage_5_0.select_inv_0 A ) ( storage_5_0.gcand A ) ( decoder_5.buf_port0 X ) + USE SIGNAL + - decoder_5.decoder0 ( storage_5_0_0.select_inv_0 A ) ( storage_5_0_0.gcand A ) ( decoder_5.buf_port0 X ) + USE SIGNAL + ROUTED met1 ( 10143 1581 ) ( 10879 * ) NEW met1 ( 9913 1479 ) ( * 1513 ) NEW met1 ( 9913 1513 ) ( 10143 * ) @@ -1432,7 +1432,7 @@ NETS 152 ; NEW li1 ( 10419 1513 ) L1M1_PR_MR NEW li1 ( 10741 1513 ) L1M1_PR_MR ; - decoder_5.layer_in1 + USE SIGNAL ; - - decoder_6.decoder0 ( storage_6_0.select_inv_0 A ) ( storage_6_0.gcand A ) ( decoder_6.buf_port0 X ) + USE SIGNAL + - decoder_6.decoder0 ( storage_6_0_0.select_inv_0 A ) ( storage_6_0_0.gcand A ) ( decoder_6.buf_port0 X ) + USE SIGNAL + ROUTED met1 ( 10143 1717 ) ( 10235 * ) NEW met1 ( 10235 1683 ) ( * 1717 ) NEW met1 ( 10235 1683 ) ( 10879 * ) @@ -1452,7 +1452,7 @@ NETS 152 ; NEW li1 ( 10419 1785 ) L1M1_PR_MR NEW li1 ( 10741 1819 ) L1M1_PR_MR ; - decoder_6.layer_in1 + USE SIGNAL ; - - decoder_7.decoder0 ( storage_7_0.select_inv_0 A ) ( storage_7_0.gcand A ) ( decoder_7.buf_port0 X ) + USE SIGNAL + - decoder_7.decoder0 ( storage_7_0_0.select_inv_0 A ) ( storage_7_0_0.gcand A ) ( decoder_7.buf_port0 X ) + USE SIGNAL + ROUTED met1 ( 10143 2125 ) ( 10879 * ) NEW met1 ( 9913 2023 ) ( * 2057 ) NEW met1 ( 9913 2057 ) ( 10143 * ) @@ -1470,7 +1470,7 @@ NETS 152 ; NEW li1 ( 10419 2057 ) L1M1_PR_MR NEW li1 ( 10741 2057 ) L1M1_PR_MR ; - decoder_7.layer_in1 + USE SIGNAL ; - - inv.addr[0] ( decoder.inv_0 Y ) ( decoder_6.and_layer0 A ) ( decoder_4.and_layer0 A ) ( decoder_2.and_layer0 A ) ( decoder_0.and_layer0 A ) + USE SIGNAL + - inv.addr0 ( decoder.inv_0 Y ) ( decoder_6.and_layer0 A ) ( decoder_4.and_layer0 A ) ( decoder_2.and_layer0 A ) ( decoder_0.and_layer0 A ) + USE SIGNAL + ROUTED met1 ( 10327 1819 ) ( * 1853 ) NEW met1 ( 10327 1853 ) ( 10971 * ) NEW met2 ( 10327 1275 ) ( * 1819 ) @@ -1485,7 +1485,7 @@ NETS 152 ; NEW met1 ( 10327 731 ) M1M2_PR NEW li1 ( 10327 187 ) L1M1_PR_MR NEW met1 ( 10327 187 ) M1M2_PR ; - - inv.addr[1] ( decoder.inv_1 Y ) ( decoder_5.and_layer1 A ) ( decoder_4.and_layer1 A ) ( decoder_1.and_layer1 A ) ( decoder_0.and_layer1 A ) + USE SIGNAL + - inv.addr1 ( decoder.inv_1 Y ) ( decoder_5.and_layer1 A ) ( decoder_4.and_layer1 A ) ( decoder_1.and_layer1 A ) ( decoder_0.and_layer1 A ) + USE SIGNAL + ROUTED met2 ( 10557 1241 ) ( * 1445 ) NEW met2 ( 10971 1037 ) ( * 1241 ) NEW met1 ( 10557 1241 ) ( 10971 * ) @@ -1502,7 +1502,7 @@ NETS 152 ; NEW met1 ( 10557 391 ) M1M2_PR NEW li1 ( 10557 153 ) L1M1_PR_MR NEW met1 ( 10557 153 ) M1M2_PR ; - - inv.addr[2] ( decoder.inv_2 Y ) ( decoder_3.and_layer1 B ) ( decoder_2.and_layer1 B ) ( decoder_1.and_layer1 B ) ( decoder_0.and_layer1 B ) + USE SIGNAL + - inv.addr2 ( decoder.inv_2 Y ) ( decoder_3.and_layer1 B ) ( decoder_2.and_layer1 B ) ( decoder_1.and_layer1 B ) ( decoder_0.and_layer1 B ) + USE SIGNAL + ROUTED met1 ( 10649 153 ) ( 10971 * ) NEW met2 ( 10649 153 ) ( * 391 ) NEW met2 ( 10649 391 ) ( * 663 ) @@ -1516,48 +1516,48 @@ NETS 152 ; NEW met1 ( 10649 663 ) M1M2_PR NEW li1 ( 10649 935 ) L1M1_PR_MR NEW met1 ( 10649 935 ) M1M2_PR ; - - storage_0_0.bit0.storage ( storage_0_0.bit0.obuf0 A ) ( storage_0_0.bit0.bit Q ) + USE SIGNAL + - storage_0_0_0.bit0.storage ( storage_0_0_0.bit0.obuf0 A ) ( storage_0_0_0.bit0.bit Q ) + USE SIGNAL + ROUTED met1 ( 805 153 ) ( * 187 ) NEW met1 ( 759 187 ) ( 805 * ) NEW li1 ( 805 153 ) L1M1_PR_MR NEW li1 ( 759 187 ) L1M1_PR_MR ; - - storage_0_0.bit1.storage ( storage_0_0.bit1.obuf0 A ) ( storage_0_0.bit1.bit Q ) + USE SIGNAL + - storage_0_0_0.bit1.storage ( storage_0_0_0.bit1.obuf0 A ) ( storage_0_0_0.bit1.bit Q ) + USE SIGNAL + ROUTED met1 ( 1955 153 ) ( * 187 ) NEW met1 ( 1909 187 ) ( 1955 * ) NEW li1 ( 1955 153 ) L1M1_PR_MR NEW li1 ( 1909 187 ) L1M1_PR_MR ; - - storage_0_0.bit2.storage ( storage_0_0.bit2.obuf0 A ) ( storage_0_0.bit2.bit Q ) + USE SIGNAL + - storage_0_0_0.bit2.storage ( storage_0_0_0.bit2.obuf0 A ) ( storage_0_0_0.bit2.bit Q ) + USE SIGNAL + ROUTED met1 ( 3105 153 ) ( * 187 ) NEW met1 ( 3059 187 ) ( 3105 * ) NEW li1 ( 3105 153 ) L1M1_PR_MR NEW li1 ( 3059 187 ) L1M1_PR_MR ; - - storage_0_0.bit3.storage ( storage_0_0.bit3.obuf0 A ) ( storage_0_0.bit3.bit Q ) + USE SIGNAL + - storage_0_0_0.bit3.storage ( storage_0_0_0.bit3.obuf0 A ) ( storage_0_0_0.bit3.bit Q ) + USE SIGNAL + ROUTED met1 ( 4255 153 ) ( * 187 ) NEW met1 ( 4209 187 ) ( 4255 * ) NEW li1 ( 4255 153 ) L1M1_PR_MR NEW li1 ( 4209 187 ) L1M1_PR_MR ; - - storage_0_0.bit4.storage ( storage_0_0.bit4.obuf0 A ) ( storage_0_0.bit4.bit Q ) + USE SIGNAL + - storage_0_0_0.bit4.storage ( storage_0_0_0.bit4.obuf0 A ) ( storage_0_0_0.bit4.bit Q ) + USE SIGNAL + ROUTED met1 ( 5405 153 ) ( * 187 ) NEW met1 ( 5359 187 ) ( 5405 * ) NEW li1 ( 5405 153 ) L1M1_PR_MR NEW li1 ( 5359 187 ) L1M1_PR_MR ; - - storage_0_0.bit5.storage ( storage_0_0.bit5.obuf0 A ) ( storage_0_0.bit5.bit Q ) + USE SIGNAL + - storage_0_0_0.bit5.storage ( storage_0_0_0.bit5.obuf0 A ) ( storage_0_0_0.bit5.bit Q ) + USE SIGNAL + ROUTED met1 ( 6555 153 ) ( * 187 ) NEW met1 ( 6509 187 ) ( 6555 * ) NEW li1 ( 6555 153 ) L1M1_PR_MR NEW li1 ( 6509 187 ) L1M1_PR_MR ; - - storage_0_0.bit6.storage ( storage_0_0.bit6.obuf0 A ) ( storage_0_0.bit6.bit Q ) + USE SIGNAL + - storage_0_0_0.bit6.storage ( storage_0_0_0.bit6.obuf0 A ) ( storage_0_0_0.bit6.bit Q ) + USE SIGNAL + ROUTED met1 ( 7705 153 ) ( * 187 ) NEW met1 ( 7659 187 ) ( 7705 * ) NEW li1 ( 7705 153 ) L1M1_PR_MR NEW li1 ( 7659 187 ) L1M1_PR_MR ; - - storage_0_0.bit7.storage ( storage_0_0.bit7.obuf0 A ) ( storage_0_0.bit7.bit Q ) + USE SIGNAL + - storage_0_0_0.bit7.storage ( storage_0_0_0.bit7.obuf0 A ) ( storage_0_0_0.bit7.bit Q ) + USE SIGNAL + ROUTED met1 ( 8855 153 ) ( * 187 ) NEW met1 ( 8809 187 ) ( 8855 * ) NEW li1 ( 8855 153 ) L1M1_PR_MR NEW li1 ( 8809 187 ) L1M1_PR_MR ; - - storage_0_0.gclock ( storage_0_0.cg GCLK ) ( storage_0_0.bit7.bit CLK ) ( storage_0_0.bit6.bit CLK ) ( storage_0_0.bit5.bit CLK ) ( storage_0_0.bit4.bit CLK ) ( storage_0_0.bit3.bit CLK ) ( storage_0_0.bit2.bit CLK ) - ( storage_0_0.bit1.bit CLK ) ( storage_0_0.bit0.bit CLK ) + USE SIGNAL + - storage_0_0_0.gclock ( storage_0_0_0.cg GCLK ) ( storage_0_0_0.bit7.bit CLK ) ( storage_0_0_0.bit6.bit CLK ) ( storage_0_0_0.bit5.bit CLK ) ( storage_0_0_0.bit4.bit CLK ) ( storage_0_0_0.bit3.bit CLK ) ( storage_0_0_0.bit2.bit CLK ) + ( storage_0_0_0.bit1.bit CLK ) ( storage_0_0_0.bit0.bit CLK ) + USE SIGNAL + ROUTED met1 ( 1219 153 ) ( * 221 ) NEW met1 ( 69 85 ) ( * 119 ) NEW met1 ( 69 85 ) ( 851 * ) @@ -1600,8 +1600,8 @@ NETS 152 ; NEW li1 ( 6969 153 ) L1M1_PR_MR NEW li1 ( 8119 119 ) L1M1_PR_MR NEW li1 ( 9867 51 ) L1M1_PR_MR ; - - storage_0_0.select0_b ( storage_0_0.select_inv_0 Y ) ( storage_0_0.bit7.obuf0 TE_B ) ( storage_0_0.bit6.obuf0 TE_B ) ( storage_0_0.bit5.obuf0 TE_B ) ( storage_0_0.bit4.obuf0 TE_B ) ( storage_0_0.bit3.obuf0 TE_B ) ( storage_0_0.bit2.obuf0 TE_B ) - ( storage_0_0.bit1.obuf0 TE_B ) ( storage_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + - storage_0_0_0.select0_b ( storage_0_0_0.select_inv_0 Y ) ( storage_0_0_0.bit7.obuf0 TE_B ) ( storage_0_0_0.bit6.obuf0 TE_B ) ( storage_0_0_0.bit5.obuf0 TE_B ) ( storage_0_0_0.bit4.obuf0 TE_B ) ( storage_0_0_0.bit3.obuf0 TE_B ) ( storage_0_0_0.bit2.obuf0 TE_B ) + ( storage_0_0_0.bit1.obuf0 TE_B ) ( storage_0_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + ROUTED met1 ( 897 85 ) ( * 119 ) NEW met1 ( 6647 85 ) ( * 119 ) NEW met1 ( 5497 119 ) ( 5773 * ) @@ -1649,55 +1649,55 @@ NETS 152 ; NEW li1 ( 7797 153 ) L1M1_PR_MR NEW met1 ( 8073 153 ) M1M2_PR NEW met1 ( 8119 221 ) M1M2_PR ; - - storage_0_0.we0 ( storage_0_0.gcand X ) ( storage_0_0.cg GATE ) + USE SIGNAL + - storage_0_0_0.we0 ( storage_0_0_0.gcand X ) ( storage_0_0_0.cg GATE ) + USE SIGNAL + ROUTED met2 ( 9453 153 ) ( * 221 ) NEW met1 ( 9453 221 ) ( 10097 * ) NEW li1 ( 9453 153 ) L1M1_PR_MR NEW met1 ( 9453 153 ) M1M2_PR NEW met1 ( 9453 221 ) M1M2_PR NEW li1 ( 10097 221 ) L1M1_PR_MR ; - - storage_1_0.bit0.storage ( storage_1_0.bit0.obuf0 A ) ( storage_1_0.bit0.bit Q ) + USE SIGNAL + - storage_1_0_0.bit0.storage ( storage_1_0_0.bit0.obuf0 A ) ( storage_1_0_0.bit0.bit Q ) + USE SIGNAL + ROUTED met1 ( 759 391 ) ( 805 * ) NEW met1 ( 759 357 ) ( * 391 ) NEW li1 ( 805 391 ) L1M1_PR_MR NEW li1 ( 759 357 ) L1M1_PR_MR ; - - storage_1_0.bit1.storage ( storage_1_0.bit1.obuf0 A ) ( storage_1_0.bit1.bit Q ) + USE SIGNAL + - storage_1_0_0.bit1.storage ( storage_1_0_0.bit1.obuf0 A ) ( storage_1_0_0.bit1.bit Q ) + USE SIGNAL + ROUTED met1 ( 1909 391 ) ( 1955 * ) NEW met1 ( 1909 357 ) ( * 391 ) NEW li1 ( 1955 391 ) L1M1_PR_MR NEW li1 ( 1909 357 ) L1M1_PR_MR ; - - storage_1_0.bit2.storage ( storage_1_0.bit2.obuf0 A ) ( storage_1_0.bit2.bit Q ) + USE SIGNAL + - storage_1_0_0.bit2.storage ( storage_1_0_0.bit2.obuf0 A ) ( storage_1_0_0.bit2.bit Q ) + USE SIGNAL + ROUTED met1 ( 3059 391 ) ( 3105 * ) NEW met1 ( 3059 357 ) ( * 391 ) NEW li1 ( 3105 391 ) L1M1_PR_MR NEW li1 ( 3059 357 ) L1M1_PR_MR ; - - storage_1_0.bit3.storage ( storage_1_0.bit3.obuf0 A ) ( storage_1_0.bit3.bit Q ) + USE SIGNAL + - storage_1_0_0.bit3.storage ( storage_1_0_0.bit3.obuf0 A ) ( storage_1_0_0.bit3.bit Q ) + USE SIGNAL + ROUTED met1 ( 4209 391 ) ( 4255 * ) NEW met1 ( 4209 357 ) ( * 391 ) NEW li1 ( 4255 391 ) L1M1_PR_MR NEW li1 ( 4209 357 ) L1M1_PR_MR ; - - storage_1_0.bit4.storage ( storage_1_0.bit4.obuf0 A ) ( storage_1_0.bit4.bit Q ) + USE SIGNAL + - storage_1_0_0.bit4.storage ( storage_1_0_0.bit4.obuf0 A ) ( storage_1_0_0.bit4.bit Q ) + USE SIGNAL + ROUTED met1 ( 5359 391 ) ( 5405 * ) NEW met1 ( 5359 357 ) ( * 391 ) NEW li1 ( 5405 391 ) L1M1_PR_MR NEW li1 ( 5359 357 ) L1M1_PR_MR ; - - storage_1_0.bit5.storage ( storage_1_0.bit5.obuf0 A ) ( storage_1_0.bit5.bit Q ) + USE SIGNAL + - storage_1_0_0.bit5.storage ( storage_1_0_0.bit5.obuf0 A ) ( storage_1_0_0.bit5.bit Q ) + USE SIGNAL + ROUTED met1 ( 6509 391 ) ( 6555 * ) NEW met1 ( 6509 357 ) ( * 391 ) NEW li1 ( 6555 391 ) L1M1_PR_MR NEW li1 ( 6509 357 ) L1M1_PR_MR ; - - storage_1_0.bit6.storage ( storage_1_0.bit6.obuf0 A ) ( storage_1_0.bit6.bit Q ) + USE SIGNAL + - storage_1_0_0.bit6.storage ( storage_1_0_0.bit6.obuf0 A ) ( storage_1_0_0.bit6.bit Q ) + USE SIGNAL + ROUTED met1 ( 7659 391 ) ( 7705 * ) NEW met1 ( 7659 357 ) ( * 391 ) NEW li1 ( 7705 391 ) L1M1_PR_MR NEW li1 ( 7659 357 ) L1M1_PR_MR ; - - storage_1_0.bit7.storage ( storage_1_0.bit7.obuf0 A ) ( storage_1_0.bit7.bit Q ) + USE SIGNAL + - storage_1_0_0.bit7.storage ( storage_1_0_0.bit7.obuf0 A ) ( storage_1_0_0.bit7.bit Q ) + USE SIGNAL + ROUTED met1 ( 8809 391 ) ( 8855 * ) NEW met1 ( 8809 357 ) ( * 391 ) NEW li1 ( 8855 391 ) L1M1_PR_MR NEW li1 ( 8809 357 ) L1M1_PR_MR ; - - storage_1_0.gclock ( storage_1_0.cg GCLK ) ( storage_1_0.bit7.bit CLK ) ( storage_1_0.bit6.bit CLK ) ( storage_1_0.bit5.bit CLK ) ( storage_1_0.bit4.bit CLK ) ( storage_1_0.bit3.bit CLK ) ( storage_1_0.bit2.bit CLK ) - ( storage_1_0.bit1.bit CLK ) ( storage_1_0.bit0.bit CLK ) + USE SIGNAL + - storage_1_0_0.gclock ( storage_1_0_0.cg GCLK ) ( storage_1_0_0.bit7.bit CLK ) ( storage_1_0_0.bit6.bit CLK ) ( storage_1_0_0.bit5.bit CLK ) ( storage_1_0_0.bit4.bit CLK ) ( storage_1_0_0.bit3.bit CLK ) ( storage_1_0_0.bit2.bit CLK ) + ( storage_1_0_0.bit1.bit CLK ) ( storage_1_0_0.bit0.bit CLK ) + USE SIGNAL + ROUTED met1 ( 69 425 ) ( 1219 * ) NEW met1 ( 3519 425 ) ( * 459 ) NEW met1 ( 3473 459 ) ( 3519 * ) @@ -1727,8 +1727,8 @@ NETS 152 ; NEW li1 ( 6969 391 ) L1M1_PR_MR NEW li1 ( 8119 391 ) L1M1_PR_MR NEW li1 ( 9867 323 ) L1M1_PR_MR ; - - storage_1_0.select0_b ( storage_1_0.select_inv_0 Y ) ( storage_1_0.bit7.obuf0 TE_B ) ( storage_1_0.bit6.obuf0 TE_B ) ( storage_1_0.bit5.obuf0 TE_B ) ( storage_1_0.bit4.obuf0 TE_B ) ( storage_1_0.bit3.obuf0 TE_B ) ( storage_1_0.bit2.obuf0 TE_B ) - ( storage_1_0.bit1.obuf0 TE_B ) ( storage_1_0.bit0.obuf0 TE_B ) + USE SIGNAL + - storage_1_0_0.select0_b ( storage_1_0_0.select_inv_0 Y ) ( storage_1_0_0.bit7.obuf0 TE_B ) ( storage_1_0_0.bit6.obuf0 TE_B ) ( storage_1_0_0.bit5.obuf0 TE_B ) ( storage_1_0_0.bit4.obuf0 TE_B ) ( storage_1_0_0.bit3.obuf0 TE_B ) ( storage_1_0_0.bit2.obuf0 TE_B ) + ( storage_1_0_0.bit1.obuf0 TE_B ) ( storage_1_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + ROUTED met1 ( 897 323 ) ( * 391 ) NEW met1 ( 5497 425 ) ( 6647 * ) NEW met1 ( 4347 425 ) ( 5497 * ) @@ -1758,26 +1758,26 @@ NETS 152 ; NEW li1 ( 7797 425 ) L1M1_PR_MR NEW met1 ( 8947 493 ) M1M2_PR NEW met1 ( 8947 391 ) M1M2_PR ; - - storage_1_0.we0 ( storage_1_0.gcand X ) ( storage_1_0.cg GATE ) + USE SIGNAL + - storage_1_0_0.we0 ( storage_1_0_0.gcand X ) ( storage_1_0_0.cg GATE ) + USE SIGNAL + ROUTED met1 ( 9453 493 ) ( 10097 * ) NEW li1 ( 9453 493 ) L1M1_PR_MR NEW li1 ( 10097 493 ) L1M1_PR_MR ; - - storage_2_0.bit0.storage ( storage_2_0.bit0.obuf0 A ) ( storage_2_0.bit0.bit Q ) + USE SIGNAL + - storage_2_0_0.bit0.storage ( storage_2_0_0.bit0.obuf0 A ) ( storage_2_0_0.bit0.bit Q ) + USE SIGNAL + ROUTED met1 ( 759 663 ) ( 805 * ) NEW met1 ( 759 595 ) ( * 663 ) NEW li1 ( 805 663 ) L1M1_PR_MR NEW li1 ( 759 595 ) L1M1_PR_MR ; - - storage_2_0.bit1.storage ( storage_2_0.bit1.obuf0 A ) ( storage_2_0.bit1.bit Q ) + USE SIGNAL + - storage_2_0_0.bit1.storage ( storage_2_0_0.bit1.obuf0 A ) ( storage_2_0_0.bit1.bit Q ) + USE SIGNAL + ROUTED met1 ( 1955 663 ) ( * 731 ) NEW met1 ( 1909 731 ) ( 1955 * ) NEW li1 ( 1955 663 ) L1M1_PR_MR NEW li1 ( 1909 731 ) L1M1_PR_MR ; - - storage_2_0.bit2.storage ( storage_2_0.bit2.obuf0 A ) ( storage_2_0.bit2.bit Q ) + USE SIGNAL + - storage_2_0_0.bit2.storage ( storage_2_0_0.bit2.obuf0 A ) ( storage_2_0_0.bit2.bit Q ) + USE SIGNAL + ROUTED met1 ( 3059 663 ) ( 3105 * ) NEW met1 ( 3059 595 ) ( * 663 ) NEW li1 ( 3105 663 ) L1M1_PR_MR NEW li1 ( 3059 595 ) L1M1_PR_MR ; - - storage_2_0.bit3.storage ( storage_2_0.bit3.obuf0 A ) ( storage_2_0.bit3.bit Q ) + USE SIGNAL + - storage_2_0_0.bit3.storage ( storage_2_0_0.bit3.obuf0 A ) ( storage_2_0_0.bit3.bit Q ) + USE SIGNAL + ROUTED met1 ( 4209 595 ) ( 4255 * ) NEW met2 ( 4255 595 ) ( * 663 ) NEW met1 ( 4254 663 ) ( 4255 * ) @@ -1785,28 +1785,28 @@ NETS 152 ; NEW met1 ( 4255 595 ) M1M2_PR NEW met1 ( 4255 663 ) M1M2_PR NEW li1 ( 4254 663 ) L1M1_PR_MR ; - - storage_2_0.bit4.storage ( storage_2_0.bit4.obuf0 A ) ( storage_2_0.bit4.bit Q ) + USE SIGNAL + - storage_2_0_0.bit4.storage ( storage_2_0_0.bit4.obuf0 A ) ( storage_2_0_0.bit4.bit Q ) + USE SIGNAL + ROUTED met1 ( 5359 663 ) ( 5405 * ) NEW met1 ( 5359 595 ) ( * 663 ) NEW li1 ( 5405 663 ) L1M1_PR_MR NEW li1 ( 5359 595 ) L1M1_PR_MR ; - - storage_2_0.bit5.storage ( storage_2_0.bit5.obuf0 A ) ( storage_2_0.bit5.bit Q ) + USE SIGNAL + - storage_2_0_0.bit5.storage ( storage_2_0_0.bit5.obuf0 A ) ( storage_2_0_0.bit5.bit Q ) + USE SIGNAL + ROUTED met1 ( 6509 663 ) ( 6555 * ) NEW met1 ( 6509 663 ) ( * 731 ) NEW li1 ( 6555 663 ) L1M1_PR_MR NEW li1 ( 6509 731 ) L1M1_PR_MR ; - - storage_2_0.bit6.storage ( storage_2_0.bit6.obuf0 A ) ( storage_2_0.bit6.bit Q ) + USE SIGNAL + - storage_2_0_0.bit6.storage ( storage_2_0_0.bit6.obuf0 A ) ( storage_2_0_0.bit6.bit Q ) + USE SIGNAL + ROUTED met1 ( 7705 697 ) ( * 731 ) NEW met1 ( 7659 731 ) ( 7705 * ) NEW li1 ( 7705 697 ) L1M1_PR_MR NEW li1 ( 7659 731 ) L1M1_PR_MR ; - - storage_2_0.bit7.storage ( storage_2_0.bit7.obuf0 A ) ( storage_2_0.bit7.bit Q ) + USE SIGNAL + - storage_2_0_0.bit7.storage ( storage_2_0_0.bit7.obuf0 A ) ( storage_2_0_0.bit7.bit Q ) + USE SIGNAL + ROUTED met1 ( 8855 697 ) ( * 731 ) NEW met1 ( 8809 731 ) ( 8855 * ) NEW li1 ( 8855 697 ) L1M1_PR_MR NEW li1 ( 8809 731 ) L1M1_PR_MR ; - - storage_2_0.gclock ( storage_2_0.cg GCLK ) ( storage_2_0.bit7.bit CLK ) ( storage_2_0.bit6.bit CLK ) ( storage_2_0.bit5.bit CLK ) ( storage_2_0.bit4.bit CLK ) ( storage_2_0.bit3.bit CLK ) ( storage_2_0.bit2.bit CLK ) - ( storage_2_0.bit1.bit CLK ) ( storage_2_0.bit0.bit CLK ) + USE SIGNAL + - storage_2_0_0.gclock ( storage_2_0_0.cg GCLK ) ( storage_2_0_0.bit7.bit CLK ) ( storage_2_0_0.bit6.bit CLK ) ( storage_2_0_0.bit5.bit CLK ) ( storage_2_0_0.bit4.bit CLK ) ( storage_2_0_0.bit3.bit CLK ) ( storage_2_0_0.bit2.bit CLK ) + ( storage_2_0_0.bit1.bit CLK ) ( storage_2_0_0.bit0.bit CLK ) + USE SIGNAL + ROUTED met1 ( 943 663 ) ( 1219 * ) NEW met1 ( 943 663 ) ( * 697 ) NEW met1 ( 713 697 ) ( 943 * ) @@ -1860,8 +1860,8 @@ NETS 152 ; NEW li1 ( 9867 595 ) L1M1_PR_MR NEW met1 ( 7613 459 ) M1M2_PR NEW met1 ( 7613 595 ) M1M2_PR ; - - storage_2_0.select0_b ( storage_2_0.select_inv_0 Y ) ( storage_2_0.bit7.obuf0 TE_B ) ( storage_2_0.bit6.obuf0 TE_B ) ( storage_2_0.bit5.obuf0 TE_B ) ( storage_2_0.bit4.obuf0 TE_B ) ( storage_2_0.bit3.obuf0 TE_B ) ( storage_2_0.bit2.obuf0 TE_B ) - ( storage_2_0.bit1.obuf0 TE_B ) ( storage_2_0.bit0.obuf0 TE_B ) + USE SIGNAL + - storage_2_0_0.select0_b ( storage_2_0_0.select_inv_0 Y ) ( storage_2_0_0.bit7.obuf0 TE_B ) ( storage_2_0_0.bit6.obuf0 TE_B ) ( storage_2_0_0.bit5.obuf0 TE_B ) ( storage_2_0_0.bit4.obuf0 TE_B ) ( storage_2_0_0.bit3.obuf0 TE_B ) ( storage_2_0_0.bit2.obuf0 TE_B ) + ( storage_2_0_0.bit1.obuf0 TE_B ) ( storage_2_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + ROUTED met1 ( 897 595 ) ( * 663 ) NEW met1 ( 3013 697 ) ( 3151 * ) NEW met1 ( 5313 697 ) ( 5451 * ) @@ -1905,55 +1905,55 @@ NETS 152 ; NEW li1 ( 8947 697 ) L1M1_PR_MR NEW li1 ( 10189 731 ) L1M1_PR_MR NEW li1 ( 7797 697 ) L1M1_PR_MR ; - - storage_2_0.we0 ( storage_2_0.gcand X ) ( storage_2_0.cg GATE ) + USE SIGNAL + - storage_2_0_0.we0 ( storage_2_0_0.gcand X ) ( storage_2_0_0.cg GATE ) + USE SIGNAL + ROUTED met2 ( 9453 697 ) ( * 765 ) NEW met1 ( 9453 765 ) ( 10097 * ) NEW li1 ( 9453 697 ) L1M1_PR_MR NEW met1 ( 9453 697 ) M1M2_PR NEW met1 ( 9453 765 ) M1M2_PR NEW li1 ( 10097 765 ) L1M1_PR_MR ; - - storage_3_0.bit0.storage ( storage_3_0.bit0.obuf0 A ) ( storage_3_0.bit0.bit Q ) + USE SIGNAL + - storage_3_0_0.bit0.storage ( storage_3_0_0.bit0.obuf0 A ) ( storage_3_0_0.bit0.bit Q ) + USE SIGNAL + ROUTED met1 ( 759 935 ) ( 805 * ) NEW met1 ( 759 901 ) ( * 935 ) NEW li1 ( 805 935 ) L1M1_PR_MR NEW li1 ( 759 901 ) L1M1_PR_MR ; - - storage_3_0.bit1.storage ( storage_3_0.bit1.obuf0 A ) ( storage_3_0.bit1.bit Q ) + USE SIGNAL + - storage_3_0_0.bit1.storage ( storage_3_0_0.bit1.obuf0 A ) ( storage_3_0_0.bit1.bit Q ) + USE SIGNAL + ROUTED met1 ( 1909 935 ) ( 1955 * ) NEW met1 ( 1909 901 ) ( * 935 ) NEW li1 ( 1955 935 ) L1M1_PR_MR NEW li1 ( 1909 901 ) L1M1_PR_MR ; - - storage_3_0.bit2.storage ( storage_3_0.bit2.obuf0 A ) ( storage_3_0.bit2.bit Q ) + USE SIGNAL + - storage_3_0_0.bit2.storage ( storage_3_0_0.bit2.obuf0 A ) ( storage_3_0_0.bit2.bit Q ) + USE SIGNAL + ROUTED met1 ( 3059 935 ) ( 3105 * ) NEW met1 ( 3059 901 ) ( * 935 ) NEW li1 ( 3105 935 ) L1M1_PR_MR NEW li1 ( 3059 901 ) L1M1_PR_MR ; - - storage_3_0.bit3.storage ( storage_3_0.bit3.obuf0 A ) ( storage_3_0.bit3.bit Q ) + USE SIGNAL + - storage_3_0_0.bit3.storage ( storage_3_0_0.bit3.obuf0 A ) ( storage_3_0_0.bit3.bit Q ) + USE SIGNAL + ROUTED met1 ( 4209 935 ) ( 4255 * ) NEW met1 ( 4209 901 ) ( * 935 ) NEW li1 ( 4255 935 ) L1M1_PR_MR NEW li1 ( 4209 901 ) L1M1_PR_MR ; - - storage_3_0.bit4.storage ( storage_3_0.bit4.obuf0 A ) ( storage_3_0.bit4.bit Q ) + USE SIGNAL + - storage_3_0_0.bit4.storage ( storage_3_0_0.bit4.obuf0 A ) ( storage_3_0_0.bit4.bit Q ) + USE SIGNAL + ROUTED met1 ( 5359 935 ) ( 5405 * ) NEW met1 ( 5359 901 ) ( * 935 ) NEW li1 ( 5405 935 ) L1M1_PR_MR NEW li1 ( 5359 901 ) L1M1_PR_MR ; - - storage_3_0.bit5.storage ( storage_3_0.bit5.obuf0 A ) ( storage_3_0.bit5.bit Q ) + USE SIGNAL + - storage_3_0_0.bit5.storage ( storage_3_0_0.bit5.obuf0 A ) ( storage_3_0_0.bit5.bit Q ) + USE SIGNAL + ROUTED met1 ( 6509 935 ) ( 6555 * ) NEW met1 ( 6509 901 ) ( * 935 ) NEW li1 ( 6555 935 ) L1M1_PR_MR NEW li1 ( 6509 901 ) L1M1_PR_MR ; - - storage_3_0.bit6.storage ( storage_3_0.bit6.obuf0 A ) ( storage_3_0.bit6.bit Q ) + USE SIGNAL + - storage_3_0_0.bit6.storage ( storage_3_0_0.bit6.obuf0 A ) ( storage_3_0_0.bit6.bit Q ) + USE SIGNAL + ROUTED met1 ( 7659 935 ) ( 7705 * ) NEW met1 ( 7659 901 ) ( * 935 ) NEW li1 ( 7705 935 ) L1M1_PR_MR NEW li1 ( 7659 901 ) L1M1_PR_MR ; - - storage_3_0.bit7.storage ( storage_3_0.bit7.obuf0 A ) ( storage_3_0.bit7.bit Q ) + USE SIGNAL + - storage_3_0_0.bit7.storage ( storage_3_0_0.bit7.obuf0 A ) ( storage_3_0_0.bit7.bit Q ) + USE SIGNAL + ROUTED met1 ( 8809 935 ) ( 8855 * ) NEW met1 ( 8809 901 ) ( * 935 ) NEW li1 ( 8855 935 ) L1M1_PR_MR NEW li1 ( 8809 901 ) L1M1_PR_MR ; - - storage_3_0.gclock ( storage_3_0.cg GCLK ) ( storage_3_0.bit7.bit CLK ) ( storage_3_0.bit6.bit CLK ) ( storage_3_0.bit5.bit CLK ) ( storage_3_0.bit4.bit CLK ) ( storage_3_0.bit3.bit CLK ) ( storage_3_0.bit2.bit CLK ) - ( storage_3_0.bit1.bit CLK ) ( storage_3_0.bit0.bit CLK ) + USE SIGNAL + - storage_3_0_0.gclock ( storage_3_0_0.cg GCLK ) ( storage_3_0_0.bit7.bit CLK ) ( storage_3_0_0.bit6.bit CLK ) ( storage_3_0_0.bit5.bit CLK ) ( storage_3_0_0.bit4.bit CLK ) ( storage_3_0_0.bit3.bit CLK ) ( storage_3_0_0.bit2.bit CLK ) + ( storage_3_0_0.bit1.bit CLK ) ( storage_3_0_0.bit0.bit CLK ) + USE SIGNAL + ROUTED met1 ( 1219 867 ) ( * 935 ) NEW met1 ( 69 969 ) ( 851 * ) NEW met1 ( 851 935 ) ( * 969 ) @@ -1980,8 +1980,8 @@ NETS 152 ; NEW li1 ( 5819 935 ) L1M1_PR_MR NEW li1 ( 8119 935 ) L1M1_PR_MR NEW li1 ( 9867 867 ) L1M1_PR_MR ; - - storage_3_0.select0_b ( storage_3_0.select_inv_0 Y ) ( storage_3_0.bit7.obuf0 TE_B ) ( storage_3_0.bit6.obuf0 TE_B ) ( storage_3_0.bit5.obuf0 TE_B ) ( storage_3_0.bit4.obuf0 TE_B ) ( storage_3_0.bit3.obuf0 TE_B ) ( storage_3_0.bit2.obuf0 TE_B ) - ( storage_3_0.bit1.obuf0 TE_B ) ( storage_3_0.bit0.obuf0 TE_B ) + USE SIGNAL + - storage_3_0_0.select0_b ( storage_3_0_0.select_inv_0 Y ) ( storage_3_0_0.bit7.obuf0 TE_B ) ( storage_3_0_0.bit6.obuf0 TE_B ) ( storage_3_0_0.bit5.obuf0 TE_B ) ( storage_3_0_0.bit4.obuf0 TE_B ) ( storage_3_0_0.bit3.obuf0 TE_B ) ( storage_3_0_0.bit2.obuf0 TE_B ) + ( storage_3_0_0.bit1.obuf0 TE_B ) ( storage_3_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + ROUTED met1 ( 4347 969 ) ( 5497 * ) NEW met1 ( 3197 969 ) ( 4347 * ) NEW met1 ( 2047 969 ) ( 3197 * ) @@ -2006,52 +2006,52 @@ NETS 152 ; NEW li1 ( 7797 969 ) L1M1_PR_MR NEW met1 ( 8947 1037 ) M1M2_PR NEW met1 ( 8947 935 ) M1M2_PR ; - - storage_3_0.we0 ( storage_3_0.gcand X ) ( storage_3_0.cg GATE ) + USE SIGNAL + - storage_3_0_0.we0 ( storage_3_0_0.gcand X ) ( storage_3_0_0.cg GATE ) + USE SIGNAL + ROUTED met1 ( 9453 1037 ) ( 10097 * ) NEW li1 ( 9453 1037 ) L1M1_PR_MR NEW li1 ( 10097 1037 ) L1M1_PR_MR ; - - storage_4_0.bit0.storage ( storage_4_0.bit0.obuf0 A ) ( storage_4_0.bit0.bit Q ) + USE SIGNAL + - storage_4_0_0.bit0.storage ( storage_4_0_0.bit0.obuf0 A ) ( storage_4_0_0.bit0.bit Q ) + USE SIGNAL + ROUTED met1 ( 805 1241 ) ( * 1275 ) NEW met1 ( 759 1275 ) ( 805 * ) NEW li1 ( 805 1241 ) L1M1_PR_MR NEW li1 ( 759 1275 ) L1M1_PR_MR ; - - storage_4_0.bit1.storage ( storage_4_0.bit1.obuf0 A ) ( storage_4_0.bit1.bit Q ) + USE SIGNAL + - storage_4_0_0.bit1.storage ( storage_4_0_0.bit1.obuf0 A ) ( storage_4_0_0.bit1.bit Q ) + USE SIGNAL + ROUTED met1 ( 1955 1241 ) ( * 1275 ) NEW met1 ( 1909 1275 ) ( 1955 * ) NEW li1 ( 1955 1241 ) L1M1_PR_MR NEW li1 ( 1909 1275 ) L1M1_PR_MR ; - - storage_4_0.bit2.storage ( storage_4_0.bit2.obuf0 A ) ( storage_4_0.bit2.bit Q ) + USE SIGNAL + - storage_4_0_0.bit2.storage ( storage_4_0_0.bit2.obuf0 A ) ( storage_4_0_0.bit2.bit Q ) + USE SIGNAL + ROUTED met1 ( 3105 1241 ) ( * 1275 ) NEW met1 ( 3059 1275 ) ( 3105 * ) NEW li1 ( 3105 1241 ) L1M1_PR_MR NEW li1 ( 3059 1275 ) L1M1_PR_MR ; - - storage_4_0.bit3.storage ( storage_4_0.bit3.obuf0 A ) ( storage_4_0.bit3.bit Q ) + USE SIGNAL + - storage_4_0_0.bit3.storage ( storage_4_0_0.bit3.obuf0 A ) ( storage_4_0_0.bit3.bit Q ) + USE SIGNAL + ROUTED met1 ( 4255 1241 ) ( * 1275 ) NEW met1 ( 4209 1275 ) ( 4255 * ) NEW li1 ( 4255 1241 ) L1M1_PR_MR NEW li1 ( 4209 1275 ) L1M1_PR_MR ; - - storage_4_0.bit4.storage ( storage_4_0.bit4.obuf0 A ) ( storage_4_0.bit4.bit Q ) + USE SIGNAL + - storage_4_0_0.bit4.storage ( storage_4_0_0.bit4.obuf0 A ) ( storage_4_0_0.bit4.bit Q ) + USE SIGNAL + ROUTED met1 ( 5405 1241 ) ( * 1275 ) NEW met1 ( 5359 1275 ) ( 5405 * ) NEW li1 ( 5405 1241 ) L1M1_PR_MR NEW li1 ( 5359 1275 ) L1M1_PR_MR ; - - storage_4_0.bit5.storage ( storage_4_0.bit5.obuf0 A ) ( storage_4_0.bit5.bit Q ) + USE SIGNAL + - storage_4_0_0.bit5.storage ( storage_4_0_0.bit5.obuf0 A ) ( storage_4_0_0.bit5.bit Q ) + USE SIGNAL + ROUTED met1 ( 6555 1241 ) ( * 1275 ) NEW met1 ( 6509 1275 ) ( 6555 * ) NEW li1 ( 6555 1241 ) L1M1_PR_MR NEW li1 ( 6509 1275 ) L1M1_PR_MR ; - - storage_4_0.bit6.storage ( storage_4_0.bit6.obuf0 A ) ( storage_4_0.bit6.bit Q ) + USE SIGNAL + - storage_4_0_0.bit6.storage ( storage_4_0_0.bit6.obuf0 A ) ( storage_4_0_0.bit6.bit Q ) + USE SIGNAL + ROUTED met1 ( 7705 1241 ) ( * 1275 ) NEW met1 ( 7659 1275 ) ( 7705 * ) NEW li1 ( 7705 1241 ) L1M1_PR_MR NEW li1 ( 7659 1275 ) L1M1_PR_MR ; - - storage_4_0.bit7.storage ( storage_4_0.bit7.obuf0 A ) ( storage_4_0.bit7.bit Q ) + USE SIGNAL + - storage_4_0_0.bit7.storage ( storage_4_0_0.bit7.obuf0 A ) ( storage_4_0_0.bit7.bit Q ) + USE SIGNAL + ROUTED met1 ( 8855 1241 ) ( * 1275 ) NEW met1 ( 8809 1275 ) ( 8855 * ) NEW li1 ( 8855 1241 ) L1M1_PR_MR NEW li1 ( 8809 1275 ) L1M1_PR_MR ; - - storage_4_0.gclock ( storage_4_0.cg GCLK ) ( storage_4_0.bit7.bit CLK ) ( storage_4_0.bit6.bit CLK ) ( storage_4_0.bit5.bit CLK ) ( storage_4_0.bit4.bit CLK ) ( storage_4_0.bit3.bit CLK ) ( storage_4_0.bit2.bit CLK ) - ( storage_4_0.bit1.bit CLK ) ( storage_4_0.bit0.bit CLK ) + USE SIGNAL + - storage_4_0_0.gclock ( storage_4_0_0.cg GCLK ) ( storage_4_0_0.bit7.bit CLK ) ( storage_4_0_0.bit6.bit CLK ) ( storage_4_0_0.bit5.bit CLK ) ( storage_4_0_0.bit4.bit CLK ) ( storage_4_0_0.bit3.bit CLK ) ( storage_4_0_0.bit2.bit CLK ) + ( storage_4_0_0.bit1.bit CLK ) ( storage_4_0_0.bit0.bit CLK ) + USE SIGNAL + ROUTED met1 ( 1219 1241 ) ( * 1309 ) NEW met1 ( 69 1173 ) ( * 1207 ) NEW met1 ( 69 1173 ) ( 851 * ) @@ -2088,8 +2088,8 @@ NETS 152 ; NEW li1 ( 5819 1241 ) L1M1_PR_MR NEW li1 ( 8119 1207 ) L1M1_PR_MR NEW li1 ( 9867 1139 ) L1M1_PR_MR ; - - storage_4_0.select0_b ( storage_4_0.select_inv_0 Y ) ( storage_4_0.bit7.obuf0 TE_B ) ( storage_4_0.bit6.obuf0 TE_B ) ( storage_4_0.bit5.obuf0 TE_B ) ( storage_4_0.bit4.obuf0 TE_B ) ( storage_4_0.bit3.obuf0 TE_B ) ( storage_4_0.bit2.obuf0 TE_B ) - ( storage_4_0.bit1.obuf0 TE_B ) ( storage_4_0.bit0.obuf0 TE_B ) + USE SIGNAL + - storage_4_0_0.select0_b ( storage_4_0_0.select_inv_0 Y ) ( storage_4_0_0.bit7.obuf0 TE_B ) ( storage_4_0_0.bit6.obuf0 TE_B ) ( storage_4_0_0.bit5.obuf0 TE_B ) ( storage_4_0_0.bit4.obuf0 TE_B ) ( storage_4_0_0.bit3.obuf0 TE_B ) ( storage_4_0_0.bit2.obuf0 TE_B ) + ( storage_4_0_0.bit1.obuf0 TE_B ) ( storage_4_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + ROUTED met1 ( 897 1173 ) ( * 1207 ) NEW met1 ( 6647 1241 ) ( * 1309 ) NEW met1 ( 6969 1275 ) ( * 1309 ) @@ -2124,55 +2124,55 @@ NETS 152 ; NEW li1 ( 8947 1241 ) L1M1_PR_MR NEW li1 ( 10189 1275 ) L1M1_PR_MR NEW li1 ( 7797 1241 ) L1M1_PR_MR ; - - storage_4_0.we0 ( storage_4_0.gcand X ) ( storage_4_0.cg GATE ) + USE SIGNAL + - storage_4_0_0.we0 ( storage_4_0_0.gcand X ) ( storage_4_0_0.cg GATE ) + USE SIGNAL + ROUTED met2 ( 9453 1241 ) ( * 1309 ) NEW met1 ( 9453 1309 ) ( 10097 * ) NEW li1 ( 9453 1241 ) L1M1_PR_MR NEW met1 ( 9453 1241 ) M1M2_PR NEW met1 ( 9453 1309 ) M1M2_PR NEW li1 ( 10097 1309 ) L1M1_PR_MR ; - - storage_5_0.bit0.storage ( storage_5_0.bit0.obuf0 A ) ( storage_5_0.bit0.bit Q ) + USE SIGNAL + - storage_5_0_0.bit0.storage ( storage_5_0_0.bit0.obuf0 A ) ( storage_5_0_0.bit0.bit Q ) + USE SIGNAL + ROUTED met1 ( 759 1479 ) ( 805 * ) NEW met1 ( 759 1445 ) ( * 1479 ) NEW li1 ( 805 1479 ) L1M1_PR_MR NEW li1 ( 759 1445 ) L1M1_PR_MR ; - - storage_5_0.bit1.storage ( storage_5_0.bit1.obuf0 A ) ( storage_5_0.bit1.bit Q ) + USE SIGNAL + - storage_5_0_0.bit1.storage ( storage_5_0_0.bit1.obuf0 A ) ( storage_5_0_0.bit1.bit Q ) + USE SIGNAL + ROUTED met1 ( 1909 1479 ) ( 1955 * ) NEW met1 ( 1909 1445 ) ( * 1479 ) NEW li1 ( 1955 1479 ) L1M1_PR_MR NEW li1 ( 1909 1445 ) L1M1_PR_MR ; - - storage_5_0.bit2.storage ( storage_5_0.bit2.obuf0 A ) ( storage_5_0.bit2.bit Q ) + USE SIGNAL + - storage_5_0_0.bit2.storage ( storage_5_0_0.bit2.obuf0 A ) ( storage_5_0_0.bit2.bit Q ) + USE SIGNAL + ROUTED met1 ( 3059 1479 ) ( 3105 * ) NEW met1 ( 3059 1445 ) ( * 1479 ) NEW li1 ( 3105 1479 ) L1M1_PR_MR NEW li1 ( 3059 1445 ) L1M1_PR_MR ; - - storage_5_0.bit3.storage ( storage_5_0.bit3.obuf0 A ) ( storage_5_0.bit3.bit Q ) + USE SIGNAL + - storage_5_0_0.bit3.storage ( storage_5_0_0.bit3.obuf0 A ) ( storage_5_0_0.bit3.bit Q ) + USE SIGNAL + ROUTED met1 ( 4209 1479 ) ( 4255 * ) NEW met1 ( 4209 1445 ) ( * 1479 ) NEW li1 ( 4255 1479 ) L1M1_PR_MR NEW li1 ( 4209 1445 ) L1M1_PR_MR ; - - storage_5_0.bit4.storage ( storage_5_0.bit4.obuf0 A ) ( storage_5_0.bit4.bit Q ) + USE SIGNAL + - storage_5_0_0.bit4.storage ( storage_5_0_0.bit4.obuf0 A ) ( storage_5_0_0.bit4.bit Q ) + USE SIGNAL + ROUTED met1 ( 5359 1479 ) ( 5405 * ) NEW met1 ( 5359 1445 ) ( * 1479 ) NEW li1 ( 5405 1479 ) L1M1_PR_MR NEW li1 ( 5359 1445 ) L1M1_PR_MR ; - - storage_5_0.bit5.storage ( storage_5_0.bit5.obuf0 A ) ( storage_5_0.bit5.bit Q ) + USE SIGNAL + - storage_5_0_0.bit5.storage ( storage_5_0_0.bit5.obuf0 A ) ( storage_5_0_0.bit5.bit Q ) + USE SIGNAL + ROUTED met1 ( 6509 1479 ) ( 6555 * ) NEW met1 ( 6509 1445 ) ( * 1479 ) NEW li1 ( 6555 1479 ) L1M1_PR_MR NEW li1 ( 6509 1445 ) L1M1_PR_MR ; - - storage_5_0.bit6.storage ( storage_5_0.bit6.obuf0 A ) ( storage_5_0.bit6.bit Q ) + USE SIGNAL + - storage_5_0_0.bit6.storage ( storage_5_0_0.bit6.obuf0 A ) ( storage_5_0_0.bit6.bit Q ) + USE SIGNAL + ROUTED met1 ( 7659 1479 ) ( 7705 * ) NEW met1 ( 7659 1445 ) ( * 1479 ) NEW li1 ( 7705 1479 ) L1M1_PR_MR NEW li1 ( 7659 1445 ) L1M1_PR_MR ; - - storage_5_0.bit7.storage ( storage_5_0.bit7.obuf0 A ) ( storage_5_0.bit7.bit Q ) + USE SIGNAL + - storage_5_0_0.bit7.storage ( storage_5_0_0.bit7.obuf0 A ) ( storage_5_0_0.bit7.bit Q ) + USE SIGNAL + ROUTED met1 ( 8809 1479 ) ( 8855 * ) NEW met1 ( 8809 1445 ) ( * 1479 ) NEW li1 ( 8855 1479 ) L1M1_PR_MR NEW li1 ( 8809 1445 ) L1M1_PR_MR ; - - storage_5_0.gclock ( storage_5_0.cg GCLK ) ( storage_5_0.bit7.bit CLK ) ( storage_5_0.bit6.bit CLK ) ( storage_5_0.bit5.bit CLK ) ( storage_5_0.bit4.bit CLK ) ( storage_5_0.bit3.bit CLK ) ( storage_5_0.bit2.bit CLK ) - ( storage_5_0.bit1.bit CLK ) ( storage_5_0.bit0.bit CLK ) + USE SIGNAL + - storage_5_0_0.gclock ( storage_5_0_0.cg GCLK ) ( storage_5_0_0.bit7.bit CLK ) ( storage_5_0_0.bit6.bit CLK ) ( storage_5_0_0.bit5.bit CLK ) ( storage_5_0_0.bit4.bit CLK ) ( storage_5_0_0.bit3.bit CLK ) ( storage_5_0_0.bit2.bit CLK ) + ( storage_5_0_0.bit1.bit CLK ) ( storage_5_0_0.bit0.bit CLK ) + USE SIGNAL + ROUTED met1 ( 1219 1411 ) ( * 1479 ) NEW met1 ( 69 1513 ) ( 851 * ) NEW met1 ( 851 1479 ) ( * 1513 ) @@ -2203,8 +2203,8 @@ NETS 152 ; NEW li1 ( 5819 1479 ) L1M1_PR_MR NEW li1 ( 8119 1513 ) L1M1_PR_MR NEW li1 ( 9867 1581 ) L1M1_PR_MR ; - - storage_5_0.select0_b ( storage_5_0.select_inv_0 Y ) ( storage_5_0.bit7.obuf0 TE_B ) ( storage_5_0.bit6.obuf0 TE_B ) ( storage_5_0.bit5.obuf0 TE_B ) ( storage_5_0.bit4.obuf0 TE_B ) ( storage_5_0.bit3.obuf0 TE_B ) ( storage_5_0.bit2.obuf0 TE_B ) - ( storage_5_0.bit1.obuf0 TE_B ) ( storage_5_0.bit0.obuf0 TE_B ) + USE SIGNAL + - storage_5_0_0.select0_b ( storage_5_0_0.select_inv_0 Y ) ( storage_5_0_0.bit7.obuf0 TE_B ) ( storage_5_0_0.bit6.obuf0 TE_B ) ( storage_5_0_0.bit5.obuf0 TE_B ) ( storage_5_0_0.bit4.obuf0 TE_B ) ( storage_5_0_0.bit3.obuf0 TE_B ) ( storage_5_0_0.bit2.obuf0 TE_B ) + ( storage_5_0_0.bit1.obuf0 TE_B ) ( storage_5_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + ROUTED met1 ( 6647 1513 ) ( 6923 * ) NEW met1 ( 6923 1513 ) ( * 1581 ) NEW met1 ( 6210 1513 ) ( 6647 * ) @@ -2233,55 +2233,55 @@ NETS 152 ; NEW li1 ( 7797 1479 ) L1M1_PR_MR NEW met1 ( 7797 1581 ) M1M2_PR NEW met1 ( 7797 1479 ) M1M2_PR ; - - storage_5_0.we0 ( storage_5_0.gcand X ) ( storage_5_0.cg GATE ) + USE SIGNAL + - storage_5_0_0.we0 ( storage_5_0_0.gcand X ) ( storage_5_0_0.cg GATE ) + USE SIGNAL + ROUTED met2 ( 9453 1411 ) ( * 1479 ) NEW met1 ( 9453 1411 ) ( 10097 * ) NEW li1 ( 9453 1479 ) L1M1_PR_MR NEW met1 ( 9453 1479 ) M1M2_PR NEW met1 ( 9453 1411 ) M1M2_PR NEW li1 ( 10097 1411 ) L1M1_PR_MR ; - - storage_6_0.bit0.storage ( storage_6_0.bit0.obuf0 A ) ( storage_6_0.bit0.bit Q ) + USE SIGNAL + - storage_6_0_0.bit0.storage ( storage_6_0_0.bit0.obuf0 A ) ( storage_6_0_0.bit0.bit Q ) + USE SIGNAL + ROUTED met1 ( 805 1785 ) ( * 1819 ) NEW met1 ( 759 1819 ) ( 805 * ) NEW li1 ( 805 1785 ) L1M1_PR_MR NEW li1 ( 759 1819 ) L1M1_PR_MR ; - - storage_6_0.bit1.storage ( storage_6_0.bit1.obuf0 A ) ( storage_6_0.bit1.bit Q ) + USE SIGNAL + - storage_6_0_0.bit1.storage ( storage_6_0_0.bit1.obuf0 A ) ( storage_6_0_0.bit1.bit Q ) + USE SIGNAL + ROUTED met1 ( 1955 1785 ) ( * 1819 ) NEW met1 ( 1909 1819 ) ( 1955 * ) NEW li1 ( 1955 1785 ) L1M1_PR_MR NEW li1 ( 1909 1819 ) L1M1_PR_MR ; - - storage_6_0.bit2.storage ( storage_6_0.bit2.obuf0 A ) ( storage_6_0.bit2.bit Q ) + USE SIGNAL + - storage_6_0_0.bit2.storage ( storage_6_0_0.bit2.obuf0 A ) ( storage_6_0_0.bit2.bit Q ) + USE SIGNAL + ROUTED met1 ( 3105 1785 ) ( * 1819 ) NEW met1 ( 3059 1819 ) ( 3105 * ) NEW li1 ( 3105 1785 ) L1M1_PR_MR NEW li1 ( 3059 1819 ) L1M1_PR_MR ; - - storage_6_0.bit3.storage ( storage_6_0.bit3.obuf0 A ) ( storage_6_0.bit3.bit Q ) + USE SIGNAL + - storage_6_0_0.bit3.storage ( storage_6_0_0.bit3.obuf0 A ) ( storage_6_0_0.bit3.bit Q ) + USE SIGNAL + ROUTED met1 ( 4255 1785 ) ( * 1819 ) NEW met1 ( 4209 1819 ) ( 4255 * ) NEW li1 ( 4255 1785 ) L1M1_PR_MR NEW li1 ( 4209 1819 ) L1M1_PR_MR ; - - storage_6_0.bit4.storage ( storage_6_0.bit4.obuf0 A ) ( storage_6_0.bit4.bit Q ) + USE SIGNAL + - storage_6_0_0.bit4.storage ( storage_6_0_0.bit4.obuf0 A ) ( storage_6_0_0.bit4.bit Q ) + USE SIGNAL + ROUTED met1 ( 5405 1785 ) ( * 1819 ) NEW met1 ( 5359 1819 ) ( 5405 * ) NEW li1 ( 5405 1785 ) L1M1_PR_MR NEW li1 ( 5359 1819 ) L1M1_PR_MR ; - - storage_6_0.bit5.storage ( storage_6_0.bit5.obuf0 A ) ( storage_6_0.bit5.bit Q ) + USE SIGNAL + - storage_6_0_0.bit5.storage ( storage_6_0_0.bit5.obuf0 A ) ( storage_6_0_0.bit5.bit Q ) + USE SIGNAL + ROUTED met1 ( 6555 1785 ) ( * 1819 ) NEW met1 ( 6509 1819 ) ( 6555 * ) NEW li1 ( 6555 1785 ) L1M1_PR_MR NEW li1 ( 6509 1819 ) L1M1_PR_MR ; - - storage_6_0.bit6.storage ( storage_6_0.bit6.obuf0 A ) ( storage_6_0.bit6.bit Q ) + USE SIGNAL + - storage_6_0_0.bit6.storage ( storage_6_0_0.bit6.obuf0 A ) ( storage_6_0_0.bit6.bit Q ) + USE SIGNAL + ROUTED met1 ( 7705 1785 ) ( * 1819 ) NEW met1 ( 7659 1819 ) ( 7705 * ) NEW li1 ( 7705 1785 ) L1M1_PR_MR NEW li1 ( 7659 1819 ) L1M1_PR_MR ; - - storage_6_0.bit7.storage ( storage_6_0.bit7.obuf0 A ) ( storage_6_0.bit7.bit Q ) + USE SIGNAL + - storage_6_0_0.bit7.storage ( storage_6_0_0.bit7.obuf0 A ) ( storage_6_0_0.bit7.bit Q ) + USE SIGNAL + ROUTED met1 ( 8855 1785 ) ( * 1819 ) NEW met1 ( 8809 1819 ) ( 8855 * ) NEW li1 ( 8855 1785 ) L1M1_PR_MR NEW li1 ( 8809 1819 ) L1M1_PR_MR ; - - storage_6_0.gclock ( storage_6_0.cg GCLK ) ( storage_6_0.bit7.bit CLK ) ( storage_6_0.bit6.bit CLK ) ( storage_6_0.bit5.bit CLK ) ( storage_6_0.bit4.bit CLK ) ( storage_6_0.bit3.bit CLK ) ( storage_6_0.bit2.bit CLK ) - ( storage_6_0.bit1.bit CLK ) ( storage_6_0.bit0.bit CLK ) + USE SIGNAL + - storage_6_0_0.gclock ( storage_6_0_0.cg GCLK ) ( storage_6_0_0.bit7.bit CLK ) ( storage_6_0_0.bit6.bit CLK ) ( storage_6_0_0.bit5.bit CLK ) ( storage_6_0_0.bit4.bit CLK ) ( storage_6_0_0.bit3.bit CLK ) ( storage_6_0_0.bit2.bit CLK ) + ( storage_6_0_0.bit1.bit CLK ) ( storage_6_0_0.bit0.bit CLK ) + USE SIGNAL + ROUTED met1 ( 1219 1683 ) ( * 1751 ) NEW met1 ( 69 1717 ) ( * 1751 ) NEW met1 ( 69 1717 ) ( 1219 * ) @@ -2322,8 +2322,8 @@ NETS 152 ; NEW met1 ( 2415 1683 ) M1M2_PR NEW li1 ( 8119 1751 ) L1M1_PR_MR NEW li1 ( 9867 1683 ) L1M1_PR_MR ; - - storage_6_0.select0_b ( storage_6_0.select_inv_0 Y ) ( storage_6_0.bit7.obuf0 TE_B ) ( storage_6_0.bit6.obuf0 TE_B ) ( storage_6_0.bit5.obuf0 TE_B ) ( storage_6_0.bit4.obuf0 TE_B ) ( storage_6_0.bit3.obuf0 TE_B ) ( storage_6_0.bit2.obuf0 TE_B ) - ( storage_6_0.bit1.obuf0 TE_B ) ( storage_6_0.bit0.obuf0 TE_B ) + USE SIGNAL + - storage_6_0_0.select0_b ( storage_6_0_0.select_inv_0 Y ) ( storage_6_0_0.bit7.obuf0 TE_B ) ( storage_6_0_0.bit6.obuf0 TE_B ) ( storage_6_0_0.bit5.obuf0 TE_B ) ( storage_6_0_0.bit4.obuf0 TE_B ) ( storage_6_0_0.bit3.obuf0 TE_B ) ( storage_6_0_0.bit2.obuf0 TE_B ) + ( storage_6_0_0.bit1.obuf0 TE_B ) ( storage_6_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + ROUTED met1 ( 1265 1751 ) ( * 1785 ) NEW met1 ( 897 1785 ) ( 1265 * ) NEW met1 ( 6647 1785 ) ( 6877 * ) @@ -2367,54 +2367,54 @@ NETS 152 ; NEW li1 ( 10189 1819 ) L1M1_PR_MR NEW li1 ( 7797 1785 ) L1M1_PR_MR NEW met1 ( 5497 1785 ) RECT ( -35 -7 0 7 ) ; - - storage_6_0.we0 ( storage_6_0.gcand X ) ( storage_6_0.cg GATE ) + USE SIGNAL + - storage_6_0_0.we0 ( storage_6_0_0.gcand X ) ( storage_6_0_0.cg GATE ) + USE SIGNAL + ROUTED met1 ( 9453 1785 ) ( 9821 * ) NEW met1 ( 9821 1717 ) ( * 1785 ) NEW met1 ( 9821 1717 ) ( 10097 * ) NEW li1 ( 9453 1785 ) L1M1_PR_MR NEW li1 ( 10097 1717 ) L1M1_PR_MR ; - - storage_7_0.bit0.storage ( storage_7_0.bit0.obuf0 A ) ( storage_7_0.bit0.bit Q ) + USE SIGNAL + - storage_7_0_0.bit0.storage ( storage_7_0_0.bit0.obuf0 A ) ( storage_7_0_0.bit0.bit Q ) + USE SIGNAL + ROUTED met1 ( 759 2023 ) ( 805 * ) NEW met1 ( 759 1989 ) ( * 2023 ) NEW li1 ( 805 2023 ) L1M1_PR_MR NEW li1 ( 759 1989 ) L1M1_PR_MR ; - - storage_7_0.bit1.storage ( storage_7_0.bit1.obuf0 A ) ( storage_7_0.bit1.bit Q ) + USE SIGNAL + - storage_7_0_0.bit1.storage ( storage_7_0_0.bit1.obuf0 A ) ( storage_7_0_0.bit1.bit Q ) + USE SIGNAL + ROUTED met1 ( 1909 2023 ) ( 1955 * ) NEW met1 ( 1909 1989 ) ( * 2023 ) NEW li1 ( 1955 2023 ) L1M1_PR_MR NEW li1 ( 1909 1989 ) L1M1_PR_MR ; - - storage_7_0.bit2.storage ( storage_7_0.bit2.obuf0 A ) ( storage_7_0.bit2.bit Q ) + USE SIGNAL + - storage_7_0_0.bit2.storage ( storage_7_0_0.bit2.obuf0 A ) ( storage_7_0_0.bit2.bit Q ) + USE SIGNAL + ROUTED met1 ( 3059 2023 ) ( 3105 * ) NEW met1 ( 3059 1989 ) ( * 2023 ) NEW li1 ( 3105 2023 ) L1M1_PR_MR NEW li1 ( 3059 1989 ) L1M1_PR_MR ; - - storage_7_0.bit3.storage ( storage_7_0.bit3.obuf0 A ) ( storage_7_0.bit3.bit Q ) + USE SIGNAL + - storage_7_0_0.bit3.storage ( storage_7_0_0.bit3.obuf0 A ) ( storage_7_0_0.bit3.bit Q ) + USE SIGNAL + ROUTED met1 ( 4209 2023 ) ( 4255 * ) NEW met1 ( 4209 1989 ) ( * 2023 ) NEW li1 ( 4255 2023 ) L1M1_PR_MR NEW li1 ( 4209 1989 ) L1M1_PR_MR ; - - storage_7_0.bit4.storage ( storage_7_0.bit4.obuf0 A ) ( storage_7_0.bit4.bit Q ) + USE SIGNAL + - storage_7_0_0.bit4.storage ( storage_7_0_0.bit4.obuf0 A ) ( storage_7_0_0.bit4.bit Q ) + USE SIGNAL + ROUTED met1 ( 5359 2023 ) ( 5405 * ) NEW met1 ( 5359 1989 ) ( * 2023 ) NEW li1 ( 5405 2023 ) L1M1_PR_MR NEW li1 ( 5359 1989 ) L1M1_PR_MR ; - - storage_7_0.bit5.storage ( storage_7_0.bit5.obuf0 A ) ( storage_7_0.bit5.bit Q ) + USE SIGNAL + - storage_7_0_0.bit5.storage ( storage_7_0_0.bit5.obuf0 A ) ( storage_7_0_0.bit5.bit Q ) + USE SIGNAL + ROUTED met1 ( 6509 2023 ) ( 6555 * ) NEW met1 ( 6509 1989 ) ( * 2023 ) NEW li1 ( 6555 2023 ) L1M1_PR_MR NEW li1 ( 6509 1989 ) L1M1_PR_MR ; - - storage_7_0.bit6.storage ( storage_7_0.bit6.obuf0 A ) ( storage_7_0.bit6.bit Q ) + USE SIGNAL + - storage_7_0_0.bit6.storage ( storage_7_0_0.bit6.obuf0 A ) ( storage_7_0_0.bit6.bit Q ) + USE SIGNAL + ROUTED met1 ( 7659 2023 ) ( 7705 * ) NEW met1 ( 7659 1989 ) ( * 2023 ) NEW li1 ( 7705 2023 ) L1M1_PR_MR NEW li1 ( 7659 1989 ) L1M1_PR_MR ; - - storage_7_0.bit7.storage ( storage_7_0.bit7.obuf0 A ) ( storage_7_0.bit7.bit Q ) + USE SIGNAL + - storage_7_0_0.bit7.storage ( storage_7_0_0.bit7.obuf0 A ) ( storage_7_0_0.bit7.bit Q ) + USE SIGNAL + ROUTED met1 ( 8809 2023 ) ( 8855 * ) NEW met1 ( 8809 1989 ) ( * 2023 ) NEW li1 ( 8855 2023 ) L1M1_PR_MR NEW li1 ( 8809 1989 ) L1M1_PR_MR ; - - storage_7_0.gclock ( storage_7_0.cg GCLK ) ( storage_7_0.bit7.bit CLK ) ( storage_7_0.bit6.bit CLK ) ( storage_7_0.bit5.bit CLK ) ( storage_7_0.bit4.bit CLK ) ( storage_7_0.bit3.bit CLK ) ( storage_7_0.bit2.bit CLK ) - ( storage_7_0.bit1.bit CLK ) ( storage_7_0.bit0.bit CLK ) + USE SIGNAL + - storage_7_0_0.gclock ( storage_7_0_0.cg GCLK ) ( storage_7_0_0.bit7.bit CLK ) ( storage_7_0_0.bit6.bit CLK ) ( storage_7_0_0.bit5.bit CLK ) ( storage_7_0_0.bit4.bit CLK ) ( storage_7_0_0.bit3.bit CLK ) ( storage_7_0_0.bit2.bit CLK ) + ( storage_7_0_0.bit1.bit CLK ) ( storage_7_0_0.bit0.bit CLK ) + USE SIGNAL + ROUTED met1 ( 1219 1955 ) ( * 2023 ) NEW met1 ( 69 1955 ) ( * 2023 ) NEW met1 ( 69 1955 ) ( 1219 * ) @@ -2440,8 +2440,8 @@ NETS 152 ; NEW li1 ( 5819 2023 ) L1M1_PR_MR NEW li1 ( 8119 2023 ) L1M1_PR_MR NEW li1 ( 9867 1955 ) L1M1_PR_MR ; - - storage_7_0.select0_b ( storage_7_0.select_inv_0 Y ) ( storage_7_0.bit7.obuf0 TE_B ) ( storage_7_0.bit6.obuf0 TE_B ) ( storage_7_0.bit5.obuf0 TE_B ) ( storage_7_0.bit4.obuf0 TE_B ) ( storage_7_0.bit3.obuf0 TE_B ) ( storage_7_0.bit2.obuf0 TE_B ) - ( storage_7_0.bit1.obuf0 TE_B ) ( storage_7_0.bit0.obuf0 TE_B ) + USE SIGNAL + - storage_7_0_0.select0_b ( storage_7_0_0.select_inv_0 Y ) ( storage_7_0_0.bit7.obuf0 TE_B ) ( storage_7_0_0.bit6.obuf0 TE_B ) ( storage_7_0_0.bit5.obuf0 TE_B ) ( storage_7_0_0.bit4.obuf0 TE_B ) ( storage_7_0_0.bit3.obuf0 TE_B ) ( storage_7_0_0.bit2.obuf0 TE_B ) + ( storage_7_0_0.bit1.obuf0 TE_B ) ( storage_7_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + ROUTED met1 ( 897 2057 ) ( * 2091 ) NEW met1 ( 6647 2057 ) ( * 2091 ) NEW met1 ( 6210 2057 ) ( 6647 * ) @@ -2470,12 +2470,12 @@ NETS 152 ; NEW li1 ( 8947 2023 ) L1M1_PR_MR NEW li1 ( 10189 1989 ) L1M1_PR_MR NEW li1 ( 7797 2057 ) L1M1_PR_MR ; - - storage_7_0.we0 ( storage_7_0.gcand X ) ( storage_7_0.cg GATE ) + USE SIGNAL + - storage_7_0_0.we0 ( storage_7_0_0.gcand X ) ( storage_7_0_0.cg GATE ) + USE SIGNAL + ROUTED met1 ( 9453 2125 ) ( 10097 * ) NEW li1 ( 9453 2125 ) L1M1_PR_MR NEW li1 ( 10097 2125 ) L1M1_PR_MR ; - - we[0] ( PIN we[0] ) ( storage_7_0.gcand B ) ( storage_6_0.gcand B ) ( storage_5_0.gcand B ) ( storage_4_0.gcand B ) ( storage_3_0.gcand B ) ( storage_2_0.gcand B ) - ( storage_1_0.gcand B ) ( storage_0_0.gcand B ) + USE SIGNAL + - we[0] ( PIN we[0] ) ( storage_7_0_0.gcand B ) ( storage_6_0_0.gcand B ) ( storage_5_0_0.gcand B ) ( storage_4_0_0.gcand B ) ( storage_3_0_0.gcand B ) ( storage_2_0_0.gcand B ) + ( storage_1_0_0.gcand B ) ( storage_0_0_0.gcand B ) + USE SIGNAL + ROUTED met1 ( 10005 391 ) ( 10097 * ) NEW met2 ( 10097 306 ) ( * 391 ) NEW met3 ( 10097 306 ) ( 10994 * 0 ) diff --git a/src/ram/test/make_8x8_sky130.lefok b/src/ram/test/make_8x8_sky130.lefok index f2cc5993d81..31b51310f11 100644 --- a/src/ram/test/make_8x8_sky130.lefok +++ b/src/ram/test/make_8x8_sky130.lefok @@ -25,36 +25,36 @@ MACRO RAM8x8 RECT 109.6 2.91 110.4 3.21 ; END END we[0] - PIN addr[0] + PIN addr_rw[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; RECT 109.6 4.27 110.4 4.57 ; END - END addr[0] - PIN addr[1] + END addr_rw[0] + PIN addr_rw[1] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; RECT 109.6 6.99 110.4 7.29 ; END - END addr[1] - PIN addr[2] + END addr_rw[1] + PIN addr_rw[2] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; RECT 109.6 5.63 110.4 5.93 ; END - END addr[2] + END addr_rw[2] PIN D[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 2 23.995 2.14 24.48 ; + RECT 1.08 23.995 1.22 24.48 ; END END D[0] PIN Q[0] @@ -254,11 +254,13 @@ MACRO RAM8x8 RECT 1.94 12.57 109.38 16.99 ; RECT 1.94 16.99 107.08 20.39 ; RECT 1.94 20.39 100.24 22.43 ; - RECT 1.94 22.43 24.28 23.11 ; + RECT 1.02 22.79 1.28 23.11 ; + RECT 11.2 22.43 24.28 23.11 ; RECT 34.2 22.43 47.28 23.11 ; RECT 57.2 22.43 70.28 23.11 ; RECT 79.76 22.43 81.32 23.11 ; - RECT 2 23.11 24.22 24.14 ; + RECT 1.08 23.11 1.22 24.14 ; + RECT 11.2 23.11 24.22 24.14 ; RECT 34.2 23.11 47.22 24.14 ; RECT 57.2 23.11 70.22 24.14 ; RECT 79.76 23.11 81.26 24.14 ; diff --git a/src/ram/test/make_8x8_sky130.ok b/src/ram/test/make_8x8_sky130.ok index 80acfa17f6f..324f7704a65 100644 --- a/src/ram/test/make_8x8_sky130.ok +++ b/src/ram/test/make_8x8_sky130.ok @@ -2,20 +2,28 @@ [INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells [INFO RAM-0003] Generating RAM8x8 [INFO RAM-0016] Selected inverter cell sky130_fd_sc_hd__clkinv_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__clkinv_1: Y [INFO RAM-0016] Selected tristate cell sky130_fd_sc_hd__ebufn_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__ebufn_1: Z [INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__and2_0: X +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__dfxtp_1: Q [INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__dlclkp_1: GCLK [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 +[INFO RAM-0030] buildPortMap DataOut for sky130_fd_sc_hd__buf_1: X +[INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-110.40u at the TOP edge. -[INFO PPL-0001] Number of available slots 258 +[INFO PPL-0067] Restrict pins [ clk we[0] addr_rw[0] addr_rw[1] addr_rw[2] ... ] to region 0.00u-24.48u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 270 [INFO PPL-0002] Number of I/O 21 [INFO PPL-0003] Number of I/O w/sink 21 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 331.91 um. +[INFO PPL-0012] I/O nets HPWL: 330.99 um. [INFO DPL-0001] Placed 48 filler instances. [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon diff --git a/src/ram/test/regression_tests.tcl b/src/ram/test/regression_tests.tcl index 3a5ac9bd078..3793dda99a2 100644 --- a/src/ram/test/regression_tests.tcl +++ b/src/ram/test/regression_tests.tcl @@ -1,4 +1,6 @@ record_tests { make_8x8_sky130 make_7x7_nangate45 + make_8x8_mux2_sky130 + make_8x8_mux4_sky130 }