Fix err output during the transition to start

Author: TimRudy

Uart8Receiver.v

@@ -107,7 +107,12 @@ always @(posedge clk) begin
             // outputs
             busy           <= 1'b0;
             done           <= 1'b0;
-            err            <= 1'b0;
+            if (en && err && !in_sample) begin // in error condition already -
+                // leave the output uninterrupted
+                err        <= 1'b1;
+            end else begin
+                err        <= 1'b0;
+            end
             out            <= 8'b0; // output parallel data only during {done}
             // next state
             if (en) begin

tests/30.gtkw

@@ -0,0 +1,55 @@
+[*]
+[*] GTKWave Analyzer v3.3.81 (w)1999-2017 BSI
+[*] Sun Jan 01 23:26:14 2023
+[*]
+[dumpfile] "30.vcd"
+[dumpfile_mtime] "Sun Jan 01 23:25:38 2023"
+[dumpfile_size] 873907
+[savefile] "30.gtkw"
+[timestart] 704900
+[size] 1536 937
+[pos] -9 -9
+*-16.818604 1054500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] test.
+[treeopen] test.uart.
+[sst_width] 197
+[signals_width] 290
+[sst_expanded] 1
+[sst_vpaned_height] 444
+@28
+test.txByte_1[7:0]
+test.rx
+test.uart.rxInst.clk
+test.uart.rxInst.en
+test.uart.rxInst.busy
+test.uart.rxInst.done
+test.uart.rxInst.err
+test.uart.rxInst.in_sample
+@c00022
+test.uart.rxInst.in_prior_hold_reg[3:0]
+@28
+(0)test.uart.rxInst.in_prior_hold_reg[3:0]
+(1)test.uart.rxInst.in_prior_hold_reg[3:0]
+(2)test.uart.rxInst.in_prior_hold_reg[3:0]
+(3)test.uart.rxInst.in_prior_hold_reg[3:0]
+@1401200
+-group_end
+@c00022
+test.uart.rxInst.in_current_hold_reg[3:0]
+@28
+(0)test.uart.rxInst.in_current_hold_reg[3:0]
+(1)test.uart.rxInst.in_current_hold_reg[3:0]
+(2)test.uart.rxInst.in_current_hold_reg[3:0]
+(3)test.uart.rxInst.in_current_hold_reg[3:0]
+@1401200
+-group_end
+@22
+test.uart.rxInst.sample_count[3:0]
+test.uart.rxInst.out_hold_count[4:0]
+@28
+test.uart.rxInst.state[2:0]
+test.uart.rxInst.bit_index[2:0]
+test.uart.rxInst.received_data[7:0]
+test.uart.rxInst.out[7:0]
+[pattern_trace] 1
+[pattern_trace] 0

tests/30.v

@@ -0,0 +1,115 @@
+`timescale 100ns/1ns
+`default_nettype none
+
+`include "Uart8.v"
+
+module test;
+
+localparam CLOCK_FREQ = 12000000; // Alhambra board
+localparam SIM_STEP_FREQ = 1 / 0.0000001 / 2; // this sim timescale 100ns
+
+// for the simulation timeline:
+// ratio SIM_STEP_FREQ MHz / CLOCK_FREQ MHz gives the output waveform in proper time
+// (*but note all clocks and the timeline are approximate due to rounding)
+localparam SIM_TIMESTEP_FACTOR = SIM_STEP_FREQ / CLOCK_FREQ;
+
+reg        clk;
+reg        en_1;
+reg        rx;
+wire       rxBusy_2;
+wire       rxDone_2;
+wire       rxErr_2;
+reg [7:0]  txByte_1;
+wire [7:0] rxByte_2;
+
+Uart8 #(.CLOCK_RATE(CLOCK_FREQ)) uart(
+  .clk(clk),
+
+  // rx interface
+  .rxEn(en_1),
+  .rx(rx),
+  .rxBusy(rxBusy_2),
+  .rxDone(rxDone_2),
+  .rxErr(rxErr_2),
+  .out(rxByte_2)
+
+  // tx interface (unused)
+);
+
+initial clk = 1'b0;
+
+always #SIM_TIMESTEP_FACTOR clk = ~clk;
+
+initial begin
+  $dumpfile(`DUMP_FILE_NAME);
+  $dumpvars(0, test);
+
+// #65 == 1 rx clock period (approximately) at 9600 baud
+#240
+  en_1 = 1'b1;
+  txByte_1 = 8'b11010110;
+  rx = 1'b0;
+
+  $display("            tx data: %8b", txByte_1);
+#160
+  rx = 1'b1;
+#360
+  rx = 1'b0;
+#1075 // instead of #1042, this makes transmit clock sync with receive clock (a 3% difference)
+  rx = txByte_1[0];
+
+  $display("%7.2fms | rx first bit: %1b", $realtime/10000, rx);
+#1075
+  rx = txByte_1[1];
+
+  $display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
+#1075
+  rx = txByte_1[2];
+
+  $display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
+#1075
+  rx = txByte_1[3];
+
+  $display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
+#1075
+  rx = txByte_1[4];
+
+  $display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
+#1075
+  rx = txByte_1[5];
+
+  $display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
+#1075
+  rx = txByte_1[6];
+
+  $display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
+#1075
+  rx = txByte_1[7];
+
+  $display("%7.2fms | rx last bit: %1b", $realtime/10000, rx);
+#530
+  rx = 1'b1;
+#530
+  rx = 1'b0;
+
+  $display("%7.4fms | end of stop bit | start of start bit: %1b", $realtime/10000, rx);
+#530
+  rx = 1'b1;
+
+  $display("%7.4fms | rx start bit glitch: %1b", $realtime/10000, rx);
+#545
+  rx = txByte_1[0];
+
+  $display("%7.2fms | rx first bit: %1b", $realtime/10000, rx);
+#1075
+  rx = txByte_1[1];
+
+  $display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
+#1075
+  rx = txByte_1[2];
+#1120
+
+  $finish();
+end
+
+endmodule

tests/Key.txt

@@ -27,3 +27,4 @@
 27. One frame, and next xaction starts during the READY state: success
 28: One frame, next xaction does not start in READY state, goes to RESET state: fail to start second xaction because rx stop signal too long (*shows err)
 29. Error at beginning of next xaction due to rx start signal not long enough to meet its extra hold requirement: success accepting previous xaction (*shows done, shows err)
+30. Error at end of xaction held over to beginning of next xaction: fail to accept, fail to start (*shows err sustained high, no glitch low-high)