Upstream update available: litedram
| Field |
Value |
| Pinned |
744b143f (2026-05-11) |
| Upstream |
c7bcb5dc (2026-05-18) |
| Commits behind |
2 |
| Days stale |
7 |
Severity: moderate
Justification: Range includes two RTL changes — frontend: coalesce narrow Wishbone bursts (+203 lines in litedram/frontend/wishbone.py with new test coverage) and phy/gw5ddrphy: Align control latencies with GW2 DDR PHY (a small PHY-latency tweak, +4/-4). The Wishbone coalescing is a meaningful frontend feature; the PHY change targets Gowin GW5 (not used by HighTide). Both are RTL-relevant for the LiteX-Python-generated litedram_core.v used by HighTide's 3 litedram variants.
What changed (highlights)
916b8b6 — frontend: coalesce narrow Wishbone bursts. New coalescing logic on the Wishbone frontend (litedram/frontend/wishbone.py +203, test/test_wishbone.py +101).c7bcb5d — phy/gw5ddrphy: Align control latencies with GW2 DDR PHY. Small Gowin GW5 PHY-latency alignment (only relevant if targeting GW5).
Recommendation
Update opportunistically — small enough to bump in isolation. Re-baseline timing/area on all 3 litedram platforms; verify our litedram_core.v sdram_dq inout patch (LiteX GENSDRPHY workaround) still applies cleanly after the bump. The Wishbone coalescing may shift the SDR DRAM controller's QoR.
Last refreshed: 2026-05-25T10:34Z
Upstream update available: litedram
744b143f(2026-05-11)c7bcb5dc(2026-05-18)Severity: moderate
Justification: Range includes two RTL changes —
frontend: coalesce narrow Wishbone bursts(+203 lines inlitedram/frontend/wishbone.pywith new test coverage) andphy/gw5ddrphy: Align control latencies with GW2 DDR PHY(a small PHY-latency tweak, +4/-4). The Wishbone coalescing is a meaningful frontend feature; the PHY change targets Gowin GW5 (not used by HighTide). Both are RTL-relevant for the LiteX-Python-generatedlitedram_core.vused by HighTide's 3 litedram variants.What changed (highlights)
916b8b6—frontend: coalesce narrow Wishbone bursts. New coalescing logic on the Wishbone frontend (litedram/frontend/wishbone.py+203,test/test_wishbone.py+101).c7bcb5d—phy/gw5ddrphy: Align control latencies with GW2 DDR PHY. Small Gowin GW5 PHY-latency alignment (only relevant if targeting GW5).Recommendation
Update opportunistically — small enough to bump in isolation. Re-baseline timing/area on all 3 litedram platforms; verify our
litedram_core.vsdram_dqinoutpatch (LiteX GENSDRPHY workaround) still applies cleanly after the bump. The Wishbone coalescing may shift the SDR DRAM controller's QoR.Last refreshed: 2026-05-25T10:34Z