Upstream update available: litepci
| Field |
Value |
| Pinned |
95f47311 (2026-05-11) |
| Upstream |
c1b2d8c0 (2026-05-22) |
| Commits behind |
12 |
| Days stale |
11 |
Severity: moderate
Justification: Range is dominated by test infrastructure cleanup (6 commits — slow-test split, opt-in VCD, trim workloads, temp-output metadata, LiteX-style alignment, isolated example builds) plus 4 software/kernel changes (liteuart RX/TX polling, DMA mmap fix on coherent buffers, shared DMA device fd, PCIe rescan utility). The RTL-affecting commits are tlp/packetizer: keep 128-bit 4DW payload in DATA (datapath change) and its follow-up coverage test: cover continuous 128-bit 4DW payload handoff. The packetizer change directly touches the TLP datapath.
What changed (highlights)
00e5bcf — tlp/packetizer: keep 128-bit 4DW payload in DATA (RTL packetizer datapath, litepcie/tlp/packetizer.py +36/-42).c1b2d8c — test: cover continuous 128-bit 4DW payload handoff (test/test_header_inserter.py +116, tip commit).b5c8f01 — software/user: support shared DMA device fd.43a21eb — software: add PCIe rescan utility (litepcie/software/rescan.py new file, +153).e5f4760 — software/kernel/liteuart: improve RX/TX polling robustness (+94/-57).c52a6fe — software/kernel: fix DMA mmap of coherent buffers.9d332cd — test: split slow tests from default CI.37c4b12 — test: make simulation VCD dumps opt-in.4653b9a — test: trim high-level simulation workloads.3a13f28 — test: isolate example build outputs.b08c6b5 — test: align test style with LiteX conventions.a3cae57 — test: keep generated metadata in temp outputs.
Recommendation
Update opportunistically — the packetizer change is small but RTL-relevant; bump it together with the rest of the LiteX-family submodules (liteeth / litedram) at the next refresh window. Re-baseline timing/area on litepci after the bump. Kernel/userspace changes don't affect synthesis.
Last refreshed: 2026-05-25T10:34Z
Upstream update available: litepci
95f47311(2026-05-11)c1b2d8c0(2026-05-22)Severity: moderate
Justification: Range is dominated by test infrastructure cleanup (6 commits — slow-test split, opt-in VCD, trim workloads, temp-output metadata, LiteX-style alignment, isolated example builds) plus 4 software/kernel changes (liteuart RX/TX polling, DMA mmap fix on coherent buffers, shared DMA device fd, PCIe rescan utility). The RTL-affecting commits are
tlp/packetizer: keep 128-bit 4DW payload in DATA(datapath change) and its follow-up coveragetest: cover continuous 128-bit 4DW payload handoff. The packetizer change directly touches the TLP datapath.What changed (highlights)
00e5bcf—tlp/packetizer: keep 128-bit 4DW payload in DATA(RTL packetizer datapath,litepcie/tlp/packetizer.py+36/-42).c1b2d8c—test: cover continuous 128-bit 4DW payload handoff(test/test_header_inserter.py+116, tip commit).b5c8f01—software/user: support shared DMA device fd.43a21eb—software: add PCIe rescan utility(litepcie/software/rescan.pynew file, +153).e5f4760—software/kernel/liteuart: improve RX/TX polling robustness(+94/-57).c52a6fe—software/kernel: fix DMA mmap of coherent buffers.9d332cd—test: split slow tests from default CI.37c4b12—test: make simulation VCD dumps opt-in.4653b9a—test: trim high-level simulation workloads.3a13f28—test: isolate example build outputs.b08c6b5—test: align test style with LiteX conventions.a3cae57—test: keep generated metadata in temp outputs.Recommendation
Update opportunistically — the packetizer change is small but RTL-relevant; bump it together with the rest of the LiteX-family submodules (liteeth / litedram) at the next refresh window. Re-baseline timing/area on litepci after the bump. Kernel/userspace changes don't affect synthesis.
Last refreshed: 2026-05-25T10:34Z