From 3734d9c9f55882837c1a2ee60f1163088fdec7fe Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Tue, 5 May 2026 16:24:26 +0530 Subject: [PATCH 01/12] arch/tricore: drop iLLD SDK and the legacy per-chip directories The iLLD path requires an external SDK download at build time. An upstream tree cannot depend on a build-time network fetch, and the requirement also prevents any offline build. The chip-per-name directories under arch/tricore/src and boards/tricore were built around that iLLD path. Removing them together with the SDK lets the following commits introduce a family-based layout against a clean slate. Co-Authored-By: Saravanan Sekar Signed-off-by: Parthiban Nallathambi --- Documentation/platforms/tricore/index.rst | 73 +- .../tc397/boards/kit_a2g_tc397_tft/index.rst | 61 - .../platforms/tricore/tc397/index.rst | 23 - .../tc4d9/boards/triboard_tc4x9_com/index.rst | 55 - .../platforms/tricore/tc4d9/index.rst | 23 - arch/tricore/Kconfig | 107 -- arch/tricore/include/setjmp.h | 81 -- arch/tricore/include/tc397/chip.h | 48 - arch/tricore/include/tc397/irq.h | 71 - arch/tricore/include/tc4da/chip.h | 48 - arch/tricore/include/tc4da/irq.h | 71 - arch/tricore/src/cmake/chip.cmake | 23 +- arch/tricore/src/common/CMakeLists.txt | 21 +- arch/tricore/src/common/Ifx_Cfg_Trap.h | 63 - arch/tricore/src/common/Make.defs | 21 +- arch/tricore/src/common/tricore_cache.c | 524 ------- arch/tricore/src/common/tricore_fpu.c | 70 - arch/tricore/src/common/tricore_hwdebug.c | 412 ------ arch/tricore/src/common/tricore_main.c | 124 -- arch/tricore/src/common/tricore_mpu.c | 1244 ----------------- arch/tricore/src/common/tricore_mpu.h | 382 ----- arch/tricore/src/common/tricore_perf.c | 72 - arch/tricore/src/common/tricore_systimer.c | 328 ----- .../src/illd/tc3xx/Configurations/Ifx_Cfg.h | 68 - .../illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c | 65 - .../illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h | 111 -- .../src/illd/tc3xx/patches/change_illd.patch | 60 - .../src/illd/tc4xx/Configurations/Ifx_Cfg.h | 79 -- .../illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c | 211 --- .../illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h | 81 -- .../patches/add_coprocessor_trap_id.patch | 11 - .../src/illd/tc4xx/patches/change_illd.patch | 33 - arch/tricore/src/tc397/.gitignore | 3 - arch/tricore/src/tc397/CMakeLists.txt | 21 - arch/tricore/src/tc397/Kconfig | 5 - arch/tricore/src/tc397/Make.defs | 21 - arch/tricore/src/tc397/chip.h | 33 - arch/tricore/src/tc3xx/.gitignore | 3 - arch/tricore/src/tc3xx/CMakeLists.txt | 140 -- arch/tricore/src/tc3xx/Kconfig | 18 - arch/tricore/src/tc3xx/Make.defs | 122 -- arch/tricore/src/tc3xx/tc3xx_dummy.c | 29 - arch/tricore/src/tc3xx/tc3xx_libc.c | 86 -- arch/tricore/src/tc3xx/tc3xx_serial.c | 732 ---------- arch/tricore/src/tc3xx/tc3xx_timerisr.c | 61 - arch/tricore/src/tc4da/CMakeLists.txt | 21 - arch/tricore/src/tc4da/Kconfig | 5 - arch/tricore/src/tc4da/Make.defs | 21 - arch/tricore/src/tc4da/chip.h | 33 - arch/tricore/src/tc4xx/CMakeLists.txt | 171 --- arch/tricore/src/tc4xx/Kconfig | 18 - arch/tricore/src/tc4xx/Make.defs | 157 --- arch/tricore/src/tc4xx/tc4xx_dummy.c | 29 - arch/tricore/src/tc4xx/tc4xx_libc.c | 86 -- arch/tricore/src/tc4xx/tc4xx_serial.c | 732 ---------- arch/tricore/src/tc4xx/tc4xx_timerisr.c | 61 - boards/Kconfig | 19 - .../tc397/a2g-tc397-5v-tft/CMakeLists.txt | 23 - boards/tricore/tc397/a2g-tc397-5v-tft/Kconfig | 7 - .../a2g-tc397-5v-tft/configs/nsh/defconfig | 57 - .../tc397/a2g-tc397-5v-tft/include/board.h | 40 - .../include/board_memorymap.h | 366 ----- .../scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel | 554 -------- .../scripts/Lcf_Gnuc_Tricore_Tc.lsl.user | 264 ---- .../scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel | 633 --------- .../scripts/Lcf_Tasking_Tricore_Tc.lsl.user | 189 --- .../tc397/a2g-tc397-5v-tft/scripts/Make.defs | 44 - .../tc397/a2g-tc397-5v-tft/src/CMakeLists.txt | 42 - .../tc397/a2g-tc397-5v-tft/src/Makefile | 27 - .../tc397/a2g-tc397-5v-tft/src/tc397.h | 65 - .../a2g-tc397-5v-tft/src/tc397_boardinit.c | 119 -- .../a2g-tc397-5v-tft/src/tc397_bringup.c | 75 - .../tc4da/triboard_tc4x9_com/CMakeLists.txt | 23 - .../tricore/tc4da/triboard_tc4x9_com/Kconfig | 7 - .../triboard_tc4x9_com/configs/nsh/defconfig | 57 - .../tc4da/triboard_tc4x9_com/include/board.h | 40 - .../include/board_memorymap.h | 457 ------ .../scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel | 590 -------- .../scripts/Lcf_Gnuc_Tricore_Tc.lsl.user | 264 ---- .../scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel | 639 --------- .../scripts/Lcf_Tasking_Tricore_Tc.lsl.user | 204 --- .../triboard_tc4x9_com/scripts/Make.defs | 44 - .../triboard_tc4x9_com/src/CMakeLists.txt | 42 - .../tc4da/triboard_tc4x9_com/src/Makefile | 27 - .../tc4da/triboard_tc4x9_com/src/tc4da.h | 65 - .../triboard_tc4x9_com/src/tc4da_boardinit.c | 121 -- .../triboard_tc4x9_com/src/tc4da_bringup.c | 75 - 87 files changed, 44 insertions(+), 12407 deletions(-) delete mode 100644 Documentation/platforms/tricore/tc397/boards/kit_a2g_tc397_tft/index.rst delete mode 100644 Documentation/platforms/tricore/tc397/index.rst delete mode 100644 Documentation/platforms/tricore/tc4d9/boards/triboard_tc4x9_com/index.rst delete mode 100644 Documentation/platforms/tricore/tc4d9/index.rst delete mode 100644 arch/tricore/include/setjmp.h delete mode 100644 arch/tricore/include/tc397/chip.h delete mode 100644 arch/tricore/include/tc397/irq.h delete mode 100644 arch/tricore/include/tc4da/chip.h delete mode 100644 arch/tricore/include/tc4da/irq.h delete mode 100644 arch/tricore/src/common/Ifx_Cfg_Trap.h delete mode 100644 arch/tricore/src/common/tricore_cache.c delete mode 100644 arch/tricore/src/common/tricore_fpu.c delete mode 100644 arch/tricore/src/common/tricore_hwdebug.c delete mode 100644 arch/tricore/src/common/tricore_main.c delete mode 100644 arch/tricore/src/common/tricore_mpu.c delete mode 100644 arch/tricore/src/common/tricore_mpu.h delete mode 100644 arch/tricore/src/common/tricore_perf.c delete mode 100644 arch/tricore/src/common/tricore_systimer.c delete mode 100644 arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h delete mode 100644 arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c delete mode 100644 arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h delete mode 100644 arch/tricore/src/illd/tc3xx/patches/change_illd.patch delete mode 100644 arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h delete mode 100644 arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c delete mode 100644 arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h delete mode 100644 arch/tricore/src/illd/tc4xx/patches/add_coprocessor_trap_id.patch delete mode 100644 arch/tricore/src/illd/tc4xx/patches/change_illd.patch delete mode 100644 arch/tricore/src/tc397/.gitignore delete mode 100644 arch/tricore/src/tc397/CMakeLists.txt delete mode 100644 arch/tricore/src/tc397/Kconfig delete mode 100644 arch/tricore/src/tc397/Make.defs delete mode 100644 arch/tricore/src/tc397/chip.h delete mode 100644 arch/tricore/src/tc3xx/.gitignore delete mode 100644 arch/tricore/src/tc3xx/Kconfig delete mode 100644 arch/tricore/src/tc3xx/tc3xx_dummy.c delete mode 100644 arch/tricore/src/tc3xx/tc3xx_libc.c delete mode 100644 arch/tricore/src/tc3xx/tc3xx_serial.c delete mode 100644 arch/tricore/src/tc3xx/tc3xx_timerisr.c delete mode 100644 arch/tricore/src/tc4da/CMakeLists.txt delete mode 100644 arch/tricore/src/tc4da/Kconfig delete mode 100644 arch/tricore/src/tc4da/Make.defs delete mode 100644 arch/tricore/src/tc4da/chip.h delete mode 100644 arch/tricore/src/tc4xx/Kconfig delete mode 100644 arch/tricore/src/tc4xx/tc4xx_dummy.c delete mode 100644 arch/tricore/src/tc4xx/tc4xx_libc.c delete mode 100644 arch/tricore/src/tc4xx/tc4xx_serial.c delete mode 100644 arch/tricore/src/tc4xx/tc4xx_timerisr.c delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/CMakeLists.txt delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/Kconfig delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/configs/nsh/defconfig delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/include/board.h delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/src/Makefile delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397.h delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_boardinit.c delete mode 100644 boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_bringup.c delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/Kconfig delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/configs/nsh/defconfig delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/include/board.h delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/include/board_memorymap.h delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/scripts/Make.defs delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/src/CMakeLists.txt delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/src/Makefile delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da.h delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_boardinit.c delete mode 100644 boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_bringup.c diff --git a/Documentation/platforms/tricore/index.rst b/Documentation/platforms/tricore/index.rst index ad2ea204337b5..3f677acaf4bcb 100644 --- a/Documentation/platforms/tricore/index.rst +++ b/Documentation/platforms/tricore/index.rst @@ -2,40 +2,49 @@ TriCore ======= -All TriCore source reside in lower-level common, chip-specific, and architecture-specific -directories. - -arch/tricore/src/common/ Directory -================================== - -This directory holds source files common to all TriCore architectures. - -Architecture-Specific Directories -================================= - -Architecture-specific directories hold common source files shared for by -implementations of specific TriCore architectures. - -``TriCore`` - This directory holds logic appropriate for any instantiation of the 32-bit - TriCore architecture. - -Chip-Specific directories -========================= - -For SoC chips, in particular, on-chip devices and differing interrupt -structures may require special, chip-specific definitions in these chip- -specific directories. - -The core Chip implementation is based on Infineon Low Level Drivers (iLLDs). -The unified API is more friendly to developers familiar with Infineon SDK/HAL. -We can get more code examples on Infineon's official Github: `AURIX_code_examples `__ - -``TC3xx/TC4xx`` - This is the implementation of NuttX on the Infineon’s AURIX™- TC3xx/TC4xx microcontroller family. +NuttX runs on Infineon AURIX TriCore microcontrollers in flat 32-bit address +mode. The port is implemented entirely with direct SFR access; there is no +dependency on Infineon's iLLD SDK, low-level startup is provided by NuttX. + +The port covers two AURIX SoC families: + +================ ================ ===================== + Family TriCore ISA ARCH_FAMILY +================ ================ ===================== + TC3X (TC1.6.2) TC162 ``tc1v6`` + TC4X (TC1.8) TC18 ``tc1v8`` +================ ================ ===================== + +Common features: + +- Runs in Supervisor Mode on CPU0. +- IRQs routed by the Interrupt Router (IR), per-Service-Request-Node SRC + registers; SRPN equals the IRQ number. +- System Timer (STM) drives the NuttX systick (oneshot lower-half). +- ASCLIN-based UART for the NSH console. +- GPIO pinmuxing for both families through a shared aurix layer. +- HighTec LLVM 10.2.0 (clang -target tricore) and tricore-elf-gcc 11.3.1 + toolchains are both supported. + +Source layout +============= + +:: + + arch/tricore/ + include/{tc3x,tc4x}/ chip-public headers + src/ + common/ core arch (boot, traps, IRQs, scheduling) + aurix/ shared peripherals (ASCLIN UART, GPIO) + tc3x/ TC3X-specific (clock tree, ENDINIT, GPIO) + tc4x/ TC4X-specific (clock tree, GPIO) + +Supported boards +================ .. toctree:: :maxdepth: 1 :glob: - */* + tc3x/* + tc4x/* diff --git a/Documentation/platforms/tricore/tc397/boards/kit_a2g_tc397_tft/index.rst b/Documentation/platforms/tricore/tc397/boards/kit_a2g_tc397_tft/index.rst deleted file mode 100644 index 2029a9e28efb6..0000000000000 --- a/Documentation/platforms/tricore/tc397/boards/kit_a2g_tc397_tft/index.rst +++ /dev/null @@ -1,61 +0,0 @@ -================= -A2G_TC397_5V_TFT -================= - -This page file describes the contents of the build configurations available -for the NuttX TriCore port. - -Infineon’s AURIX™- TC3xx `A2G_TC397_5V_TFT `__ Board -===================================================================================================================================== - -This port should work on A2G_TC397_5V_TFT with a proper CPU. -The mandatory CPU features are: - -* System Timer (STM) -* Asynchronous Serial Interface(ASCLIN) UART -* IRQs are managed by Interrupt Router(INT), IR Service Request Control Registers(SRC). - -Toolchains -========== - -Currently, only the Infineon’s AURIX™ Tasking toolchain is tested. - -Configurations -============== - -Common Configuration Notes --------------------------- - -1. Each A2G_TC397_5V_TFT configuration is maintained in a sub-directory - and can be selected as follow:: - - tools/configure.sh a2g-tc397-5v-tft: - - Where ```` is one of the configuration sub-directories described in - the following paragraph. - - NuttX Shell:: - - tools/configure.sh a2g-tc397-5v-tft:nsh - -2. These configurations use the mconf-based configuration tool. To - change a configurations using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute ``make menuconfig`` in nuttx/ in order to start the - reconfiguration process. - -3. By default, all configurations assume the Linux. This is easily - reconfigured:: - - CONFIG_HOST_LINUX=y - -Configuration Sub-Directories ------------------------------ - -ostest ------- - -The "standard" NuttX examples/ostest configuration. diff --git a/Documentation/platforms/tricore/tc397/index.rst b/Documentation/platforms/tricore/tc397/index.rst deleted file mode 100644 index 840228bb58e4e..0000000000000 --- a/Documentation/platforms/tricore/tc397/index.rst +++ /dev/null @@ -1,23 +0,0 @@ -============= -TriCore/TC397 -============= - -**TriCore/TC397** An TriCore flat address port was ported in NuttX-12.0. It -consists of the following features: - -- Runs in Supervisor Mode. -- IRQs are managed by Interrupt Router (INT), IR Service Request Control Registers (SRC). -- Used System timer (STM) for systick. - -This kernel with ostest have been tested with - -- Infineon's AURIX™ TC397 Evaluation Board: KIT_A2G_TC397_5V_TFT - -Supported Boards -================ - -.. toctree:: - :glob: - :maxdepth: 1 - - boards/*/* diff --git a/Documentation/platforms/tricore/tc4d9/boards/triboard_tc4x9_com/index.rst b/Documentation/platforms/tricore/tc4d9/boards/triboard_tc4x9_com/index.rst deleted file mode 100644 index c3b391fc564fe..0000000000000 --- a/Documentation/platforms/tricore/tc4d9/boards/triboard_tc4x9_com/index.rst +++ /dev/null @@ -1,55 +0,0 @@ -================== -TRIBOARD_TC4X9_COM -================== - -This port should work on TRIBOARD_TC4X9_COM with a proper CPU. -The mandatory CPU features are: - -* System Timer (STM) -* Asynchronous Serial Interface(ASCLIN) UART -* IRQs are managed by Interrupt Router(INT), IR Service Request Control Registers(SRC). - -Toolchains -========== - -Currently, only the Infineon’s AURIX™ GCC toolchain is tested. - -Configurations -============== - -Common Configuration Notes --------------------------- - -1. Each TRIBOARD_TC4X9_COM configuration is maintained in a sub-directory - and can be selected as follow:: - - tools/configure.sh triboard_tc4x9_com: - - Where ```` is one of the configuration sub-directories described in - the following paragraph. - - NuttX Shell:: - - tools/configure.sh triboard_tc4x9_com:nsh - -2. These configurations use the mconf-based configuration tool. To - change a configurations using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute ``make menuconfig`` in nuttx/ in order to start the - reconfiguration process. - -3. By default, all configurations assume the Linux. This is easily - reconfigured:: - - CONFIG_HOST_LINUX=y - -Configuration Sub-Directories ------------------------------ - -ostest ------- - -The "standard" NuttX examples/ostest configuration. diff --git a/Documentation/platforms/tricore/tc4d9/index.rst b/Documentation/platforms/tricore/tc4d9/index.rst deleted file mode 100644 index a5a70d757b39b..0000000000000 --- a/Documentation/platforms/tricore/tc4d9/index.rst +++ /dev/null @@ -1,23 +0,0 @@ -============= -TriCore/TC4DA -============= - -**TriCore/TC4DA** An TriCore flat address port was ported in NuttX-12.0. It -consists of the following features: - -- Runs in Supervisor Mode. -- IRQs are managed by Interrupt Router (INT), IR Service Request Control Registers (SRC). -- Used System timer (STM) for systick. - -This kernel with ostest have been tested with - -- Infineon's AURIX™ TC4DA Evaluation Board: TRIBOARD_TC4X9_COM - -Supported Boards -================ - -.. toctree:: - :glob: - :maxdepth: 1 - - boards/*/* diff --git a/arch/tricore/Kconfig b/arch/tricore/Kconfig index 0974cc18fe38c..a9beb4f81bfb3 100644 --- a/arch/tricore/Kconfig +++ b/arch/tricore/Kconfig @@ -6,26 +6,8 @@ if ARCH_TRICORE comment "Tricore Options" -choice - prompt "Tricore Toolchain Selection" - default TRICORE_TOOLCHAIN_GNU - -config TRICORE_TOOLCHAIN_TASKING - bool "AURIX Tasking C/C++ toolchain" - select ARCH_TOOLCHAIN_TASKING - -config TRICORE_TOOLCHAIN_GNU - bool "Generic GNU toolchain" - select ARCH_TOOLCHAIN_GNU - ---help--- - This option should work for any modern GNU toolchain (GCC 4.5 or newer) - -endchoice # Tricore Toolchain Selection - config ARCH_TC1V6 bool - select ARCH_HAVE_DEBUG - select ARCH_HAVE_MPU select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_PERF_EVENTS select ARCH_HAVE_POWEROFF @@ -33,15 +15,10 @@ config ARCH_TC1V6 select ARCH_HAVE_SETJMP select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET - select ARCH_SETJMP_H default n config ARCH_TC1V8 bool - select ARCH_DCACHE - select ARCH_HAVE_DEBUG - select ARCH_ICACHE - select ARCH_HAVE_MPU select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_PERF_EVENTS select ARCH_HAVE_PERF_EVENTS_USER_ACCESS @@ -49,7 +26,6 @@ config ARCH_TC1V8 select ARCH_HAVE_SETJMP select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET - select ARCH_SETJMP_H default n config ARCH_FAMILY @@ -57,92 +33,9 @@ config ARCH_FAMILY default "tc1v6" if ARCH_TC1V6 default "tc1v8" if ARCH_TC1V8 -config ARCH_CHIP_TC3XX - bool - select ARCH_TC1V6 - select ARCH_HAVE_ADDRENV - select ARCH_HAVE_I2CRESET - select ARCH_MINIMAL_VECTORTABLE - select ARCH_MINIMAL_VECTORTABLE_DYNAMIC - select ALARM_ARCH - select ONESHOT - select ONESHOT_COUNT - ---help--- - Infineon aurix tc3xx (six cores) - -config ARCH_CHIP_TC4XX - bool - select ARCH_TC1V8 - select ARCH_HAVE_ADDRENV - select ARCH_HAVE_FPU if !TRICORE_CSRM - select ARCH_HAVE_I2CRESET - select ARCH_MINIMAL_VECTORTABLE - select ARCH_MINIMAL_VECTORTABLE_DYNAMIC - select ALARM_ARCH - select ONESHOT - select ONESHOT_COUNT - select HAVE_SECURITY_CORE - ---help--- - Infineon aurix tc4xx (six cores and one security core) - -config ARCH_CHIP_TC397 - bool "AURIX CHIP TC397" - select ARCH_CHIP_TC3XX - -config ARCH_CHIP_TC4DA - bool "AURIX CHIP TC4DA" - select ARCH_CHIP_TC4XX - -config ARCH_CHIP - string - default "tc397" if ARCH_CHIP_TC397 - default "tc4da" if ARCH_CHIP_TC4DA - -config ARCH_DCACHE_ADDR - hex "AURIX Dcache base address" - default 0x7003C000 - ---help--- - AURIX Dcache base address, dcache line clear and invalidate need - use the address. - -config ARCH_MPU_NSETS - int "Protection sets number" - default 7 - ---help--- - The protection sets count - -config ARCH_MPU_DATA_NREGIONS - int "Data regions number" - default 23 - ---help--- - The data regions count - -config ARCH_MPU_CODE_NREGIONS - int "Code regions variables" - default 15 - ---help--- - The code regions count - -config HAVE_SECURITY_CORE - bool - ---help--- - In addition to the 6 cores, tc4xx also has one more security core. - config CPU_COREID int "TRICORE CPU CORE ID" default 0 range 0 6 -if ARCH_CHIP_TC3XX -source "arch/tricore/src/tc3xx/Kconfig" -endif -if ARCH_CHIP_TC4XX -source "arch/tricore/src/tc4xx/Kconfig" -endif -if ARCH_CHIP_TC397 -source "arch/tricore/src/tc397/Kconfig" -endif -if ARCH_CHIP_TC4DA -source "arch/tricore/src/tc4da/Kconfig" -endif endif # ARCH_TRICORE diff --git a/arch/tricore/include/setjmp.h b/arch/tricore/include/setjmp.h deleted file mode 100644 index fdb9d062e2a06..0000000000000 --- a/arch/tricore/include/setjmp.h +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * arch/tricore/include/setjmp.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_INCLUDE_SETJUMP_H -#define __ARCH_TRICORE_INCLUDE_SETJUMP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -struct setjmp_buf_s -{ - uintptr_t pcxi; - uintptr_t psw; - uintptr_t sp; - uintptr_t a11; - uintptr_t d8; - uintptr_t d9; - uintptr_t d10; - uintptr_t d11; - uintptr_t a12; - uintptr_t a13; - uintptr_t a14; - uintptr_t a15; - uintptr_t d12; - uintptr_t d13; - uintptr_t d14; - uintptr_t d15; -}; - -/* Traditional typedef for setjmp_buf */ - -typedef struct setjmp_buf_s jmp_buf[1]; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -int setjmp(jmp_buf env); -void longjmp(jmp_buf env, int val) noreturn_function; - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ARCH_TRICORE_INCLUDE_SETJUMP_H */ diff --git a/arch/tricore/include/tc397/chip.h b/arch/tricore/include/tc397/chip.h deleted file mode 100644 index b2106bf710608..0000000000000 --- a/arch/tricore/include/tc397/chip.h +++ /dev/null @@ -1,48 +0,0 @@ -/**************************************************************************** - * arch/tricore/include/tc397/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_INCLUDE_TC397_CHIP_H -#define __ARCH_TRICORE_INCLUDE_TC397_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_TRICORE_INCLUDE_TC397_CHIP_H */ diff --git a/arch/tricore/include/tc397/irq.h b/arch/tricore/include/tc397/irq.h deleted file mode 100644 index 00a3fe21bd55e..0000000000000 --- a/arch/tricore/include/tc397/irq.h +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * arch/tricore/include/tc397/irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_TRICORE_INCLUDE_TC397_IRQ_H -#define __ARCH_TRICORE_INCLUDE_TC397_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -#define TRICORE_UART_RX_IRQ 21 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_TRICORE_INCLUDE_TC397_IRQ_H */ diff --git a/arch/tricore/include/tc4da/chip.h b/arch/tricore/include/tc4da/chip.h deleted file mode 100644 index f063fabbe5d33..0000000000000 --- a/arch/tricore/include/tc4da/chip.h +++ /dev/null @@ -1,48 +0,0 @@ -/**************************************************************************** - * arch/tricore/include/tc4da/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_INCLUDE_TC4DA_CHIP_H -#define __ARCH_TRICORE_INCLUDE_TC4DA_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_TRICORE_INCLUDE_TC4DA_CHIP_H */ diff --git a/arch/tricore/include/tc4da/irq.h b/arch/tricore/include/tc4da/irq.h deleted file mode 100644 index afa681aac9f59..0000000000000 --- a/arch/tricore/include/tc4da/irq.h +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * arch/tricore/include/tc4da/irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_TRICORE_INCLUDE_TC4DA_IRQ_H -#define __ARCH_TRICORE_INCLUDE_TC4DA_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -#define TRICORE_UART_RX_IRQ 173 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_TRICORE_INCLUDE_TC4DA_IRQ_H */ diff --git a/arch/tricore/src/cmake/chip.cmake b/arch/tricore/src/cmake/chip.cmake index a9847c3a19aeb..79cd5f0c4028e 100644 --- a/arch/tricore/src/cmake/chip.cmake +++ b/arch/tricore/src/cmake/chip.cmake @@ -1,5 +1,5 @@ # ############################################################################## -# arch/tricore/src/cmake/tc3xx.cmake +# arch/tricore/src/cmake/chip.cmake # # SPDX-License-Identifier: Apache-2.0 # @@ -19,24 +19,3 @@ # the License. # # ############################################################################## - -set(PLATFORM_FLAGS) - -if(CONFIG_ARCH_CHIP_TC3XX) - if(CONFIG_TRICORE_TOOLCHAIN_TASKING) - add_compile_options(--cpu=tc39xb) - add_link_options(-Ctc39xb) - else() - list(APPEND PLATFORM_FLAGS -mcpu=tc39xx -mtc162) - endif() -elseif(CONFIG_ARCH_CHIP_TC4XX) - if(CONFIG_TRICORE_TOOLCHAIN_TASKING) - add_compile_options(--cpu=tc4DAx) - add_link_options(-Ctc4DAx) - else() - list(APPEND PLATFORM_FLAGS -mcpu=tc4DAx -mtc18) - endif() -endif() - -add_compile_options(${PLATFORM_FLAGS}) -add_link_options(${PLATFORM_FLAGS}) diff --git a/arch/tricore/src/common/CMakeLists.txt b/arch/tricore/src/common/CMakeLists.txt index 1c51d7ef35b73..1bbf4a0426231 100644 --- a/arch/tricore/src/common/CMakeLists.txt +++ b/arch/tricore/src/common/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS tricore_allocateheap.c - tricore_cache.c + tricore_backtrace.c tricore_checkstack.c tricore_createstack.c tricore_csa.c @@ -32,9 +32,7 @@ set(SRCS tricore_initialize.c tricore_initialstate.c tricore_irq.c - tricore_main.c tricore_nputs.c - tricore_perf.c tricore_registerdump.c tricore_releasestack.c tricore_saveusercontext.c @@ -42,13 +40,8 @@ set(SRCS tricore_svcall.c tricore_tcbinfo.c tricore_trapcall.c - tricore_systimer.c tricore_usestack.c) -if(CONFIG_SCHED_BACKTRACE) - list(APPEND SRCS tricore_backtrace.c) -endif() - if(CONFIG_ENABLE_ALL_SIGNALS) list(APPEND SRCS tricore_schedulesigaction.c tricore_sigdeliver.c) endif() @@ -57,18 +50,6 @@ if(CONFIG_SPINLOCK) list(APPEND SRCS tricore_testset.c) endif() -if(CONFIG_ARCH_USE_MPU) - list(APPEND SRCS tricore_mpu.c) -endif() - -if(CONFIG_ARCH_HAVE_FPU) - list(APPEND SRCS tricore_fpu.c) -endif() - -if(CONFIG_ARCH_HAVE_DEBUG) - list(APPEND SRCS tricore_hwdebug.c) -endif() - set(IFXFLAGS -DIFX_CFG_EXTEND_TRAP_HOOKS -DIFX_USE_SW_MANAGED_INT) target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/tricore/src/common/Ifx_Cfg_Trap.h b/arch/tricore/src/common/Ifx_Cfg_Trap.h deleted file mode 100644 index 87b0723bd1765..0000000000000 --- a/arch/tricore/src/common/Ifx_Cfg_Trap.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/Ifx_Cfg_Trap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_SRC_COMMON_IFX_CFG_TRAP_H -#define __ARCH_TRICORE_SRC_COMMON_IFX_CFG_TRAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "tricore_internal.h" - -#if (IFX_CFG_EXTEND_TRAP_HOOKS == 1) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Trap Hook definition */ - -/* Trap Call */ - -#define IFX_CFG_CPU_TRAP_TSR_HOOK(trapInfo) tricore_trapcall(&trapInfo) -#define IFX_CFG_CPU_TRAP_NMI_HOOK(trapInfo) tricore_trapcall(&trapInfo) -#define IFX_CFG_CPU_TRAP_MME_HOOK(trapInfo) tricore_trapcall(&trapInfo) -#define IFX_CFG_CPU_TRAP_IPE_HOOK(trapInfo) tricore_trapcall(&trapInfo) -#define IFX_CFG_CPU_TRAP_IE_HOOK(trapInfo) tricore_trapcall(&trapInfo) -#define IFX_CFG_CPU_TRAP_CME_HOOK(trapInfo) tricore_trapcall(&trapInfo) -#define IFX_CFG_CPU_TRAP_BE_HOOK(trapInfo) tricore_trapcall(&trapInfo) -#define IFX_CFG_CPU_TRAP_ASSERT_HOOK(trapInfo) tricore_trapcall(&trapInfo) - -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU0_HOOK(trapWatch) tricore_svcall(&trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU1_HOOK(trapWatch) tricore_svcall(&trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU2_HOOK(trapWatch) tricore_svcall(&trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU3_HOOK(trapWatch) tricore_svcall(&trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU4_HOOK(trapWatch) tricore_svcall(&trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU5_HOOK(trapWatch) tricore_svcall(&trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU6_HOOK(trapWatch) tricore_svcall(&trapWatch) - -#endif /* IFX_CFG_EXTEND_TRAP_HOOKS */ - -#endif /* __ARCH_TRICORE_SRC_COMMON_IFX_CFG_TRAP_H */ diff --git a/arch/tricore/src/common/Make.defs b/arch/tricore/src/common/Make.defs index a73d35c576583..0b961757673ba 100644 --- a/arch/tricore/src/common/Make.defs +++ b/arch/tricore/src/common/Make.defs @@ -23,7 +23,7 @@ HEAD_CSRC += tricore_doirq.c CMN_CSRCS += tricore_allocateheap.c -CMN_CSRCS += tricore_cache.c +CMN_CSRCS += tricore_backtrace.c CMN_CSRCS += tricore_checkstack.c CMN_CSRCS += tricore_createstack.c CMN_CSRCS += tricore_csa.c @@ -33,9 +33,7 @@ CMN_CSRCS += tricore_idle.c CMN_CSRCS += tricore_initialize.c CMN_CSRCS += tricore_initialstate.c CMN_CSRCS += tricore_irq.c -CMN_CSRCS += tricore_main.c CMN_CSRCS += tricore_nputs.c -CMN_CSRCS += tricore_perf.c CMN_CSRCS += tricore_registerdump.c CMN_CSRCS += tricore_releasestack.c CMN_CSRCS += tricore_saveusercontext.c @@ -43,13 +41,8 @@ CMN_CSRCS += tricore_stackframe.c CMN_CSRCS += tricore_svcall.c CMN_CSRCS += tricore_tcbinfo.c CMN_CSRCS += tricore_trapcall.c -CMN_CSRCS += tricore_systimer.c CMN_CSRCS += tricore_usestack.c -ifeq ($(CONFIG_SCHED_BACKTRACE),y) - CMN_CSRCS += tricore_backtrace.c -endif - ifeq ($(CONFIG_ENABLE_ALL_SIGNALS),y) CMN_CSRCS += tricore_schedulesigaction.c tricore_sigdeliver.c endif @@ -58,17 +51,5 @@ ifeq ($(CONFIG_SPINLOCK),y) CMN_CSRCS += tricore_testset.c endif -ifeq ($(CONFIG_ARCH_USE_MPU),y) - CMN_CSRCS += tricore_mpu.c -endif - -ifeq ($(CONFIG_ARCH_HAVE_FPU),y) - CMN_CSRCS += tricore_fpu.c -endif - -ifeq ($(CONFIG_ARCH_HAVE_DEBUG),y) - CMN_CSRCS += tricore_hwdebug.c -endif - CFLAGS += -DIFX_CFG_EXTEND_TRAP_HOOKS CFLAGS += -DIFX_USE_SW_MANAGED_INT diff --git a/arch/tricore/src/common/tricore_cache.c b/arch/tricore/src/common/tricore_cache.c deleted file mode 100644 index d86924b024b47..0000000000000 --- a/arch/tricore/src/common/tricore_cache.c +++ /dev/null @@ -1,524 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/tricore_cache.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "tricore_internal.h" -#include "IfxCpu_cfg.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define tc_invalidate_cache_byaddr(addr) \ - __asm__ __volatile__("cachea.i [%0]0"::"a"(addr)) -#define tc_clear_cache_byaddr(addr) \ - __asm__ __volatile__("cachea.w [%0]0"::"a"(addr)) -#define tc_flush_cache_byaddr(addr) \ - __asm__ __volatile__("cachea.wi [%0]0"::"a"(addr)) -#define tc_invalidate_cache_byline(line) \ - __asm__ __volatile__("cachei.i [%0]0"::"a"(line)) -#define tc_clear_cache_byline(line) \ - __asm__ __volatile__("cachei.w [%0]0"::"a"(line)) -#define tc_flush_cache_byline(line) \ - __asm__ __volatile__("cachei.wi [%0]0"::"a"(line)) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef CONFIG_ARCH_ICACHE -/**************************************************************************** - * Name: up_get_icache_linesize - * - * Description: - * Get icache linesize - * - * Input Parameters: - * None - * - * Returned Value: - * Cache line size - * - ****************************************************************************/ - -size_t up_get_icache_linesize(void) -{ - return IFXCPU_PCACHE_LINE_SIZE / 8; -} - -/**************************************************************************** - * Name: up_get_icache_size - * - * Description: - * Get icache size - * - * Input Parameters: - * None - * - * Returned Value: - * Cache size - * - ****************************************************************************/ - -size_t up_get_icache_size(void) -{ - Ifx_CPU_PCON2 pcon2; - - pcon2.U = __mfcr(CPU_PCON2); - return pcon2.B.PCACHE_SZE * 1000; -} - -/**************************************************************************** - * Name: up_enable_icache - * - * Description: - * Enable the I-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Caution: - * The writable global variables aren't initialized yet. - * - ****************************************************************************/ - -void up_enable_icache(void) -{ - Ifx_CPU_PCON0 pcon0; - - pcon0.B.PCBYP = 0; - __mtcr(CPU_PCON0, pcon0.U); - - __isync(); -} - -/**************************************************************************** - * Name: up_disable_icache - * - * Description: - * Disable the I-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_disable_icache(void) -{ - Ifx_CPU_PCON0 pcon0; - - pcon0.U = 0; - pcon0.B.PCBYP = 1; - __mtcr(CPU_PCON0, pcon0.U); - - __isync(); -} - -/**************************************************************************** - * Name: up_invalidate_icache - * - * Description: - * Invalidate the instruction cache within the specified region. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_invalidate_icache(uintptr_t start, uintptr_t end) -{ - up_invalidate_icache_all(); -} - -/**************************************************************************** - * Name: up_invalidate_icache_all - * - * Description: - * Invalidate the entire contents of I cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_invalidate_icache_all(void) -{ - Ifx_CPU_PCON1 pcon1; - - pcon1.U = 0; - pcon1.B.PCINV = 1; - __mtcr(CPU_PCON1, pcon1.U); - - __isync(); -} -#endif - -#ifdef CONFIG_ARCH_DCACHE -/**************************************************************************** - * Name: up_get_dcache_linesize - * - * Description: - * Get dcache linesize - * - * Input Parameters: - * None - * - * Returned Value: - * Cache line size - * - ****************************************************************************/ - -size_t up_get_dcache_linesize(void) -{ - return IFXCPU_DCACHE_LINE_SIZE / 8; -} - -/**************************************************************************** - * Name: up_get_dcache_size - * - * Description: - * Get dcache size - * - * Input Parameters: - * None - * - * Returned Value: - * Cache size - * - ****************************************************************************/ - -size_t up_get_dcache_size(void) -{ - Ifx_CPU_DCON2 dcon2; - - dcon2.U = __mfcr(CPU_DCON2); - return dcon2.B.DCACHE_SZE * 1000; -} - -/**************************************************************************** - * Name: up_enable_dcache - * - * Description: - * Enable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Caution: - * The writable global variables aren't initialized yet. - * - ****************************************************************************/ - -void up_enable_dcache(void) -{ - Ifx_CPU_DCON0 dcon0; - - /* Check if the D-Cache is enabled */ - - dcon0.U = __mfcr(CPU_DCON0); - if (dcon0.B.DCBYP == 0) - { - return; - } - - up_invalidate_dcache_all(); - - dcon0.U = 0; - dcon0.B.DCBYP = 0; - __mtcr(CPU_DCON0, dcon0.U); - - __dsync(); - __isync(); -} - -/**************************************************************************** - * Name: up_disable_dcache - * - * Description: - * Disable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_disable_dcache(void) -{ - Ifx_CPU_DCON0 dcon0; - - dcon0.B.DCBYP = 1; - __mtcr(CPU_DCON0, dcon0.U); - - __dsync(); - __isync(); -} - -/**************************************************************************** - * Name: up_invalidate_dcache - * - * Description: - * Invalidate the data cache within the specified region; we will be - * performing a DMA operation in this region and we want to purge old data - * in the cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_invalidate_dcache(uintptr_t start, uintptr_t end) -{ - size_t line_size = up_get_dcache_linesize(); - - if ((start & (line_size - 1)) != 0) - { - start &= ~(line_size - 1); - tc_flush_cache_byaddr(start); - start += line_size; - } - - while (start < end) - { - if (start + line_size <= end) - { - tc_invalidate_cache_byaddr(start); - } - else - { - tc_flush_cache_byaddr(start); - } - - start += line_size; - } - - __dsync(); - __isync(); -} - -/**************************************************************************** - * Name: up_invalidate_dcache_all - * - * Description: - * Invalidate the entire contents of D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_invalidate_dcache_all(void) -{ - Ifx_CPU_DCON1 dcon1; - - dcon1.U = 0; - dcon1.B.DCINV = 1; - __mtcr(CPU_DCON1, dcon1.U); - - __dsync(); - __isync(); -} - -/**************************************************************************** - * Name: up_clean_dcache - * - * Description: - * Clean the data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_clean_dcache(uintptr_t start, uintptr_t end) -{ - size_t line_size = up_get_dcache_linesize(); - - start &= ~(line_size - 1); - - while (start < end) - { - tc_clear_cache_byaddr(start); - start += line_size; - } - - __dsync(); - __isync(); -} - -/**************************************************************************** - * Name: up_clean_dcache_all - * - * Description: - * Clean the entire data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_clean_dcache_all(void) -{ - uintptr_t cache_addr = CONFIG_ARCH_DCACHE_ADDR; - size_t line_size = up_get_dcache_linesize(); - size_t line_cnt = up_get_dcache_size() / line_size; - size_t i; - - for (i = 0; i < line_cnt; i++) - { - tc_clear_cache_byline(cache_addr); - cache_addr += line_size; - } - - __dsync(); - __isync(); -} - -/**************************************************************************** - * Name: up_flush_dcache - * - * Description: - * Flush the data cache within the specified region by cleaning and - * invalidating the D cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_flush_dcache(uintptr_t start, uintptr_t end) -{ - size_t line_size = up_get_dcache_linesize(); - - start &= ~(line_size - 1); - - while (start < end) - { - tc_flush_cache_byaddr(start); - start += line_size; - } - - __dsync(); - __isync(); -} - -/**************************************************************************** - * Name: up_flush_dcache_all - * - * Description: - * Flush the entire data cache by cleaning and invalidating the D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_flush_dcache_all(void) -{ - uintptr_t cache_addr = CONFIG_ARCH_DCACHE_ADDR; - size_t line_size = up_get_dcache_linesize(); - size_t line_cnt = up_get_dcache_size() / line_size; - size_t i; - - for (i = 0; i < line_cnt; i++) - { - tc_flush_cache_byline(cache_addr); - cache_addr += line_size; - } - - __dsync(); - __isync(); -} - -/**************************************************************************** - * Name: up_coherent_dcache - * - * Description: - * Ensure that the I and D caches are coherent within specified region - * by cleaning the D cache (i.e., flushing the D cache contents to memory - * and invalidating the I cache. This is typically used when code has been - * written to a memory region, and will be executed. - * - * Input Parameters: - * addr - virtual start address of region - * len - Size of the address region in bytes - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_coherent_dcache(uintptr_t addr, size_t len) -{ - if (len > 0) - { - up_flush_dcache(addr, addr + len); - up_invalidate_icache_all(); - } -} -#endif diff --git a/arch/tricore/src/common/tricore_fpu.c b/arch/tricore/src/common/tricore_fpu.c deleted file mode 100644 index ec1c4343e9033..0000000000000 --- a/arch/tricore/src/common/tricore_fpu.c +++ /dev/null @@ -1,70 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/tricore_fpu.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "tricore_internal.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: tricore_fpuinit - ****************************************************************************/ - -void tricore_fpuinit(void) -{ - /* FPU zero-divide trap enable */ - - __mtcr(FPU_SYNC_TRAP_REG, - __mfcr(FPU_SYNC_TRAP_REG) | (1U << FPU_TRAP_FZE_SHIFT)); -} - -/**************************************************************************** - * Name: up_fpucmp - ****************************************************************************/ - -bool up_fpucmp(const void *saveregs1, const void *saveregs2) -{ - const uintptr_t *regs1 = (const uintptr_t *)saveregs1 + TC_CONTEXT_REGS; - const uintptr_t *regs2 = (const uintptr_t *)saveregs2 + TC_CONTEXT_REGS; - - /* TriCore uses D8-D15 in upper CSA as FPU data registers. - * Skip A12-A15 (offsets 8-11) which naturally differ between saves. - */ - - if (memcmp(®s1[REG_D8], ®s2[REG_D8], - 4 * sizeof(uintptr_t)) != 0) - { - return false; - } - - return memcmp(®s1[REG_D12], ®s2[REG_D12], - 4 * sizeof(uintptr_t)) == 0; -} diff --git a/arch/tricore/src/common/tricore_hwdebug.c b/arch/tricore/src/common/tricore_hwdebug.c deleted file mode 100644 index 16b0a93a7d6d1..0000000000000 --- a/arch/tricore/src/common/tricore_hwdebug.c +++ /dev/null @@ -1,412 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/tricore_hwdebug.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "tricore_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Watchpoint and breakpoint share a set of trigger events */ - -#define TREVT_DEBUG_NUM 8 -#define TREVT_DEBUG_REGS 4 -#define TREVT_DEBUG_MATCH_TRAPMODE 0x03 -#define TREVT_DEBUG_EVTSRC_BASE 0x10 -#ifdef CONFIG_ARCH_TC1V8 -# define IFX_CPU_TR_EVT_BBM_OFF IFX_CPU_TREVT_BBM_OFF -# define IFX_CPU_TR_EVT_TYP_OFF IFX_CPU_TREVT_TYP_OFF -# define IFX_CPU_TR_EVT_AST_OFF IFX_CPU_TREVT_AST_OFF -# define IFX_CPU_TR_EVT_ALD_OFF IFX_CPU_TREVT_ALD_OFF -#endif - -#define TREVT_DEBUG_BBM (1 << IFX_CPU_TR_EVT_BBM_OFF) -#define TREVT_DEBUG_WP (0 << IFX_CPU_TR_EVT_TYP_OFF) -#define TREVT_DEBUG_BP (1 << IFX_CPU_TR_EVT_TYP_OFF) -#define TREVT_DEBUG_WP_AST (1 << IFX_CPU_TR_EVT_AST_OFF) -#define TREVT_DEBUG_WP_ALD (1 << IFX_CPU_TR_EVT_ALD_OFF) -#define TREVT_DEBUG_WP_ASTLD (TREVT_DEBUG_WP_AST | TREVT_DEBUG_WP_ALD) - -/* Register TREVT[2:0] have difference between tc3xx and tc4xx */ - -#ifdef CONFIG_ARCH_TC1V6 -# define TREVT_CFG_REG_EN_MASK IFX_CPU_TR_EVT_EVTA_MSK -# define TREVT_CFG_REG_EN_VALUE TREVT_DEBUG_MATCH_TRAPMODE -#elif defined(CONFIG_ARCH_TC1V8) -# define TREVT_CFG_REG_EN_MASK IFX_CPU_TREVT_EN_MSK -# define TREVT_CFG_REG_EN_VALUE 0x01 -#endif - -#define TREVT_SET_CASE(reg, n, val) \ - case n: __mtcr(CPU_TR##n##_##reg, val); break; -#define TREVT_GET_CASE(reg, n, val) \ - case n: val = __mfcr(CPU_TR##n##_##reg); break; - -#define TREVT_GET_CFG_REG(n) TREVT_GET(EVT, n) -#define TREVT_SET_CFG_REG(n, val) TREVT_SET(EVT, n, val) -#define TREVT_GET_ADDR_REG(n) TREVT_GET(ADR, n) -#define TREVT_SET_ADDR_REG(n, val) TREVT_SET(ADR, n, val) - -#define TREVT_SET(reg, n, val) \ - ({ \ - switch (n) \ - { \ - TREVT_SET_CASE(reg, 0, val) \ - TREVT_SET_CASE(reg, 1, val) \ - TREVT_SET_CASE(reg, 2, val) \ - TREVT_SET_CASE(reg, 3, val) \ - TREVT_SET_CASE(reg, 4, val) \ - TREVT_SET_CASE(reg, 5, val) \ - TREVT_SET_CASE(reg, 6, val) \ - TREVT_SET_CASE(reg, 7, val) \ - } \ - }) - -#define TREVT_GET(reg, n) \ - ({ \ - uint32_t _val = 0; \ - switch (n) \ - { \ - TREVT_GET_CASE(reg, 0, _val) \ - TREVT_GET_CASE(reg, 1, _val) \ - TREVT_GET_CASE(reg, 2, _val) \ - TREVT_GET_CASE(reg, 3, _val) \ - TREVT_GET_CASE(reg, 4, _val) \ - TREVT_GET_CASE(reg, 5, _val) \ - TREVT_GET_CASE(reg, 6, _val) \ - TREVT_GET_CASE(reg, 7, _val) \ - } \ - _val; \ - }) - -/**************************************************************************** - * Private Type - ****************************************************************************/ - -struct tricore_debugpoint_s -{ - int type; - void *addr; - size_t size; - debug_callback_t callback; - void *arg; -}; - -struct tricore_debug_s -{ - uintptr_t aligned_data(XCPTCONTEXT_SIZE) dcx[TREVT_DEBUG_REGS]; - struct tricore_debugpoint_s dp[TREVT_DEBUG_NUM]; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct tricore_debug_s g_trevt_debug; - -/**************************************************************************** - * Private Function - ****************************************************************************/ - -static uint32_t tricore_convert_type(int type) -{ - switch (type) - { - case DEBUGPOINT_WATCHPOINT_RO: - return TREVT_DEBUG_WP | TREVT_DEBUG_WP_ALD; - - case DEBUGPOINT_WATCHPOINT_WO: - return TREVT_DEBUG_WP | TREVT_DEBUG_WP_AST; - - case DEBUGPOINT_WATCHPOINT_RW: - return TREVT_DEBUG_WP | TREVT_DEBUG_WP_ASTLD; - - case DEBUGPOINT_BREAKPOINT: - case DEBUGPOINT_STEPPOINT: - default: - return TREVT_DEBUG_BP; - } -} - -/**************************************************************************** - * Name: tricore_trevt_add - * - * Description: - * Add a watchpoint on the address. - * - * Input Parameters: - * type - The type of the watchpoint - * addr - The address to be watched - * size - The size of the address to be watched - * - * Returned Value: - * Index in wprs array on success; a negated errno value on failure - * - ****************************************************************************/ - -static int tricore_trevt_add(int type, uint32_t addr, size_t size) -{ - int i; - - for (i = 0; i < TREVT_DEBUG_NUM; i++) - { - if (!(TREVT_GET_CFG_REG(i) & TREVT_CFG_REG_EN_MASK)) - { - TREVT_SET_ADDR_REG(i, addr); - TREVT_SET_CFG_REG(i, tricore_convert_type(type) | - TREVT_CFG_REG_EN_VALUE); - return i; - } - } - - return -ENOSPC; -} - -/**************************************************************************** - * Name: tricore_trevt_remove - * - * Description: - * Remove a trevt on the address. - * - * Input Parameters: - * addr - The address to be debugged. - * - * Returned Value: - * Index of trevt on success; a negated errno value on failure - * - ****************************************************************************/ - -static int tricore_trevt_remove(uint32_t addr) -{ - int i; - - for (i = 0; i < TREVT_DEBUG_NUM; i++) - { - if (TREVT_GET_ADDR_REG(i) == addr) - { - TREVT_SET_CFG_REG(i, 0); - TREVT_SET_ADDR_REG(i, 0); - return i; - } - } - - return -ENOENT; -} - -/**************************************************************************** - * Name: tricore_dbgmonitor - * - * Description: - * This is Debug Monitor exception handler. This function is entered when - * the processor enters debug mode. The debug monitor handler will handle - * debug events, and resume execution. - * - ****************************************************************************/ - -static void tricore_dbgmonitor(void) -{ - __asm__ __volatile__ ( - "svlcx\n\t" - "call tricore_trevt_match\n\t" - "rslcx\n\t" - "rfm\n\t" - ); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: tricore_trevt_match - ****************************************************************************/ - -void tricore_trevt_match(void) -{ - struct tricore_debugpoint_s *dp; - int evtsrc; - - dp = g_trevt_debug.dp; - - evtsrc = ((__mfcr(CPU_DBGSR) >> IFX_CPU_DBGSR_EVTSRC_OFF) & - IFX_CPU_DBGSR_EVTSRC_MSK) - TREVT_DEBUG_EVTSRC_BASE; - - dp[evtsrc].callback(dp[evtsrc].type, dp[evtsrc].addr, - dp[evtsrc].size, dp[evtsrc].arg); -} - -/**************************************************************************** - * Name: tricore_init_dbgmonitor - * - * Description: - * This function init the debug monitor exception. - * - ****************************************************************************/ - -int tricore_init_dbgmonitor(void) -{ - Ifx_CPU_DBGTCR dbgtcr; - - dbgtcr.B.DTA = 0; - - if (!(__mfcr(CPU_DBGSR) & 0x1)) - { - CBS_OEC.U = 0xa1; - CBS_OEC.U = 0x5e; - CBS_OEC.U = 0xa1; - CBS_OEC.U = 0x5e; - } - -#ifdef CONFIG_ARCH_TC1V8 - Ifx_CPU_DBGCFG dbgcfg; - Ifx_CPU_DBGACT dbgact; - - dbgcfg.B.EN = 1; - dbgcfg.B.TC = 0; - dbgcfg.B.TCP = 0; - dbgact.B.EVTA = TREVT_DEBUG_MATCH_TRAPMODE; - - /* Set debug configuration register */ - - __mtcr(CPU_DBGCFG, dbgcfg.U); - - /* Set debug action configuration register */ - - __mtcr(CPU_DBGACT, dbgact.U); -#endif - - /* Set debug trap control register */ - - __mtcr(CPU_DBGTCR, dbgtcr.U); - - /* Set trevt trap handler */ - - __mtcr(CPU_DMS, (uintptr_t)tricore_dbgmonitor); - - /* Set dcx register */ - - __mtcr(CPU_DCX, (uintptr_t)g_trevt_debug.dcx); - - return OK; -} - -/**************************************************************************** - * Name: up_debugpoint_add - * - * Description: - * Add a debugpoint. - * - * Input Parameters: - * type - The debugpoint type. optional value: - * DEBUGPOINT_WATCHPOINT_RO - Read only watchpoint. - * DEBUGPOINT_WATCHPOINT_WO - Write only watchpoint. - * DEBUGPOINT_WATCHPOINT_RW - Read and write watchpoint. - * DEBUGPOINT_BREAKPOINT - Breakpoint. - * DEBUGPOINT_STEPPOINT - Single step. - * addr - The address to be debugged. - * size - The watchpoint size. only for watchpoint. - * callback - The callback function when debugpoint triggered. - * if NULL, the debugpoint will be removed. - * arg - The argument of callback function. - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -int up_debugpoint_add(int type, void *addr, size_t size, - debug_callback_t callback, void *arg) -{ - struct tricore_debugpoint_s *dp; - int ret; - - ret = tricore_trevt_add(type, (uint32_t)addr, size); - - if (ret < 0) - { - return ret; - } - - dp = g_trevt_debug.dp; - dp[ret].type = type; - dp[ret].addr = addr; - dp[ret].size = size; - dp[ret].callback = callback; - dp[ret].arg = arg; - - return OK; -} - -/**************************************************************************** - * Name: up_debugpoint_remove - * - * Description: - * Remove a debugpoint. - * - * Input Parameters: - * type - The debugpoint type. optional value: - * DEBUGPOINT_WATCHPOINT_RO - Read only watchpoint. - * DEBUGPOINT_WATCHPOINT_WO - Write only watchpoint. - * DEBUGPOINT_WATCHPOINT_RW - Read and write watchpoint. - * DEBUGPOINT_BREAKPOINT - Breakpoint. - * DEBUGPOINT_STEPPOINT - Single step. - * addr - The address to be debugged. - * size - The watchpoint size. only for watchpoint. - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -int up_debugpoint_remove(int type, void *addr, size_t size) -{ - struct tricore_debugpoint_s *dp; - int ret; - - ret = tricore_trevt_remove((uintptr_t)addr); - - if (ret < 0) - { - return ret; - } - - dp = g_trevt_debug.dp; - dp[ret].type = 0; - dp[ret].addr = 0; - dp[ret].size = 0; - dp[ret].callback = NULL; - dp[ret].arg = NULL; - - return OK; -} diff --git a/arch/tricore/src/common/tricore_main.c b/arch/tricore/src/common/tricore_main.c deleted file mode 100644 index a297fd8438302..0000000000000 --- a/arch/tricore/src/common/tricore_main.c +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/tricore_main.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "Ifx_Types.h" -#include "IfxCpu.h" - -#ifdef CONFIG_ARCH_CHIP_TC4XX -# include "IfxWtu.h" -#else -# include "IfxScuWdt.h" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void core_main(void) -{ - static IfxCpu_syncEvent g_sync_event = 0; - -#ifdef CONFIG_ARCH_HAVE_FPU - tricore_fpuinit(); -#endif - - /* !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!! - * Enable the watchdogs and service them periodically if it is required - */ - - /* Wait for CPU sync event */ - - IfxCpu_emitEvent(&g_sync_event); - -#if defined(CONFIG_ARCH_CHIP_TC3XX) - IfxCpu_waitEvent(&g_sync_event, 1); -#else - IfxCpu_waitEvent(&g_sync_event, UINT32_MAX, 1); -#endif - - if (IfxCpu_getCoreIndex() == 0) - { - tricore_earlyserialinit(); - nx_start(); - } - - while (1); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void core0_main(void) -{ - /* All WDTs except WDTCPU0 and system watchdog WDTSYS are in - * disabled mode after Boot-FW execution. Disable the watchdog - * to ensure the normal startup of the system. - */ - -#if defined(CONFIG_ARCH_CHIP_TC3XX) - IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); - IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword()); -#elif defined(CONFIG_ARCH_CHIP_TC4XX) - IfxWtu_disableCpuWatchdog(IfxWtu_getCpuWatchdogPassword()); - IfxWtu_disableSystemWatchdog(IfxWtu_getSystemWatchdogPassword()); -#endif - - core_main(); -} - -void core1_main(void) -{ - core_main(); -} - -void core2_main(void) -{ - core_main(); -} - -void core3_main(void) -{ - core_main(); -} - -void core4_main(void) -{ - core_main(); -} - -void core5_main(void) -{ - core_main(); -} - -void core6_main(void) -{ - core_main(); -} diff --git a/arch/tricore/src/common/tricore_mpu.c b/arch/tricore/src/common/tricore_mpu.c deleted file mode 100644 index d8c3b6d1f9852..0000000000000 --- a/arch/tricore/src/common/tricore_mpu.c +++ /dev/null @@ -1,1244 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/tricore_mpu.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "tricore_mpu.h" -#include "tricore_internal.h" - -/**************************************************************************** - * Private Variables - ****************************************************************************/ - -static unsigned int g_mpu_data_region; -static unsigned int g_mpu_code_region; -static unsigned int g_mpu_set; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static Ifx_CPU_DPRE get_dpre_value(unsigned int set) -{ - Ifx_CPU_DPRE dpre_value; - - switch (set) - { - case 0: - dpre_value.U = __mfcr(CPU_DPRE_0); - break; - case 1: - dpre_value.U = __mfcr(CPU_DPRE_1); - break; - case 2: - dpre_value.U = __mfcr(CPU_DPRE_2); - break; - case 3: - dpre_value.U = __mfcr(CPU_DPRE_3); - break; - case 4: - dpre_value.U = __mfcr(CPU_DPRE_4); - break; - case 5: - dpre_value.U = __mfcr(CPU_DPRE_5); - break; -#ifndef CONFIG_ARCH_CHIP_TC3XX - case 6: - dpre_value.U = __mfcr(CPU_DPRE_6); - break; - case 7: - dpre_value.U = __mfcr(CPU_DPRE_7); - break; -#endif - default: - dpre_value.U = 0; - break; - } - - return dpre_value; -} - -static void set_dpre_value(unsigned int set, Ifx_CPU_DPRE dpre_value) -{ - switch (set) - { - case 0: - __mtcr(CPU_DPRE_0, dpre_value.U); - break; - case 1: - __mtcr(CPU_DPRE_1, dpre_value.U); - break; - case 2: - __mtcr(CPU_DPRE_2, dpre_value.U); - break; - case 3: - __mtcr(CPU_DPRE_3, dpre_value.U); - break; - case 4: - __mtcr(CPU_DPRE_4, dpre_value.U); - break; - case 5: - __mtcr(CPU_DPRE_5, dpre_value.U); - break; -#ifndef CONFIG_ARCH_CHIP_TC3XX - case 6: - __mtcr(CPU_DPRE_6, dpre_value.U); - break; - case 7: - __mtcr(CPU_DPRE_7, dpre_value.U); - break; -#endif - default: - break; - } - - UP_ISB(); -} - -static Ifx_CPU_DPWE get_dpwe_value(unsigned int set) -{ - Ifx_CPU_DPWE dpwe_value; - - switch (set) - { - case 0: - dpwe_value.U = __mfcr(CPU_DPWE_0); - break; - case 1: - dpwe_value.U = __mfcr(CPU_DPWE_1); - break; - case 2: - dpwe_value.U = __mfcr(CPU_DPWE_2); - break; - case 3: - dpwe_value.U = __mfcr(CPU_DPWE_3); - break; - case 4: - dpwe_value.U = __mfcr(CPU_DPWE_4); - break; - case 5: - dpwe_value.U = __mfcr(CPU_DPWE_5); - break; -#ifndef CONFIG_ARCH_CHIP_TC3XX - case 6: - dpwe_value.U = __mfcr(CPU_DPWE_6); - break; - case 7: - dpwe_value.U = __mfcr(CPU_DPWE_7); - break; -#endif - default: - dpwe_value.U = 0; - break; - } - - return dpwe_value; -} - -static void set_dpwe_value(unsigned int set, Ifx_CPU_DPWE dpwe_value) -{ - switch (set) - { - case 0: - __mtcr(CPU_DPWE_0, dpwe_value.U); - break; - case 1: - __mtcr(CPU_DPWE_1, dpwe_value.U); - break; - case 2: - __mtcr(CPU_DPWE_2, dpwe_value.U); - break; - case 3: - __mtcr(CPU_DPWE_3, dpwe_value.U); - break; - case 4: - __mtcr(CPU_DPWE_4, dpwe_value.U); - break; - case 5: - __mtcr(CPU_DPWE_5, dpwe_value.U); - break; - case 6: -#ifndef CONFIG_ARCH_CHIP_TC3XX - __mtcr(CPU_DPWE_6, dpwe_value.U); - break; - case 7: - __mtcr(CPU_DPWE_7, dpwe_value.U); - break; -#endif - default: - break; - } - - UP_ISB(); -} - -static Ifx_CPU_CPXE get_cpxe_value(unsigned int set) -{ - Ifx_CPU_CPXE cpxe_value; - - switch (set) - { - case 0: - cpxe_value.U = __mfcr(CPU_CPXE_0); - break; - case 1: - cpxe_value.U = __mfcr(CPU_CPXE_1); - break; - case 2: - cpxe_value.U = __mfcr(CPU_CPXE_2); - break; - case 3: - cpxe_value.U = __mfcr(CPU_CPXE_3); - break; - case 4: - cpxe_value.U = __mfcr(CPU_CPXE_4); - break; - case 5: - cpxe_value.U = __mfcr(CPU_CPXE_5); - break; -#ifndef CONFIG_ARCH_CHIP_TC3XX - case 6: - cpxe_value.U = __mfcr(CPU_CPXE_6); - break; - case 7: - cpxe_value.U = __mfcr(CPU_CPXE_7); - break; -#endif - default: - cpxe_value.U = 0; - break; - } - - return cpxe_value; -} - -static void set_cpxe_value(unsigned int set, Ifx_CPU_CPXE cpxe_value) -{ - switch (set) - { - case 0: - __mtcr(CPU_CPXE_0, cpxe_value.U); - break; - case 1: - __mtcr(CPU_CPXE_1, cpxe_value.U); - break; - case 2: - __mtcr(CPU_CPXE_2, cpxe_value.U); - break; - case 3: - __mtcr(CPU_CPXE_3, cpxe_value.U); - break; - case 4: - __mtcr(CPU_CPXE_4, cpxe_value.U); - break; - case 5: - __mtcr(CPU_CPXE_5, cpxe_value.U); - break; -#ifndef CONFIG_ARCH_CHIP_TC3XX - case 6: - __mtcr(CPU_CPXE_6, cpxe_value.U); - break; - case 7: - __mtcr(CPU_CPXE_7, cpxe_value.U); - break; -#endif - default: - break; - } - - UP_ISB(); -} - -static int get_dpr_addrass_value(unsigned int region, - Ifx_CPU_DPR_L *dpr_l, - Ifx_CPU_DPR_U *dpr_u) -{ - switch (region) - { - case 0: - dpr_l->U = __mfcr(CPU_DPR0_L); - dpr_u->U = __mfcr(CPU_DPR0_U); - break; - case 1: - dpr_l->U = __mfcr(CPU_DPR1_L); - dpr_u->U = __mfcr(CPU_DPR1_U); - break; - case 2: - dpr_l->U = __mfcr(CPU_DPR2_L); - dpr_u->U = __mfcr(CPU_DPR2_U); - break; - case 3: - dpr_l->U = __mfcr(CPU_DPR3_L); - dpr_u->U = __mfcr(CPU_DPR3_U); - break; - case 4: - dpr_l->U = __mfcr(CPU_DPR4_L); - dpr_u->U = __mfcr(CPU_DPR4_U); - break; - case 5: - dpr_l->U = __mfcr(CPU_DPR5_L); - dpr_u->U = __mfcr(CPU_DPR5_U); - break; - case 6: - dpr_l->U = __mfcr(CPU_DPR6_L); - dpr_u->U = __mfcr(CPU_DPR6_U); - break; - case 7: - dpr_l->U = __mfcr(CPU_DPR7_L); - dpr_u->U = __mfcr(CPU_DPR7_U); - break; - case 8: - dpr_l->U = __mfcr(CPU_DPR8_L); - dpr_u->U = __mfcr(CPU_DPR8_U); - break; - case 9: - dpr_l->U = __mfcr(CPU_DPR9_L); - dpr_u->U = __mfcr(CPU_DPR9_U); - break; - case 10: - dpr_l->U = __mfcr(CPU_DPR10_L); - dpr_u->U = __mfcr(CPU_DPR10_U); - break; - case 11: - dpr_l->U = __mfcr(CPU_DPR11_L); - dpr_u->U = __mfcr(CPU_DPR11_U); - break; - case 12: - dpr_l->U = __mfcr(CPU_DPR12_L); - dpr_u->U = __mfcr(CPU_DPR12_U); - break; - case 13: - dpr_l->U = __mfcr(CPU_DPR13_L); - dpr_u->U = __mfcr(CPU_DPR13_U); - break; - case 14: - dpr_l->U = __mfcr(CPU_DPR14_L); - dpr_u->U = __mfcr(CPU_DPR14_U); - break; - case 15: - dpr_l->U = __mfcr(CPU_DPR15_L); - dpr_u->U = __mfcr(CPU_DPR15_U); - break; - case 16: - dpr_l->U = __mfcr(CPU_DPR16_L); - dpr_u->U = __mfcr(CPU_DPR16_U); - break; - case 17: - dpr_l->U = __mfcr(CPU_DPR17_L); - dpr_u->U = __mfcr(CPU_DPR17_U); - break; -#ifndef CONFIG_ARCH_CHIP_TC3XX - case 18: - dpr_l->U = __mfcr(CPU_DPR18_L); - dpr_u->U = __mfcr(CPU_DPR18_U); - break; - case 19: - dpr_l->U = __mfcr(CPU_DPR19_L); - dpr_u->U = __mfcr(CPU_DPR19_U); - break; - case 20: - dpr_l->U = __mfcr(CPU_DPR20_L); - dpr_u->U = __mfcr(CPU_DPR20_U); - break; - case 21: - dpr_l->U = __mfcr(CPU_DPR21_L); - dpr_u->U = __mfcr(CPU_DPR21_U); - break; - case 22: - dpr_l->U = __mfcr(CPU_DPR22_L); - dpr_u->U = __mfcr(CPU_DPR22_U); - break; - case 23: - dpr_l->U = __mfcr(CPU_DPR23_L); - dpr_u->U = __mfcr(CPU_DPR23_U); - break; -#endif - default: - return -EINVAL; - } - - return 0; -} - -static void set_dpr_address_value(unsigned int region, - Ifx_CPU_DPR_L dpr_l, - Ifx_CPU_DPR_U dpr_u) -{ - switch (region) - { - case 0: - __mtcr(CPU_DPR0_L, dpr_l.U); - __mtcr(CPU_DPR0_U, dpr_u.U); - break; - case 1: - __mtcr(CPU_DPR1_L, dpr_l.U); - __mtcr(CPU_DPR1_U, dpr_u.U); - break; - case 2: - __mtcr(CPU_DPR2_L, dpr_l.U); - __mtcr(CPU_DPR2_U, dpr_u.U); - break; - case 3: - __mtcr(CPU_DPR3_L, dpr_l.U); - __mtcr(CPU_DPR3_U, dpr_u.U); - break; - case 4: - __mtcr(CPU_DPR4_L, dpr_l.U); - __mtcr(CPU_DPR4_U, dpr_u.U); - break; - case 5: - __mtcr(CPU_DPR5_L, dpr_l.U); - __mtcr(CPU_DPR5_U, dpr_u.U); - break; - case 6: - __mtcr(CPU_DPR6_L, dpr_l.U); - __mtcr(CPU_DPR6_U, dpr_u.U); - break; - case 7: - __mtcr(CPU_DPR7_L, dpr_l.U); - __mtcr(CPU_DPR7_U, dpr_u.U); - break; - case 8: - __mtcr(CPU_DPR8_L, dpr_l.U); - __mtcr(CPU_DPR8_U, dpr_u.U); - break; - case 9: - __mtcr(CPU_DPR9_L, dpr_l.U); - __mtcr(CPU_DPR9_U, dpr_u.U); - break; - case 10: - __mtcr(CPU_DPR10_L, dpr_l.U); - __mtcr(CPU_DPR10_U, dpr_u.U); - break; - case 11: - __mtcr(CPU_DPR11_L, dpr_l.U); - __mtcr(CPU_DPR11_U, dpr_u.U); - break; - case 12: - __mtcr(CPU_DPR12_L, dpr_l.U); - __mtcr(CPU_DPR12_U, dpr_u.U); - break; - case 13: - __mtcr(CPU_DPR13_L, dpr_l.U); - __mtcr(CPU_DPR13_U, dpr_u.U); - break; - case 14: - __mtcr(CPU_DPR14_L, dpr_l.U); - __mtcr(CPU_DPR14_U, dpr_u.U); - break; - case 15: - __mtcr(CPU_DPR15_L, dpr_l.U); - __mtcr(CPU_DPR15_U, dpr_u.U); - break; - case 16: - __mtcr(CPU_DPR16_L, dpr_l.U); - __mtcr(CPU_DPR16_U, dpr_u.U); - break; - case 17: - __mtcr(CPU_DPR17_L, dpr_l.U); - __mtcr(CPU_DPR17_U, dpr_u.U); - break; -#ifndef CONFIG_ARCH_CHIP_TC3XX - case 18: - __mtcr(CPU_DPR18_L, dpr_l.U); - __mtcr(CPU_DPR18_U, dpr_u.U); - break; - case 19: - __mtcr(CPU_DPR19_L, dpr_l.U); - __mtcr(CPU_DPR19_U, dpr_u.U); - break; - case 20: - __mtcr(CPU_DPR20_L, dpr_l.U); - __mtcr(CPU_DPR20_U, dpr_u.U); - break; - case 21: - __mtcr(CPU_DPR21_L, dpr_l.U); - __mtcr(CPU_DPR21_U, dpr_u.U); - break; - case 22: - __mtcr(CPU_DPR22_L, dpr_l.U); - __mtcr(CPU_DPR22_U, dpr_u.U); - break; - case 23: - __mtcr(CPU_DPR23_L, dpr_l.U); - __mtcr(CPU_DPR23_U, dpr_u.U); - break; -#endif - default: - break; - } - - UP_ISB(); -} - -static int get_cpr_address_region(unsigned int region, - Ifx_CPU_CPR_L *cpr_l, - Ifx_CPU_CPR_U *cpr_u) -{ - switch (region) - { - case 0: - cpr_l->U = __mfcr(CPU_CPR0_L); - cpr_u->U = __mfcr(CPU_CPR0_U); - break; - case 1: - cpr_l->U = __mfcr(CPU_CPR1_L); - cpr_u->U = __mfcr(CPU_CPR1_U); - break; - case 2: - cpr_l->U = __mfcr(CPU_CPR2_L); - cpr_u->U = __mfcr(CPU_CPR2_U); - break; - case 3: - cpr_l->U = __mfcr(CPU_CPR3_L); - cpr_u->U = __mfcr(CPU_CPR3_U); - break; - case 4: - cpr_l->U = __mfcr(CPU_CPR4_L); - cpr_u->U = __mfcr(CPU_CPR4_U); - break; - case 5: - cpr_l->U = __mfcr(CPU_CPR5_L); - cpr_u->U = __mfcr(CPU_CPR5_U); - break; - case 6: - cpr_l->U = __mfcr(CPU_CPR6_L); - cpr_u->U = __mfcr(CPU_CPR6_U); - break; - case 7: - cpr_l->U = __mfcr(CPU_CPR7_L); - cpr_u->U = __mfcr(CPU_CPR7_U); - break; - case 8: - cpr_l->U = __mfcr(CPU_CPR8_L); - cpr_u->U = __mfcr(CPU_CPR8_U); - break; - case 9: - cpr_l->U = __mfcr(CPU_CPR9_L); - cpr_u->U = __mfcr(CPU_CPR9_U); - break; -#ifndef CONFIG_ARCH_CHIP_TC3XX - case 10: - cpr_l->U = __mfcr(CPU_CPR10_L); - cpr_u->U = __mfcr(CPU_CPR10_U); - break; - case 11: - cpr_l->U = __mfcr(CPU_CPR11_L); - cpr_u->U = __mfcr(CPU_CPR11_U); - break; - case 12: - cpr_l->U = __mfcr(CPU_CPR12_L); - cpr_u->U = __mfcr(CPU_CPR12_U); - break; - case 13: - cpr_l->U = __mfcr(CPU_CPR13_L); - cpr_u->U = __mfcr(CPU_CPR13_U); - break; - case 14: - cpr_l->U = __mfcr(CPU_CPR14_L); - cpr_u->U = __mfcr(CPU_CPR14_U); - break; - case 15: - cpr_l->U = __mfcr(CPU_CPR15_L); - cpr_u->U = __mfcr(CPU_CPR15_U); - break; -#endif - default: - return -EINVAL; - } - - return 0; -} - -static void set_cpr_address_value(unsigned int region, - Ifx_CPU_CPR_L cpr_l, - Ifx_CPU_CPR_U cpr_u) -{ - switch (region) - { - case 0: - __mtcr(CPU_CPR0_L, cpr_l.U); - __mtcr(CPU_CPR0_U, cpr_u.U); - break; - case 1: - __mtcr(CPU_CPR1_L, cpr_l.U); - __mtcr(CPU_CPR1_U, cpr_u.U); - break; - case 2: - __mtcr(CPU_CPR2_L, cpr_l.U); - __mtcr(CPU_CPR2_U, cpr_u.U); - break; - case 3: - __mtcr(CPU_CPR3_L, cpr_l.U); - __mtcr(CPU_CPR3_U, cpr_u.U); - break; - case 4: - __mtcr(CPU_CPR4_L, cpr_l.U); - __mtcr(CPU_CPR4_U, cpr_u.U); - break; - case 5: - __mtcr(CPU_CPR5_L, cpr_l.U); - __mtcr(CPU_CPR5_U, cpr_u.U); - break; - case 6: - __mtcr(CPU_CPR6_L, cpr_l.U); - __mtcr(CPU_CPR6_U, cpr_u.U); - break; - case 7: - __mtcr(CPU_CPR7_L, cpr_l.U); - __mtcr(CPU_CPR7_U, cpr_u.U); - break; - case 8: - __mtcr(CPU_CPR8_L, cpr_l.U); - __mtcr(CPU_CPR8_U, cpr_u.U); - break; - case 9: - __mtcr(CPU_CPR9_L, cpr_l.U); - __mtcr(CPU_CPR9_U, cpr_u.U); - break; -#ifndef CONFIG_ARCH_CHIP_TC3XX - case 10: - __mtcr(CPU_CPR10_L, cpr_l.U); - __mtcr(CPU_CPR10_U, cpr_u.U); - break; - case 11: - __mtcr(CPU_CPR11_L, cpr_l.U); - __mtcr(CPU_CPR11_U, cpr_u.U); - break; - case 12: - __mtcr(CPU_CPR12_L, cpr_l.U); - __mtcr(CPU_CPR12_U, cpr_u.U); - break; - case 13: - __mtcr(CPU_CPR13_L, cpr_l.U); - __mtcr(CPU_CPR13_U, cpr_u.U); - break; - case 14: - __mtcr(CPU_CPR14_L, cpr_l.U); - __mtcr(CPU_CPR14_U, cpr_u.U); - break; - case 15: - __mtcr(CPU_CPR15_L, cpr_l.U); - __mtcr(CPU_CPR15_U, cpr_u.U); - break; -#endif - } - - UP_ISB(); -} - -static void mpu_modify_data_region(unsigned int region, uintptr_t base, - size_t size) -{ - /* Check valid */ - - DEBUGASSERT(region < CONFIG_ARCH_MPU_DATA_NREGIONS); - - Ifx_CPU_DPR_L dpr_l_value; - Ifx_CPU_DPR_U dpr_u_value; - dpr_l_value.U = base; - dpr_u_value.U = base + size; - - /* Set the lower bound and upper bound of CPU Data Protection Region */ - - set_dpr_address_value(region, dpr_l_value, dpr_u_value); -} - -static void mpu_modify_code_region(unsigned int region, uintptr_t base, - size_t size) -{ - /* Check valid */ - - DEBUGASSERT(region < CONFIG_ARCH_MPU_CODE_NREGIONS); - - Ifx_CPU_CPR_L cpr_l_value; - Ifx_CPU_CPR_U cpr_u_value; - cpr_l_value.U = base; - cpr_u_value.U = base + size; - - /* Set the lower bound and upper bound of CPU Code Protection Region */ - - set_cpr_address_value(region, cpr_l_value, cpr_u_value); -} - -static void mpu_modify_data_set(unsigned int set, unsigned int region, - int flags) -{ - /* Check valid */ - - DEBUGASSERT(set < CONFIG_ARCH_MPU_NSETS); - DEBUGASSERT(region < CONFIG_ARCH_MPU_DATA_NREGIONS); - - Ifx_CPU_DPRE dpre_value = get_dpre_value(set); - Ifx_CPU_DPWE dpwe_value = get_dpwe_value(set); - - /* Set the bit corresponding to the given Data Protection Region */ - - dpre_value.U = flags & REGION_ATTR_RE ? - dpre_value.U | (0x01 << region) : - dpre_value.U & ~(0x01 << region); - dpwe_value.U = flags & REGION_ATTR_WE ? - dpwe_value.U | (0x01 << region) : - dpwe_value.U & ~(0x01 << region); - - set_dpre_value(set, dpre_value); - set_dpwe_value(set, dpwe_value); -} - -static void mpu_modify_code_set(unsigned int set, unsigned int region, - int flags) -{ - /* Check valid */ - - DEBUGASSERT(set < CONFIG_ARCH_MPU_NSETS); - DEBUGASSERT(region < CONFIG_ARCH_MPU_CODE_NREGIONS); - - /* Get the CPU CPXE register value of the input protection set */ - - Ifx_CPU_CPXE cpxe_value = get_cpxe_value(set); - - /* Set the bit corresponding to the given code protection region */ - - cpxe_value.U = flags & REGION_ATTR_XE ? - cpxe_value.U | (0x1 << region) : - cpxe_value.U & ~(0x1 << region); - - /* Set the CPU CPXE value to enable code execution */ - - set_cpxe_value(set, cpxe_value); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: mpu_allocdataregions - * - * Description: - * Allocate data regions - * - * Input Parameters: - * nregions - Number of regions to allocate. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -unsigned int mpu_allocdataregions(unsigned int nregions) -{ - unsigned int i = ffs(~g_mpu_data_region) - 1; - - /* There are not enough regions to apply */ - - DEBUGASSERT((i + nregions - 1) < CONFIG_ARCH_MPU_DATA_NREGIONS); - - g_mpu_data_region |= ((1 << nregions) - 1) << i; - return i; -} - -/**************************************************************************** - * Name: mpu_alloccoderegions - * - * Description: - * Allocate code regions - * - * Input Parameters: - * nregions - Number of regions to allocate. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -unsigned int mpu_alloccoderegions(unsigned int nregions) -{ - unsigned int i = ffs(~g_mpu_code_region) - 1; - - /* There are not enough regions to apply */ - - DEBUGASSERT((i + nregions - 1) < CONFIG_ARCH_MPU_CODE_NREGIONS); - - g_mpu_code_region |= ((1 << nregions) - 1) << i; - return i; -} - -/**************************************************************************** - * Name: mpu_freedataregion - * - * Description: - * Free data region - * - * Input Parameters: - * region - Region to free. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void mpu_freedataregion(unsigned int region) -{ - DEBUGASSERT(region < CONFIG_ARCH_MPU_DATA_NREGIONS); - - mpu_modify_data_region(region, 0, 0); - - g_mpu_data_region &= ~(1 << region); -} - -/**************************************************************************** - * Name: mpu_freecoderegion - * - * Description: - * Free code region - * - * Input Parameters: - * region - Region to free. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void mpu_freecoderegion(unsigned int region) -{ - DEBUGASSERT(region < CONFIG_ARCH_MPU_CODE_NREGIONS); - - mpu_modify_code_region(region, 0, 0); - - g_mpu_code_region &= ~(1 << region); -} - -/**************************************************************************** - * Name: mpu_allocregions - * - * Description: - * Allocate data or code regions - * - * Input Parameters: - * nregions - Number of regions to allocate. - * flags - Region flags. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -unsigned int mpu_allocregions(unsigned int nregions, int flags) -{ - if ((flags & REGION_TYPE_MASK) == REGION_TYPE_CODE) - { - return mpu_alloccoderegions(nregions); - } - else - { - return mpu_allocdataregions(nregions); - } -} - -/**************************************************************************** - * Name: mpu_freeregion - * - * Description: - * Free data region - * - * Input Parameters: - * flags - Region flags. - * region - Region to free. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void mpu_freeregion(unsigned int region, int flags) -{ - if ((flags & REGION_TYPE_MASK) == REGION_TYPE_CODE) - { - mpu_freecoderegion(region); - } - else - { - mpu_freedataregion(region); - } -} - -/**************************************************************************** - * Name: mpu_alloc_set - * - * Description: - * Allocate a protection set - * - * Input Parameters: - * None - * - * Returned Value: - * The index of the allocated set. - * - ****************************************************************************/ - -unsigned int mpu_alloc_set(void) -{ - unsigned int i = ffs(~g_mpu_set) - 1; - - /* There are not enough set to apply */ - - DEBUGASSERT(i < CONFIG_ARCH_MPU_NSETS); - - g_mpu_set |= 1 << i; - - return i; -} - -/**************************************************************************** - * Name: mpu_free_set - * - * Description: - * Free a protection set - * - * Input Parameters: - * set - Set to free. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void mpu_free_set(unsigned int set) -{ - DEBUGASSERT(set < CONFIG_ARCH_MPU_NSETS); - g_mpu_set &= ~(1 << set); -} - -/**************************************************************************** - * Name: mpu_control - * - * Description: - * Configure and enable (or disable) the MPU - * - * Input Parameters: - * enable - Flag indicating whether to enable the MPU. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_control(bool enable) -{ - Ifx_CPU_CORECON corecon_value; - - corecon_value.U = __mfcr(CPU_CORECON); - corecon_value.B.PROTEN = enable; - __mtcr(CPU_CORECON, corecon_value.U); - - UP_ISB(); -} - -/**************************************************************************** - * Name: mpu_dump_set - * - * Description: - * Dump the regions of a protection set. - * - * Input Parameters: - * set - protection set. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_dump_set(unsigned int set) -{ - /* Check valid */ - - DEBUGASSERT(set < CONFIG_ARCH_MPU_NSETS); - - Ifx_CPU_DPRE dpre_value = get_dpre_value(set); - Ifx_CPU_DPWE dpwe_value = get_dpwe_value(set); - Ifx_CPU_CPXE cpxe_value = get_cpxe_value(set); - Ifx_CPU_DPR_L dprl_value; - Ifx_CPU_DPR_U dpru_value; - Ifx_CPU_CPR_L cprl_value; - Ifx_CPU_CPR_U cpru_value; - unsigned int i; - int ret; - - _info("data regions:\n"); - for (i = 0; i < CONFIG_ARCH_MPU_DATA_NREGIONS; i++) - { - ret = get_dpr_addrass_value(i, &dprl_value, &dpru_value); - if (ret == 0) - { - _info("region: %02d, lower address: 0x%08X, \ - upper address: 0x%08X, \ - read enable:%s, write enable:%s\n", - i, dprl_value.U, dpru_value.U, - dpre_value.U & (0x01 << i) ? "yes" : "no", - dpwe_value.U & (0x01 << i) ? "yes" : "no"); - } - else - { - _info("region: %02d, get region info fail\n", i); - } - } - - _info("code regions :\n"); - for (i = 0; i < CONFIG_ARCH_MPU_CODE_NREGIONS; i++) - { - ret = get_cpr_address_region(i, &cprl_value, &cpru_value); - if (ret == 0) - { - _info("region: %02d, lower address: 0x%08X, \ - upper address: 0x%08X, \ - exec enable:%s\n", - i, cprl_value.U, cpru_value.U, - cpxe_value.U & (0x01 << i) ? "yes" : "no"); - } - else - { - _info("region: %02d, get region info fail\n", i); - } - } -} - -/**************************************************************************** - * Name: mpu_dump_regions - * - * Description: - * Dump the regions of all sets. - * - * Input Parameters: - * set - protection set. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_dump_regions(void) -{ - unsigned int i; - - _info("active set is: %02d\n", mpu_get_active_set()); - _info("dump all sets info:\n"); - - for (i = 0; i < CONFIG_ARCH_MPU_NSETS; i++) - { - if (g_mpu_set & (1 << i)) - { - _info("set %02d:\n", i); - mpu_dump_set(i); - } - } -} - -/**************************************************************************** - * Name: mpu_modify_region - * - * Description: - * Modify a region's attributes in the special protection set. - * - * Input Parameters: - * set - Set number to modify. - * region - Region number to modify. - * base - Base address of the region. - * size - Size of the region. - * flags - Flags to configure the region. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_modify_region(unsigned int set, unsigned int region, - uintptr_t base, size_t size, int flags) -{ - if ((flags & REGION_TYPE_MASK) == REGION_TYPE_CODE) - { - if (size != 0) - { - mpu_modify_code_region(region, base, base + size); - } - - mpu_modify_code_set(set, region, flags); - } - else - { - if (size != 0) - { - mpu_modify_data_region(region, base, base + size); - } - - mpu_modify_data_set(set, region, flags); - } -} - -/**************************************************************************** - * Name: mpu_configure_region - * - * Description: - * Configure a region's attributes in the special protection set. - * - * Input Parameters: - * set - Set number to modify. - * base - Base address of the region. - * size - Size of the region. - * flags - Flags to configure the region. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -unsigned int mpu_configure_region(unsigned int set, uintptr_t base, - size_t size, int flags) -{ - unsigned int region; - - if ((flags & REGION_TYPE_MASK) == REGION_TYPE_CODE) - { - region = mpu_alloccoderegion(); - mpu_modify_code_region(region, base, size); - mpu_modify_code_set(set, region, flags); - } - else - { - region = mpu_allocdataregion(); - mpu_modify_data_region(region, base, size); - mpu_modify_data_set(set, region, flags); - } - - return region; -} - -/**************************************************************************** - * Name: mpu_get_active_set - * - * Description: - * Get current protection set - * - * Input Parameters: - * None. - * - * Returned Value: - * Current protection set. - * - ****************************************************************************/ - -unsigned int mpu_get_active_set(void) -{ - Ifx_CPU_PSW psw_value; - - psw_value.U = __mfcr(CPU_PSW); - return (psw_value.B.PRS2 << 2) | psw_value.B.PRS; -} - -/**************************************************************************** - * Name: mpu_set_active_set - * - * Description: - * Set active protection set - * - * Input Parameters: - * Protection set . - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_set_active_set(unsigned int set) -{ - /* Check that the set valid */ - - DEBUGASSERT(set < CONFIG_ARCH_MPU_NSETS); - - Ifx_CPU_PSW psw_value; - psw_value.U = __mfcr(CPU_PSW); - psw_value.B.PRS2 = set >> 2; /* bit[2] */ - psw_value.B.PRS = set & 0x03; /* bit[1:0] */ - __mtcr(CPU_PSW, psw_value.U); - - UP_ISB(); -} - -/**************************************************************************** - * Name: mpu_initialize - * - * Description: - * Initialize the MPU regions. - * - * Input Parameters: - * table - MPU initialization table. - * count - Initialize the number of entries in the region table. - * - * Returned Value: - * NULL. - * - ****************************************************************************/ - -void mpu_initialize(const struct mpu_region_s *table, size_t count) -{ - const struct mpu_region_s *conf; - unsigned int kset = mpu_alloc_set(); -#ifdef CONFIG_BUILD_PROTECTED - unsigned int uset = mpu_alloc_set(); -#endif - unsigned int region; - size_t index; - - mpu_control(false); - for (index = 0; index < count; index++) - { - conf = &table[index]; - - if ((conf->kflags & REGION_TYPE_MASK) == REGION_TYPE_CODE) - { - region = mpu_alloccoderegion(); - mpu_modify_code_region(region, conf->base, conf->size); - mpu_modify_code_set(kset, region, conf->kflags); -#ifdef CONFIG_BUILD_PROTECTED - mpu_modify_code_set(uset, region, conf->uflags); -#endif - } - else - { - region = mpu_allocdataregion(); - mpu_modify_data_region(region, conf->base, conf->size); - mpu_modify_data_set(kset, region, conf->kflags); - #ifdef CONFIG_BUILD_PROTECTED - mpu_modify_data_set(uset, region, conf->uflags); - #endif - } - } - - mpu_set_active_set(kset); - mpu_control(true); -} diff --git a/arch/tricore/src/common/tricore_mpu.h b/arch/tricore/src/common/tricore_mpu.h deleted file mode 100644 index 4ddb597d3afc9..0000000000000 --- a/arch/tricore/src/common/tricore_mpu.h +++ /dev/null @@ -1,382 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/tricore_mpu.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_SRC_COMMON_TRICORE_MPU_H -#define __ARCH_TRICORE_SRC_COMMON_TRICORE_MPU_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* MPU Region Attributes Bit Definitions */ - -#define REGION_TYPE_SHIFT 0 -#define REGION_TYPE_MASK (0x03 << REGION_TYPE_SHIFT) -#define REGION_TYPE_CODE (0x01 << REGION_TYPE_SHIFT) -#define REGION_TYPE_DATA (0x02 << REGION_TYPE_SHIFT) - -#define REGION_ATTR_SHIFT 2 -#define REGION_ATTR_MASK (0x07 << REGION_ATTR_SHIFT) -#define REGION_ATTR_RE (0x01 << REGION_ATTR_SHIFT) -#define REGION_ATTR_WE (0x02 << REGION_ATTR_SHIFT) -#define REGION_ATTR_XE (0x04 << REGION_ATTR_SHIFT) -#define REGION_ATTR_RO REGION_ATTR_RE -#define REGION_ATTR_WO REGION_ATTR_WE -#define REGION_ATTR_RW (REGION_ATTR_RE | REGION_ATTR_WE) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -struct mpu_region_s -{ - uintptr_t base; - size_t size; - int kflags; - int uflags; -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: mpu_allocdataregions - * - * Description: - * Allocate data regions - * - * Input Parameters: - * nregions - Number of regions to allocate. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -unsigned int mpu_allocdataregions(unsigned int nregions); - -/**************************************************************************** - * Name: mpu_alloccoderegions - * - * Description: - * Allocate code regions - * - * Input Parameters: - * nregions - Number of regions to allocate. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -unsigned int mpu_alloccoderegions(unsigned int nregions); - -/**************************************************************************** - * Name: mpu_allocdataregion - * - * Description: - * Allocate data region - * - * Input Parameters: - * nregions - Number of regions to allocate. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -#define mpu_allocdataregion() mpu_allocdataregions(1) - -/**************************************************************************** - * Name: mpu_alloccoderegion - * - * Description: - * Allocate code region - * - * Input Parameters: - * nregions - Number of regions to allocate. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -#define mpu_alloccoderegion() mpu_alloccoderegions(1) - -/**************************************************************************** - * Name: mpu_freedataregion - * - * Description: - * Free data region - * - * Input Parameters: - * region - Region to free. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void mpu_freedataregion(unsigned int region); - -/**************************************************************************** - * Name: mpu_freecoderegion - * - * Description: - * Free code region - * - * Input Parameters: - * region - Region to free. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void mpu_freecoderegion(unsigned int region); - -/**************************************************************************** - * Name: mpu_allocregions - * - * Description: - * Allocate data or code regions - * - * Input Parameters: - * nregions - Number of regions to allocate. - * flags - Region flags. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -unsigned int mpu_allocregions(unsigned int nregions, int flags); - -/**************************************************************************** - * Name: mpu_allocregion - * - * Description: - * Allocate the next region - * - * Input Parameters: - * flags - Region flags. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -#define mpu_allocregion(flags) mpu_allocregions(1, flags) - -/**************************************************************************** - * Name: mpu_freeregion - * - * Description: - * Free data region - * - * Input Parameters: - * region - Region to free. - * flags - Region flags. - * Returned Value: - * None - * - ****************************************************************************/ - -void mpu_freeregion(unsigned int region, int flags); - -/**************************************************************************** - * Name: mpu_alloc_set - * - * Description: - * Allocate a protection set - * - * Input Parameters: - * None - * - * Returned Value: - * The index of the allocated set. - * - ****************************************************************************/ - -unsigned int mpu_alloc_set(void); - -/**************************************************************************** - * Name: mpu_free_set - * - * Description: - * Free a protection set - * - * Input Parameters: - * set - Set to free. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void mpu_free_set(unsigned int set); - -/**************************************************************************** - * Name: mpu_control - * - * Description: - * Configure and enable (or disable) the MPU - * - * Input Parameters: - * enable - Flag indicating whether to enable the MPU. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_control(bool enable); - -/**************************************************************************** - * Name: mpu_dump_set - * - * Description: - * Dump the regions of a protection set. - * - * Input Parameters: - * set - protection set. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_dump_set(unsigned int set); - -/**************************************************************************** - * Name: mpu_dump_regions - * - * Description: - * Dump the regions of all sets. - * - * Input Parameters: - * set - protection set. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_dump_regions(void); - -/**************************************************************************** - * Name: mpu_modify_region - * - * Description: - * Modify a region's attributes in the special protection set. - * - * Input Parameters: - * set - Set number to modify. - * region - Region number to modify. - * base - Base address of the region. - * size - Size of the region. - * flags - Flags to configure the region. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_modify_region(unsigned int set, unsigned int region, - uintptr_t base, size_t size, int flags); - -/**************************************************************************** - * Name: mpu_configure_region - * - * Description: - * Configure a region's attributes in the special protection set. - * - * Input Parameters: - * set - Set number to modify. - * base - Base address of the region. - * size - Size of the region. - * flags - Flags to configure the region. - * - * Returned Value: - * The index of the allocated region. - * - ****************************************************************************/ - -unsigned int mpu_configure_region(unsigned int set, uintptr_t base, - size_t size, int flags); - -/**************************************************************************** - * Name: mpu_get_active_set - * - * Description: - * Get the active protection set. - * - * Input Parameters: - * None. - * - * Returned Value: - * The active protection set. - * - ****************************************************************************/ - -unsigned int mpu_get_active_set(void); - -/**************************************************************************** - * Name: mpu_set_active_set - * - * Description: - * Set the active protection set. - * - * Input Parameters: - * set - The protection set to activate. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void mpu_set_active_set(unsigned int set); - -/**************************************************************************** - * Name: mpu_initialize - * - * Description: - * Initialize the MPU regions. - * - * Input Parameters: - * table - MPU initialization table. - * count - Initialize the number of entries in the region table. - * - * Returned Value: - * NULL. - * - ****************************************************************************/ - -void mpu_initialize(const struct mpu_region_s *table, size_t count); - -#endif /* __ARCH_TRICORE_SRC_COMMON_TRICORE_MPU_H */ diff --git a/arch/tricore/src/common/tricore_perf.c b/arch/tricore/src/common/tricore_perf.c deleted file mode 100644 index 987c9f12023c0..0000000000000 --- a/arch/tricore/src/common/tricore_perf.c +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/tricore_perf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "tricore_internal.h" - -#ifdef CONFIG_ARCH_PERF_EVENTS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static unsigned long g_cpu_freq = ULONG_MAX; -static invdiv_param64_t g_invdiv_param; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void up_perf_init(void *arg) -{ - g_cpu_freq = (unsigned long)(uintptr_t)arg; - - invdiv_init_param64(g_cpu_freq, &g_invdiv_param); - IfxCpu_resetAndStartCounters(IfxCpu_CounterMode_normal); -} - -unsigned long up_perf_getfreq(void) -{ - return g_cpu_freq; -} - -clock_t up_perf_gettime(void) -{ - return (clock_t)IfxCpu_getClockCounter(); -} - -void up_perf_convert(clock_t elapsed, struct timespec *ts) -{ - clock_t left; - - ts->tv_sec = invdiv_u64(elapsed, &g_invdiv_param); - left = elapsed - ts->tv_sec * g_cpu_freq; - ts->tv_nsec = invdiv_u64(NSEC_PER_SEC * (uint64_t)left, &g_invdiv_param); -} -#endif diff --git a/arch/tricore/src/common/tricore_systimer.c b/arch/tricore/src/common/tricore_systimer.c deleted file mode 100644 index 3e8a0470b35eb..0000000000000 --- a/arch/tricore/src/common/tricore_systimer.c +++ /dev/null @@ -1,328 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/tricore_systimer.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include "tricore_internal.h" - -#include "IfxStm.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Since the tricore hardware timer triggers an interrupt only when the - * compare value is equal to the counter, setting a compare value that has - * already timed out will not trigger an interrupt. To avoid missing - * interrupts when setting the timer, we should set a minimum delay. - * The minimum delay is calculated based on the CPU frequency and the timer - * frequency. We assume that the worst-case execution time for setting the - * timer does not exceed 40 CPU cycles, and calculate the minimum timer - * delay accordingly. - * 40 CPU cycles (100ns at 400Mhz) ~ 10 timer cycles (for 100 Mhz timer). - */ - -#define IFX_CFG_CPU_CLOCK_FREQUENCY 100000000 - -#define TRICORE_SYSTIMER_MIN_DELAY \ - (40ull * SCU_FREQUENCY / IFX_CFG_CPU_CLOCK_FREQUENCY) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * oneshot_lowerhalf_s structure. - */ - -struct tricore_systimer_lowerhalf_s -{ - struct oneshot_lowerhalf_s lower; - volatile void *tbase; - spinlock_t lock; -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static uint64_t -tricore_systimer_get_time(struct tricore_systimer_lowerhalf_s *priv) -{ - irqstate_t flags; - uint64_t ticks; - - flags = spin_lock_irqsave(&priv->lock); - - ticks = IfxStm_get(priv->tbase); - - spin_unlock_irqrestore(&priv->lock, flags); - - return ticks; -} - -static void -tricore_systimer_set_timecmp(struct tricore_systimer_lowerhalf_s *priv, - uint64_t value) -{ - irqstate_t flags; - - flags = spin_lock_irqsave(&priv->lock); - - IfxStm_updateCompare(priv->tbase, IfxStm_Comparator_0, value); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: tricore_systimer_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * - * Returned Value: - * The maximum delay value. - * - ****************************************************************************/ - -static clkcnt_t tricore_systimer_max_delay(struct oneshot_lowerhalf_s *lower) -{ - return UINT32_MAX; -} - -/**************************************************************************** - * Name: tricore_systimer_start - * - * Description: - * Start the oneshot timer. Note that the tricore systimer is special, the - * IRQ is only triggered when timecmp == mtime, so we should avoid the case - * that we miss the timecmp. - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * delta Provides the duration of delta count. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void tricore_systimer_start(struct oneshot_lowerhalf_s *lower, - clkcnt_t delta) -{ - struct tricore_systimer_lowerhalf_s *priv = - (struct tricore_systimer_lowerhalf_s *)lower; - irqstate_t flags; - uint64_t mtime; - - delta = delta < TRICORE_SYSTIMER_MIN_DELAY ? - TRICORE_SYSTIMER_MIN_DELAY : delta; - flags = up_irq_save(); - mtime = tricore_systimer_get_time(priv); - - tricore_systimer_set_timecmp(priv, mtime + delta); - - up_irq_restore(flags); -} - -/**************************************************************************** - * Name: tricore_systimer_start_absolute - * - * Description: - * Start the oneshot timer. Note that the tricore systimer is special, the - * IRQ is only triggered when timecmp == mtime, so we should avoid the case - * that we miss the timecmp. - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * expected Target - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void -tricore_systimer_start_absolute(struct oneshot_lowerhalf_s *lower, - clkcnt_t expected) -{ - struct tricore_systimer_lowerhalf_s *priv = - (struct tricore_systimer_lowerhalf_s *)lower; - - irqstate_t flags = up_irq_save(); - uint64_t min_expected = tricore_systimer_get_time(priv) + - TRICORE_SYSTIMER_MIN_DELAY; - expected = expected < min_expected ? min_expected : expected; - tricore_systimer_set_timecmp(priv, expected); - - up_irq_restore(flags); -} - -/**************************************************************************** - * Name: tricore_systimer_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * lower Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void tricore_systimer_cancel(struct oneshot_lowerhalf_s *lower) -{ - struct tricore_systimer_lowerhalf_s *priv = - (struct tricore_systimer_lowerhalf_s *)lower; - - tricore_systimer_set_timecmp(priv, UINT64_MAX); -} - -/**************************************************************************** - * Name: tricore_systimer_current - * - * Description: - * Get the current time. - * - * Input Parameters: - * lower Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * - * Returned Value: - * Current timer count. - * - ****************************************************************************/ - -static clkcnt_t tricore_systimer_current(struct oneshot_lowerhalf_s *lower) -{ - struct tricore_systimer_lowerhalf_s *priv = - (struct tricore_systimer_lowerhalf_s *)lower; - - return tricore_systimer_get_time(priv); -} - -/**************************************************************************** - * Name: tricore_systimer_interrupt - * - * Description: - * This function is software interrupt handler to proceed - * the system timer interrupt. - * - ****************************************************************************/ - -static int tricore_systimer_interrupt(int irq, void *context, void *arg) -{ - struct tricore_systimer_lowerhalf_s *priv = arg; - - /* We do not need to clear the compare register here. */ - - oneshot_process_callback(&priv->lower); - - return 0; -} - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct oneshot_operations_s g_tricore_oneshot_ops = -{ - .current = tricore_systimer_current, - .start = tricore_systimer_start, - .start_absolute = tricore_systimer_start_absolute, - .cancel = tricore_systimer_cancel, - .max_delay = tricore_systimer_max_delay -}; - -static struct tricore_systimer_lowerhalf_s g_tricore_oneshot_lowerhalf = -{ - .lower.ops = &g_tricore_oneshot_ops -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: tricore_systimer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -struct oneshot_lowerhalf_s * -tricore_systimer_initialize(volatile void *tbase, int irq, uint64_t freq) -{ - struct tricore_systimer_lowerhalf_s *priv = &g_tricore_oneshot_lowerhalf; - - priv->tbase = tbase; - spin_lock_init(&priv->lock); - - ASSERT(freq <= UINT32_MAX); - - oneshot_count_init(&priv->lower, (uint32_t)freq); - - IfxStm_setSuspendMode(priv->tbase, IfxStm_SuspendMode_hard); - - IfxStm_setCompareControl(tbase, - IfxStm_Comparator_0, - IfxStm_ComparatorOffset_0, - IfxStm_ComparatorSize_32Bits, - IfxStm_ComparatorInterrupt_ir0); - - IfxStm_clearCompareFlag(tbase, IfxStm_Comparator_0); - tricore_systimer_set_timecmp(priv, UINT64_MAX); - IfxStm_enableComparatorInterrupt(tbase, IfxStm_Comparator_0); - - irq_attach(irq, tricore_systimer_interrupt, priv); - up_enable_irq(irq); - - return (struct oneshot_lowerhalf_s *)priv; -} diff --git a/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h b/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h deleted file mode 100644 index ed353ea3ad47b..0000000000000 --- a/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_H -#define __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DEVICE_TC39XB 1 -#define IFX_PIN_PACKAGE_LFBGA292 1 - -#define IFX_CFG_SCU_XTAL_FREQUENCY (20000000) -#define IFX_CFG_SCU_PLL_FREQUENCY (300000000) -#define IFX_CFG_SCU_PLL1_FREQUENCY (320000000) -#define IFX_CFG_SCU_PLL2_FREQUENCY (200000000) - -#define IFX_CFG_CPU_CLOCK_FREQUENCY IFX_CFG_SCU_PLL_FREQUENCY - -#define ISR_PRIORITY_STM_TICK 1 -#define ISR_PRIORITY_GETH_DMA0_TX 2 -#define ISR_PRIORITY_GETH_DMA0_RX 3 - -#ifdef CONFIG_TRICORE_BL -# define IFX_CFG_SSW_ENABLE_TRICORE0 1 -# define IFX_CFG_SSW_ENABLE_TRICORE1 0 -# define IFX_CFG_SSW_ENABLE_TRICORE2 0 -# define IFX_CFG_SSW_ENABLE_TRICORE3 0 -# define IFX_CFG_SSW_ENABLE_TRICORE4 0 -# define IFX_CFG_SSW_ENABLE_TRICORE5 0 -#else -# define IFX_CFG_SSW_ENABLE_TRICORE0 1 -# define IFX_CFG_SSW_ENABLE_TRICORE1 1 -# define IFX_CFG_SSW_ENABLE_TRICORE2 1 -# define IFX_CFG_SSW_ENABLE_TRICORE3 1 -# define IFX_CFG_SSW_ENABLE_TRICORE4 1 -# define IFX_CFG_SSW_ENABLE_TRICORE5 1 -#endif - -#define IFX_CFG_SSW_ENABLE_INDIVIDUAL_C_INIT (1U) - -#endif /* __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_H */ diff --git a/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c b/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c deleted file mode 100644 index d52c6a9c3822c..0000000000000 --- a/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "Ifx_Cfg_Ssw.h" -#include "Ifx_Ssw_Infra.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#if defined(__TASKING__) -#pragma optimize RL -#elif defined(__GNUC__) -#pragma GCC optimize ("O1") -#endif - -#if (IFX_CFG_SSW_ENABLE_LBIST == 1) -void Ifx_Ssw_Lbist(void) -{ - if (!IfxScuLbist_isDone()) - { - if(Ifx_Ssw_isColdPoweronReset()) - { - IfxScuLbist_triggerInline(&IfxScuLbist_defaultConfig); - } - } - - if (!IfxScuLbist_evaluateResult(IfxScuLbist_defaultConfig.signature)) - { - __debug(); - while(1); - } - - Ifx_Ssw_jumpBackToLink(); -} -#endif - -#if defined(__TASKING__) -#pragma endoptimize -#elif defined(__GNUC__) -#pragma GCC reset_options -#endif diff --git a/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h b/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h deleted file mode 100644 index 2b6c5909713a5..0000000000000 --- a/arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_SSW_H -#define __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_SSW_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "Ifx_Cfg.h" -#include "Ifx_Ssw.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef IFX_CFG_SSW_ENABLE_LBIST -#define IFX_CFG_SSW_ENABLE_LBIST (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_MONBIST -#define IFX_CFG_SSW_ENABLE_MONBIST (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_PLL_INIT -#define IFX_CFG_SSW_ENABLE_PLL_INIT (1U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_MBIST -#define IFX_CFG_SSW_ENABLE_MBIST (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_SMU -#define IFX_CFG_SSW_ENABLE_SMU (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_EMEM_INIT -#define IFX_CFG_SSW_ENABLE_EMEM_INIT (0U) -#endif - -#ifndef IFX_SCU_FLASHWAITSTATECHECK -#define IFX_SCU_FLASHWAITSTATECHECK (0U) -#endif - -#if IFX_CFG_SSW_ENABLE_LBIST == 1U -#include "IfxScuLbist.h" - -extern void Ifx_Ssw_Lbist(void); -#define IFX_CFG_SSW_CALLOUT_LBIST() \ -{ \ - Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Lbist); \ -} -#endif - -#if IFX_CFG_SSW_ENABLE_MONBIST == 1U -#include "IfxSmuStdby.h" - -extern void Ifx_Ssw_Monbist(void); -#define IFX_CFG_SSW_CALLOUT_MONBIST() \ -{ \ - Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Monbist); \ -} -#endif - -#if IFX_CFG_SSW_ENABLE_PLL_INIT == 1U -#include "IfxScuCcu.h" - -#define IFX_CFG_SSW_CALLOUT_PLL_INIT() \ -{ \ - if (IfxScuCcu_init(&IfxScuCcu_defaultClockConfig) == 1) \ - { \ - __debug(); \ - } \ -} - -#endif - -#if IFX_CFG_SSW_ENABLE_MBIST == 1U -#include "IfxMtu.h" - -#define IFX_CFG_SSW_CALLOUT_MBIST() \ -{ \ - IFX_EXTERN const IfxMtu_MbistConfig *const mbistGangConfig[]; \ - if (IfxMtu_runMbistAll(mbistGangConfig) == 1U) \ - { \ - __debug(); \ - } \ -} - -#endif -#endif /* __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_SSW_H */ diff --git a/arch/tricore/src/illd/tc3xx/patches/change_illd.patch b/arch/tricore/src/illd/tc3xx/patches/change_illd.patch deleted file mode 100644 index ee7ec37bf3961..0000000000000 --- a/arch/tricore/src/illd/tc3xx/patches/change_illd.patch +++ /dev/null @@ -1,60 +0,0 @@ -diff --git a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c -index f893b3e7e4b..e86811079d2 100644 ---- a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c -+++ b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c -@@ -45,6 +45,12 @@ - /*-------------------------Infrastructure Functions---------------------------*/ - /******************************************************************************/ - -+IFX_SSW_WEAK void hardware_init_hook(void) -+{} -+ -+IFX_SSW_WEAK void software_init_hook(void) -+{} -+ - unsigned short Ifx_Ssw_getCpuWatchdogPassword(Ifx_SCU_WDTCPU *watchdog) - { - return Ifx_Ssw_getCpuWatchdogPasswordInline(watchdog); -@@ -200,6 +206,7 @@ void Ifx_Ssw_doCppInit(void) - { - Ifx_Ssw_C_InitInline(); - -+#ifndef __NuttX__ - #ifdef __TASKING__ - extern void _main(void); /* cpp initialization */ - _main(); -@@ -219,10 +226,12 @@ void Ifx_Ssw_doCppInit(void) - extern void _main(void); /* cpp initialization */ - _main(); - #endif -+#endif /* __NuttX__ */ - } - - void Ifx_Ssw_doCppExit(int status) - { -+#ifndef __NuttX__ - #ifdef __TASKING__ - extern void _doexit(void); /* cpp deinitialization */ - _doexit(); -@@ -239,7 +248,7 @@ void Ifx_Ssw_doCppExit(int status) - extern void exit(int); /* cpp deinitialization */ - exit(0); - #endif -- -+#endif /* __NuttX__ */ - } - - -diff --git a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c -index 0c6b0771bf0..4b68b8b4121 100644 ---- a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c -+++ b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c -@@ -344,7 +344,7 @@ void IfxCpu_Trap_vectorTable0(void) - /* Map Instruction Error trap to its handler for CPU0 */ - IfxCpu_Tsr_CallTSR(IfxCpu_Trap_instructionError); - /* Map Context Management Error trap to its handler for CPU0 */ -- IfxCpu_Tsr_CallCSATSR(IfxCpu_Trap_contextManagementError); -+ IfxCpu_Tsr_CallTSR(IfxCpu_Trap_contextManagementError); - /* Map Bus Error trap to its handler for CPU0 */ - IfxCpu_Tsr_CallTSR(IfxCpu_Trap_busError); - /* Map Assertion trap to its handler for CPU0 */ diff --git a/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h b/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h deleted file mode 100644 index 8ba0031e1418b..0000000000000 --- a/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_H -#define __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#define DEVICE_TC4DX 1 - -#define IFX_CFG_CLOCK_XTAL_FREQUENCY (25000000) -#define IFX_CFG_CLOCK_SYSPLL_FREQUENCY (500000000) -#define IFX_CFG_CLOCK_PPUPLL_FREQUENCY (450000000) -#define IFX_CFG_CLOCK_PERPLL1_FREQUENCY (160000000) -#define IFX_CFG_CLOCK_PERPLL2_FREQUENCY (200000000) -#define IFX_CFG_CLOCK_PERPLL3_FREQUENCY (200000000) - -#define IFX_CFG_CPU_CLOCK_FREQUENCY IFX_CFG_CLOCK_SYSPLL_FREQUENCY - -#define IFX_PROT_ENABLED 0 -#define IFX_CFG_VIRTUALIZATION_DISABLED 1 -#define IFX_CFG_STM_MORPHING_ENABLE 1 -#define IFX_CLOCK_BYPASS_FOSC_F 0 - -#define IFX_STM_RESOULTION IFX_CFG_CLOCK_SYSPLL_FREQUENCY - -#define IFX_CFG_INTERRUPT_INTERVAL (0.003) - -#define IFX_CFG_CPU0_PRIO 10 -#define IFX_CFG_CPU1_PRIO 10 -#define IFX_CFG_CPU2_PRIO 10 -#define IFX_CFG_CPU3_PRIO 10 -#define IFX_CFG_CPU4_PRIO 10 -#define IFX_CFG_CPU5_PRIO 10 - -#define ISR_PRIORITY_STM0_TICK 1 -#define ISR_PRIORITY_GETH0_DMA0_TX 2 -#define ISR_PRIORITY_GETH0_DMA0_RX 3 - -#ifdef CONFIG_TRICORE_BL -# define IFX_CFG_SSW_ENABLE_TRICORE0 1 -# define IFX_CFG_SSW_ENABLE_TRICORE1 0 -# define IFX_CFG_SSW_ENABLE_TRICORE2 0 -# define IFX_CFG_SSW_ENABLE_TRICORE3 0 -# define IFX_CFG_SSW_ENABLE_TRICORE4 0 -# define IFX_CFG_SSW_ENABLE_TRICORE5 0 -#else -# define IFX_CFG_SSW_ENABLE_TRICORE0 1 -# define IFX_CFG_SSW_ENABLE_TRICORE1 1 -# define IFX_CFG_SSW_ENABLE_TRICORE2 1 -# define IFX_CFG_SSW_ENABLE_TRICORE3 1 -# define IFX_CFG_SSW_ENABLE_TRICORE4 1 -# define IFX_CFG_SSW_ENABLE_TRICORE5 1 -#endif - -#endif /* __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_H */ diff --git a/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c b/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c deleted file mode 100644 index 42f8cff1384eb..0000000000000 --- a/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c +++ /dev/null @@ -1,211 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "Ifx_Cfg_Ssw.h" -#include "Ifx_Ssw_Infra.h" - -#if (IFX_CFG_SSW_ENABLE_LBIST == 1) -#include "IfxApProt.h" -#include "IfxTriLbist.h" -#endif - -#include "IfxVmt.h" -#include "IfxPmsPm.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#if defined(__TASKING__) -#pragma optimize RL -#elif defined(__GNUC__) -#pragma GCC optimize ("O1") -#endif - -#if (IFX_CFG_SSW_ENABLE_LBIST == 1) -void Ifx_Ssw_Lbist(void) -{ - uint16 result; - - IfxApProt_setState((Ifx_PROT_PROT *)&TRI_PROTSE, IfxApProt_State_config); - TRI_ACCEN_WRA.U = 0xFFFFFFFFU; - TRI_ACCEN_WRB.U = 0xFFFFFFFFU; - IfxApProt_setState((Ifx_PROT_PROT *)&TRI_PROTSE, IfxApProt_State_run); - - result = IfxTriLbist_evaluateResult(&IfxTriLbist_keyOnDefaultConfig.signature[0]); - - if (result) - { - if (IfxTriLbist_getFailCount() >= 2) - { - Ifx_Ssw_debug(); - } - else - { - IfxTriLbist_incrementFailCount(); - } - - IfxTriLbist_resetLbist(); - IfxTriLbist_triggerInline(&IfxTriLbist_keyOnDefaultConfig); - } -} -#endif - -#if (IFX_CFG_SSW_ENABLE_MONBIST == 1) -void Ifx_Ssw_Monbist(void) -{ -} -#endif - -#if (IFX_CFG_SSW_ENABLE_MBIST_DSPRS_DMARAM == 1) -void Ifx_Ssw_MbistDsprsDmaRam(void) -{ -} -#endif - -#if IFX_CFG_SSW_ENABLE_PLL_INIT == 1U -#include "IfxClock.h" - -void Ifx_Ssw_PowerOnCrystalOsc(void) -{ - Ifx_CLOCK_OSCCON scuOsccon; - unsigned int initError = 0U; - unsigned int timeoutCycleCount = IFX_CFG_SSW_CCUCON_LCK_BIT_TIMEOUT_COUNT; - scuOsccon.U = CLOCK_OSCCON.U; - -#if (IFX_CFG_SSW_CLOCK_EXT_CLOCK == 1) - scuOsccon.B.MODE = 2U; -#else - scuOsccon.B.MODE = 0U; -#endif - - while (CLOCK_CCUSTAT.B.LCK != 0U) - { - IFX_CFG_SSW_LOOP_TIMEOUT_CHECK(timeoutCycleCount, initError); - } - - CLOCK_OSCCON.U = scuOsccon.U; - - if (initError) - { - Ifx_Ssw_debug(); - } -} - -void Ifx_Ssw_PllInit(void) -{ - if (IfxClock_init(&IfxClock_defaultClockConfig) != 0U) - { - __debug(); - } -} -#endif - -#if IFX_CFG_SSW_ENABLE_MBIST == 1U -void Ifx_Ssw_Mbist(void) -{ - IfxVmt_clearSram(IfxVmt_MbistSel_lmu0); - IfxVmt_clearSram(IfxVmt_MbistSel_lmu1); - IfxVmt_clearSram(IfxVmt_MbistSel_lmu2); - IfxVmt_clearSram(IfxVmt_MbistSel_lmu3); - IfxVmt_clearSram(IfxVmt_MbistSel_lmu4); - IfxVmt_clearSram(IfxVmt_MbistSel_lmu5); - IfxVmt_clearSram(IfxVmt_MbistSel_lmu6); - IfxVmt_clearSram(IfxVmt_MbistSel_lmu7); - IfxVmt_clearSram(IfxVmt_MbistSel_lmu8); - IfxVmt_clearSram(IfxVmt_MbistSel_lmu9); - - /* clear CAN Message RAM */ - - IfxVmt_clearSram(IfxVmt_MbistSel_mcan0); - IfxVmt_clearSram(IfxVmt_MbistSel_mcan1); - IfxVmt_clearSram(IfxVmt_MbistSel_mcan2); - IfxVmt_clearSram(IfxVmt_MbistSel_mcan3); - IfxVmt_clearSram(IfxVmt_MbistSel_mcan4); -} -#endif - -#if IFX_CFG_SSW_ENABLE_SMU == 1U -void Ifx_Ssw_Smu(void) -{ -} -#endif - -#if (IFX_CFG_SSW_ENABLE_KEYOFF_LBIST == 1) -void Ifx_Ssw_Keyoff_Lbist(void) -{ -} -#endif - -#if IFX_CFG_SSW_ENABLE_KEYOFF_MBIST == 1U -void Ifx_Ssw_Keyoff_Mbist(void) -{ -} -#endif - -#if (IFX_CFG_SSW_ENABLE_KEYOFF_MBIST_DSPRS_DMARAM == 1) -void Ifx_Ssw_Keyoff_MbistDsprsDmaRam(void) -{ -} -#endif - -#if IFX_CFG_SSW_ENABLE_AP_INIT == 1U -void weak_function Ifx_Ssw_AP_Init(void) -{ -} -#endif - -void Ifx_Ssw_MultiCore_Sync_Cpu0(void) -{ -} - -void Ifx_Ssw_MultiCore_Sync_Cpu1(void) -{ -} - -void Ifx_Ssw_MultiCore_Sync_Cpu2(void) -{ -} - -void Ifx_Ssw_MultiCore_Sync_Cpu3(void) -{ -} - -void Ifx_Ssw_MultiCore_Sync_Cpu4(void) -{ -} - -void Ifx_Ssw_MultiCore_Sync_Cpu5(void) -{ -} - -#if defined(__TASKING__) -#pragma endoptimize -#elif defined(__GNUC__) -#pragma GCC reset_options -#endif diff --git a/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h b/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h deleted file mode 100644 index e26e3f85b88e7..0000000000000 --- a/arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_SSW_H -#define __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_SSW_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "Ifx_Cfg.h" -#include "Ifx_Ssw.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef IFX_CFG_SSW_ENABLE_LBIST -#define IFX_CFG_SSW_ENABLE_LBIST (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_MONBIST -#define IFX_CFG_SSW_ENABLE_MONBIST (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_MBIST_DSPRS_DMARAM -#define IFX_CFG_SSW_ENABLE_MBIST_DSPRS_DMARAM (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_XTALSRC_CHECK -#define IFX_CFG_SSW_ENABLE_XTALSRC_CHECK (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_PLL_INIT -#define IFX_CFG_SSW_ENABLE_PLL_INIT (1U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_MBIST -#define IFX_CFG_SSW_ENABLE_MBIST (1U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_SMU -#define IFX_CFG_SSW_ENABLE_SMU (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_AP_INIT -#define IFX_CFG_SSW_ENABLE_AP_INIT (1U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_KEYOFF_LBIST -#define IFX_CFG_SSW_ENABLE_KEYOFF_LBIST (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_KEYOFF_MBIST -#define IFX_CFG_SSW_ENABLE_KEYOFF_MBIST (0U) -#endif - -#ifndef IFX_CFG_SSW_ENABLE_KEYOFF_MBIST_DSPRS_DMARAM -#define IFX_CFG_SSW_ENABLE_KEYOFF_MBIST_DSPRS_DMARAM (0U) -#endif - -#endif /* __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_SSW_H */ diff --git a/arch/tricore/src/illd/tc4xx/patches/add_coprocessor_trap_id.patch b/arch/tricore/src/illd/tc4xx/patches/add_coprocessor_trap_id.patch deleted file mode 100644 index 4fcf2f103dfa8..0000000000000 --- a/arch/tricore/src/illd/tc4xx/patches/add_coprocessor_trap_id.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff --git a/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.h b/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.h ---- a/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.h -+++ b/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.h -@@ -99,6 +99,7 @@ - IfxCpu_Trap_InstructionErrors_Id_invalidOperand = 3U, - IfxCpu_Trap_InstructionErrors_Id_dataAddressAlignment = 4U, - IfxCpu_Trap_InstructionErrors_Id_invalidMemoryAddress = 5U, -+ IfxCpu_Trap_InstructionErrors_Id_CoprocessorTrapSynchronousError = 6U, - } IfxCpu_Trap_InstructionErrors_Id; - - /** \brief Enum for available Identification numbers under Context Management Trap. diff --git a/arch/tricore/src/illd/tc4xx/patches/change_illd.patch b/arch/tricore/src/illd/tc4xx/patches/change_illd.patch deleted file mode 100644 index 946e38af31394..0000000000000 --- a/arch/tricore/src/illd/tc4xx/patches/change_illd.patch +++ /dev/null @@ -1,33 +0,0 @@ -diff --git a/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c b/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c -index cf3c6c74010..f386599481e 100644 ---- a/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c -+++ b/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c -@@ -429,6 +429,7 @@ void Ifx_Ssw_doCppInit(void) - { - Ifx_Ssw_C_InitInline(); - -+#ifndef __NuttX__ - #ifdef __TASKING__ - extern void _main(void); /* cpp initialization */ - _main(); -@@ -451,10 +452,12 @@ void Ifx_Ssw_doCppInit(void) - #elif defined(__DCC__) - /* Cpp Init part of the init_main called in C Init Inline */ - #endif -+#endif - } - - void Ifx_Ssw_doCppExit(int status) - { -+#ifndef __NuttX__ - #ifdef __TASKING__ - extern void _doexit(void); /* cpp deinitialization */ - _doexit(); -@@ -474,6 +477,7 @@ void Ifx_Ssw_doCppExit(int status) - extern void exit(int); /* cpp deinitialization */ - exit(0); - #endif -+#endif - } - - diff --git a/arch/tricore/src/tc397/.gitignore b/arch/tricore/src/tc397/.gitignore deleted file mode 100644 index 6e279e3dd9ae5..0000000000000 --- a/arch/tricore/src/tc397/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/*_unpack -/tc397 -/*tar.gz diff --git a/arch/tricore/src/tc397/CMakeLists.txt b/arch/tricore/src/tc397/CMakeLists.txt deleted file mode 100644 index 90bed2ddc6017..0000000000000 --- a/arch/tricore/src/tc397/CMakeLists.txt +++ /dev/null @@ -1,21 +0,0 @@ -# ############################################################################## -# arch/tricore/src/tc397/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## diff --git a/arch/tricore/src/tc397/Kconfig b/arch/tricore/src/tc397/Kconfig deleted file mode 100644 index 18c7905aed7cf..0000000000000 --- a/arch/tricore/src/tc397/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - diff --git a/arch/tricore/src/tc397/Make.defs b/arch/tricore/src/tc397/Make.defs deleted file mode 100644 index 79e00f2bc279b..0000000000000 --- a/arch/tricore/src/tc397/Make.defs +++ /dev/null @@ -1,21 +0,0 @@ -############################################################################ -# arch/tricore/src/tc397/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ diff --git a/arch/tricore/src/tc397/chip.h b/arch/tricore/src/tc397/chip.h deleted file mode 100644 index 1521ff4237422..0000000000000 --- a/arch/tricore/src/tc397/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc397/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_SRC_TC397_CHIP_H -#define __ARCH_TRICORE_SRC_TC397_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#define UART_PIN_RX IfxAsclin0_RXA_P14_1_IN /* UART receive port pin */ -#define UART_PIN_TX IfxAsclin0_TX_P14_0_OUT /* UART transmit port pin */ - -#endif /* __ARCH_TRICORE_SRC_TC397_CHIP_H */ diff --git a/arch/tricore/src/tc3xx/.gitignore b/arch/tricore/src/tc3xx/.gitignore deleted file mode 100644 index 6e279e3dd9ae5..0000000000000 --- a/arch/tricore/src/tc3xx/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/*_unpack -/tc397 -/*tar.gz diff --git a/arch/tricore/src/tc3xx/CMakeLists.txt b/arch/tricore/src/tc3xx/CMakeLists.txt index ebb9ee5edb02e..b21d9f0465783 100644 --- a/arch/tricore/src/tc3xx/CMakeLists.txt +++ b/arch/tricore/src/tc3xx/CMakeLists.txt @@ -19,143 +19,3 @@ # the License. # # ############################################################################## - -set(SRCS tc3xx_timerisr.c tc3xx_serial.c) - -target_sources(arch PRIVATE ${SRCS}) - -if(CONFIG_TRICORE_TOOLCHAIN_TASKING) - nuttx_add_kernel_library(c_fpu) - target_sources(c_fpu PRIVATE tc3xx_libc.c) - target_link_options( - nuttx PRIVATE - --library-directory=${CMAKE_BINARY_DIR}/arch/tricore/src/exclude_chip) -endif() - -set(ILLD_UNPACK "${CMAKE_CURRENT_SOURCE_DIR}/../illd/tc3xx") -set(ILLD_TARBALL "${ILLD_UNPACK}/illd.tar.gz") -set(ILLD_UNPACK_NAME "illd_release_tc3x-main") -set(ILLD_SRC "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}/src/BaseSw") -set(ILLD_URL - "https://github.com/Infineon/illd_release_tc3x/archive/refs/heads/main.tar.gz" -) - -set(CONFIG_DIR "${ILLD_UNPACK}/Configurations") -set(ILLD_DIR "${ILLD_UNPACK}/Libraries/src") -set(PATCHES_DIR "${ILLD_UNPACK}/patches") - -if(NOT EXISTS "${ILLD_DIR}/Libraries") - file(MAKE_DIRECTORY "${ILLD_UNPACK}") - file(DOWNLOAD "${ILLD_URL}" "${ILLD_TARBALL}" SHOW_PROGRESS) - - message(STATUS "Unpacking: ILLD for tc3xx") - execute_process( - COMMAND ${CMAKE_COMMAND} -E tar xzf "${ILLD_TARBALL}" - WORKING_DIRECTORY "${ILLD_UNPACK}" - RESULT_VARIABLE tar_result) - if(NOT tar_result EQUAL 0) - message(FATAL_ERROR "Failed to unpack ${ILLD_TARBALL}") - endif() - - file(MAKE_DIRECTORY "${ILLD_DIR}/Libraries") - - execute_process(COMMAND ${CMAKE_COMMAND} -E copy_directory "${ILLD_SRC}/" - "${ILLD_DIR}/Libraries/" RESULT_VARIABLE copy_result) - if(NOT copy_result EQUAL 0) - message( - FATAL_ERROR - "Failed to stage ILLD from ${ILLD_SRC} to ${ILLD_DIR}/Libraries") - endif() - - file(REMOVE_RECURSE "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}") -endif() - -file(GLOB PATCH_FILES "${PATCHES_DIR}/*.patch") - -foreach(PATCH ${PATCH_FILES}) - execute_process( - COMMAND git apply --reverse --check ${PATCH} - WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo - # root - RESULT_VARIABLE PATCH_NEEDED - OUTPUT_QUIET ERROR_QUIET) - - if(PATCH_NEEDED EQUAL 0) - message(STATUS "Patch ${PATCH} already applied, skipping.") - else() - execute_process( - COMMAND git apply --whitespace=nowarn ${PATCH} - WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo - # root - RESULT_VARIABLE APPLY_RESULT) - if(NOT APPLY_RESULT EQUAL 0) - message(FATAL_ERROR "Failed to apply patch ${PATCH}!") - else() - message(STATUS "Successfully applied patch ${PATCH}.") - endif() - endif() -endforeach() - -set(SDK_INCDIR - "${CONFIG_DIR}" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Std" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Pms/Std" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Stm/Std" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Src/Std" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Stm/Timer" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_PinMap" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x" - "${ILLD_DIR}/Libraries/Infra/Platform" - "${ILLD_DIR}/Libraries/Infra/Platform/Tricore" - "${ILLD_DIR}/Libraries/Infra/Sfr/TC39xB" - "${ILLD_DIR}/Libraries/Infra/Ssw/TC3xx/Tricore" - "${ILLD_DIR}/Libraries/Service/CpuGeneric") - -target_include_directories(arch PRIVATE ${SDK_INCDIR}) -target_include_directories(nuttx PRIVATE ${SDK_INCDIR}) - -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_INCLUDE_DIRECTORIES ${SDK_INCDIR}) - -set(SDK_CSRCS - "${CONFIG_DIR}/Ifx_Cfg_Ssw.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Asclin/Std/IfxAsclin.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Std/IfxCpu.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxAsclin_cfg.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxCpu_cfg.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxStm_cfg.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x/IfxAsclin_PinMap_TC39xB_LFBGA292.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsEvr.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsPm.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Port/Std/IfxPort.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuCcu.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuEru.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuLbist.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuRcu.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuWdt.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Src/Std/IfxSrc.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Stm/Std/IfxStm.c" - "${ILLD_DIR}/Libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.c" - "${ILLD_DIR}/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c" - "${ILLD_DIR}/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Tc0.c") - -target_sources(nuttx PRIVATE ${SDK_CSRCS}) - -if(NOT CONFIG_TRICORE_TOOLCHAIN_TASKING) - target_compile_options(nuttx PRIVATE -Wno-undef -Wno-strict-prototypes - -Wno-shadow) - target_compile_options(nuttx PRIVATE -fstrict-volatile-bitfields) - target_compile_options(nuttx PRIVATE -Wno-unused-parameter - -Wno-unused-but-set-parameter) - target_compile_options(nuttx PRIVATE -Wno-implicit-fallthrough) -else() - nuttx_add_extra_library( - "${CMAKE_CURRENT_LIST_DIR}/illd/prebuilts/tc162/cinit.o") -endif() diff --git a/arch/tricore/src/tc3xx/Kconfig b/arch/tricore/src/tc3xx/Kconfig deleted file mode 100644 index 1c3f45744d0af..0000000000000 --- a/arch/tricore/src/tc3xx/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "TC3XX Configuration Options" - -menu "TC3XX Peripheral Support" - -# These are the peripheral selections proper - -config TC3XX_UART0 - bool "TC3XX UART0" - default y - select UART0_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -endmenu diff --git a/arch/tricore/src/tc3xx/Make.defs b/arch/tricore/src/tc3xx/Make.defs index 124d8cf644781..1671f0458f852 100644 --- a/arch/tricore/src/tc3xx/Make.defs +++ b/arch/tricore/src/tc3xx/Make.defs @@ -20,126 +20,4 @@ # ############################################################################ -CHIP_CSRCS += tc3xx_timerisr.c -CHIP_CSRCS += tc3xx_serial.c - VPATH += tc3xx - -ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - -tc3xx_libc$(OBJEXT): tc3xx_libc.c - $(call COMPILE, $<, $@) - -libc_fpu$(LIBEXT): tc3xx_libc$(OBJEXT) - $(call ARCHIVE, $@, $<) - -EXTRA_LIBS += libc_fpu$(LIBEXT) - -else - -tc3xx_dummy$(OBJEXT): tc3xx_dummy.c - $(call COMPILE, $<, $@) - -libos$(LIBEXT): tc3xx_dummy$(OBJEXT) - $(call ARCHIVE, $@, $<) - -EXTRA_LIBS += libos$(LIBEXT) - -endif - -ILLD_UNPACK = illd/tc3xx -ILLD_TARBALL = $(ILLD_UNPACK)/illd.tar.gz -ILLD_UNPACK_NAME = illd_release_tc3x-main -ILLD_SRC = $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME)/src/BaseSw -ILLD_URL = https://github.com/Infineon/illd_release_tc3x/archive/refs/heads - -$(ILLD_TARBALL): - $(call DOWNLOAD,$(ILLD_URL),main.tar.gz,$(ILLD_TARBALL)) - -$(ILLD_UNPACK)/.illd_unpack: $(ILLD_TARBALL) - $(Q) echo "Unpacking: ILLD" - $(Q) tar xzf $(ILLD_TARBALL) -C $(ILLD_UNPACK) - $(Q) mkdir -p $(ILLD_UNPACK)/Libraries/src/Libraries - $(Q) mv $(ILLD_SRC)/* $(ILLD_UNPACK)/Libraries/src/Libraries/ - $(Q) rm -rf $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME) - $(Q) touch $(ILLD_UNPACK)/.illd_unpack - -ifeq ($(wildcard $(ILLD_UNPACK)/.git),) -context:: $(ILLD_UNPACK)/.illd_unpack - -distclean:: - $(call DELFILE, $(ILLD_UNPACK)/.illd_unpack) - $(call DELFILE, $(ILLD_TARBALL)) - $(call DELDIR, $(ILLD_UNPACK)/Libraries/src/Libraries) -endif - -CONFIG_DIR = $(ILLD_UNPACK)/Configurations -ILLD_DIR = $(ILLD_UNPACK)/Libraries/src -PATCHES_DIR = $(ILLD_UNPACK)/patches -PATCH_FILES = $(wildcard $(CURDIR)/$(PATCHES_DIR)/*.patch) - -apply_change_patches: - @if [ -n "$(PATCH_FILES)" ]; then \ - for p in $(PATCH_FILES); do \ - if git -C "$(CURDIR)" apply --reverse --check "$$p" >/dev/null 2>&1; then \ - echo "-- Patch $$p already applied, skipping."; \ - else \ - if git -C "$(CURDIR)" apply --whitespace=nowarn "$$p" >/dev/null 2>&1; then \ - echo "-- Successfully applied patch $$p."; \ - else \ - echo "-- Failed to apply patch $$p!"; \ - exit 1; \ - fi; \ - fi; \ - done; \ - fi - -context:: apply_change_patches - -SDK_INCDIR += ${CONFIG_DIR} -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Pms/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Stm/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Src/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Stm/Timer -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_PinMap -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x -SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform -SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform/Tricore -SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Sfr/TC39xB -SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Ssw/TC3xx/Tricore -SDK_INCDIR += $(ILLD_DIR)/Libraries/Service/CpuGeneric - -SDK_CSRCS += ${CONFIG_DIR}/Ifx_Cfg_Ssw.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Asclin/Std/IfxAsclin.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Std/IfxCpu.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxAsclin_cfg.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxCpu_cfg.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxStm_cfg.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x/IfxAsclin_PinMap_TC39xB_LFBGA292.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsEvr.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsPm.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Port/Std/IfxPort.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuCcu.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuEru.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuLbist.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuRcu.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuWdt.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Src/Std/IfxSrc.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Stm/Std/IfxStm.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Tc0.c - -CFLAGS += $(addprefix ${INCDIR_PREFIX},$(SDK_INCDIR)) - -VPATH += $(dir $(SDK_CSRCS)) - -HEAD_CSRC += $(notdir $(SDK_CSRCS)) - -LIBPATHS += $(CURDIR) diff --git a/arch/tricore/src/tc3xx/tc3xx_dummy.c b/arch/tricore/src/tc3xx/tc3xx_dummy.c deleted file mode 100644 index 8375101e279f2..0000000000000 --- a/arch/tricore/src/tc3xx/tc3xx_dummy.c +++ /dev/null @@ -1,29 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc3xx/tc3xx_dummy.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/arch/tricore/src/tc3xx/tc3xx_libc.c b/arch/tricore/src/tc3xx/tc3xx_libc.c deleted file mode 100644 index 4e55d90c5ed90..0000000000000 --- a/arch/tricore/src/tc3xx/tc3xx_libc.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc3xx/tc3xx_libc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/* TODO: - * The data copy from flash to ram reuses the implementation in tricore sdk. - * The next update will reimplement _c_init() to abandon the copy code. - * - * Usage: ltc [options] files - * -i --user-provided-initialization-code - * - * the user provides his own initialization - * routine, do not emit the copytable - * - * void _c_init(void) - * { - * } - */ - -/* The implementation of libc is introduced by default in the Tricore - * toolchain, in nuttx we made a fake libc_fpu.a library to bypass - * this issue, but the linker will still generate markup code, - * add a few definitions to fool the linker. - */ - -void __printf_float(void) -{ -} - -void __printf_int(void) -{ -} - -void __printf_llong(void) -{ -} - -void _main(void) -{ -} - -void _doexit(void) -{ -} - -/* BUG, Workaround for tasking compiler: - * - * ltc E106: unresolved external: regulator_gpio_init - - * (drivers_initialize.o) - * ltc F019: unrecoverable error: fatal link error - * - */ - -int regulator_gpio_init(void *iodev, void *desc) -{ - return 0; -} diff --git a/arch/tricore/src/tc3xx/tc3xx_serial.c b/arch/tricore/src/tc3xx/tc3xx_serial.c deleted file mode 100644 index 808386e5ecc5c..0000000000000 --- a/arch/tricore/src/tc3xx/tc3xx_serial.c +++ /dev/null @@ -1,732 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc3xx/tc3xx_serial.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "tricore_internal.h" - -#include "Asclin/Asc/IfxAsclin_Asc.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If we are not using the serial driver for the console, then we still must - * provide some minimal implementation of up_putc. - */ - -#ifdef USE_SERIALDRIVER - -/* Which UART with be tty0/console and which tty1? The console will always - * be ttyS0. If there is no console then will use the lowest numbered UART. - */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_TC3XX_UART0) -# define HAVE_SERIAL_CONSOLE 1 -#else -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef HAVE_SERIAL_CONSOLE -#endif - -#ifdef HAVE_SERIAL_CONSOLE -# if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart0port /* UART0 is console */ -# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ -# define SERIAL_CONSOLE 1 -# else -# error "I'm confused... Do we have a serial console or not?" -# endif -#else -# undef CONSOLE_DEV /* No console */ -# undef CONFIG_UART0_SERIAL_CONSOLE -# if defined(CONFIG_TC3XX_UART0) -# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ -# define SERIAL_CONSOLE 1 -# else -# undef TTYS0_DEV -# endif -#endif - -#undef HAVE_UART_DEVICE -#if defined(CONFIG_TC3XX_UART0) -# define HAVE_UART_DEVICE 1 -#endif - -/* Common initialization logic will not not know that the all of the UARTs - * have been disabled. So, as a result, we may still have to provide - * stub implementations of tricore_earlyserialinit(), - * tricore_serialinit(), and up_putc(). - */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct up_dev_s -{ - volatile void *uartbase; /* Base address of UART registers */ - const void *pins; /* Pin configuration */ - uint32_t baud; /* Configured baud */ - uint8_t irq; /* IRQ associated with this UART */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Serial driver methods */ - -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context, void *arg); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, unsigned int *status); -static void up_rxint(struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(struct uart_dev_s *dev); -static void up_send(struct uart_dev_s *dev, int ch); -static void up_txint(struct uart_dev_s *dev, bool enable); -static bool up_txready(struct uart_dev_s *dev); -static bool up_txempty(struct uart_dev_s *dev); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct uart_ops_s g_uart_ops = -{ - .setup = up_setup, - .shutdown = up_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = NULL, -#endif - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txempty, -}; - -/* I/O buffers */ - -#ifdef CONFIG_TC3XX_UART0 -static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; -static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; -#endif - -#ifdef CONFIG_TC3XX_UART0 - -/* Pin configuration */ - -static const IfxAsclin_Asc_Pins g_uart0_pins = -{ - NULL, IfxPort_InputMode_pullUp, /* CTS pin not used */ - &UART_PIN_RX, IfxPort_InputMode_pullUp, /* RX pin */ - NULL, IfxPort_OutputMode_pushPull, /* RTS pin not used */ - &UART_PIN_TX, IfxPort_OutputMode_pushPull, /* TX pin */ - IfxPort_PadDriver_cmosAutomotiveSpeed1 -}; - -static struct up_dev_s g_uart0priv = -{ - .uartbase = &MODULE_ASCLIN0, - .pins = &g_uart0_pins, - .baud = CONFIG_UART0_BAUD, - .irq = TRICORE_UART_RX_IRQ, -}; - -static uart_dev_t g_uart0port = -{ -#if SERIAL_CONSOLE == 1 - .isconsole = 1, -#endif - .recv = - { - .size = CONFIG_UART0_RXBUFSIZE, - .buffer = g_uart0rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART0_TXBUFSIZE, - .buffer = g_uart0txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart0priv, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: asclin_init - * - * Description: - * Configure the UART baud, bits, parity, etc. This method is called the - * first time that the serial port is opened. - * - ****************************************************************************/ - -static void asclin_init(struct up_dev_s *priv) -{ - Ifx_ASCLIN *asclin = priv->uartbase; - const IfxAsclin_Asc_Pins *pins = priv->pins; - - /* enabling the module */ - - IfxAsclin_enableModule(asclin); - - /* disabling the clock */ - - IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_noClock); - - /* setting the module in Initialise mode */ - - IfxAsclin_setFrameMode(asclin, IfxAsclin_FrameMode_initialise); - - /* sets the prescaler */ - - IfxAsclin_setPrescaler(asclin, 1); - - /* temporary set the clock source for baudrate configuration */ - - IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_ascFastClock); - - /* setting the baudrate bit fields to generate the required baudrate */ - - IfxAsclin_setBitTiming(asclin, priv->baud, - IfxAsclin_OversamplingFactor_16, - IfxAsclin_SamplePointPosition_8, - IfxAsclin_SamplesPerBit_three); - - /* disabling the clock again */ - - IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_noClock); - - /* selecting the loopback mode */ - - IfxAsclin_enableLoopBackMode(asclin, false); - - /* setting parity enable */ - - IfxAsclin_enableParity(asclin, false); - - /* setting parity type (odd/even) */ - - IfxAsclin_setParityType(asclin, IfxAsclin_ParityType_even); - - /* setting the stop bit */ - - IfxAsclin_setStopBit(asclin, IfxAsclin_StopBit_1); - - /* setting the shift direction */ - - IfxAsclin_setShiftDirection(asclin, - IfxAsclin_ShiftDirection_lsbFirst); - - /* setting the data length */ - - IfxAsclin_setDataLength(asclin, IfxAsclin_DataLength_8); - - /* setting Tx FIFO inlet width */ - - IfxAsclin_setTxFifoInletWidth(asclin, - IfxAsclin_TxFifoInletWidth_1); - - /* setting Rx FIFO outlet width */ - - IfxAsclin_setRxFifoOutletWidth(asclin, - IfxAsclin_RxFifoOutletWidth_1); - - /* setting idle delay */ - - IfxAsclin_setIdleDelay(asclin, IfxAsclin_IdleDelay_0); - - /* setting Tx FIFO level at which a Tx interrupt will be triggered */ - - IfxAsclin_setTxFifoInterruptLevel(asclin, - IfxAsclin_TxFifoInterruptLevel_0); - - /* setting Rx FIFO interrupt level at which a Rx - * interrupt will be triggered - */ - - IfxAsclin_setRxFifoInterruptLevel(asclin, - IfxAsclin_RxFifoInterruptLevel_1); - - /* setting Tx FIFO interrupt generation mode */ - - IfxAsclin_setTxFifoInterruptMode(asclin, - IfxAsclin_FifoInterruptMode_combined); - - /* setting Rx FIFO interrupt generation mode */ - - IfxAsclin_setRxFifoInterruptMode(asclin, - IfxAsclin_FifoInterruptMode_combined); - - /* selecting the frame mode */ - - IfxAsclin_setFrameMode(asclin, IfxAsclin_FrameMode_asc); - - /* Pin mapping */ - - if (pins != NULL) - { - IfxAsclin_Cts_In *cts = pins->cts; - - if (cts != NULL) - { - IfxAsclin_initCtsPin(cts, pins->ctsMode, pins->pinDriver); - } - - IfxAsclin_Rx_In *rx = pins->rx; - - if (rx != NULL) - { - IfxAsclin_initRxPin(rx, pins->rxMode, pins->pinDriver); - } - - IfxAsclin_Rts_Out *rts = pins->rts; - - if (rts != NULL) - { - IfxAsclin_initRtsPin(rts, pins->rtsMode, pins->pinDriver); - } - - IfxAsclin_Tx_Out *tx = pins->tx; - - if (tx != NULL) - { - IfxAsclin_initTxPin(tx, pins->txMode, pins->pinDriver); - } - } - - /* select the clock source */ - - IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_ascFastClock); - - /* disable all flags */ - - IfxAsclin_disableAllFlags(asclin); - - /* clear all flags */ - - IfxAsclin_clearAllFlags(asclin); - - /* HW error flags */ - - IfxAsclin_enableParityErrorFlag(asclin, true); - IfxAsclin_enableFrameErrorFlag(asclin, true); - IfxAsclin_enableRxFifoOverflowFlag(asclin, true); - IfxAsclin_enableRxFifoUnderflowFlag(asclin, true); - IfxAsclin_enableTxFifoOverflowFlag(asclin, true); - - /* enable transfers */ - - IfxAsclin_enableRxFifoInlet(asclin, true); - IfxAsclin_enableTxFifoOutlet(asclin, true); - - IfxAsclin_flushRxFifo(asclin); - IfxAsclin_flushTxFifo(asclin); -} - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the UART baud, bits, parity, etc. This method is called the - * first time that the serial port is opened. - * - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev) -{ - asclin_init(dev->priv); - - return OK; -} - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the UART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -static void up_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - - /* Disable interrupts */ - - up_disable_irq(priv->irq); -} - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the - * the setup() method is called, however, the serial console may operate in - * a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() are called. - * - ****************************************************************************/ - -static int up_attach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - int ret; - - /* Initialize interrupt generation on the peripheral */ - - ret = irq_attach(priv->irq, up_interrupt, dev); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ - - up_enable_irq(priv->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception - * is the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - - /* Disable interrupts */ - - up_disable_irq(priv->irq); - - /* Detach from the interrupt */ - - irq_detach(priv->irq); -} - -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the UART interrupt handler. It will be invoked when an - * interrupt is received on the 'irq'. It should call uart_xmitchars or - * uart_recvchars to perform the appropriate data transfers. The - * interrupt handling logic must be able to map the 'arg' to the - * appropriate uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context, void *arg) -{ - struct uart_dev_s *dev = arg; - - if (up_rxavailable(dev)) - { - uart_recvchars(dev); - } - - if (up_txready(dev)) - { - uart_xmitchars(dev); - } - - return OK; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - return -ENOTTY; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the UART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -static int up_receive(struct uart_dev_s *dev, unsigned int *status) -{ - struct up_dev_s *priv = dev->priv; - - return IfxAsclin_readRxData(priv->uartbase); -} - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -static void up_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = dev->priv; - irqstate_t flags = enter_critical_section(); - - IfxAsclin_enableRxFifoFillLevelFlag(priv->uartbase, enable); - IfxAsclin_enableRxFifoInlet(priv->uartbase, enable); - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive register is not empty - * - ****************************************************************************/ - -static bool up_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - - return IfxAsclin_getRxFifoFillLevel(priv->uartbase) > 0; -} - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the UART. - * - ****************************************************************************/ - -static void up_send(struct uart_dev_s *dev, int ch) -{ - struct up_dev_s *priv = dev->priv; - - /* Wait for FIFO */ - - if (dev == &CONSOLE_DEV) - { - up_putc(ch); - return; - } - - while (IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0); - - IfxAsclin_clearAllFlags(priv->uartbase); - IfxAsclin_writeTxData(priv->uartbase, ch); -} - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void up_txint(struct uart_dev_s *dev, bool enable) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - if (enable) - { - /* Enable the TX interrupt */ - - uart_xmitchars(dev); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the tranmsit data register is not full - * - ****************************************************************************/ - -static bool up_txready(struct uart_dev_s *dev) -{ - return true; -} - -/**************************************************************************** - * Name: up_txempty - * - * Description: - * Return true if the tranmsit data register is empty - * - ****************************************************************************/ - -static bool up_txempty(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - - /* Return true if the TX wartermak is pending */ - - return IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0; -} - -/**************************************************************************** - * Name: tricore_lowputc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -void tricore_lowputc(char ch) -{ -#ifdef HAVE_SERIAL_CONSOLE - struct up_dev_s *priv = CONSOLE_DEV.priv; - - /* Wait for FIFO */ - - while (IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0); - - IfxAsclin_clearAllFlags(priv->uartbase); - IfxAsclin_writeTxData(priv->uartbase, ch); -#endif /* HAVE_CONSOLE */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef USE_EARLYSERIALINIT - -/**************************************************************************** - * Name: tricore_earlyserialinit - * - * Description: - * Performs the low level UART initialization early in debug so that the - * serial console will be available during boot up. This must be called - * before tricore_serialinit. NOTE: This function depends on GPIO pin - * configuration performed in up_consoleinit() and main clock - * initialization performed in up_clkinitialize(). - * - ****************************************************************************/ - -void tricore_earlyserialinit(void) -{ - /* Configuration whichever one is the console */ - -#ifdef HAVE_SERIAL_CONSOLE - CONSOLE_DEV.isconsole = true; - up_setup(&CONSOLE_DEV); -#endif -} -#endif - -/**************************************************************************** - * Name: tricore_serialinit - * - * Description: - * Register serial console and serial ports. This assumes - * that tricore_earlyserialinit was called previously. - * - ****************************************************************************/ - -void tricore_serialinit(void) -{ - /* Register the console */ - -#ifdef HAVE_SERIAL_CONSOLE - uart_register("/dev/console", &CONSOLE_DEV); -#endif - - /* Register all UARTs */ - - uart_register("/dev/ttyS0", &TTYS0_DEV); -} - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -void up_putc(int ch) -{ -#ifdef HAVE_SERIAL_CONSOLE - tricore_lowputc(ch); -#endif -} -#endif /* USE_SERIALDRIVER */ diff --git a/arch/tricore/src/tc3xx/tc3xx_timerisr.c b/arch/tricore/src/tc3xx/tc3xx_timerisr.c deleted file mode 100644 index 44d03b34c3be4..0000000000000 --- a/arch/tricore/src/tc3xx/tc3xx_timerisr.c +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc3xx/tc3xx_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include "tricore_internal.h" - -#include "IfxStm.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - struct oneshot_lowerhalf_s *lower; - - lower = tricore_systimer_initialize(&MODULE_STM0, - TRICORE_SRC2IRQ(&SRC_STM0SR0), - SCU_FREQUENCY); - - DEBUGASSERT(lower != NULL); - - up_alarm_set_lowerhalf(lower); -} diff --git a/arch/tricore/src/tc4da/CMakeLists.txt b/arch/tricore/src/tc4da/CMakeLists.txt deleted file mode 100644 index 869adb877b157..0000000000000 --- a/arch/tricore/src/tc4da/CMakeLists.txt +++ /dev/null @@ -1,21 +0,0 @@ -# ############################################################################## -# arch/tricore/src/tc4da/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## diff --git a/arch/tricore/src/tc4da/Kconfig b/arch/tricore/src/tc4da/Kconfig deleted file mode 100644 index 18c7905aed7cf..0000000000000 --- a/arch/tricore/src/tc4da/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - diff --git a/arch/tricore/src/tc4da/Make.defs b/arch/tricore/src/tc4da/Make.defs deleted file mode 100644 index fd041dcf882e9..0000000000000 --- a/arch/tricore/src/tc4da/Make.defs +++ /dev/null @@ -1,21 +0,0 @@ -############################################################################ -# arch/tricore/src/tc4da/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ diff --git a/arch/tricore/src/tc4da/chip.h b/arch/tricore/src/tc4da/chip.h deleted file mode 100644 index 89f26c2d6677f..0000000000000 --- a/arch/tricore/src/tc4da/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc4da/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_SRC_TC4DA_CHIP_H -#define __ARCH_TRICORE_SRC_TC4DA_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#define UART_PIN_RX IfxAsclin0_RXA_F_P14_1_IN /* UART receive port pin */ -#define UART_PIN_TX IfxAsclin0_TX_F_P14_0_OUT /* UART transmit port pin */ - -#endif /* __ARCH_TRICORE_SRC_TC4DA_CHIP_H */ diff --git a/arch/tricore/src/tc4xx/CMakeLists.txt b/arch/tricore/src/tc4xx/CMakeLists.txt index 0735c9b48dc9d..1da5dfad24c3d 100644 --- a/arch/tricore/src/tc4xx/CMakeLists.txt +++ b/arch/tricore/src/tc4xx/CMakeLists.txt @@ -19,174 +19,3 @@ # the License. # # ############################################################################## - -set(SRCS tc4xx_timerisr.c tc4xx_serial.c) - -target_sources(arch PRIVATE ${SRCS}) - -if(CONFIG_TRICORE_TOOLCHAIN_TASKING) - nuttx_add_kernel_library(c_fpu) - target_sources(c_fpu PRIVATE tc4xx_libc.c) - target_link_options( - nuttx PRIVATE - --library-directory=${CMAKE_BINARY_DIR}/arch/tricore/src/exclude_chip) -endif() - -set(ILLD_UNPACK "${CMAKE_CURRENT_SOURCE_DIR}/../illd/tc4xx") -set(ILLD_TARBALL "${ILLD_UNPACK}/illd.tar.gz") -set(ILLD_UNPACK_NAME "illd_release_tc4x-main") -set(ILLD_SRC "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}/src/Libraries") -set(ILLD_URL - "https://github.com/Infineon/illd_release_tc4x/archive/refs/heads/main.tar.gz" -) - -set(CONFIG_DIR "${ILLD_UNPACK}/Configurations") -set(ILLD_DIR "${ILLD_UNPACK}/Libraries/src") -set(PATCHES_DIR "${ILLD_UNPACK}/patches") - -if(NOT EXISTS "${ILLD_DIR}/Libraries") - file(MAKE_DIRECTORY "${ILLD_UNPACK}") - file(DOWNLOAD "${ILLD_URL}" "${ILLD_TARBALL}") - - message(STATUS "Unpacking: ILLD for tc4xx") - execute_process( - COMMAND ${CMAKE_COMMAND} -E tar xzf "${ILLD_TARBALL}" - WORKING_DIRECTORY "${ILLD_UNPACK}" - RESULT_VARIABLE tar_result) - if(NOT tar_result EQUAL 0) - message(FATAL_ERROR "Failed to unpack ${ILLD_TARBALL}") - endif() - - file(MAKE_DIRECTORY "${ILLD_DIR}/Libraries") - - execute_process(COMMAND ${CMAKE_COMMAND} -E copy_directory "${ILLD_SRC}/" - "${ILLD_DIR}/Libraries/" RESULT_VARIABLE copy_result) - if(NOT copy_result EQUAL 0) - message( - FATAL_ERROR - "Failed to stage ILLD from ${ILLD_SRC} to ${ILLD_DIR}/Libraries") - endif() - - file(REMOVE_RECURSE "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}") -endif() - -file(GLOB PATCH_FILES "${PATCHES_DIR}/*.patch") - -foreach(PATCH ${PATCH_FILES}) - execute_process( - COMMAND git apply --reverse --check ${PATCH} - WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo - # root - RESULT_VARIABLE PATCH_NEEDED - OUTPUT_QUIET ERROR_QUIET) - - if(PATCH_NEEDED EQUAL 0) - message(STATUS "Patch ${PATCH} already applied, skipping.") - else() - execute_process( - COMMAND git apply --whitespace=nowarn ${PATCH} - WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo - # root - RESULT_VARIABLE APPLY_RESULT) - if(NOT APPLY_RESULT EQUAL 0) - message(FATAL_ERROR "Failed to apply patch ${PATCH}!") - else() - message(STATUS "Successfully applied patch ${PATCH}.") - endif() - endif() -endforeach() - -set(SDK_INCDIR - "${CONFIG_DIR}" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/ArcEV" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Asc" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Lin" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Atom" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Tom" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Crc" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Scr" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_PinMap" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_PinMap/TC4Dx" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Can/Can" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Can/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Flash/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/I2c/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Pms/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Scu/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smu/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Src/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Timer" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Vmt/Std" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Wtu/Std" - "${ILLD_DIR}/Libraries/Infra/Platform" - "${ILLD_DIR}/Libraries/Infra/Sfr/TC4Dx" - "${ILLD_DIR}/Libraries/Infra/Ssw/TC4xx/Tricore" - "${ILLD_DIR}/Libraries/Service/CpuGeneric" - "${ILLD_DIR}/Libraries/Infra/Platform/Compilers") - -target_include_directories(arch PRIVATE ${SDK_INCDIR}) -target_include_directories(nuttx PRIVATE ${SDK_INCDIR}) - -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_INCLUDE_DIRECTORIES ${SDK_INCDIR}) - -set(SDK_CSRCS - "${CONFIG_DIR}/Ifx_Cfg_Ssw.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxAp_cfg.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxDma_cfg.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx/IfxAsclin_PinMap_TC4Dx_BGA436_COM.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Std/IfxAsclin.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApApu.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApProt.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std/IfxClock.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Dma/IfxDma_Dma.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Std/IfxDma.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std/IfxPort.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std/IfxSrc.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxCpu_cfg.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxStm_cfg.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Std/IfxCpu.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Scu/Std/IfxScuEru.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Std/IfxStm.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmm.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmmRst.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smu/Std/IfxSmu.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Vmt/Std/IfxVmt.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Wtu/Std/IfxWtu.c" - "${ILLD_DIR}/Libraries/Infra/Platform/Compilers/CompilerTasking.c" - "${ILLD_DIR}/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c" - "${ILLD_DIR}/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Tc0.c") - -target_sources(nuttx PRIVATE ${SDK_CSRCS}) - -if(NOT CONFIG_TRICORE_TOOLCHAIN_TASKING) - target_compile_options(nuttx PRIVATE -Wno-undef -Wno-strict-prototypes - -Wno-shadow) - target_compile_options(nuttx PRIVATE -fstrict-volatile-bitfields) - target_compile_options(nuttx PRIVATE -Wno-unused-parameter - -Wno-unused-but-set-parameter) - target_compile_options(nuttx PRIVATE -Wno-implicit-fallthrough) -endif() - -target_compile_definitions( - arch PRIVATE -DSRC_GPSR00=SRC_GPSR0SR0 -DSRC_CPU_CPU0_SB=SRC_CPU0SB - -DMODULE_STM0=MODULE_CPU0 -DSRC_STM0SR0=SRC_STMCPU0_SR2) diff --git a/arch/tricore/src/tc4xx/Kconfig b/arch/tricore/src/tc4xx/Kconfig deleted file mode 100644 index dfe17717c535d..0000000000000 --- a/arch/tricore/src/tc4xx/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "TC4XX Configuration Options" - -menu "TC4XX Peripheral Support" - -# These are the peripheral selections proper - -config TC4XX_UART0 - bool "TC4XX UART0" - default y - select UART0_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -endmenu diff --git a/arch/tricore/src/tc4xx/Make.defs b/arch/tricore/src/tc4xx/Make.defs index 7df4ec01e9230..2363894a66b6f 100644 --- a/arch/tricore/src/tc4xx/Make.defs +++ b/arch/tricore/src/tc4xx/Make.defs @@ -20,161 +20,4 @@ # ############################################################################ -CHIP_CSRCS += tc4xx_timerisr.c -CHIP_CSRCS += tc4xx_serial.c - VPATH += tc4xx - -ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - -tc4xx_libc$(OBJEXT): tc4xx_libc.c - $(call COMPILE, $<, $@) - -libc_fpu$(LIBEXT): tc4xx_libc$(OBJEXT) - $(call ARCHIVE, $@, $<) - -EXTRA_LIBS += libc_fpu$(LIBEXT) - -else - -tc4xx_dummy$(OBJEXT): tc4xx_dummy.c - $(call COMPILE, $<, $@) - -libos$(LIBEXT): tc4xx_dummy$(OBJEXT) - $(call ARCHIVE, $@, $<) - -EXTRA_LIBS += libos$(LIBEXT) - -endif - -ILLD_UNPACK = illd/tc4xx -ILLD_TARBALL = $(ILLD_UNPACK)/illd.tar.gz -ILLD_UNPACK_NAME = illd_release_tc4x-main -ILLD_SRC = $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME)/src/Libraries -ILLD_URL = https://github.com/Infineon/illd_release_tc4x/archive/refs/heads - -$(ILLD_TARBALL): - $(call DOWNLOAD,$(ILLD_URL),main.tar.gz,$(ILLD_TARBALL)) - -$(ILLD_UNPACK)/.illd_unpack: $(ILLD_TARBALL) - $(Q) echo "Unpacking: ILLD" - $(Q) tar xzf $(ILLD_TARBALL) -C $(ILLD_UNPACK) - $(Q) mkdir -p $(ILLD_UNPACK)/Libraries/src/Libraries - $(Q) mv $(ILLD_SRC)/* $(ILLD_UNPACK)/Libraries/src/Libraries/ - $(Q) rm -rf $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME) - $(Q) touch $(ILLD_UNPACK)/.illd_unpack - -ifeq ($(wildcard $(ILLD_UNPACK)/.git),) -context:: $(ILLD_UNPACK)/.illd_unpack - -distclean:: - $(call DELFILE, $(ILLD_UNPACK)/.illd_unpack) - $(call DELFILE, $(ILLD_TARBALL)) - $(call DELDIR, $(ILLD_UNPACK)/Libraries/src/Libraries) -endif - -CONFIG_DIR = $(ILLD_UNPACK)/Configurations -ILLD_DIR = $(ILLD_UNPACK)/Libraries/src -PATCHES_DIR = $(ILLD_UNPACK)/patches - -PATCH_FILES = $(wildcard $(CURDIR)/$(PATCHES_DIR)/*.patch) - -apply_change_patches: - @if [ -n "$(PATCH_FILES)" ]; then \ - for p in $(PATCH_FILES); do \ - if git -C "$(CURDIR)" apply --reverse --check "$$p" >/dev/null 2>&1; then \ - echo "-- Patch $$p already applied, skipping."; \ - else \ - if git -C "$(CURDIR)" apply --whitespace=nowarn "$$p" >/dev/null 2>&1; then \ - echo "-- Successfully applied patch $$p."; \ - else \ - echo "-- Failed to apply patch $$p!"; \ - exit 1; \ - fi; \ - fi; \ - done; \ - fi - -context:: apply_change_patches - -SDK_INCDIR += ${CONFIG_DIR} -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/ArcEV -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Asc -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Lin -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Atom -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Tom -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Crc -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Scr -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_PinMap -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_PinMap/TC4Dx -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Can/Can -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Can/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Flash/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/I2c/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Pms/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Scu/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smu/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Src/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Timer -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Vmt/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Wtu/Std -SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform -SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Sfr/TC4Dx -SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Ssw/TC4xx/Tricore -SDK_INCDIR += $(ILLD_DIR)/Libraries/Service/CpuGeneric -SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform/Compilers - -SDK_CSRCS += $(CONFIG_DIR)/Ifx_Cfg_Ssw.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxAp_cfg.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxDma_cfg.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx/IfxAsclin_PinMap_TC4Dx_BGA436_COM.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Std/IfxAsclin.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApApu.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApProt.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std/IfxClock.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Dma/IfxDma_Dma.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Std/IfxDma.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std/IfxPort.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std/IfxSrc.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxCpu_cfg.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxStm_cfg.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Std/IfxCpu.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Scu/Std/IfxScuEru.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Std/IfxStm.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmm.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmmRst.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smu/Std/IfxSmu.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Vmt/Std/IfxVmt.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Wtu/Std/IfxWtu.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Platform/Compilers/CompilerTasking.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Tc0.c - -CFLAGS += $(addprefix ${INCDIR_PREFIX},$(SDK_INCDIR)) -CFLAGS += -DSRC_CPU_CPU0_SB=SRC_CPU0SB -CFLAGS += -DSRC_GPSR00=SRC_GPSR0SR0 -CFLAGS += -DMODULE_STM0=MODULE_CPU0 -CFLAGS += -DSRC_STM0SR0=SRC_STMCPU0_SR2 - -VPATH += $(dir $(SDK_CSRCS)) - -HEAD_CSRC += $(notdir $(SDK_CSRCS)) - -LIBPATHS += $(CURDIR) diff --git a/arch/tricore/src/tc4xx/tc4xx_dummy.c b/arch/tricore/src/tc4xx/tc4xx_dummy.c deleted file mode 100644 index 720c66095fe5e..0000000000000 --- a/arch/tricore/src/tc4xx/tc4xx_dummy.c +++ /dev/null @@ -1,29 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc4xx/tc4xx_dummy.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/arch/tricore/src/tc4xx/tc4xx_libc.c b/arch/tricore/src/tc4xx/tc4xx_libc.c deleted file mode 100644 index ba1138e7f84fa..0000000000000 --- a/arch/tricore/src/tc4xx/tc4xx_libc.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc4xx/tc4xx_libc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/* TODO: - * The data copy from flash to ram reuses the implementation in tricore sdk. - * The next update will reimplement _c_init() to abandon the copy code. - * - * Usage: ltc [options] files - * -i --user-provided-initialization-code - * - * the user provides his own initialization - * routine, do not emit the copytable - * - * void _c_init(void) - * { - * } - */ - -/* The implementation of libc is introduced by default in the Tricore - * toolchain, in nuttx we made a fake libc_fpu.a library to bypass - * this issue, but the linker will still generate markup code, - * add a few definitions to fool the linker. - */ - -void __printf_float(void) -{ -} - -void __printf_int(void) -{ -} - -void __printf_llong(void) -{ -} - -void _main(void) -{ -} - -void _doexit(void) -{ -} - -/* BUG, Workaround for tasking compiler: - * - * ltc E106: unresolved external: regulator_gpio_init - - * (drivers_initialize.o) - * ltc F019: unrecoverable error: fatal link error - * - */ - -int regulator_gpio_init(void *iodev, void *desc) -{ - return 0; -} diff --git a/arch/tricore/src/tc4xx/tc4xx_serial.c b/arch/tricore/src/tc4xx/tc4xx_serial.c deleted file mode 100644 index 8f635caeab9c1..0000000000000 --- a/arch/tricore/src/tc4xx/tc4xx_serial.c +++ /dev/null @@ -1,732 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc4xx/tc4xx_serial.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "tricore_internal.h" - -#include "Asclin/Asc/IfxAsclin_Asc.h" -#include "IfxAsclin_PinMap.h" -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If we are not using the serial driver for the console, then we still must - * provide some minimal implementation of up_putc. - */ - -#ifdef USE_SERIALDRIVER - -/* Which UART with be tty0/console and which tty1? The console will always - * be ttyS0. If there is no console then will use the lowest numbered UART. - */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_TC4XX_UART0) -# define HAVE_SERIAL_CONSOLE 1 -#else -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef HAVE_SERIAL_CONSOLE -#endif - -#ifdef HAVE_SERIAL_CONSOLE -# if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart0port /* UART0 is console */ -# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ -# define SERIAL_CONSOLE 1 -# else -# error "I'm confused... Do we have a serial console or not?" -# endif -#else -# undef CONSOLE_DEV /* No console */ -# undef CONFIG_UART0_SERIAL_CONSOLE -# if defined(CONFIG_TC4XX_UART0) -# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ -# define SERIAL_CONSOLE 1 -# else -# undef TTYS0_DEV -# endif -#endif - -#undef HAVE_UART_DEVICE -#if defined(CONFIG_TC4XX_UART0) -# define HAVE_UART_DEVICE 1 -#endif - -/* Common initialization logic will not not know that the all of the UARTs - * have been disabled. So, as a result, we may still have to provide - * stub implementations of tricore_earlyserialinit(), - * tricore_serialinit(), and up_putc(). - */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct up_dev_s -{ - volatile void *uartbase; /* Base address of UART registers */ - const void *pins; /* Pin configuration */ - uint32_t baud; /* Configured baud */ - uint8_t irq; /* IRQ associated with this UART */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Serial driver methods */ - -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context, void *arg); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, unsigned int *status); -static void up_rxint(struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(struct uart_dev_s *dev); -static void up_send(struct uart_dev_s *dev, int ch); -static void up_txint(struct uart_dev_s *dev, bool enable); -static bool up_txready(struct uart_dev_s *dev); -static bool up_txempty(struct uart_dev_s *dev); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct uart_ops_s g_uart_ops = -{ - .setup = up_setup, - .shutdown = up_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = NULL, -#endif - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txempty, -}; - -/* I/O buffers */ - -#ifdef CONFIG_TC4XX_UART0 -static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; -static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; -#endif - -#ifdef CONFIG_TC4XX_UART0 - -/* Pin configuration */ - -static const IfxAsclin_Asc_Pins g_uart0_pins = -{ - NULL, IfxPort_InputMode_pullUp, /* CTS pin not used */ - &UART_PIN_RX, IfxPort_InputMode_pullUp, /* RX pin */ - NULL, IfxPort_OutputMode_pushPull, /* RTS pin not used */ - &UART_PIN_TX, IfxPort_OutputMode_pushPull, /* TX pin */ - IfxPort_PadDriver_cmosAutomotiveSpeed1 -}; - -static struct up_dev_s g_uart0priv = -{ - .uartbase = &MODULE_ASCLIN0, - .pins = &g_uart0_pins, - .baud = CONFIG_UART0_BAUD, - .irq = TRICORE_UART_RX_IRQ, -}; - -static uart_dev_t g_uart0port = -{ -#if SERIAL_CONSOLE == 1 - .isconsole = 1, -#endif - .recv = - { - .size = CONFIG_UART0_RXBUFSIZE, - .buffer = g_uart0rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART0_TXBUFSIZE, - .buffer = g_uart0txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart0priv, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: asclin_init - * - * Description: - * Configure the UART baud, bits, parity, etc. This method is called the - * first time that the serial port is opened. - * - ****************************************************************************/ - -static void asclin_init(struct up_dev_s *priv) -{ - Ifx_ASCLIN *asclin = priv->uartbase; - const IfxAsclin_Asc_Pins *pins = priv->pins; - - /* enabling the module */ - - IfxAsclin_enableModule(asclin); - - /* disabling the clock */ - - IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_noClock); - - /* setting the module in Initialise mode */ - - IfxAsclin_setFrameMode(asclin, IfxAsclin_FrameMode_initialise); - - /* sets the prescaler */ - - IfxAsclin_setPrescaler(asclin, 1); - - /* temporary set the clock source for baudrate configuration */ - - IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_ascFastClock); - - /* setting the baudrate bit fields to generate the required baudrate */ - - IfxAsclin_setBitTiming(asclin, priv->baud, - IfxAsclin_OversamplingFactor_16, - IfxAsclin_SamplePointPosition_8, - IfxAsclin_SamplesPerBit_three); - - /* disabling the clock again */ - - IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_noClock); - - /* selecting the loopback mode */ - - IfxAsclin_enableLoopBackMode(asclin, false); - - /* setting parity enable */ - - IfxAsclin_enableParity(asclin, false); - - /* setting parity type (odd/even) */ - - IfxAsclin_setParityType(asclin, IfxAsclin_ParityType_even); - - /* setting the stop bit */ - - IfxAsclin_setStopBit(asclin, IfxAsclin_StopBit_1); - - /* setting the shift direction */ - - IfxAsclin_setShiftDirection(asclin, - IfxAsclin_ShiftDirection_lsbFirst); - - /* setting the data length */ - - IfxAsclin_setDataLength(asclin, IfxAsclin_DataLength_8); - - /* setting Tx FIFO inlet width */ - - IfxAsclin_setTxFifoInletWidth(asclin, - IfxAsclin_TxFifoInletWidth_1); - - /* setting Rx FIFO outlet width */ - - IfxAsclin_setRxFifoOutletWidth(asclin, - IfxAsclin_RxFifoOutletWidth_1); - - /* setting idle delay */ - - IfxAsclin_setIdleDelay(asclin, IfxAsclin_IdleDelay_0); - - /* setting Tx FIFO level at which a Tx interrupt will be triggered */ - - IfxAsclin_setTxFifoInterruptLevel(asclin, - IfxAsclin_TxFifoInterruptLevel_0); - - /* setting Rx FIFO interrupt level at which a Rx - * interrupt will be triggered - */ - - IfxAsclin_setRxFifoInterruptLevel(asclin, - IfxAsclin_RxFifoInterruptLevel_1); - - /* setting Tx FIFO interrupt generation mode */ - - IfxAsclin_setTxFifoInterruptMode(asclin, - IfxAsclin_FifoInterruptMode_combined); - - /* setting Rx FIFO interrupt generation mode */ - - IfxAsclin_setRxFifoInterruptMode(asclin, - IfxAsclin_FifoInterruptMode_combined); - - /* selecting the frame mode */ - - IfxAsclin_setFrameMode(asclin, IfxAsclin_FrameMode_asc); - - /* Pin mapping */ - - if (pins != NULL) - { - IfxAsclin_Cts_In *cts = pins->cts; - - if (cts != NULL) - { - IfxAsclin_initCtsPin(cts, pins->ctsMode, pins->pinDriver); - } - - IfxAsclin_Rx_In *rx = pins->rx; - - if (rx != NULL) - { - IfxAsclin_initRxPin(rx, pins->rxMode, pins->pinDriver); - } - - IfxAsclin_Rts_Out *rts = pins->rts; - - if (rts != NULL) - { - IfxAsclin_initRtsPin(rts, pins->rtsMode, pins->pinDriver); - } - - IfxAsclin_Tx_Out *tx = pins->tx; - - if (tx != NULL) - { - IfxAsclin_initTxPin(tx, pins->txMode, pins->pinDriver); - } - } - - /* select the clock source */ - - IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_ascFastClock); - - /* disable all flags */ - - IfxAsclin_disableAllFlags(asclin); - - /* clear all flags */ - - IfxAsclin_clearAllFlags(asclin); - - /* HW error flags */ - - IfxAsclin_enableParityErrorFlag(asclin, true); - IfxAsclin_enableFrameErrorFlag(asclin, true); - IfxAsclin_enableRxFifoOverflowFlag(asclin, true); - IfxAsclin_enableRxFifoUnderflowFlag(asclin, true); - IfxAsclin_enableTxFifoOverflowFlag(asclin, true); - - /* enable transfers */ - - IfxAsclin_enableRxFifoInlet(asclin, true); - IfxAsclin_enableTxFifoOutlet(asclin, true); - - IfxAsclin_flushRxFifo(asclin); - IfxAsclin_flushTxFifo(asclin); -} - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the UART baud, bits, parity, etc. This method is called the - * first time that the serial port is opened. - * - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev) -{ - asclin_init(dev->priv); - - return OK; -} - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the UART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -static void up_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - - /* Disable interrupts */ - - up_disable_irq(priv->irq); -} - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the - * the setup() method is called, however, the serial console may operate in - * a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() are called. - * - ****************************************************************************/ - -static int up_attach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - int ret; - - /* Initialize interrupt generation on the peripheral */ - - ret = irq_attach(priv->irq, up_interrupt, dev); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ - - up_enable_irq(priv->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception - * is the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - - /* Disable interrupts */ - - up_disable_irq(priv->irq); - - /* Detach from the interrupt */ - - irq_detach(priv->irq); -} - -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the UART interrupt handler. It will be invoked when an - * interrupt is received on the 'irq'. It should call uart_xmitchars or - * uart_recvchars to perform the appropriate data transfers. The - * interrupt handling logic must be able to map the 'arg' to the - * appropriate uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context, void *arg) -{ - struct uart_dev_s *dev = arg; - - if (up_rxavailable(dev)) - { - uart_recvchars(dev); - } - - if (up_txready(dev)) - { - uart_xmitchars(dev); - } - - return OK; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - return -ENOTTY; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the UART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -static int up_receive(struct uart_dev_s *dev, unsigned int *status) -{ - struct up_dev_s *priv = dev->priv; - - return IfxAsclin_readRxData(priv->uartbase); -} - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -static void up_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = dev->priv; - irqstate_t flags = enter_critical_section(); - - IfxAsclin_enableRxFifoFillLevelFlag(priv->uartbase, enable); - IfxAsclin_enableRxFifoInlet(priv->uartbase, enable); - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive register is not empty - * - ****************************************************************************/ - -static bool up_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - - return IfxAsclin_getRxFifoFillLevel(priv->uartbase) > 0; -} - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the UART. - * - ****************************************************************************/ - -static void up_send(struct uart_dev_s *dev, int ch) -{ - struct up_dev_s *priv = dev->priv; - - /* Wait for FIFO */ - - if (dev == &CONSOLE_DEV) - { - up_putc(ch); - return; - } - - while (IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0); - - IfxAsclin_clearAllFlags(priv->uartbase); - IfxAsclin_writeTxData(priv->uartbase, ch); -} - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void up_txint(struct uart_dev_s *dev, bool enable) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - if (enable) - { - /* Enable the TX interrupt */ - - uart_xmitchars(dev); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the tranmsit data register is not full - * - ****************************************************************************/ - -static bool up_txready(struct uart_dev_s *dev) -{ - return true; -} - -/**************************************************************************** - * Name: up_txempty - * - * Description: - * Return true if the tranmsit data register is empty - * - ****************************************************************************/ - -static bool up_txempty(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - - /* Return true if the TX wartermak is pending */ - - return IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0; -} - -/**************************************************************************** - * Name: tricore_lowputc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -void tricore_lowputc(char ch) -{ -#ifdef HAVE_SERIAL_CONSOLE - struct up_dev_s *priv = CONSOLE_DEV.priv; - - /* Wait for FIFO */ - - while (IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0); - - IfxAsclin_clearAllFlags(priv->uartbase); - IfxAsclin_writeTxData(priv->uartbase, ch); -#endif /* HAVE_CONSOLE */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef USE_EARLYSERIALINIT - -/**************************************************************************** - * Name: tricore_earlyserialinit - * - * Description: - * Performs the low level UART initialization early in debug so that the - * serial console will be available during boot up. This must be called - * before tricore_serialinit. NOTE: This function depends on GPIO pin - * configuration performed in up_consoleinit() and main clock - * initialization performed in up_clkinitialize(). - * - ****************************************************************************/ - -void tricore_earlyserialinit(void) -{ - /* Configuration whichever one is the console */ - -#ifdef HAVE_SERIAL_CONSOLE - CONSOLE_DEV.isconsole = true; - up_setup(&CONSOLE_DEV); -#endif -} -#endif - -/**************************************************************************** - * Name: tricore_serialinit - * - * Description: - * Register serial console and serial ports. This assumes - * that tricore_earlyserialinit was called previously. - * - ****************************************************************************/ - -void tricore_serialinit(void) -{ - /* Register the console */ - -#ifdef HAVE_SERIAL_CONSOLE - uart_register("/dev/console", &CONSOLE_DEV); -#endif - - /* Register all UARTs */ - - uart_register("/dev/ttyS0", &TTYS0_DEV); -} - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -void up_putc(int ch) -{ -#ifdef HAVE_SERIAL_CONSOLE - tricore_lowputc(ch); -#endif -} -#endif /* USE_SERIALDRIVER */ diff --git a/arch/tricore/src/tc4xx/tc4xx_timerisr.c b/arch/tricore/src/tc4xx/tc4xx_timerisr.c deleted file mode 100644 index 85625685a36b4..0000000000000 --- a/arch/tricore/src/tc4xx/tc4xx_timerisr.c +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/tc4xx/tc4xx_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include "tricore_internal.h" - -#include "IfxStm.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - struct oneshot_lowerhalf_s *lower; - - lower = tricore_systimer_initialize(&MODULE_CPU0, - TRICORE_SRC2IRQ(&SRC_STMCPU0_SR2), - SCU_FREQUENCY); - - DEBUGASSERT(lower != NULL); - - up_alarm_set_lowerhalf(lower); -} diff --git a/boards/Kconfig b/boards/Kconfig index 2a6a401dd15a0..262e992ecc7d3 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -2454,20 +2454,6 @@ config ARCH_BOARD_SABRE_6QUAD This options selects support for NuttX on the NXP/Freescale Sabre board featuring the iMX 6Quad CPU. -config ARCH_BOARD_A2G_TC397_5V_TFT - bool "Infineon's AURIX TC397 board: KIT_A2G_TC397_5V_TFT" - depends on ARCH_CHIP_TC397 - ---help--- - This options selects support for NuttX on the Infineon's AURIX board - board featuring the TC397 6Quad CPU. - -config ARCH_BOARD_TRIBOARD_TC4X9_COM - bool "Infineon's AURIX TC4DA board: TRIBOARD_TC4X9_COM" - depends on ARCH_CHIP_TC4DA - ---help--- - This options selects support for NuttX on the Infineon's AURIX board - board featuring the TC4DA 6Quad CPU. - config ARCH_BOARD_QEMU_ARMV7A bool "Qemu ARMv7a CPUs board" depends on ARCH_CHIP_QEMU_ARM @@ -3898,8 +3884,6 @@ config ARCH_BOARD default "milkv_duos" if ARCH_BOARD_SG2000_MILKV_DUOS default "starpro64" if ARCH_BOARD_EIC7700X_STARPRO64 default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD - default "a2g-tc397-5v-tft" if ARCH_BOARD_A2G_TC397_5V_TFT - default "triboard_tc4x9_com" if ARCH_BOARD_TRIBOARD_TC4X9_COM default "qemu-armv7a" if ARCH_BOARD_QEMU_ARMV7A default "qemu-armv7r" if ARCH_BOARD_QEMU_ARMV7R default "qemu-armv8a" if ARCH_BOARD_QEMU_ARMV8A @@ -4122,9 +4106,6 @@ endif if ARCH_BOARD_SABRE_6QUAD source "boards/arm/imx6/sabre-6quad/Kconfig" endif -if ARCH_BOARD_A2G_TC397_5V_TFT -source "boards/tricore/tc397/a2g-tc397-5v-tft/Kconfig" -endif if ARCH_BOARD_MPS2_AN500 source "boards/arm/mps/mps2-an500/Kconfig" endif diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/CMakeLists.txt b/boards/tricore/tc397/a2g-tc397-5v-tft/CMakeLists.txt deleted file mode 100644 index dea61821ca73a..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/tricore/tc397/a2g-tc397-5v-tft/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/Kconfig b/boards/tricore/tc397/a2g-tc397-5v-tft/Kconfig deleted file mode 100644 index 66142b2180cda..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_A2G_TC397_5V_TFT -endif diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/configs/nsh/defconfig b/boards/tricore/tc397/a2g-tc397-5v-tft/configs/nsh/defconfig deleted file mode 100644 index fe5e74cabecf5..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/configs/nsh/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="tricore" -CONFIG_ARCH_BOARD="a2g-tc397-5v-tft" -CONFIG_ARCH_BOARD_A2G_TC397_5V_TFT=y -CONFIG_ARCH_CHIP="tc397" -CONFIG_ARCH_CHIP_TC397=y -CONFIG_ARCH_CHIP_TC3XX=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_NUSER_INTERRUPTS=48 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_TRICORE=y -CONFIG_BOARD_LOOPSPERMSEC=99369 -CONFIG_BOOT_RUNFROMSDRAM=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_ASSERTIONS=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXPERIMENTAL=y -CONFIG_FS_PROCFS=y -CONFIG_FS_TMPFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_MEMFD_ERROR=y -CONFIG_NDEBUG=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=245760 -CONFIG_RAM_START=0x70000000 -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SPINLOCK=y -CONFIG_STACK_COLORATION=y -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2016 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSLOG_BUFFER=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSLOG_INTBUFFER=y -CONFIG_SYSLOG_MAX_CHANNELS=2 -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_SCHED_EVENTS=y -CONFIG_HRTIMER=y diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/include/board.h b/boards/tricore/tc397/a2g-tc397-5v-tft/include/board.h deleted file mode 100644 index 0e4f012fc588c..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/include/board.h +++ /dev/null @@ -1,40 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_H -#define __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Definitions - ****************************************************************************/ - -#endif /* __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_H */ diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h b/boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h deleted file mode 100644 index 681acca15b79d..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h +++ /dev/null @@ -1,366 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_MEMORYMAP_H -#define __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BANKA_CORE0_PFLASH_KERNEL_START 0x80000000 -#define BANKA_CORE0_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE0_PFLASH_USER_START 0x80180000 -#define BANKA_CORE0_PFLASH_USER_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE1_PFLASH_KERNEL_START 0x80300000 -#define BANKA_CORE1_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE1_PFLASH_USER_START 0x80480000 -#define BANKA_CORE1_PFLASH_USER_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE2_PFLASH_KERNEL_START 0x80600000 -#define BANKA_CORE2_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE2_PFLASH_USER_START 0x80780000 -#define BANKA_CORE2_PFLASH_USER_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE3_PFLASH_KERNEL_START 0x80900000 -#define BANKA_CORE3_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE3_PFLASH_USER_START 0x80A80000 -#define BANKA_CORE3_PFLASH_USER_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE4_PFLASH_KERNEL_START 0x80C00000 -#define BANKA_CORE4_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE4_PFLASH_USER_START 0x80D80000 -#define BANKA_CORE4_PFLASH_USER_SIZE 0x180000 /* 1536KB */ -#define BANKA_CORE5_PFLASH_KERNEL_START 0x80F00000 -#define BANKA_CORE5_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ -#define BANKA_CORE5_PFLASH_USER_START 0x80F80000 -#define BANKA_CORE5_PFLASH_USER_SIZE 0x80000 /* 512KB */ -#define CORE0_STACK_KERNEL_START 0x70000000 -#define CORE0_STACK_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE0_STACK_USER_START 0x70008000 -#define CORE0_STACK_USER_SIZE 0x8000 /* 32KB */ -#define CORE0_DSPR_KERNEL_START 0x70010000 -#define CORE0_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ -#define CORE0_DSPR_USER_START 0x7003C000 -#define CORE0_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE0_PSPR_KERNEL_START 0x70100000 -#define CORE0_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE0_PSPR_USER_START 0x70108000 -#define CORE0_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE0_DLMU_KERNEL_START 0x90000000 -#define CORE0_DLMU_KERNEL_SIZE 0x0 /* 0KB */ -#define CORE0_DLMU_USER_START 0x90000000 -#define CORE0_DLMU_USER_SIZE 0x10000 /* 64KB */ -#define CORE1_STACK_KERNEL_START 0x60000000 -#define CORE1_STACK_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE1_STACK_USER_START 0x60008000 -#define CORE1_STACK_USER_SIZE 0x8000 /* 32KB */ -#define CORE1_DSPR_KERNEL_START 0x60010000 -#define CORE1_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ -#define CORE1_DSPR_USER_START 0x6003C000 -#define CORE1_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE1_PSPR_KERNEL_START 0x60100000 -#define CORE1_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE1_PSPR_USER_START 0x60108000 -#define CORE1_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE1_DLMU_KERNEL_START 0x90010000 -#define CORE1_DLMU_KERNEL_SIZE 0x0 /* 0KB */ -#define CORE1_DLMU_USER_START 0x90010000 -#define CORE1_DLMU_USER_SIZE 0x10000 /* 64KB */ -#define CORE2_STACK_KERNEL_START 0x50000000 -#define CORE2_STACK_KERNEL_SIZE 0x6000 /* 24KB */ -#define CORE2_STACK_USER_START 0x50006000 -#define CORE2_STACK_USER_SIZE 0x5000 /* 20KB */ -#define CORE2_DSPR_KERNEL_START 0x5000B000 -#define CORE2_DSPR_KERNEL_SIZE 0xD000 /* 52KB */ -#define CORE2_DSPR_USER_START 0x50018000 -#define CORE2_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE2_PSPR_KERNEL_START 0x50100000 -#define CORE2_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE2_PSPR_USER_START 0x50108000 -#define CORE2_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE2_DLMU_KERNEL_START 0x90020000 -#define CORE2_DLMU_KERNEL_SIZE 0x0 /* 0KB */ -#define CORE2_DLMU_USER_START 0x90020000 -#define CORE2_DLMU_USER_SIZE 0x10000 /* 64KB */ -#define CORE3_STACK_KERNEL_START 0x40000000 -#define CORE3_STACK_KERNEL_SIZE 0x6000 /* 24KB */ -#define CORE3_STACK_USER_START 0x40006000 -#define CORE3_STACK_USER_SIZE 0x5000 /* 20KB */ -#define CORE3_DSPR_KERNEL_START 0x4000B000 -#define CORE3_DSPR_KERNEL_SIZE 0xD000 /* 52KB */ -#define CORE3_DSPR_USER_START 0x40018000 -#define CORE3_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE3_PSPR_KERNEL_START 0x40100000 -#define CORE3_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE3_PSPR_USER_START 0x40108000 -#define CORE3_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE3_DLMU_KERNEL_START 0x90030000 -#define CORE3_DLMU_KERNEL_SIZE 0x0 /* 0KB */ -#define CORE3_DLMU_USER_START 0x90030000 -#define CORE3_DLMU_USER_SIZE 0x10000 /* 64KB */ -#define CORE4_STACK_KERNEL_START 0x30000000 -#define CORE4_STACK_KERNEL_SIZE 0x6000 /* 24KB */ -#define CORE4_STACK_USER_START 0x30006000 -#define CORE4_STACK_USER_SIZE 0x5000 /* 20KB */ -#define CORE4_DSPR_KERNEL_START 0x3000B000 -#define CORE4_DSPR_KERNEL_SIZE 0xD000 /* 52KB */ -#define CORE4_DSPR_USER_START 0x30018000 -#define CORE4_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE4_PSPR_KERNEL_START 0x30100000 -#define CORE4_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE4_PSPR_USER_START 0x30108000 -#define CORE4_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE4_DLMU_KERNEL_START 0x90100000 -#define CORE4_DLMU_KERNEL_SIZE 0x0 /* 0KB */ -#define CORE4_DLMU_USER_START 0x90100000 -#define CORE4_DLMU_USER_SIZE 0x10000 /* 64KB */ -#define CORE5_STACK_KERNEL_START 0x10000000 -#define CORE5_STACK_KERNEL_SIZE 0x6000 /* 24KB */ -#define CORE5_STACK_USER_START 0x10006000 -#define CORE5_STACK_USER_SIZE 0x5000 /* 20KB */ -#define CORE5_DSPR_KERNEL_START 0x1000B000 -#define CORE5_DSPR_KERNEL_SIZE 0xD000 /* 52KB */ -#define CORE5_DSPR_USER_START 0x10018000 -#define CORE5_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE5_PSPR_KERNEL_START 0x10100000 -#define CORE5_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE5_PSPR_USER_START 0x10108000 -#define CORE5_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE5_DLMU_KERNEL_START 0x90110000 -#define CORE5_DLMU_KERNEL_SIZE 0x0 /* 0KB */ -#define CORE5_DLMU_USER_START 0x90110000 -#define CORE5_DLMU_USER_SIZE 0x10000 /* 64KB */ -#define LMU0_UNUSED_START 0xB0040000 -#define LMU0_UNUSED_SIZE 0x40000 /* 256KB */ -#define LMU1_UNUSED_START 0xB0080000 -#define LMU1_UNUSED_SIZE 0x40000 /* 256KB */ -#define LMU2_UNUSED_START 0xB00C0000 -#define LMU2_UNUSED_SIZE 0x40000 /* 256KB */ -#define DFLASH0_NVM_START 0xAF000000 -#define DFLASH0_NVM_SIZE 0x40000 /* 256KB */ -#define DFLASH0_MANUFACTURY_START 0xAF040000 -#define DFLASH0_MANUFACTURY_SIZE 0x2800 /* 10K */ -#define DFLASH0_BSWLOG_START 0xAF042800 -#define DFLASH0_BSWLOG_SIZE 0x10000 /* 64K */ -#define DFLASH0_TRAPINFO_START 0xAF052800 -#define DFLASH0_TRAPINFO_SIZE 0x4000 /* 16K */ -#define DFLASH0_DFXLOG_START 0xAF056800 -#define DFLASH0_DFXLOG_SIZE 0x4000 /* 16K */ -#define DFLASH0_UNUSED_START 0xAF05A800 -#define DFLASH0_UNUSED_SIZE 0xA5800 /* 662K */ -#define UCB0_START 0xAF400000 -#define UCB0_SIZE 0x6000 /* 24K */ -#define PERIPHERALS_START 0xF0000000 -#define PERIPHERALS_SIZE 0xB720000 /* 187520K */ -#define CORE0_DCACHE_START 0x7003C000 -#define CORE0_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE1_DCACHE_START 0x6003C000 -#define CORE1_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE2_DCACHE_START 0x50018000 -#define CORE2_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE3_DCACHE_START 0x40018000 -#define CORE3_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE4_DCACHE_START 0x30018000 -#define CORE4_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE5_DCACHE_START 0x10018000 -#define CORE5_DCACHE_SIZE 0x4000 /* 16K */ - -/**************************************************************************** - * Common macros - * - ****************************************************************************/ - -#ifdef CONFIG_BUILD_FLAT - -# define CORE0_PFLASH_KERNEL_START BANKA_CORE0_PFLASH_KERNEL_START -# define CORE0_PFLASH_KERNEL_SIZE BANKA_CORE0_PFLASH_KERNEL_SIZE -# define CORE1_PFLASH_KERNEL_START BANKA_CORE1_PFLASH_KERNEL_START -# define CORE1_PFLASH_KERNEL_SIZE BANKA_CORE1_PFLASH_KERNEL_SIZE -# define CORE2_PFLASH_KERNEL_START BANKA_CORE2_PFLASH_KERNEL_START -# define CORE2_PFLASH_KERNEL_SIZE BANKA_CORE2_PFLASH_KERNEL_SIZE -# define CORE3_PFLASH_KERNEL_START BANKA_CORE3_PFLASH_KERNEL_START -# define CORE3_PFLASH_KERNEL_SIZE BANKA_CORE3_PFLASH_KERNEL_SIZE -# define CORE4_PFLASH_KERNEL_START BANKA_CORE4_PFLASH_KERNEL_START -# define CORE4_PFLASH_KERNEL_SIZE BANKA_CORE4_PFLASH_KERNEL_SIZE -# define CORE5_PFLASH_KERNEL_START BANKA_CORE5_PFLASH_KERNEL_START -# define CORE5_PFLASH_KERNEL_SIZE BANKA_CORE5_PFLASH_KERNEL_SIZE - -#else - -# define CORE0_PFLASH_KERNEL_START BANKA_CORE0_PFLASH_KERNEL_START -# define CORE0_PFLASH_KERNEL_SIZE BANKA_CORE0_PFLASH_KERNEL_SIZE -# define CORE0_PFLASH_USER_START BANKA_CORE0_PFLASH_USER_START -# define CORE0_PFLASH_USER_SIZE BANKA_CORE0_PFLASH_USER_SIZE - -# define CORE1_PFLASH_KERNEL_START BANKA_CORE1_PFLASH_KERNEL_START -# define CORE1_PFLASH_KERNEL_SIZE BANKA_CORE1_PFLASH_KERNEL_SIZE -# define CORE1_PFLASH_USER_START BANKA_CORE1_PFLASH_USER_START -# define CORE1_PFLASH_USER_SIZE BANKA_CORE1_PFLASH_USER_SIZE - -# define CORE2_PFLASH_KERNEL_START BANKA_CORE2_PFLASH_KERNEL_START -# define CORE2_PFLASH_KERNEL_SIZE BANKA_CORE2_PFLASH_KERNEL_SIZE -# define CORE2_PFLASH_USER_START BANKA_CORE2_PFLASH_USER_START -# define CORE2_PFLASH_USER_SIZE BANKA_CORE2_PFLASH_USER_SIZE - -# define CORE3_PFLASH_KERNEL_START BANKA_CORE3_PFLASH_KERNEL_START -# define CORE3_PFLASH_KERNEL_SIZE BANKA_CORE3_PFLASH_KERNEL_SIZE -# define CORE3_PFLASH_USER_START BANKA_CORE3_PFLASH_USER_START -# define CORE3_PFLASH_USER_SIZE BANKA_CORE3_PFLASH_USER_SIZE - -# define CORE4_PFLASH_KERNEL_START BANKA_CORE4_PFLASH_KERNEL_START -# define CORE4_PFLASH_KERNEL_SIZE BANKA_CORE4_PFLASH_KERNEL_SIZE -# define CORE4_PFLASH_USER_START BANKA_CORE4_PFLASH_USER_START -# define CORE4_PFLASH_USER_SIZE BANKA_CORE4_PFLASH_USER_SIZE - -# define CORE5_PFLASH_KERNEL_START BANKA_CORE5_PFLASH_KERNEL_START -# define CORE5_PFLASH_KERNEL_SIZE BANKA_CORE5_PFLASH_KERNEL_SIZE -# define CORE5_PFLASH_USER_START BANKA_CORE5_PFLASH_USER_START -# define CORE5_PFLASH_USER_SIZE BANKA_CORE5_PFLASH_USER_SIZE - -#endif - -#define BL_PFLASH_START BANKA_BL_PFLASH_START -#define BL_PFLASH_SIZE BANKA_BL_PFLASH_SIZE -#define BL_DLMU_START CORE0_DLMU_KERNEL_START -#define BL_DLMU_SIZE CORE0_DLMU_KERNEL_SIZE -#define BL_DSPR_START CORE0_DSPR_KERNEL_START -#define BL_DSPR_SIZE CORE0_DSPR_KERNEL_SIZE -#define BL_PSPR_START CORE0_PSPR_KERNEL_START -#define BL_PSPR_SIZE CORE0_PSPR_KERNEL_SIZE -#define MBF_HASH_START BANKA_MBF_HASH_START -#define MBF_HASH_SIZE BANKA_MBF_HASH_SIZE - -#define NC_START(addr) \ - ((addr) >= 0x80000000 && (addr) <= 0x9FFFFFFF ? (addr) + 0x20000000 : (addr)) - -#define AURIX_PERIPHERAL_BASE_ADDR 0xF0000000 -#define AURIX_PERIPHERAL_SIZE 0x0B720000 - -#define DSPR_LOCAL_START 0xD0000000 -#define PSPR_LOCAL_START 0xC0000000 - -#define BACKGROUND_START 0x0 -#define BACKGROUND_SIZE 0xFFFFFFFF - -#define CORE0_DCACHE_KERNEL_START 0x7003C000 -#define CORE0_DCACHE_KERNEL_SIZE 0x4000 -#define CORE1_DCACHE_KERNEL_START 0x6003C000 -#define CORE1_DCACHE_KERNEL_SIZE 0x4000 -#define CORE2_DCACHE_KERNEL_START 0x50018000 -#define CORE2_DCACHE_KERNEL_SIZE 0x4000 -#define CORE3_DCACHE_KERNEL_START 0x40018000 -#define CORE3_DCACHE_KERNEL_SIZE 0x4000 -#define CORE4_DCACHE_KERNEL_START 0x30018000 -#define CORE4_DCACHE_KERNEL_SIZE 0x4000 -#define CORE5_DCACHE_KERNEL_START 0x10018000 -#define CORE5_DCACHE_KERNEL_SIZE 0x4000 - -#define CORE_PFLASH_KERNEL_START(COREID) CORE##COREID##_PFLASH_KERNEL_START -#define CORE_PFLASH_KERNEL_SIZE(COREID) CORE##COREID##_PFLASH_KERNEL_SIZE -#define GENERATE_CORE_PFLASH_KERNEL_START(COREID) CORE_PFLASH_KERNEL_START(COREID) -#define GENERATE_CORE_PFLASH_KERNEL_SIZE(COREID) CORE_PFLASH_KERNEL_SIZE(COREID) - -#define CORE_STACK_KERNEL_START(COREID) CORE##COREID##_STACK_KERNEL_START -#define CORE_STACK_KERNEL_SIZE(COREID) CORE##COREID##_STACK_KERNEL_SIZE -#define GENERATE_CORE_STACK_KERNEL_START(COREID) CORE_STACK_KERNEL_START(COREID) -#define GENERATE_CORE_STACK_KERNEL_SIZE(COREID) CORE_STACK_KERNEL_SIZE(COREID) - -#define CORE_DSPR_KERNEL_START(COREID) CORE##COREID##_DSPR_KERNEL_START -#define CORE_DSPR_KERNEL_SIZE(COREID) CORE##COREID##_DSPR_KERNEL_SIZE -#define GENERATE_CORE_DSPR_KERNEL_START(COREID) CORE_DSPR_KERNEL_START(COREID) -#define GENERATE_CORE_DSPR_KERNEL_SIZE(COREID) CORE_DSPR_KERNEL_SIZE(COREID) - -#define CORE_PSPR_KERNEL_START(COREID) CORE##COREID##_PSPR_KERNEL_START -#define CORE_PSPR_KERNEL_SIZE(COREID) CORE##COREID##_PSPR_KERNEL_SIZE -#define GENERATE_CORE_PSPR_KERNEL_START(COREID) CORE_PSPR_KERNEL_START(COREID) -#define GENERATE_CORE_PSPR_KERNEL_SIZE(COREID) CORE_PSPR_KERNEL_SIZE(COREID) - -#define CORE_DLMU_KERNEL_START(COREID) CORE##COREID##_DLMU_KERNEL_START -#define CORE_DLMU_KERNEL_SIZE(COREID) CORE##COREID##_DLMU_KERNEL_SIZE -#define GENERATE_CORE_DLMU_KERNEL_START(COREID) CORE_DLMU_KERNEL_START(COREID) -#define GENERATE_CORE_DLMU_KERNEL_SIZE(COREID) CORE_DLMU_KERNEL_SIZE(COREID) - -#define CORE_DCACHE_KERNEL_START(COREID) CORE##COREID##_DCACHE_KERNEL_START -#define CORE_DCACHE_KERNEL_SIZE(COREID) CORE##COREID##_DCACHE_KERNEL_SIZE -#define GENERATE_CORE_DCACHE_KERNEL_START(COREID) CORE_DCACHE_KERNEL_START(COREID) -#define GENERATE_CORE_DCACHE_KERNEL_SIZE(COREID) CORE_DCACHE_KERNEL_SIZE(COREID) - -#ifndef CONFIG_BUILD_FLAT - -#define CORE_PFLASH_USER_START(COREID) CORE##COREID##_PFLASH_USER_START -#define CORE_PFLASH_USER_SIZE(COREID) CORE##COREID##_PFLASH_USER_SIZE -#define GENERATE_CORE_PFLASH_USER_START(COREID) CORE_PFLASH_USER_START(COREID) -#define GENERATE_CORE_PFLASH_USER_SIZE(COREID) CORE_PFLASH_USER_SIZE(COREID) - -#define CORE_STACK_USER_START(COREID) CORE##COREID##_STACK_USER_START -#define CORE_STACK_USER_SIZE(COREID) CORE##COREID##_STACK_USER_SIZE -#define GENERATE_CORE_STACK_USER_START(COREID) CORE_STACK_USER_START(COREID) -#define GENERATE_CORE_STACK_USER_SIZE(COREID) CORE_STACK_USER_SIZE(COREID) - -#define CORE_DSPR_USER_START(COREID) CORE##COREID##_DSPR_USER_START -#define CORE_DSPR_USER_SIZE(COREID) CORE##COREID##_DSPR_USER_SIZE -#define GENERATE_CORE_DSPR_USER_START(COREID) CORE_DSPR_USER_START(COREID) -#define GENERATE_CORE_DSPR_USER_SIZE(COREID) CORE_DSPR_USER_SIZE(COREID) - -#define CORE_PSPR_USER_START(COREID) CORE##COREID##_PSPR_USER_START -#define CORE_PSPR_USER_SIZE(COREID) CORE##COREID##_PSPR_USER_SIZE -#define GENERATE_CORE_PSPR_USER_START(COREID) CORE_PSPR_USER_START(COREID) -#define GENERATE_CORE_PSPR_USER_SIZE(COREID) CORE_PSPR_USER_SIZE(COREID) - -#define CORE_DLMU_USER_START(COREID) CORE##COREID##_DLMU_USER_START -#define CORE_DLMU_USER_SIZE(COREID) CORE##COREID##_DLMU_USER_SIZE -#define GENERATE_CORE_DLMU_USER_START(COREID) CORE_DLMU_USER_START(COREID) -#define GENERATE_CORE_DLMU_USER_SIZE(COREID) CORE_DLMU_USER_SIZE(COREID) - -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel deleted file mode 100644 index 23a9c438f710b..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel +++ /dev/null @@ -1,554 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include "arch/board/board_memorymap.h" - -#define __JOIN2(x,y) x##y -#define JOIN2(x,y) __JOIN2(x,y) -#define __JOIN3(x,y,z) x##y##z -#define JOIN3(x,y,z) __JOIN3(x,y,z) -#define __JOIN4(x,y,z,w) x##y##z##w -#define JOIN4(x,y,z,w) __JOIN4(x,y,z,w) - -#define COREID_LST(x) JOIN2(x, CONFIG_CPU_COREID) -#define COREID_MID(x,y) JOIN3(x, CONFIG_CPU_COREID, y) - -/* Default linker script, for normal executables */ -OUTPUT_FORMAT("elf32-tricore") -OUTPUT_ARCH("tricore") -#if CONFIG_CPU_COREID == 0 -ENTRY(_START) -#endif - -__TRICORE_DERIVATE_MEMORY_MAP__ = 0x390; - -LCF_PFLASH_KERNEL_START = GENERATE_CORE_PFLASH_KERNEL_START(CONFIG_CPU_COREID); -LCF_PFLASH_KERNEL_SIZE = GENERATE_CORE_PFLASH_KERNEL_SIZE(CONFIG_CPU_COREID); -LCF_DSPR_KERNEL_START = GENERATE_CORE_DSPR_KERNEL_START(CONFIG_CPU_COREID); -LCF_DSPR_KERNEL_SIZE = GENERATE_CORE_DSPR_KERNEL_SIZE(CONFIG_CPU_COREID); -LCF_PSPR_KERNEL_START = GENERATE_CORE_PSPR_KERNEL_START(CONFIG_CPU_COREID); -LCF_PSPR_KERNEL_SIZE = GENERATE_CORE_PSPR_KERNEL_SIZE(CONFIG_CPU_COREID); -LCF_DLMU_KERNEL_START = GENERATE_CORE_DLMU_KERNEL_START(CONFIG_CPU_COREID); -LCF_DLMU_KERNEL_SIZE = GENERATE_CORE_DLMU_KERNEL_SIZE(CONFIG_CPU_COREID); -LCF_KSTACK_START = GENERATE_CORE_STACK_KERNEL_START(CONFIG_CPU_COREID); -LCF_KSTACK_SIZE = GENERATE_CORE_STACK_KERNEL_SIZE(CONFIG_CPU_COREID); - -LCF_CSA_SIZE = 40k; -LCF_USTACK_SIZE = CONFIG_IDLETHREAD_STACKSIZE; -LCF_ISTACK_SIZE = CONFIG_ARCH_INTERRUPTSTACK; - -LCF_CSA_OFFSET = (LCF_DSPR_KERNEL_SIZE - 1k - LCF_CSA_SIZE); -LCF_ISTACK_OFFSET = (LCF_CSA_OFFSET - 256 - LCF_ISTACK_SIZE); -LCF_USTACK_OFFSET = (LCF_ISTACK_OFFSET - 256 - LCF_USTACK_SIZE); - -LCF_STARTPTR = LCF_PFLASH_KERNEL_START; -LCF_STARTPTR_NC = NC_START(LCF_STARTPTR); -LCF_TRAPVEC_START = LCF_STARTPTR + 0x100; - -COREID_LST(__INTTAB_CPU) = LCF_PFLASH_KERNEL_START; - -LCF_STARTPTR_NC_CPU0 = NC_START(CORE0_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU1 = NC_START(CORE1_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU2 = NC_START(CORE2_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU3 = NC_START(CORE3_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU4 = NC_START(CORE4_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU5 = NC_START(CORE5_PFLASH_KERNEL_START); -RESET = CORE0_PFLASH_KERNEL_START; - -MEMORY -{ - kstack (w!xp): org = LCF_KSTACK_START, len = LCF_KSTACK_SIZE - - dspr (w!xp): org = LCF_DSPR_KERNEL_START, len = LCF_DSPR_KERNEL_SIZE - pspr (w!xp): org = LCF_PSPR_KERNEL_START, len = LCF_PSPR_KERNEL_SIZE - - psram_local (w!xp): org = PSPR_LOCAL_START, len = LCF_PSPR_KERNEL_SIZE - - pfls (rx!p): org = LCF_PFLASH_KERNEL_START, len = LCF_PFLASH_KERNEL_SIZE - pfls_nc (rx!p): org = NC_START(LCF_PFLASH_KERNEL_START), len = LCF_PFLASH_KERNEL_SIZE - - ucb (rx!p): org = 0xAF400000, len = 24K - - cpu_dlmu (w!xp): org = LCF_DLMU_KERNEL_START, len = LCF_DLMU_KERNEL_SIZE - cpu_dlmu_nc (w!xp): org = NC_START(LCF_DLMU_KERNEL_START), len = LCF_DLMU_KERNEL_SIZE -} - -/* map cached and non cached addresses */ -REGION_MIRROR("pfls", "pfls_nc") -REGION_MIRROR("cpu_dlmu", "cpu_dlmu_nc") - -/*Sections located at absolute fixed address*/ -/*Fixed memory Allocations for stack memory*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.ustack) (LCF_DSPR_KERNEL_START + LCF_USTACK_OFFSET): - { - PROVIDE(__USTACK_END = .); - PROVIDE(COREID_MID(__USTACK, _END) = .); - . = . + LCF_USTACK_SIZE; - PROVIDE(__USTACK = .); - PROVIDE(COREID_LST(__USTACK) = .); - } - - CORE_SEC(.istack) (LCF_DSPR_KERNEL_START + LCF_ISTACK_OFFSET): - { - PROVIDE(__ISTACK_END = .); - PROVIDE(COREID_MID(__ISTACK, _END) = .); - . = . + LCF_ISTACK_SIZE; - PROVIDE(__ISTACK = .); - PROVIDE(COREID_LST(__ISTACK) = .); - } - CORE_SEC(.csa) (LCF_DSPR_KERNEL_START + LCF_CSA_OFFSET): - { - PROVIDE(COREID_LST(__CSA) = .); - . = . + LCF_CSA_SIZE; - PROVIDE(COREID_MID(__CSA, _END) = .); - } -} - -/*Fixed memory Allocations for _START*/ -CORE_ID = GLOBAL ; -SECTIONS -{ - .start_tc (LCF_STARTPTR) : FLAGS(rxl) - { - KEEP (*(.start)); - KEEP (*(.start_cpu?)); - } > pfls - - .interface_const (LCF_STARTPTR + 0x20) : - { - __IF_CONST = .; - KEEP (*(.interface_const)); - } > pfls - - PROVIDE(__START = LCF_STARTPTR); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU0 = 0); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU1 = 1); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU2 = 1); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU3 = 1); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU4 = 1); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU5 = 1); -} - -/*Fixed memory Allocations for Trap Vector Table*/ -CORE_ID = GLOBAL; -SECTIONS -{ - .traptab_tc (LCF_TRAPVEC_START) : - { - PROVIDE(COREID_LST(__TRAPTAB_CPU) = .); - KEEP (*(.COREID_LST(traptab_cpu))); - } > pfls -} - -/*Fixed memory Allocations for _START1 to 5 */ -CORE_ID = GLOBAL ; -SECTIONS -{ - PROVIDE(__START1 = CORE1_PFLASH_KERNEL_START); - PROVIDE(__START2 = CORE2_PFLASH_KERNEL_START); - PROVIDE(__START3 = CORE3_PFLASH_KERNEL_START); - PROVIDE(__START4 = CORE4_PFLASH_KERNEL_START); - PROVIDE(__START5 = CORE5_PFLASH_KERNEL_START); -} - -/*Fixed memory Allocations for Interrupt Vector Table*/ -SECTIONS -{ - /*Interrupt Vector Table*/ - .COREID_MID(inttab_tc, _0FF) (COREID_LST(__INTTAB_CPU) + 0x1FE0) : - { - . = ALIGN(8); - KEEP (*(.COREID_MID(intvec_tc, _255))); - . = ALIGN(0x2000); - } > pfls -} - -/* Fixed memory Allocations for BMHD*/ -CORE_ID = GLOBAL; -SECTIONS -{ - .bmhd_0_org (0xaf400000) : FLAGS(arl) { KEEP (*(.bmhd_0_orig)); } > ucb - .bmhd_1_org (0xaf400200) : FLAGS(arl) { KEEP (*(.bmhd_1_orig)); } > ucb - .bmhd_2_org (0xaf400400) : FLAGS(arl) { KEEP (*(.bmhd_2_orig)); } > ucb - .bmhd_3_org (0xaf400600) : FLAGS(arl) { KEEP (*(.bmhd_3_orig)); } > ucb -} - -/*Relative A0/A1/A8/A9 Addressable Sections*/ -CORE_ID = GLOBAL; -SECTIONS -{ - /*Relative A0 Addressable Data, selectable with patterns and user defined sections*/ - /*Note: A0 addressable area is common, to make the functions callable in any CPU*/ - /*Relative A0 Addressable Data, selectable by toolchain*/ - CORE_SEC(.sdata) : FLAGS(awsl) - { - *(.sdata) - *(.sdata.*) - . = ALIGN(4); - } > dspr AT> pfls - - CORE_SEC(.sbss) (NOLOAD): FLAGS(aws) - { - *(.sbss) - *(.sbss.*) - } > dspr - _SMALL_DATA_ = SIZEOF(CORE_SEC(.sdata)) ? ADDR(CORE_SEC(.sdata)) : (ADDR(CORE_SEC(.sdata)) & 0xF0000000) + 32k ; - __A0_MEM = _SMALL_DATA_; -} - -CORE_ID = GLOBAL; -SECTIONS -{ - /*Relative A1 Addressable Const, selectable with patterns and user defined sections*/ - /*Note: A1 addressable area is common, to make the functions callable in any CPU*/ - /*Relative A1 Addressable Const, selectable by toolchain*/ - CORE_SEC(.sdata2) : FLAGS(arsl) - { - *(.srodata) - *(.srodata.*) - } > pfls - _SMALL_DATA2_ = SIZEOF(CORE_SEC(.sdata2)) ? ADDR(CORE_SEC(.sdata2)) : (ADDR(CORE_SEC(.sdata2)) & 0xF0000000) + 32k ; - __A1_MEM = _SMALL_DATA2_; -} - -CORE_ID = GLOBAL; -SECTIONS -{ - /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ - CORE_SEC(.sdata4) : - { - *(.a9sdata) - *(.a9sdata.*) - . = ALIGN(4); - } > dspr AT> pfls - - CORE_SEC(.sbss4) (NOLOAD) : - { - *(.a9sbss) - *(.a9sbss.*) - } > dspr - - _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; - __A9_MEM = _SMALL_DATA4_; - - /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ - CORE_SEC(.sdata3) : FLAGS(arsl) - { - *(.rodata_a8) - *(.rodata_a8.*) - } > pfls - - _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; - __A8_MEM = _SMALL_DATA3_; -} - -/*kstack*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.stack) (NOLOAD) : FLAGS(aw) - { - *(.dtcm_stack) - *(.dtcm_stack.*) - } > kstack -} - -/*data&bss*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.dspr_data) : FLAGS(awzl) - { - *Ifx_Ssw_Tc?.* (.data) - *Cpu?_Main.* (.data.*) - . = ALIGN(4); - } > dspr AT> pfls - - CORE_SEC(.dspr_bss) (NOLOAD) : FLAGS(awz) - { - *Ifx_Ssw_Tc?.* (.bss) - *Cpu?_Main.* (.bss.*) - . = ALIGN(4); - } > dspr - - CORE_SEC(.zdata) : FLAGS(awzl) - { - *(.zdata) - *(.zdata.*) - *(.gnu.linkonce.z.*) - . = ALIGN(4); - } > dspr AT> pfls - - CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) - { - *(.zbss) - *(.zbss.*) - *(.bbss) - *(.bbss.*) - *(.gnu.linkonce.zb.*) - } > dspr - - CORE_SEC(.data) : FLAGS(awl) - { - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(4); - } > dspr AT> pfls - - CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) - { - *(.bss) - *(.bss.*) - *(.lmubss_cpu?) - *(.lmubss_cpu?.*) - *(.gnu.linkonce.b.*) - } > dspr -} - -/*Heap*/ -CORE_ID = GLOBAL; -SECTIONS -{ - .heap (NOLOAD) : FLAGS(aw) - { - . = ALIGN(4); - _sheap = ABSOLUTE(.); - _eheap = ABSOLUTE(__USTACK_END); - } > dspr -} - -/*rodata*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.rodata) : FLAGS(arl) - { - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - /* - * Create the clear and copy tables that tell the startup code - * which memory areas to clear and to copy, respectively. - */ - . = ALIGN(4) ; - PROVIDE(__clear_table = .); - LONG(0 + ADDR(.dspr_bss)); LONG(SIZEOF(.dspr_bss)); - LONG(0 + ADDR(.zbss)); LONG(SIZEOF(.zbss)); - LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss)); - LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); - LONG(0 + ADDR(.sbss4)); LONG(SIZEOF(.sbss4)); - LONG(-1); LONG(-1); - PROVIDE(__clear_table_powerOn = .); - LONG(-1); LONG(-1); - PROVIDE(__copy_table = .); - LONG(LOADADDR(.dspr_data)); LONG(0 + ADDR(.dspr_data)); LONG(SIZEOF(.dspr_data)); - LONG(LOADADDR(.zdata)); LONG(0 + ADDR(.zdata)); LONG(SIZEOF(.zdata)); - LONG(LOADADDR(.sdata)); LONG(0 + ADDR(.sdata)); LONG(SIZEOF(.sdata)); - LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); - LONG(LOADADDR(.sdata4)); LONG(0 + ADDR(.sdata4)); LONG(SIZEOF(.sdata4)); - LONG(LOADADDR(.psram_text)); LONG(0 + ADDR(.psram_text)); LONG(SIZEOF(.psram_text)); - LONG(-1); LONG(-1); LONG(-1); - PROVIDE(__copy_table_powerOn = .) ; - LONG(-1); LONG(-1); LONG(-1); - . = ALIGN(8); - } > pfls -} - -/*Code selections*/ -/*Code Sections, selectable with patterns and user defined sections*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.zrodata) : FLAGS(arzl) - { - *Ifx_Ssw_Tc?.* (.zrodata) - *Cpu?_Main.* (.zrodata) - *(.zrodata_cpu?) - *(.zrodata) - *(.zrodata.*) - } > pfls - - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------Start----------------------------------------- - */ - .init : - { - PROVIDE(__init_start = .); - KEEP(*(.init)) - KEEP(*(.init*)) - PROVIDE(__init_end = .); - . = ALIGN(8); - - } > pfls - - .fini : - { - PROVIDE(__fini_start = .); - KEEP(*(.fini)) - KEEP(*(.fini*)) - PROVIDE(__fini_end = .); - . = ALIGN(8); - } > pfls - - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - CORE_SEC(.psram_text) : FLAGS(awxl) - { - . = ALIGN(4); - *aurix_mtd_flash.*(.text) - *aurix_mtd_flash.*(.text.*) - *aurix_mtd_partition.*(.text) - *aurix_mtd_partition.*(.text.*) - . = ALIGN(4); - } > pspr AT> pfls - - CORE_SEC(.text) : FLAGS(axl) - { - . = ALIGN(4); - *Ifx_Ssw_Tc?.*(.text) - *Cpu?_Main.*(.text) - *Ifx_Ssw_Tc?.*(.text.*) - *Cpu?_Main.*(.text.*) - *(.text) - *(.text.*) - *(.gcc_except_table) - *(.gnu.linkonce.t.*) - *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ - . = ALIGN(8); - } > pfls - - /* - * C++ exception handling tables. NOTE: gcc emits .eh_frame - * sections when compiling C sources with debugging enabled (-g). - * If you can be sure that your final application consists - * exclusively of C objects (i.e., no C++ objects), you may use - * the -R option of the "strip" and "objcopy" utilities to remove - * the .eh_frame section from the executable. - */ - .eh_frame_hdr : ALIGN(8) - { - KEEP (*(.eh_frame_hdr)) - . = ALIGN(8); - } > pfls - - .eh_frame : ALIGN(8) - { - __EH_FRAME_BEGIN__ = . ; - KEEP (*(.eh_frame)) - __EH_FRAME_END__ = . ; - . = ALIGN(8); - } > pfls - - /* - * Constructors and destructors. - */ - .ctors : FLAGS(ar) - { - _sinit = ABSOLUTE(.); - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------Start----------------------------------------- - */ - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - _einit = ABSOLUTE(.); - . = ALIGN(8); - } > pfls - .dtors : FLAGS(ar) - { - __DTOR_LIST__ = . ; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------Start----------------------------------------- - */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------End----------------------------------------- - */ - LONG(0) ; - __DTOR_END__ = . ; - . = ALIGN(8); - } > pfls - /* - * DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the - * beginning of the section, so we begin them at 0. - */ - /* - * DWARF 1 - */ - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* - * GNU DWARF 1 extensions - */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* - * DWARF 1.1 and DWARF 2 - */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* - * DWARF 2 - */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_ranges 0 : { *(.debug_ranges) } - /* - * SGI/MIPS DWARF 2 extensions - */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* - * Optional sections that may only appear when relocating. - */ - /* - * Optional sections that may appear regardless of relocating. - */ - .version_info 0 : { *(.version_info) } - .boffs 0 : { KEEP (*(.boffs)) } -} diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user deleted file mode 100644 index 42ddc47b3ff65..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include "arch/board/board_memorymap.h" - -/* Default linker script, for normal executables */ -OUTPUT_FORMAT("elf32-tricore") -OUTPUT_ARCH("tricore") - -LCF_PFLASH_USER_START = GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID); -LCF_PFLASH_USER_SIZE = GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID); -LCF_DLMU_USER_START = GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID); -LCF_DLMU_USER_SIZE = GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID); -LCF_USTACK_START = GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID); -LCF_USTACK_SIZE = GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID); - -MEMORY -{ - upfls (rx!p): org = LCF_PFLASH_USER_START, len = LCF_PFLASH_USER_SIZE - upfls_nc (rx!p): org = NC_START(LCF_PFLASH_USER_START), len = LCF_PFLASH_USER_SIZE - - cpu_udlmu (w!xp): org = LCF_DLMU_USER_START, len = LCF_DLMU_USER_SIZE - cpu_udlmu_nc (w!xp): org = NC_START(LCF_DLMU_USER_START), len = LCF_DLMU_USER_SIZE - - ustack (w!xp): org = LCF_USTACK_START, len = LCF_USTACK_SIZE -} - -/* map cached and non cached addresses */ -REGION_MIRROR("upfls", "upfls_nc") -REGION_MIRROR("cpu_udlmu", "cpu_udlmu_nc") - -/*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/ - -/*Code Sections, selectable by toolchain*/ -CORE_ID = GLOBAL; -SECTIONS -{ - .userspace : ALIGN(64) - { - _suserspace = ABSOLUTE(.); - KEEP(*(.userspace)) - . = ALIGN(64); /* userspace align to 64 to keep the address continuous for MBF */ - _euserspace = ABSOLUTE(.); - } > upfls - - CORE_SEC(.text) : FLAGS(axl) - { - _stext = ABSOLUTE(.); - *(.text) - *(.text.*) - *(.zrodata) - *(.zrodata.*) - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.gcc_except_table) - *(.gnu.linkonce.t.*) - *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ - . = ALIGN(4); - _etext = ABSOLUTE(.); - } > upfls - - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - - /* - * C++ exception handling tables. NOTE: gcc emits .eh_frame - * sections when compiling C sources with debugging enabled (-g). - * If you can be sure that your final application consists - * exclusively of C objects (i.e., no C++ objects), you may use - * the -R option of the "strip" and "objcopy" utilities to remove - * the .eh_frame section from the executable. - */ - .eh_frame_hdr : ALIGN(8) - { - KEEP (*(.eh_frame_hdr)) - . = ALIGN(8); - } > upfls - - .eh_frame : ALIGN(8) - { - __EH_FRAME_BEGIN__ = . ; - KEEP (*(.eh_frame)) - __EH_FRAME_END__ = . ; - . = ALIGN(8); - } > upfls - - /* - * Constructors and destructors. - */ - .ctors : FLAGS(ar) - { - _sinit = ABSOLUTE(.); - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------Start----------------------------------------- - */ - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - _einit = ABSOLUTE(.); - . = ALIGN(8); - } > upfls - .dtors : FLAGS(ar) - { - __DTOR_LIST__ = . ; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------Start----------------------------------------- - */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------End----------------------------------------- - */ - LONG(0) ; - __DTOR_END__ = . ; - . = ALIGN(8); - } > upfls - - _eronly = ABSOLUTE(.); - - /* - * DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the - * beginning of the section, so we begin them at 0. - */ - /* - * DWARF 1 - */ - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* - * GNU DWARF 1 extensions - */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* - * DWARF 1.1 and DWARF 2 - */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* - * DWARF 2 - */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_ranges 0 : { *(.debug_ranges) } - /* - * SGI/MIPS DWARF 2 extensions - */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* - * Optional sections that may only appear when relocating. - */ - /* - * Optional sections that may appear regardless of relocating. - */ - .version_info 0 : { *(.version_info) } - .boffs 0 : { KEEP (*(.boffs)) } -} - -/*Far Data Sections, selectable by toolchain*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.stack) (NOLOAD) : FLAGS(aw) - { - *(.dtcm_stack) - *(.dtcm_stack.*) - } > ustack - - CORE_SEC(.data) : FLAGS(awzl) - { - _sdata = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.zdata) - *(.zdata.*) - *(.gnu.linkonce.d.*) - *(.gnu.linkonce.z.*) - . = ALIGN(2); - _edata = ABSOLUTE(.); - } > cpu_udlmu AT> upfls - - CORE_SEC(.bss) (NOLOAD): FLAGS(awz) - { - _sbss = ABSOLUTE(.); - *(.bss) - *(.bss.*) - *(.zbss) - *(.zbss.*) - *(.bbss) - *(.bbss.*) - *(.gnu.linkonce.zb.*) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > cpu_udlmu - - .heap (NOLOAD) : FLAGS(aw) - { - _sheap = ABSOLUTE(.); - _eheap = ABSOLUTE(LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE); - } > cpu_udlmu - - _sdata_pflash = LOADADDR(.data); -} - -#if CONFIG_CPU_COREID == 5 -/* This sections is added to reserve last 4 bytes of flash in core5's user - * space. This is because the car's diagnostic service will query this area, - * and if the area has been erased but not written to, the query will cause - * an exception. Since the page size of pflash is 32 bytes, we reserve 32 - * bytes instead of 4 bytes. - */ - -CORE_ID = GLOBAL; -SECTIONS -{ - .flash_reserve (LCF_PFLASH_USER_START + LCF_PFLASH_USER_SIZE - 32) : { - . = ALIGN(32); - FILL(0x55); - . = . + 28; - LONG(0x55555555); - } > upfls -} -#endif diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel deleted file mode 100644 index 1579c1b335477..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel +++ /dev/null @@ -1,633 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include "arch/board/board_memorymap.h" - -#define __JOIN2(x,y) x##y -#define JOIN2(x,y) __JOIN2(x,y) -#define __JOIN3(x,y,z) x##y##z -#define JOIN3(x,y,z) __JOIN3(x,y,z) -#define __JOIN4(x,y,z,w) x##y##z##w -#define JOIN4(x,y,z,w) __JOIN4(x,y,z,w) - -#define LCF_PFLASH_KERNEL_START GENERATE_CORE_PFLASH_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_PFLASH_KERNEL_SIZE GENERATE_CORE_PFLASH_KERNEL_SIZE(CONFIG_CPU_COREID) -#define LCF_DSPR_KERNEL_START GENERATE_CORE_DSPR_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_DSPR_KERNEL_SIZE GENERATE_CORE_DSPR_KERNEL_SIZE(CONFIG_CPU_COREID) -#define LCF_PSPR_KERNEL_START GENERATE_CORE_PSPR_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_PSPR_KERNEL_SIZE GENERATE_CORE_PSPR_KERNEL_SIZE(CONFIG_CPU_COREID) -#define LCF_DLMU_KERNEL_START GENERATE_CORE_DLMU_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_DLMU_KERNEL_SIZE GENERATE_CORE_DLMU_KERNEL_SIZE(CONFIG_CPU_COREID) -#define LCF_KSTACK_START GENERATE_CORE_STACK_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_KSTACK_SIZE GENERATE_CORE_STACK_KERNEL_SIZE(CONFIG_CPU_COREID) - -#if CONFIG_CPU_COREID != 0 -#define LCF_SYSLOG_START JOIN3(AURIX_RPTUN_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_START) -#define LCF_SYSLOG_SIZE JOIN3(AURIX_RPTUN_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_SIZE) -#endif - -#define LCF_CSA_SIZE 40k -#define LCF_USTACK_SIZE CONFIG_IDLETHREAD_STACKSIZE -#define LCF_ISTACK_SIZE CONFIG_ARCH_INTERRUPTSTACK - -#define LCF_HEAP_SIZE 4k - -#define LCF_CPU0 0 -#define LCF_CPU1 1 -#define LCF_CPU2 2 -#define LCF_CPU3 3 -#define LCF_CPU4 4 -#define LCF_CPU5 5 - -/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/ -#define LCF_DEFAULT_HOST LCF_CPU0 - -#define LCF_CSA_OFFSET (LCF_DSPR_KERNEL_SIZE - 1k - LCF_CSA_SIZE) -#define LCF_ISTACK_OFFSET (LCF_CSA_OFFSET - 256 - LCF_ISTACK_SIZE) -#define LCF_USTACK_OFFSET (LCF_ISTACK_OFFSET - 256 - LCF_USTACK_SIZE) -#define LCF_HEAP_OFFSET (LCF_USTACK_OFFSET - LCF_HEAP_SIZE) - -#define LCF_STARTPTR_CPU LCF_PFLASH_KERNEL_START -#define LCF_TRAPVEC_START (LCF_STARTPTR_CPU + 0x20) -#define LCF_INTVEC_START (LCF_PFLASH_KERNEL_START + LCF_PFLASH_KERNEL_SIZE - 0x2000) - -#define LCF_STARTPTR_NC_CPU0 NC_START(CORE0_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU1 NC_START(CORE1_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU2 NC_START(CORE2_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU3 NC_START(CORE3_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU4 NC_START(CORE4_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU5 NC_START(CORE5_PFLASH_KERNEL_START) - -#define INTTAB (LCF_INTVEC_START) - -#define RESET CORE0_PFLASH_KERNEL_START - -#include "tc1v1_6_2.lsl" - -// Specify a multi-core processor environment (mpe) - -processor mpe -{ - derivative = tc39; -} - -derivative tc39 -{ - core tc - { - architecture = TC1V1.6.2; - space_id_offset = 100; // add 100 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core vtc - { - architecture = TC1V1.6.2; - import tc; // add all address spaces of core tc to core vtc for linking and locating - } - - bus sri - { - mau = 8; - width = 32; - - // map shared addresses one-to-one to real cores and virtual cores - map (dest=bus:tc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - } - - memory dsram // Data Scratch Pad Ram - { - mau = 8; - size = LCF_DSPR_KERNEL_SIZE; - type = ram; - map (dest=bus:tc:fpi_bus, dest_offset=DSPR_LOCAL_START, size=LCF_DSPR_KERNEL_SIZE, priority=8); - map (dest=bus:sri, dest_offset=LCF_DSPR_KERNEL_START, size=LCF_DSPR_KERNEL_SIZE); - } - - memory psram // Program Scratch Pad Ram - { - mau = 8; - size = LCF_PSPR_KERNEL_SIZE; - type = ram; - map (dest=bus:tc:fpi_bus, dest_offset=PSPR_LOCAL_START, size=LCF_PSPR_KERNEL_SIZE, priority=8); - map (dest=bus:sri, dest_offset=LCF_PSPR_KERNEL_START, size=LCF_PSPR_KERNEL_SIZE); - } - - memory pfls - { - mau = 8; - size = LCF_PFLASH_KERNEL_SIZE; - type = rom; - map cached (dest=bus:sri, dest_offset=LCF_PFLASH_KERNEL_START, size=LCF_PFLASH_KERNEL_SIZE); - map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_PFLASH_KERNEL_START), reserved, size=LCF_PFLASH_KERNEL_SIZE); - } - - memory ucb - { - mau = 8; - size = 80K; - type = rom; - map (dest=bus:sri, dest_offset=0xae400000, reserved, size=80K); - } - - memory cpu_dlmu - { - mau = 8; - size = LCF_DLMU_KERNEL_SIZE; - type = ram; - map cached (dest=bus:sri, dest_offset=LCF_DLMU_KERNEL_START, size=LCF_DLMU_KERNEL_SIZE); - map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_KERNEL_START), reserved, size=LCF_DLMU_KERNEL_SIZE); - } - - memory kstack - { - mau = 8; - size = LCF_KSTACK_SIZE; - type = ram; - map not_cached (dest=bus:sri, dest_offset=LCF_KSTACK_START, size=LCF_KSTACK_SIZE); - } - -#if CONFIG_CPU_COREID != 0 - memory syslog - { - mau = 8; - size = LCF_SYSLOG_SIZE; - type = ram; - map not_cached (dest=bus:sri, dest_offset=LCF_SYSLOG_START, size=LCF_SYSLOG_SIZE); - } -#endif - - section_setup :vtc:linear - { - heap "heap1" (min_size = LCF_HEAP_SIZE, align = 4); - heap "heap2" (min_size = LCF_HEAP_SIZE, align = 4); - } - - section_setup :vtc:linear - { - start_address - ( -#if CONFIG_CPU_COREID == 0 - symbol = "_START" -#elif CONFIG_CPU_COREID == 1 - symbol = "_START1" -#elif CONFIG_CPU_COREID == 2 - symbol = "_START2" -#elif CONFIG_CPU_COREID == 3 - symbol = "_START3" -#elif CONFIG_CPU_COREID == 4 - symbol = "_START4" -#elif CONFIG_CPU_COREID == 5 - symbol = "_START5" -#endif - ); - } - - section_setup :vtc:linear - { - stack "ustack_tc" (min_size = 1k, fixed, align = 8); - stack "istack_tc" (min_size = 1k, fixed, align = 8); - } - - /*Section setup for the copy table*/ - section_setup :vtc:linear - { - copytable - ( - align = 4, - dest = linear, - table - { - symbol = "_lc_ub_table_tc"; - space = :tc:linear, :tc:abs24, :tc:abs18, :tc:csa; - } - ); - } - - /*Sections located at absolute fixed address*/ - - section_layout :vtc:linear - { - /*Fixed memory Allocations for stack memory and CSA*/ - group (ordered) - { - group ustack(align = 8, run_addr = mem:dsram[LCF_USTACK_OFFSET]) - { - stack "ustack_tc" (size = LCF_USTACK_SIZE); - } - "__USTACK"= sizeof(group:ustack) > 0 ? "_lc_ue_ustack_tc" : 0; - "__USTACK_END"="_lc_gb_ustack"; - "__USTACK0":= "__USTACK"; - "__USTACK1":= "__USTACK"; - "__USTACK2":= "__USTACK"; - "__USTACK3":= "__USTACK"; - "__USTACK4":= "__USTACK"; - "__USTACK5":= "__USTACK"; - - group istack(align = 8, run_addr = mem:dsram[LCF_ISTACK_OFFSET]) - { - stack "istack_tc" (size = LCF_ISTACK_SIZE); - } - "__ISTACK"= sizeof(group:istack) > 0 ? "_lc_ue_istack_tc" : 0; - "__ISTACK_END"="_lc_gb_istack"; - "__ISTACK0":="__ISTACK"; - "__ISTACK1":="__ISTACK"; - "__ISTACK2":="__ISTACK"; - "__ISTACK3":="__ISTACK"; - "__ISTACK4":="__ISTACK"; - "__ISTACK5":="__ISTACK"; - - group csa_tc(align = 64, attributes=rw, run_addr=mem:dsram[LCF_CSA_OFFSET]) - { - reserved "csa_tc" (size = LCF_CSA_SIZE); - } - "__CSA"= "_lc_ub_csa_tc"; - "__CSA_END"= "_lc_ue_csa_tc"; - "__CSA0":= "__CSA"; - "__CSA0_END":= "__CSA_END"; - "__CSA1":= "__CSA"; - "__CSA1_END":= "__CSA_END"; - "__CSA2":= "__CSA"; - "__CSA2_END":= "__CSA_END"; - "__CSA3":= "__CSA"; - "__CSA3_END":= "__CSA_END"; - "__CSA4":= "__CSA"; - "__CSA4_END":= "__CSA_END"; - "__CSA5":= "__CSA"; - "__CSA5_END":= "__CSA_END"; - } - - /*Fixed memory Allocations for _START*/ - group (ordered) - { - group interface_const (run_addr=mem:pfls[0x0020]) - { - select "*.interface_const"; - } - "__IF_CONST" := addressof(group:interface_const); - "__START0" := CORE0_PFLASH_KERNEL_START; - "__START1" := CORE1_PFLASH_KERNEL_START; - "__START2" := CORE2_PFLASH_KERNEL_START; - "__START3" := CORE3_PFLASH_KERNEL_START; - "__START4" := CORE4_PFLASH_KERNEL_START; - "__START5" := CORE5_PFLASH_KERNEL_START; - } - - /*Fixed memory Allocations for Trap Vector Table*/ - group (ordered) - { - group trapvec_tc (align = 8, run_addr=LCF_TRAPVEC_START) - { - section "trapvec_tc" (size=0x100, attributes=rx, fill=0) - { -#if CONFIG_CPU_COREID == 0 - select "(.text.traptab_cpu0*)"; -#elif CONFIG_CPU_COREID == 1 - select "(.text.traptab_cpu1*)"; -#elif CONFIG_CPU_COREID == 2 - select "(.text.traptab_cpu2*)"; -#elif CONFIG_CPU_COREID == 3 - select "(.text.traptab_cpu3*)"; -#elif CONFIG_CPU_COREID == 4 - select "(.text.traptab_cpu4*)"; -#elif CONFIG_CPU_COREID == 5 - select "(.text.traptab_cpu5*)"; -#endif - } - } - "__TRAPTAB_CPU0" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU1" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU2" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU3" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU4" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU5" := LCF_TRAPVEC_START; - } - - /*Fixed memory Allocations for Start up code*/ - group (ordered, attributes=rx) - { - group start_tc (run_addr=(LCF_STARTPTR_CPU)) - { -#if CONFIG_CPU_COREID == 0 - select "(.text.start*)"; -#elif CONFIG_CPU_COREID == 1 - select "(.text.start_cpu1*)"; -#elif CONFIG_CPU_COREID == 2 - select "(.text.start_cpu2*)"; -#elif CONFIG_CPU_COREID == 3 - select "(.text.start_cpu3*)"; -#elif CONFIG_CPU_COREID == 4 - select "(.text.start_cpu4*)"; -#elif CONFIG_CPU_COREID == 5 - select "(.text.start_cpu5*)"; -#endif - } - "__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 1; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 1; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU3" := 1; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU4" := 1; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU5" := 1; /* Not used */ - } - - /*Fixed memory Allocations for Interrupt Vector Table*/ - group (ordered, attributes=rx) - { - group int_tab_tc (ordered) - { - group (run_addr=(INTTAB)+0x1FE0) select ".text.inttab0.intvec.0ff"; - } - "_lc_u_int_tab" = (LCF_INTVEC_START); - "__INTTAB_CPU0" = (LCF_INTVEC_START); - "__INTTAB_CPU1" = (LCF_INTVEC_START); - "__INTTAB_CPU2" = (LCF_INTVEC_START); - "__INTTAB_CPU3" = (LCF_INTVEC_START); - "__INTTAB_CPU4" = (LCF_INTVEC_START); - "__INTTAB_CPU5" = (LCF_INTVEC_START); - } - - /*Fixed memory Allocations for BMHD*/ - group (ordered) - { - group bmh_0_orig (run_addr=mem:ucb[0x4800]) - { - select ".rodata.bmhd_0_orig"; - } - group bmh_1_orig (run_addr=mem:ucb[0x5000]) - { - select ".rodata.bmhd_1_orig"; - } - group bmh_2_orig (run_addr=mem:ucb[0x5800]) - { - select ".rodata.bmhd_2_orig"; - } - group bmh_3_orig (run_addr=mem:ucb[0x6000]) - { - select ".rodata.bmhd_3_orig"; - } - group usercfg_0_org (run_addr=mem:ucb[0x8800]) - { - select ".rodata.usercfg_0_orig"; - } - group usercfg_0_cpy (run_addr=mem:ucb[0x9000]) - { - select ".rodata.usercfg_0_copy"; - } - } - } - - /*Near Abbsolute Addressable Data Sections*/ - section_layout :vtc:abs18 - { - /*Near Absolute Data, selectable with patterns and user defined sections*/ - group - { - group (ordered, attributes=rw, run_addr = mem:cpu_dlmu) - { - select "(.zdata.zlmudata|.zdata.zlmudata.*)"; - select "(.zbss.zlmubss|.zbss.zlmubss.*)"; - } - } - - /*Near Absolute Data, selectable by toolchain*/ - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) - { - group zdata(attributes=rw) - { - select "(.zdata|.zdata.*)"; - select "(.zbss|.zbss.*)"; - } - } - - /*Near Absolute Const, selectable with patterns and user defined sections*/ - group - { - group (ordered, contiguous, align = 4, attributes=r, run_addr=mem:pfls) - { -#if CONFIG_CPU_COREID == 0 - select ".zrodata.Ifx_Ssw_Tc?.*"; - select ".zrodata.Cpu?_Main.*"; -#elif CONFIG_CPU_COREID == 1 - select ".zrodata.Ifx_Ssw_Tc1.*"; - select ".zrodata.Cpu1_Main.*"; -#elif CONFIG_CPU_COREID == 2 - select ".zrodata.Ifx_Ssw_Tc2.*"; - select ".zrodata.Cpu2_Main.*"; -#elif CONFIG_CPU_COREID == 3 - select ".zrodata.Ifx_Ssw_Tc3.*"; - select ".zrodata.Cpu3_Main.*"; -#elif CONFIG_CPU_COREID == 4 - select ".zrodata.Ifx_Ssw_Tc4.*"; - select ".zrodata.Cpu4_Main.*"; -#elif CONFIG_CPU_COREID == 5 - select ".zrodata.Ifx_Ssw_Tc5.*"; - select ".zrodata.Cpu5_Main.*"; -#endif - /*Near Absolute Const, selectable by toolchain*/ - select "(.zrodata|.zrodata.*)"; - } - } - } - - /*Relative A0/A1/A8/A9 Addressable Sections*/ - section_layout :vtc:linear - { - /*Relative A0 Addressable Data, selectable by toolchain*/ - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) - { - select "(.sdata|.sdata.*)"; - select "(.data_a0|.data_a0.*)"; - select "(.sbss|.sbss.*)"; - select "(.bss_a0|.bss_a0.*)"; - } - "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k; - "__A0_MEM" = "_SMALL_DATA_"; - - /*Relative A1 Addressable Const, selectable by toolchain*/ - /*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/ - group a1 (ordered, align = 4, attributes=r, run_addr=mem:pfls) - { - select "(.srodata|.srodata.*)"; - select "(.ldata|.ldata.*)"; - select "(.rodata_a1|.rodata_a1.*)"; - } - "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k; - "__A1_MEM" = "_LITERAL_DATA_"; - - /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ - group a9 (ordered, align = 4, run_addr=mem:dsram) - { - select "(.a9sdata|.a9sdata.*)"; - select "(.data_a9|.data_a9.*)"; - select "(.a9sbss|.a9sbss.*)"; - select "(.bss_a9|.bss_a9.*)"; - } - "_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k; - "__A9_MEM" = "_A9_DATA_"; - - /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ - group a8 (ordered, align = 4, run_addr=mem:pfls) - { - select "(.a8srodata|.a8srodata.*)"; - select "(.rodata_a8|.rodata_a8.*)"; - } - "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k; - "__A8_MEM" = "_A8_DATA_"; - } - - /*kstack ram*/ - section_layout :vtc:linear - { - group kstack(ordered, contiguous, nocopy, run_addr=mem:kstack) - { - select "(.dtcm_stack|.dtcm_stack.*)"; - } - } - -#if CONFIG_CPU_COREID != 0 - /*syslog ram*/ - section_layout :vtc:linear - { - group syslog(ordered, contiguous, nocopy, run_addr=mem:syslog) - { - select "(.syslog|.syslog.*)"; - } - } -#endif - - /*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ - section_layout :vtc:linear - { - /*Far Data Sections, selectable with patterns and user defined sections*/ - - /*DSRAM sections*/ - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) - { - group (attributes=rw) - { - select ".data.Ifx_Ssw_Tc?.*"; - select ".data.Cpu?_Main.*"; - select ".bss.Ifx_Ssw_Tc?.*"; - select ".bss.Cpu?_Main.*"; - select ".bss.os_scheduletable_misc.*"; - select ".bss.iob_initialize.*"; - } - - /*Heap1*/ - group heap1(attributes=rw) - { - heap "heap1" (size = LCF_HEAP_SIZE); - } - "_sheap":="_lc_ub_heap1"; - "_eheap":="__USTACK_END"; - } - - /*LMU Data sections*/ - group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_dlmu/not_cached) - { - select "(.data.uncached.*)"; - select "(.bss.uncached.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr=mem:cpu_dlmu) - { - group lmubss(attributes=rw, nocopy) - { - select "(.lmubss_cpu?|.lmubss_cpu?.*)"; - } - - group data(attributes=rw) - { - select "(.data|.data.*)"; - select "(.bss|.bss.*)"; - } - - /*Heap2 allocation*/ - group heap2(attributes=rw) - { - heap "heap2" (size = LCF_HEAP_SIZE); - } - "__DLMUHEAP":="_lc_ge_data"; - "__DLMUHEAP_END":=LCF_DLMU_KERNEL_START + LCF_DLMU_KERNEL_SIZE; - } - - /*Far Const Sections, selectable with patterns and user defined sections*/ - group - { - group (ordered, align = 4, attributes=r, run_addr=mem:pfls) - { - select ".rodata.Ifx_Ssw_Tc?.*"; - select ".rodata.Cpu?_Main.*"; - } - } - - /*Far Const Sections, selectable by toolchain*/ - group (ordered, align = 4, run_addr=mem:pfls) - { - select "(.rodata|.rodata.*)"; - } - } - - /* PSRAM Code selections*/ - section_layout :vtc:linear - { - /*Code Sections, selectable with patterns and user defined sections*/ - group - { - /*Program Scratchpad Sections*/ - group - { - group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram) - { - select "(.text.aurix_mtd_flash|.text.aurix_mtd_flash.*)"; - select "(.text.aurix_mtd_partition|.text.aurix_mtd_partition.*)"; - } - } - } - } - - /* FLS Code selections*/ - section_layout :vtc:linear - { - /*Code Sections, selectable with patterns and user defined sections*/ - group - { - /*Cpu specific PFLASH Sections*/ - group - { - group (ordered, align = 4, attributes=rx, run_addr=mem:pfls) - { - select ".text.Ifx_Ssw_Tc?.*"; - select ".text.Cpu?_Main.*"; - select ".text.CompilerTasking.Ifx_C_Init"; - } - } - } - - /*Code Sections, selectable by toolchain*/ - group (ordered, run_addr=mem:pfls) - { - select "(.text|.text.*)"; - } - } -} diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user deleted file mode 100644 index 89c54f3f1164d..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user +++ /dev/null @@ -1,189 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include "arch/board/board_memorymap.h" - -#define LCF_PFLASH_USER_START GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID) -#define LCF_PFLASH_USER_SIZE GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID) -#define LCF_DLMU_USER_START GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID) -#define LCF_DLMU_USER_SIZE GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID) -#define LCF_USTACK_START GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID) -#define LCF_USTACK_SIZE GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID) - -#define LCF_HEAP_SIZE 4k - -#include "tc1v1_6_2.lsl" - -// Specify a multi-core processor environment (mpe) - -processor mpe -{ - derivative = tc39; -} - -derivative tc39 -{ - core tc - { - architecture = TC1V1.6.2; - space_id_offset = 100; // add 100 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core vtc - { - architecture = TC1V1.6.2; - import tc; // add all address spaces of core tc to core vtc for linking and locating - } - - bus sri - { - mau = 8; - width = 32; - - // map shared addresses one-to-one to real cores and virtual cores - map (dest=bus:tc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - } - - memory upfls - { - mau = 8; - size = LCF_PFLASH_USER_SIZE; - type = rom; - map cached (dest=bus:sri, dest_offset=LCF_PFLASH_USER_START, size=LCF_PFLASH_USER_SIZE); - map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_PFLASH_USER_START), reserved, size=LCF_PFLASH_USER_SIZE); - } - - memory cpu_udlmu - { - mau = 8; - size = LCF_DLMU_USER_SIZE; - type = ram; - map cached (dest=bus:sri, dest_offset=LCF_DLMU_USER_START, size=LCF_DLMU_USER_SIZE); - map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_USER_START), reserved, size=LCF_DLMU_USER_SIZE); - } - - memory ustack - { - mau = 8; - size = LCF_USTACK_SIZE; - type = ram; - map not_cached (dest=bus:sri, dest_offset=LCF_USTACK_START, size=LCF_USTACK_SIZE); - } - - /*Section setup for the copy table*/ - section_setup :vtc:linear - { - copytable - ( - align = 4, - dest = linear, - table - { - symbol = "_lc_ub_table_tc"; - space = :tc:linear, :tc:abs24, :tc:abs18; - } - ); - } - - section_setup :vtc:linear - { - heap "uheap" (min_size = LCF_HEAP_SIZE, align = 4); - } - - /* user stack section */ - section_layout :vtc:linear - { - group ustack(ordered, contiguous, nocopy, run_addr=mem:ustack) - { - select "(.dtcm_stack|.dtcm_stack.*)"; - } - } - - /*Sections located at absolute fixed address*/ - section_layout :vtc:linear - { - group userspace(ordered, run_addr=LCF_PFLASH_USER_START) - { - select "(.userspace|.userspace.*)"; - } - "_suserspace" = "_lc_gb_userspace"; - "_euserspace" = "_lc_ge_userspace"; - - group text(ordered, run_addr=mem:upfls) - { - select "(.text|.text.*)"; - select "(.zrodata|.zrodata.*)"; - select "(.rodata|.rodata.*)"; - } - "_stext" = "_lc_gb_text"; - "_etext" = "_lc_ge_text"; - } - - /* Data & Bss section */ - section_layout :vtc:linear - { - group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu/not_cached) - { - select "(.data.uncached.*)"; - select "(.bss.uncached.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu) - { - group udata - { - select "(.data|.data.*)"; - select "(.zdata|.zdata.*)"; - } - "_sdata" = "_lc_gb_udata"; - "_edata" = "_lc_ge_udata"; - - /* bss section */ - group ubss - { - select "(.bss|.bss.*)"; - select "(.zbss|.zbss.*)"; - select "(.bbss|.bbss.*)"; - } - "_sbss" = "_lc_gb_ubss"; - "_ebss" = "_lc_ge_ubss"; - - /* heap section */ - group uheap - { - heap "uheap" (size = LCF_HEAP_SIZE); - } - "_sheap" = "_ebss"; - "_eheap" = LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE; - } - - group udata_rom(ordered, contiguous, load_addr=mem:upfls) - { - select "(.data|.data.*)"; - select "(.zdata|.zdata.*)"; - } - "_sdata_pflash" = "_lc_gb_udata_rom"; - #include "symbol_share.ld" - } -} diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs b/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs deleted file mode 100644 index 9692d30d55ae5..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs +++ /dev/null @@ -1,44 +0,0 @@ -############################################################################ -# boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/tricore/src/tc3xx/Toolchain.defs - -ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - TRICORE_TOOLCHAIN := Tasking -else - TRICORE_TOOLCHAIN := Gnuc -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.kernel - -ifeq ($(CONFIG_BUILD_PROTECTED),y) - ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.user -endif - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt b/boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt deleted file mode 100644 index d034097f8b7d4..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt +++ /dev/null @@ -1,42 +0,0 @@ -# ############################################################################## -# boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS tc397_boardinit.c tc397_bringup.c) - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_TRICORE_TOOLCHAIN_TASKING) - set(toolchain "Tasking") -else() - set(toolchain "Gnuc") -endif() - -set_property( - GLOBAL - PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.kernel") -if(CONFIG_BUILD_PROTECTED) - set_property( - GLOBAL - PROPERTY LD_SCRIPT_USER - "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.user") -endif() diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/src/Makefile b/boards/tricore/tc397/a2g-tc397-5v-tft/src/Makefile deleted file mode 100644 index 49a3beb29c94c..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/src/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -############################################################################ -# boards/tricore/tc397/a2g-tc397-5v-tft/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = tc397_boardinit.c tc397_bringup.c - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397.h b/boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397.h deleted file mode 100644 index ab230a0b90700..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_SRC_TC397_H -#define __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_SRC_TC397_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Functions Definitions - ****************************************************************************/ - -/**************************************************************************** - * Name: tc397_bringup - * - * Description: - * Bring up board features - * - ****************************************************************************/ - -#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) -int tc397_bringup(void); -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_SRC_TC397_H */ diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_boardinit.c b/boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_boardinit.c deleted file mode 100644 index 9c789ca129d85..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_boardinit.c +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_boardinit.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "chip.h" -#include "tc397.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: tc397_memory_initialize - * - * Description: - * All i.MX6 architectures must provide the following entry point. This - * entry point is called early in the initialization before memory has - * been configured. This board-specific function is responsible for - * configuring any on-board memories. - * - * Logic in tc397_memory_initialize must be careful to avoid using any - * global variables because those will be uninitialized at the time this - * function is called. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void tc397_memory_initialize(void) -{ - /* SDRAM was initialized by a bootloader in the supported configurations. */ -} - -/**************************************************************************** - * Name: tc397_board_initialize - * - * Description: - * All i.MX6 architectures must provide the following entry point. This - * entry point is called in the initialization phase -- after - * tc397_memory_initialize and after all memory has been configured and - * mapped but before any devices have been initialized. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void tc397_board_initialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_intitialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - tc397_bringup(); -} -#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_bringup.c b/boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_bringup.c deleted file mode 100644 index a014c47ccafea..0000000000000 --- a/boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_bringup.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "tc397.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: tc397_bringup - * - * Description: - * Bring up board features - * - ****************************************************************************/ - -int tc397_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_TMPFS - /* Mount the tmpfs file system */ - - ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", - CONFIG_LIBC_TMPDIR, ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt b/boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt deleted file mode 100644 index c8bc3a4497bfd..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/Kconfig b/boards/tricore/tc4da/triboard_tc4x9_com/Kconfig deleted file mode 100644 index 9ae9d044c3d63..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_TRIBOARD_TC4X9_COM -endif diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/configs/nsh/defconfig b/boards/tricore/tc4da/triboard_tc4x9_com/configs/nsh/defconfig deleted file mode 100644 index bc98db1f0cc7c..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/configs/nsh/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="tricore" -CONFIG_ARCH_BOARD="triboard_tc4x9_com" -CONFIG_ARCH_BOARD_TRIBOARD_TC4X9_COM=y -CONFIG_ARCH_CHIP="tc4da" -CONFIG_ARCH_CHIP_TC4DA=y -CONFIG_ARCH_CHIP_TC4XX=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_NUSER_INTERRUPTS=48 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_TRICORE=y -CONFIG_BOARD_LOOPSPERMSEC=99369 -CONFIG_BOOT_RUNFROMSDRAM=y -CONFIG_BUILTIN=y -CONFIG_CPU_COREID=0 -CONFIG_DEBUG_ASSERTIONS=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXPERIMENTAL=y -CONFIG_FS_PROCFS=y -CONFIG_FS_TMPFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_MEMFD_ERROR=y -CONFIG_NDEBUG=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=245760 -CONFIG_RAM_START=0x70000000 -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SPINLOCK=y -CONFIG_STACK_COLORATION=y -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2016 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSLOG_BUFFER=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSLOG_INTBUFFER=y -CONFIG_SYSLOG_MAX_CHANNELS=2 -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_SCHED_EVENTS=y diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/include/board.h b/boards/tricore/tc4da/triboard_tc4x9_com/include/board.h deleted file mode 100644 index e7447146ae332..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/include/board.h +++ /dev/null @@ -1,40 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc4da/triboard_tc4x9_com/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_H -#define __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Definitions - ****************************************************************************/ - -#endif /* __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_H */ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/include/board_memorymap.h b/boards/tricore/tc4da/triboard_tc4x9_com/include/board_memorymap.h deleted file mode 100644 index 11a60dc745eec..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/include/board_memorymap.h +++ /dev/null @@ -1,457 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc4da/triboard_tc4x9_com/include/board_memorymap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_MEMORYMAP_H -#define __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BANKA_CORE0_PFLASH_KERNEL_START 0x80000000 -#define BANKA_CORE0_PFLASH_KERNEL_SIZE 0x100000 /* 1024KB */ -#define BANKA_CORE0_PFLASH_USER_START 0x80100000 -#define BANKA_CORE0_PFLASH_USER_SIZE 0x100000 /* 1024KB */ -#define BANKA_CORE1_PFLASH_KERNEL_START 0x80200000 -#define BANKA_CORE1_PFLASH_KERNEL_SIZE 0x100000 /* 1024KB */ -#define BANKA_CORE1_PFLASH_USER_START 0x80300000 -#define BANKA_CORE1_PFLASH_USER_SIZE 0x280000 /* 2560KB */ -#define BANKA_CORE2_PFLASH_KERNEL_START 0x80580000 -#define BANKA_CORE2_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ -#define BANKA_CORE2_PFLASH_USER_START 0x80600000 -#define BANKA_CORE2_PFLASH_USER_SIZE 0x80000 /* 512KB */ -#define BANKA_CORE3_PFLASH_KERNEL_START 0x80680000 -#define BANKA_CORE3_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ -#define BANKA_CORE3_PFLASH_USER_START 0x80700000 -#define BANKA_CORE3_PFLASH_USER_SIZE 0xE0000 /* */ -#define BANKA_CORE4_PFLASH_KERNEL_START 0x807E0000 -#define BANKA_CORE4_PFLASH_KERNEL_SIZE 0x88000 /* 544KB */ -#define BANKA_CORE4_PFLASH_USER_START 0x80868000 -#define BANKA_CORE4_PFLASH_USER_SIZE 0xC4000 /* 784KB */ -#define BANKA_CORE5_PFLASH_KERNEL_START 0x8092C000 -#define BANKA_CORE5_PFLASH_KERNEL_SIZE 0x70000 /* 448KB */ -#define BANKA_CORE5_PFLASH_USER_START 0x8099C000 -#define BANKA_CORE5_PFLASH_USER_SIZE 0x64000 /* 400KB */ -#define BANKB_BL_PFLASH_START 0x82000000 -#define BANKB_BL_PFLASH_SIZE 0x40000 /* 256KB */ -#define BANKB_MBF_HASH_START 0x82040000 -#define BANKB_MBF_HASH_SIZE 0x4000 /* 16KB */ -#define BANKB_CORE0_PFLASH_KERNEL_START 0x82044000 -#define BANKB_CORE0_PFLASH_KERNEL_SIZE 0x160000 /* 1408KB */ -#define BANKB_CORE0_PFLASH_USER_START 0x821A4000 -#define BANKB_CORE0_PFLASH_USER_SIZE 0x5C000 /* 368KB */ -#define BANKB_VBMETA_START 0x821FC000 -#define BANKB_VBMETA_SIZE 0x4000 /* 16KB */ -#define BANKB_CORE1_PFLASH_KERNEL_START 0x82200000 -#define BANKB_CORE1_PFLASH_KERNEL_SIZE 0x100000 /* 1024KB */ -#define BANKB_CORE1_PFLASH_USER_START 0x82300000 -#define BANKB_CORE1_PFLASH_USER_SIZE 0x280000 /* 2560KB */ -#define BANKB_CORE2_PFLASH_KERNEL_START 0x82580000 -#define BANKB_CORE2_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ -#define BANKB_CORE2_PFLASH_USER_START 0x82600000 -#define BANKB_CORE2_PFLASH_USER_SIZE 0x80000 /* 512KB */ -#define BANKB_CORE3_PFLASH_KERNEL_START 0x82680000 -#define BANKB_CORE3_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ -#define BANKB_CORE3_PFLASH_USER_START 0x82700000 -#define BANKB_CORE3_PFLASH_USER_SIZE 0xE0000 /* 896KB */ -#define BANKB_CORE4_PFLASH_KERNEL_START 0x827E0000 -#define BANKB_CORE4_PFLASH_KERNEL_SIZE 0x88000 /* 544KB */ -#define BANKB_CORE4_PFLASH_USER_START 0x82868000 -#define BANKB_CORE4_PFLASH_USER_SIZE 0xC4000 /* 784KB */ -#define BANKB_CORE5_PFLASH_KERNEL_START 0x8292C000 -#define BANKB_CORE5_PFLASH_KERNEL_SIZE 0x70000 /* 448KB */ -#define BANKB_CORE5_PFLASH_USER_START 0x8299C000 -#define BANKB_CORE5_PFLASH_USER_SIZE 0x64000 /* 400KB */ -#define BANKA_CORE6_PFLASH_KERNEL_START 0x84000000 -#define BANKA_CORE6_PFLASH_KERNEL_SIZE 0x40000 /* 256KB */ -#define BANKA_CORE6_VBMETA_START 0x8403C000 -#define BANKA_CORE6_VBMETA_SIZE 0x4000 /* 16KB */ -#define BANKB_CORE6_PFLASH_KERNEL_START 0x84040000 -#define BANKB_CORE6_PFLASH_KERNEL_SIZE 0x40000 /* 256KB */ -#define BANKB_CORE6_VBMETA_START 0x8407C000 -#define BANKB_CORE6_VBMETA_SIZE 0x4000 /* 16KB */ -#define CORE6_RES_PFLASH_KERNEL_START 0x84080000 -#define CORE6_RES_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */ -#define CORE0_STACK_KERNEL_START 0x70000000 -#define CORE0_STACK_KERNEL_SIZE 0x9800 /* 38KB */ -#define CORE0_STACK_USER_START 0x70009800 -#define CORE0_STACK_USER_SIZE 0x8000 /* 32KB */ -#define CORE0_DSPR_KERNEL_START 0x70011800 -#define CORE0_DSPR_KERNEL_SIZE 0x2A800 /* 170KB */ -#define CORE0_DSPR_USER_START 0x7003C000 -#define CORE0_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE0_PSPR_KERNEL_START 0x70100000 -#define CORE0_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE0_PSPR_USER_START 0x70108000 -#define CORE0_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE0_DLMU_KERNEL_START 0x90020400 -#define CORE0_DLMU_KERNEL_SIZE 0x2AC00 /* 171KB */ -#define CORE0_DLMU_USER_START 0x9004B000 -#define CORE0_DLMU_USER_SIZE 0x35000 /* 212KB */ -#define CORE1_STACK_KERNEL_START 0x60000000 -#define CORE1_STACK_KERNEL_SIZE 0x8800 /* 34KB */ -#define CORE1_STACK_USER_START 0x60008800 -#define CORE1_STACK_USER_SIZE 0x8000 /* 32KB */ -#define CORE1_DSPR_KERNEL_START 0x60010800 -#define CORE1_DSPR_KERNEL_SIZE 0x2B800 /* 174KB */ -#define CORE1_DSPR_USER_START 0x6003C000 -#define CORE1_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE1_PSPR_KERNEL_START 0x60100000 -#define CORE1_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE1_PSPR_USER_START 0x60108000 -#define CORE1_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE1_DLMU_KERNEL_START 0x90080000 -#define CORE1_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ -#define CORE1_DLMU_USER_START 0x900C0000 -#define CORE1_DLMU_USER_SIZE 0x40000 /* 256KB */ -#define CORE2_STACK_KERNEL_START 0x50000000 -#define CORE2_STACK_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE2_STACK_USER_START 0x50008000 -#define CORE2_STACK_USER_SIZE 0x8000 /* 32KB */ -#define CORE2_DSPR_KERNEL_START 0x50010000 -#define CORE2_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ -#define CORE2_DSPR_USER_START 0x5003C000 -#define CORE2_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE2_PSPR_KERNEL_START 0x50100000 -#define CORE2_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE2_PSPR_USER_START 0x50108000 -#define CORE2_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE2_DLMU_KERNEL_START 0x90100000 -#define CORE2_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ -#define CORE2_DLMU_USER_START 0x90140000 -#define CORE2_DLMU_USER_SIZE 0x40000 /* 256KB */ -#define CORE3_STACK_KERNEL_START 0x40000000 -#define CORE3_STACK_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE3_STACK_USER_START 0x40008000 -#define CORE3_STACK_USER_SIZE 0x8000 /* 32KB */ -#define CORE3_DSPR_KERNEL_START 0x40010000 -#define CORE3_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ -#define CORE3_DSPR_USER_START 0x4003C000 -#define CORE3_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE3_PSPR_KERNEL_START 0x40100000 -#define CORE3_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE3_PSPR_USER_START 0x40108000 -#define CORE3_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE3_DLMU_KERNEL_START 0x90180000 -#define CORE3_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ -#define CORE3_DLMU_USER_START 0x901C0000 -#define CORE3_DLMU_USER_SIZE 0x40000 /* 256KB */ -#define CORE4_STACK_KERNEL_START 0x30000000 -#define CORE4_STACK_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE4_STACK_USER_START 0x30008000 -#define CORE4_STACK_USER_SIZE 0x8000 /* 32KB */ -#define CORE4_DSPR_KERNEL_START 0x30010000 -#define CORE4_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ -#define CORE4_DSPR_USER_START 0x3003C000 -#define CORE4_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE4_PSPR_KERNEL_START 0x30100000 -#define CORE4_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE4_PSPR_USER_START 0x30108000 -#define CORE4_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE4_DLMU_KERNEL_START 0x90200000 -#define CORE4_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ -#define CORE4_DLMU_USER_START 0x90240000 -#define CORE4_DLMU_USER_SIZE 0x40000 /* 256KB */ -#define CORE5_STACK_KERNEL_START 0x20000000 -#define CORE5_STACK_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE5_STACK_USER_START 0x20008000 -#define CORE5_STACK_USER_SIZE 0x8000 /* 32KB */ -#define CORE5_DSPR_KERNEL_START 0x20010000 -#define CORE5_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */ -#define CORE5_DSPR_USER_START 0x2003C000 -#define CORE5_DSPR_USER_SIZE 0x0 /* 0KB */ -#define CORE5_PSPR_KERNEL_START 0x20100000 -#define CORE5_PSPR_KERNEL_SIZE 0x8000 /* 32KB */ -#define CORE5_PSPR_USER_START 0x20108000 -#define CORE5_PSPR_USER_SIZE 0x8000 /* 32KB */ -#define CORE5_DLMU_KERNEL_START 0x90280000 -#define CORE5_DLMU_KERNEL_SIZE 0x40000 /* 256KB */ -#define CORE5_DLMU_USER_START 0x902C0000 -#define CORE5_DLMU_USER_SIZE 0x40000 /* 256KB */ -#define CORE6_DSPR_KERNEL_START 0x10000000 -#define CORE6_DSPR_KERNEL_SIZE 0x3C000 /* 240KB */ -#define CORE6_PSPR_KERNEL_START 0x10100000 -#define CORE6_PSPR_KERNEL_SIZE 0x10000 /* 64KB */ -#define AURIX_RPMSG_SHMEM_START 0xB04D0000 -#define AURIX_RPMSG_SHMEM_SIZE 0x20000 /* 128KB */ -#define AURIX_RPMSG_CORE0CORE1_SYSLOG_START 0xB04F0000 -#define AURIX_RPMSG_CORE0CORE1_SYSLOG_SIZE 0x2000 /* 8KB */ -#define AURIX_RPMSG_CORE0CORE2_SYSLOG_START 0xB04F2000 -#define AURIX_RPMSG_CORE0CORE2_SYSLOG_SIZE 0x2000 /* 8KB */ -#define AURIX_RPMSG_CORE0CORE3_SYSLOG_START 0xB04F4000 -#define AURIX_RPMSG_CORE0CORE3_SYSLOG_SIZE 0x2000 /* 8KB */ -#define AURIX_RPMSG_CORE0CORE4_SYSLOG_START 0xB04F6000 -#define AURIX_RPMSG_CORE0CORE4_SYSLOG_SIZE 0x2000 /* 8KB */ -#define AURIX_RPMSG_CORE0CORE5_SYSLOG_START 0xB04F8000 -#define AURIX_RPMSG_CORE0CORE5_SYSLOG_SIZE 0x2000 /* 8KB */ -#define AURIX_RPMSG_CORE0CORECS_SYSLOG_START 0xB04FA000 -#define AURIX_RPMSG_CORE0CORECS_SYSLOG_SIZE 0x6000 /* 8KB */ -#define AURIX_SYSLOG_RPMSG_START 0xB04F0000 -#define AURIX_SYSLOG_RPMSG_SIZE 0x10000 /* 64KB */ -#define LMU2_UNUSED_START 0xB0565400 -#define LMU2_UNUSED_SIZE 0x1AC00 /* 107KB */ -#define LMU3_UNUSED_START 0xB0580000 -#define LMU3_UNUSED_SIZE 0x80000 /* 512KB */ -#define LMU4_UNUSED_START 0xB0600000 -#define LMU4_UNUSED_SIZE 0x80000 /* 512KB */ -#define LMU5_UNUSED_START 0xB0680000 -#define LMU5_UNUSED_SIZE 0x80000 /* 512KB */ -#define LMU6_UNUSED_START 0xB0700000 -#define LMU6_UNUSED_SIZE 0x80000 /* 512KB */ -#define LMU7_UNUSED_START 0xB0780000 -#define LMU7_UNUSED_SIZE 0x80000 /* 512KB */ -#define LMU8_UNUSED_START 0xB0800000 -#define LMU8_UNUSED_SIZE 0x80000 /* 512KB */ -#define LMU9_UNUSED_START 0xB0880000 -#define LMU9_UNUSED_SIZE 0x80000 /* 512KB */ -#define DFLASH0_NVM_START 0xAE000000 -#define DFLASH0_NVM_SIZE 0x40000 /* 256KB */ -#define DFLASH0_MANUFACTURY_START 0xAE040000 -#define DFLASH0_MANUFACTURY_SIZE 0x2800 /* 10K */ -#define DFLASH0_BSWLOG_START 0xAE042800 -#define DFLASH0_BSWLOG_SIZE 0x10000 /* 64K */ -#define DFLASH0_TRAPINFO_START 0xAE052800 -#define DFLASH0_TRAPINFO_SIZE 0x4000 /* 16K */ -#define DFLASH0_DFXLOG_START 0xAE056800 -#define DFLASH0_DFXLOG_SIZE 0x4000 /* 16K */ -#define DFLASH0_UNUSED_START 0xAE05A800 -#define DFLASH0_UNUSED_SIZE 0xA5800 /* 662K */ -#define DFLASH1_START 0xAE800000 -#define DFLASH1_SIZE 0x1E000 /* 120K */ -#define DFLASH1_SYSLOG_START 0xAE81E000 -#define DFLASH1_SYSLOG_SIZE 0x2000 /* 8K */ -#define UCB0_START 0xAE400000 -#define UCB0_SIZE 0x14000 /* 80K */ -#define UCB1_START 0xAEC00000 -#define UCB1_SIZE 0xD000 /* 52K */ -#define PERIPHERALS_START 0xE9800000 -#define PERIPHERALS_SIZE 0x118A0000 /* 287360K */ -#define CORE0_DCACHE_START 0x7003C000 -#define CORE0_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE1_DCACHE_START 0x6003C000 -#define CORE1_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE2_DCACHE_START 0x5003C000 -#define CORE2_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE3_DCACHE_START 0x4003C000 -#define CORE3_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE4_DCACHE_START 0x3003C000 -#define CORE4_DCACHE_SIZE 0x4000 /* 16K */ -#define CORE5_DCACHE_START 0x2003C000 -#define CORE5_DCACHE_SIZE 0x4000 /* 16K */ - -/**************************************************************************** - * Common macros - * - ****************************************************************************/ - -#ifdef CONFIG_BUILD_FLAT - -# define CORE0_PFLASH_KERNEL_START BANKA_CORE0_PFLASH_KERNEL_START -# define CORE0_PFLASH_KERNEL_SIZE BANKA_CORE0_PFLASH_KERNEL_SIZE -# define CORE1_PFLASH_KERNEL_START BANKA_CORE1_PFLASH_KERNEL_START -# define CORE1_PFLASH_KERNEL_SIZE BANKA_CORE1_PFLASH_KERNEL_SIZE -# define CORE2_PFLASH_KERNEL_START BANKA_CORE2_PFLASH_KERNEL_START -# define CORE2_PFLASH_KERNEL_SIZE BANKA_CORE2_PFLASH_KERNEL_SIZE -# define CORE3_PFLASH_KERNEL_START BANKA_CORE3_PFLASH_KERNEL_START -# define CORE3_PFLASH_KERNEL_SIZE BANKA_CORE3_PFLASH_KERNEL_SIZE -# define CORE4_PFLASH_KERNEL_START BANKA_CORE4_PFLASH_KERNEL_START -# define CORE4_PFLASH_KERNEL_SIZE BANKA_CORE4_PFLASH_KERNEL_SIZE -# define CORE5_PFLASH_KERNEL_START BANKA_CORE5_PFLASH_KERNEL_START -# define CORE5_PFLASH_KERNEL_SIZE BANKA_CORE5_PFLASH_KERNEL_SIZE -# define CORE6_PFLASH_KERNEL_START BANKA_CORE6_PFLASH_KERNEL_START -# define CORE6_PFLASH_KERNEL_SIZE BANKA_CORE6_PFLASH_KERNEL_SIZE - -#else - -# define CORE0_PFLASH_KERNEL_START BANKA_CORE0_PFLASH_KERNEL_START -# define CORE0_PFLASH_KERNEL_SIZE BANKA_CORE0_PFLASH_KERNEL_SIZE -# define CORE0_PFLASH_USER_START BANKA_CORE0_PFLASH_USER_START -# define CORE0_PFLASH_USER_SIZE BANKA_CORE0_PFLASH_USER_SIZE - -# define CORE1_PFLASH_KERNEL_START BANKA_CORE1_PFLASH_KERNEL_START -# define CORE1_PFLASH_KERNEL_SIZE BANKA_CORE1_PFLASH_KERNEL_SIZE -# define CORE1_PFLASH_USER_START BANKA_CORE1_PFLASH_USER_START -# define CORE1_PFLASH_USER_SIZE BANKA_CORE1_PFLASH_USER_SIZE - -# define CORE2_PFLASH_KERNEL_START BANKA_CORE2_PFLASH_KERNEL_START -# define CORE2_PFLASH_KERNEL_SIZE BANKA_CORE2_PFLASH_KERNEL_SIZE -# define CORE2_PFLASH_USER_START BANKA_CORE2_PFLASH_USER_START -# define CORE2_PFLASH_USER_SIZE BANKA_CORE2_PFLASH_USER_SIZE - -# define CORE3_PFLASH_KERNEL_START BANKA_CORE3_PFLASH_KERNEL_START -# define CORE3_PFLASH_KERNEL_SIZE BANKA_CORE3_PFLASH_KERNEL_SIZE -# define CORE3_PFLASH_USER_START BANKA_CORE3_PFLASH_USER_START -# define CORE3_PFLASH_USER_SIZE BANKA_CORE3_PFLASH_USER_SIZE - -# define CORE4_PFLASH_KERNEL_START BANKA_CORE4_PFLASH_KERNEL_START -# define CORE4_PFLASH_KERNEL_SIZE BANKA_CORE4_PFLASH_KERNEL_SIZE -# define CORE4_PFLASH_USER_START BANKA_CORE4_PFLASH_USER_START -# define CORE4_PFLASH_USER_SIZE BANKA_CORE4_PFLASH_USER_SIZE - -# define CORE5_PFLASH_KERNEL_START BANKA_CORE5_PFLASH_KERNEL_START -# define CORE5_PFLASH_KERNEL_SIZE BANKA_CORE5_PFLASH_KERNEL_SIZE -# define CORE5_PFLASH_USER_START BANKA_CORE5_PFLASH_USER_START -# define CORE5_PFLASH_USER_SIZE BANKA_CORE5_PFLASH_USER_SIZE - -# define CORE6_PFLASH_KERNEL_START BANKA_CORE6_PFLASH_KERNEL_START -# define CORE6_PFLASH_KERNEL_SIZE BANKA_CORE6_PFLASH_KERNEL_SIZE - -#endif - -#define BL_PFLASH_START BANKA_BL_PFLASH_START -#define BL_PFLASH_SIZE BANKA_BL_PFLASH_SIZE -#define BL_DLMU_START CORE0_DLMU_KERNEL_START -#define BL_DLMU_SIZE CORE0_DLMU_KERNEL_SIZE -#define BL_DSPR_START CORE0_DSPR_KERNEL_START -#define BL_DSPR_SIZE CORE0_DSPR_KERNEL_SIZE -#define BL_PSPR_START CORE0_PSPR_KERNEL_START -#define BL_PSPR_SIZE CORE0_PSPR_KERNEL_SIZE -#define MBF_HASH_START BANKA_MBF_HASH_START -#define MBF_HASH_SIZE BANKA_MBF_HASH_SIZE - -#define NC_START(addr) \ - ((addr) >= 0x80000000 && (addr) <= 0x9FFFFFFF ? (addr) + 0x20000000 : (addr)) - -#define AURIX_PERIPHERAL_BASE_ADDR 0xE9800000 -#define AURIX_PERIPHERAL_SIZE 0x118A0000 - -#define DSPR_LOCAL_START 0xD0000000 -#define PSPR_LOCAL_START 0xC0000000 - -#define BACKGROUND_START 0x10000000 -#define BACKGROUND_SIZE 0xEB0A0000 - -#define CORE0_DCACHE_KERNEL_START 0x7003C000 -#define CORE0_DCACHE_KERNEL_SIZE 0x4000 -#define CORE1_DCACHE_KERNEL_START 0x6003C000 -#define CORE1_DCACHE_KERNEL_SIZE 0x4000 -#define CORE2_DCACHE_KERNEL_START 0x5003C000 -#define CORE2_DCACHE_KERNEL_SIZE 0x4000 -#define CORE3_DCACHE_KERNEL_START 0x4003C000 -#define CORE3_DCACHE_KERNEL_SIZE 0x4000 -#define CORE4_DCACHE_KERNEL_START 0x3003C000 -#define CORE4_DCACHE_KERNEL_SIZE 0x4000 -#define CORE5_DCACHE_KERNEL_START 0x2003C000 -#define CORE5_DCACHE_KERNEL_SIZE 0x4000 - -#define CORE_PFLASH_KERNEL_START(COREID) CORE##COREID##_PFLASH_KERNEL_START -#define CORE_PFLASH_KERNEL_SIZE(COREID) CORE##COREID##_PFLASH_KERNEL_SIZE -#define GENERATE_CORE_PFLASH_KERNEL_START(COREID) CORE_PFLASH_KERNEL_START(COREID) -#define GENERATE_CORE_PFLASH_KERNEL_SIZE(COREID) CORE_PFLASH_KERNEL_SIZE(COREID) - -#define CORE_STACK_KERNEL_START(COREID) CORE##COREID##_STACK_KERNEL_START -#define CORE_STACK_KERNEL_SIZE(COREID) CORE##COREID##_STACK_KERNEL_SIZE -#define GENERATE_CORE_STACK_KERNEL_START(COREID) CORE_STACK_KERNEL_START(COREID) -#define GENERATE_CORE_STACK_KERNEL_SIZE(COREID) CORE_STACK_KERNEL_SIZE(COREID) - -#define CORE_DSPR_KERNEL_START(COREID) CORE##COREID##_DSPR_KERNEL_START -#define CORE_DSPR_KERNEL_SIZE(COREID) CORE##COREID##_DSPR_KERNEL_SIZE -#define GENERATE_CORE_DSPR_KERNEL_START(COREID) CORE_DSPR_KERNEL_START(COREID) -#define GENERATE_CORE_DSPR_KERNEL_SIZE(COREID) CORE_DSPR_KERNEL_SIZE(COREID) - -#define CORE_PSPR_KERNEL_START(COREID) CORE##COREID##_PSPR_KERNEL_START -#define CORE_PSPR_KERNEL_SIZE(COREID) CORE##COREID##_PSPR_KERNEL_SIZE -#define GENERATE_CORE_PSPR_KERNEL_START(COREID) CORE_PSPR_KERNEL_START(COREID) -#define GENERATE_CORE_PSPR_KERNEL_SIZE(COREID) CORE_PSPR_KERNEL_SIZE(COREID) - -#define CORE_DLMU_KERNEL_START(COREID) CORE##COREID##_DLMU_KERNEL_START -#define CORE_DLMU_KERNEL_SIZE(COREID) CORE##COREID##_DLMU_KERNEL_SIZE -#define GENERATE_CORE_DLMU_KERNEL_START(COREID) CORE_DLMU_KERNEL_START(COREID) -#define GENERATE_CORE_DLMU_KERNEL_SIZE(COREID) CORE_DLMU_KERNEL_SIZE(COREID) - -#define CORE_CALIB_KERNEL_START(COREID) CORE##COREID##_CALIB_KERNEL_START -#define CORE_CALIB_KERNEL_SIZE(COREID) CORE##COREID##_CALIB_KERNEL_SIZE -#define GENERATE_CORE_CALIB_KERNEL_START(COREID) CORE_CALIB_KERNEL_START(COREID) -#define GENERATE_CORE_CALIB_KERNEL_SIZE(COREID) CORE_CALIB_KERNEL_SIZE(COREID) - -#define CORE_DCACHE_KERNEL_START(COREID) CORE##COREID##_DCACHE_KERNEL_START -#define CORE_DCACHE_KERNEL_SIZE(COREID) CORE##COREID##_DCACHE_KERNEL_SIZE -#define GENERATE_CORE_DCACHE_KERNEL_START(COREID) CORE_DCACHE_KERNEL_START(COREID) -#define GENERATE_CORE_DCACHE_KERNEL_SIZE(COREID) CORE_DCACHE_KERNEL_SIZE(COREID) - -#ifndef CONFIG_BUILD_FLAT - -#define CORE_PFLASH_USER_START(COREID) CORE##COREID##_PFLASH_USER_START -#define CORE_PFLASH_USER_SIZE(COREID) CORE##COREID##_PFLASH_USER_SIZE -#define GENERATE_CORE_PFLASH_USER_START(COREID) CORE_PFLASH_USER_START(COREID) -#define GENERATE_CORE_PFLASH_USER_SIZE(COREID) CORE_PFLASH_USER_SIZE(COREID) - -#define CORE_STACK_USER_START(COREID) CORE##COREID##_STACK_USER_START -#define CORE_STACK_USER_SIZE(COREID) CORE##COREID##_STACK_USER_SIZE -#define GENERATE_CORE_STACK_USER_START(COREID) CORE_STACK_USER_START(COREID) -#define GENERATE_CORE_STACK_USER_SIZE(COREID) CORE_STACK_USER_SIZE(COREID) - -#define CORE_DSPR_USER_START(COREID) CORE##COREID##_DSPR_USER_START -#define CORE_DSPR_USER_SIZE(COREID) CORE##COREID##_DSPR_USER_SIZE -#define GENERATE_CORE_DSPR_USER_START(COREID) CORE_DSPR_USER_START(COREID) -#define GENERATE_CORE_DSPR_USER_SIZE(COREID) CORE_DSPR_USER_SIZE(COREID) - -#define CORE_PSPR_USER_START(COREID) CORE##COREID##_PSPR_USER_START -#define CORE_PSPR_USER_SIZE(COREID) CORE##COREID##_PSPR_USER_SIZE -#define GENERATE_CORE_PSPR_USER_START(COREID) CORE_PSPR_USER_START(COREID) -#define GENERATE_CORE_PSPR_USER_SIZE(COREID) CORE_PSPR_USER_SIZE(COREID) - -#define CORE_DLMU_USER_START(COREID) CORE##COREID##_DLMU_USER_START -#define CORE_DLMU_USER_SIZE(COREID) CORE##COREID##_DLMU_USER_SIZE -#define GENERATE_CORE_DLMU_USER_START(COREID) CORE_DLMU_USER_START(COREID) -#define GENERATE_CORE_DLMU_USER_SIZE(COREID) CORE_DLMU_USER_SIZE(COREID) - -#define CORE_CALIB_USER_START(COREID) CORE##COREID##_CALIB_USER_START -#define CORE_CALIB_USER_SIZE(COREID) CORE##COREID##_CALIB_USER_SIZE -#define GENERATE_CORE_CALIB_USER_START(COREID) CORE_CALIB_USER_START(COREID) -#define GENERATE_CORE_CALIB_USER_SIZE(COREID) CORE_CALIB_USER_SIZE(COREID) - -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel deleted file mode 100644 index 69780d11f5b0c..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel +++ /dev/null @@ -1,590 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.kernel - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include "arch/board/board_memorymap.h" - -#define __JOIN2(x,y) x##y -#define JOIN2(x,y) __JOIN2(x,y) -#define __JOIN3(x,y,z) x##y##z -#define JOIN3(x,y,z) __JOIN3(x,y,z) -#define __JOIN4(x,y,z,w) x##y##z##w -#define JOIN4(x,y,z,w) __JOIN4(x,y,z,w) - -#define COREID_LST(x) JOIN2(x, CONFIG_CPU_COREID) -#define COREID_MID(x,y) JOIN3(x, CONFIG_CPU_COREID, y) - -/* Default linker script, for normal executables */ -OUTPUT_FORMAT("elf32-tricore") -OUTPUT_ARCH("tricore") -#if CONFIG_CPU_COREID == 0 -ENTRY(_START) -#endif - -__TRICORE_DERIVATE_MEMORY_MAP__ = 0x490; - -LCF_PFLASH_KERNEL_START = GENERATE_CORE_PFLASH_KERNEL_START(CONFIG_CPU_COREID); -LCF_PFLASH_KERNEL_SIZE = GENERATE_CORE_PFLASH_KERNEL_SIZE(CONFIG_CPU_COREID); -LCF_DSPR_KERNEL_START = GENERATE_CORE_DSPR_KERNEL_START(CONFIG_CPU_COREID); -LCF_DSPR_KERNEL_SIZE = GENERATE_CORE_DSPR_KERNEL_SIZE(CONFIG_CPU_COREID); -LCF_PSPR_KERNEL_START = GENERATE_CORE_PSPR_KERNEL_START(CONFIG_CPU_COREID); -LCF_PSPR_KERNEL_SIZE = GENERATE_CORE_PSPR_KERNEL_SIZE(CONFIG_CPU_COREID); -LCF_DLMU_KERNEL_START = GENERATE_CORE_DLMU_KERNEL_START(CONFIG_CPU_COREID); -LCF_DLMU_KERNEL_SIZE = GENERATE_CORE_DLMU_KERNEL_SIZE(CONFIG_CPU_COREID); -LCF_KSTACK_START = GENERATE_CORE_STACK_KERNEL_START(CONFIG_CPU_COREID); -LCF_KSTACK_SIZE = GENERATE_CORE_STACK_KERNEL_SIZE(CONFIG_CPU_COREID); - -#if CONFIG_CPU_COREID != 0 -LCF_SYSLOG_START = JOIN3(AURIX_RPMSG_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_START); -LCF_SYSLOG_SIZE = JOIN3(AURIX_RPMSG_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_SIZE); -#endif - -LCF_CSA_SIZE = 40k; -LCF_USTACK_SIZE = CONFIG_IDLETHREAD_STACKSIZE; -LCF_ISTACK_SIZE = CONFIG_ARCH_INTERRUPTSTACK; - -LCF_CSA_OFFSET = (LCF_DSPR_KERNEL_SIZE - 1k - LCF_CSA_SIZE); -LCF_ISTACK_OFFSET = (LCF_CSA_OFFSET - 256 - LCF_ISTACK_SIZE); -LCF_USTACK_OFFSET = (LCF_ISTACK_OFFSET - 256 - LCF_USTACK_SIZE); - -LCF_STARTPTR = LCF_PFLASH_KERNEL_START; -LCF_STARTPTR_NC = NC_START(LCF_STARTPTR); -LCF_TRAPVEC_START = LCF_STARTPTR + 0x100; - -COREID_LST(__INTTAB_CPU) = LCF_PFLASH_KERNEL_START; - -LCF_STARTPTR_NC_CPU0 = NC_START(CORE0_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU1 = NC_START(CORE1_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU2 = NC_START(CORE2_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU3 = NC_START(CORE3_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU4 = NC_START(CORE4_PFLASH_KERNEL_START); -LCF_STARTPTR_NC_CPU5 = NC_START(CORE5_PFLASH_KERNEL_START); -RESET = CORE0_PFLASH_KERNEL_START; - -MEMORY -{ - kstack (w!xp): org = LCF_KSTACK_START, len = LCF_KSTACK_SIZE - - dspr (w!xp): org = LCF_DSPR_KERNEL_START, len = LCF_DSPR_KERNEL_SIZE - pspr (w!xp): org = LCF_PSPR_KERNEL_START, len = LCF_PSPR_KERNEL_SIZE - - psram_local (w!xp): org = PSPR_LOCAL_START, len = LCF_PSPR_KERNEL_SIZE - - pfls (rx!p): org = LCF_PFLASH_KERNEL_START, len = LCF_PFLASH_KERNEL_SIZE - pfls_nc (rx!p): org = NC_START(LCF_PFLASH_KERNEL_START), len = LCF_PFLASH_KERNEL_SIZE - - ucb (rx!p): org = 0xae404800, len = 80K - 2K - - cpu_dlmu (w!xp): org = LCF_DLMU_KERNEL_START, len = LCF_DLMU_KERNEL_SIZE - cpu_dlmu_nc (w!xp): org = NC_START(LCF_DLMU_KERNEL_START), len = LCF_DLMU_KERNEL_SIZE - - rpmsg_shmem (w!xp): org = AURIX_RPMSG_SHMEM_START, len = AURIX_RPMSG_SHMEM_SIZE -#if CONFIG_CPU_COREID != 0 - syslogram (w!xp): org = LCF_SYSLOG_START, len = LCF_SYSLOG_SIZE -#endif -} - -/* map cached and non cached addresses */ -REGION_MIRROR("pfls", "pfls_nc") -REGION_MIRROR("cpu_dlmu", "cpu_dlmu_nc") - -/*Sections located at absolute fixed address*/ -/*Fixed memory Allocations for stack memory*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.ustack) (LCF_DSPR_KERNEL_START + LCF_USTACK_OFFSET): - { - PROVIDE(__USTACK_END = .); - PROVIDE(COREID_MID(__USTACK, _END) = .); - . = . + LCF_USTACK_SIZE; - PROVIDE(__USTACK = .); - PROVIDE(COREID_LST(__USTACK) = .); - } - - CORE_SEC(.istack) (LCF_DSPR_KERNEL_START + LCF_ISTACK_OFFSET): - { - PROVIDE(__ISTACK_END = .); - PROVIDE(COREID_MID(__ISTACK, _END) = .); - . = . + LCF_ISTACK_SIZE; - PROVIDE(__ISTACK = .); - PROVIDE(COREID_LST(__ISTACK) = .); - } - CORE_SEC(.csa) (LCF_DSPR_KERNEL_START + LCF_CSA_OFFSET): - { - PROVIDE(COREID_LST(__CSA) = .); - . = . + LCF_CSA_SIZE; - PROVIDE(COREID_MID(__CSA, _END) = .); - } -} - -/*Fixed memory Allocations for _START*/ -CORE_ID = GLOBAL ; -SECTIONS -{ - .start_tc (LCF_STARTPTR) : FLAGS(rxl) - { - KEEP (*(.start)); - KEEP (*(.start_cpu?)); - } > pfls - - .interface_const (LCF_STARTPTR + 0x20) : - { - __IF_CONST = .; - KEEP (*(.interface_const)); - } > pfls - - PROVIDE(__START = LCF_STARTPTR); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU0 = 0); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU1 = 1); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU2 = 1); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU3 = 1); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU4 = 1); - PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU5 = 1); -} - -/*Fixed memory Allocations for Trap Vector Table*/ -CORE_ID = GLOBAL; -SECTIONS -{ - .traptab_tc (LCF_TRAPVEC_START) : - { - PROVIDE(COREID_LST(__TRAPTAB_CPU) = .); - KEEP (*(.COREID_LST(traptab_cpu))); - } > pfls -} - -/*Fixed memory Allocations for _START1 to 5 */ -CORE_ID = GLOBAL ; -SECTIONS -{ - PROVIDE(__START1 = CORE1_PFLASH_KERNEL_START); - PROVIDE(__START2 = CORE2_PFLASH_KERNEL_START); - PROVIDE(__START3 = CORE3_PFLASH_KERNEL_START); - PROVIDE(__START4 = CORE4_PFLASH_KERNEL_START); - PROVIDE(__START5 = CORE5_PFLASH_KERNEL_START); -} - -/*Fixed memory Allocations for Interrupt Vector Table*/ -SECTIONS -{ - /*Interrupt Vector Table*/ - .COREID_MID(inttab_tc, _0FF) (COREID_LST(__INTTAB_CPU) + 0x1FE0) : - { - . = ALIGN(8); - KEEP (*(.COREID_MID(intvec_tc, _255))); - . = ALIGN(0x2000); - } > pfls -} - -/* Fixed memory Allocations for BMHD*/ -CORE_ID = GLOBAL; -SECTIONS -{ - .bmhd_0_org (0xae404800) : FLAGS(arl) { KEEP (*(.bmhd_0_orig)); } > ucb - .bmhd_1_org (0xae405000) : FLAGS(arl) { KEEP (*(.bmhd_1_orig)); } > ucb - .bmhd_2_org (0xae405800) : FLAGS(arl) { KEEP (*(.bmhd_2_orig)); } > ucb - .bmhd_3_org (0xae406000) : FLAGS(arl) { KEEP (*(.bmhd_3_orig)); } > ucb - .usercfg_0_org (0xae408800) : FLAGS(arl) { KEEP (*(.usercfg_0_orig)); } > ucb - .usercfg_0_cpy (0xae409000) : FLAGS(arl) { KEEP (*(.usercfg_0_copy)); } > ucb -} - -/*Relative A0/A1/A8/A9 Addressable Sections*/ -CORE_ID = GLOBAL; -SECTIONS -{ - /*Relative A0 Addressable Data, selectable with patterns and user defined sections*/ - /*Note: A0 addressable area is common, to make the functions callable in any CPU*/ - /*Relative A0 Addressable Data, selectable by toolchain*/ - CORE_SEC(.sdata) : FLAGS(awsl) - { - *(.sdata) - *(.sdata.*) - . = ALIGN(4); - } > cpu_dlmu AT> pfls - - CORE_SEC(.sbss) (NOLOAD): FLAGS(aws) - { - *(.sbss) - *(.sbss.*) - } > cpu_dlmu - _SMALL_DATA_ = SIZEOF(CORE_SEC(.sdata)) ? ADDR(CORE_SEC(.sdata)) : (ADDR(CORE_SEC(.sdata)) & 0xF0000000) + 32k ; - __A0_MEM = _SMALL_DATA_; -} - -CORE_ID = GLOBAL; -SECTIONS -{ - /*Relative A1 Addressable Const, selectable with patterns and user defined sections*/ - /*Note: A1 addressable area is common, to make the functions callable in any CPU*/ - /*Relative A1 Addressable Const, selectable by toolchain*/ - CORE_SEC(.sdata2) : FLAGS(arsl) - { - *(.srodata) - *(.srodata.*) - } > pfls - _SMALL_DATA2_ = SIZEOF(CORE_SEC(.sdata2)) ? ADDR(CORE_SEC(.sdata2)) : (ADDR(CORE_SEC(.sdata2)) & 0xF0000000) + 32k ; - __A1_MEM = _SMALL_DATA2_; -} - -CORE_ID = GLOBAL; -SECTIONS -{ - /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ - CORE_SEC(.sdata4) : - { - *(.a9sdata) - *(.a9sdata.*) - . = ALIGN(4); - } > cpu_dlmu AT> pfls - - CORE_SEC(.sbss4) (NOLOAD) : - { - *(.a9sbss) - *(.a9sbss.*) - } > cpu_dlmu - - _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; - __A9_MEM = _SMALL_DATA4_; - - /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ - CORE_SEC(.sdata3) : FLAGS(arsl) - { - *(.rodata_a8) - *(.rodata_a8.*) - } > pfls - - _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; - __A8_MEM = _SMALL_DATA3_; -} - -/*kstack*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.stack) (NOLOAD) : FLAGS(aw) - { - *(.dtcm_stack) - *(.dtcm_stack.*) - } > kstack -} - -/*data&bss*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.dspr_data) : FLAGS(awzl) - { - *Ifx_Ssw_Tc?.* (.data) - *Cpu?_Main.* (.data.*) - . = ALIGN(4); - } > dspr AT> pfls - - CORE_SEC(.dspr_bss) (NOLOAD) : FLAGS(awz) - { - *Ifx_Ssw_Tc?.* (.bss) - *Cpu?_Main.* (.bss.*) - *os_scheduletable_misc.* (.bss.*) - *iob_initialize.* (.bss.*) - . = ALIGN(4); - } > dspr - - CORE_SEC(.zdata) : FLAGS(awzl) - { - *(.zdata) - *(.zdata.*) - *(.gnu.linkonce.z.*) - . = ALIGN(4); - } > cpu_dlmu AT> pfls - - CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) - { - *(.zbss) - *(.zbss.*) - *(.bbss) - *(.bbss.*) - *(.gnu.linkonce.zb.*) - } > cpu_dlmu - - CORE_SEC(.data) : FLAGS(awl) - { - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(4); - } > cpu_dlmu AT> pfls - - CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) - { - *(.bss) - *(.bss.*) - *(.lmubss_cpu?) - *(.lmubss_cpu?.*) - *(.gnu.linkonce.b.*) - } > cpu_dlmu -} - -/*Heap*/ -CORE_ID = GLOBAL; -SECTIONS -{ - .dlmuheap (NOLOAD) : FLAGS(aw) - { - . = ALIGN(4); - __DLMUHEAP = ABSOLUTE(.); - __DLMUHEAP_END = ABSOLUTE(LCF_DLMU_KERNEL_START + LCF_DLMU_KERNEL_SIZE); - } > cpu_dlmu - - .heap (NOLOAD) : FLAGS(aw) - { - . = ALIGN(4); - _sheap = ABSOLUTE(.); - _eheap = ABSOLUTE(__USTACK_END); - } > dspr -} - -/*syslog*/ -#if CONFIG_CPU_COREID != 0 -CORE_ID = GLOBAL; -SECTIONS -{ - .syslog (NOLOAD) : FLAGS(aw) - { - . = ALIGN(4); - *(.syslog) - *(.syslog.*) - } > syslogram -} -#endif - -/*rodata*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.rodata) : FLAGS(arl) - { - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - /* - * Create the clear and copy tables that tell the startup code - * which memory areas to clear and to copy, respectively. - */ - . = ALIGN(4) ; - PROVIDE(__clear_table = .); - LONG(0 + ADDR(.dspr_bss)); LONG(SIZEOF(.dspr_bss)); - LONG(0 + ADDR(.zbss)); LONG(SIZEOF(.zbss)); - LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss)); - LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); - LONG(0 + ADDR(.sbss4)); LONG(SIZEOF(.sbss4)); - - LONG(-1); LONG(-1); - PROVIDE(__clear_table_powerOn = .); - LONG(-1); LONG(-1); - PROVIDE(__copy_table = .); - LONG(LOADADDR(.dspr_data)); LONG(0 + ADDR(.dspr_data)); LONG(SIZEOF(.dspr_data)); - LONG(LOADADDR(.zdata)); LONG(0 + ADDR(.zdata)); LONG(SIZEOF(.zdata)); - LONG(LOADADDR(.sdata)); LONG(0 + ADDR(.sdata)); LONG(SIZEOF(.sdata)); - LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); - LONG(LOADADDR(.sdata4)); LONG(0 + ADDR(.sdata4)); LONG(SIZEOF(.sdata4)); - LONG(LOADADDR(.psram_text)); LONG(0 + ADDR(.psram_text)); LONG(SIZEOF(.psram_text)); - LONG(-1); LONG(-1); LONG(-1); - PROVIDE(__copy_table_powerOn = .) ; - LONG(-1); LONG(-1); LONG(-1); - . = ALIGN(8); - } > pfls -} - -/*Code selections*/ -/*Code Sections, selectable with patterns and user defined sections*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.zrodata) : FLAGS(arzl) - { - *Ifx_Ssw_Tc?.* (.zrodata) - *Cpu?_Main.* (.zrodata) - *(.zrodata_cpu?) - *(.zrodata) - *(.zrodata.*) - } > pfls - - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------Start----------------------------------------- - */ - .init : - { - PROVIDE(__init_start = .); - KEEP(*(.init)) - KEEP(*(.init*)) - PROVIDE(__init_end = .); - . = ALIGN(8); - - } > pfls - - .fini : - { - PROVIDE(__fini_start = .); - KEEP(*(.fini)) - KEEP(*(.fini*)) - PROVIDE(__fini_end = .); - . = ALIGN(8); - } > pfls - - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - CORE_SEC(.psram_text) : FLAGS(awxl) - { - . = ALIGN(4); - *aurix_mtd_flash.*(.text) - *aurix_mtd_flash.*(.text.*) - *aurix_mtd_partition.*(.text) - *aurix_mtd_partition.*(.text.*) - . = ALIGN(4); - } > pspr AT> pfls - - CORE_SEC(.text) : FLAGS(axl) - { - . = ALIGN(4); - *Ifx_Ssw_Tc?.*(.text) - *Cpu?_Main.*(.text) - *Ifx_Ssw_Tc?.*(.text.*) - *Cpu?_Main.*(.text.*) - *(.text) - *(.text.*) - *(.gcc_except_table) - *(.gnu.linkonce.t.*) - *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ - . = ALIGN(8); - } > pfls - - /* - * C++ exception handling tables. NOTE: gcc emits .eh_frame - * sections when compiling C sources with debugging enabled (-g). - * If you can be sure that your final application consists - * exclusively of C objects (i.e., no C++ objects), you may use - * the -R option of the "strip" and "objcopy" utilities to remove - * the .eh_frame section from the executable. - */ - .eh_frame_hdr : ALIGN(8) - { - KEEP (*(.eh_frame_hdr)) - . = ALIGN(8); - } > pfls - - .eh_frame : ALIGN(8) - { - __EH_FRAME_BEGIN__ = . ; - KEEP (*(.eh_frame)) - __EH_FRAME_END__ = . ; - . = ALIGN(8); - } > pfls - - /* - * Constructors and destructors. - */ - .ctors : FLAGS(ar) - { - _sinit = ABSOLUTE(.); - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------Start----------------------------------------- - */ - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - _einit = ABSOLUTE(.); - . = ALIGN(8); - } > pfls - .dtors : FLAGS(ar) - { - __DTOR_LIST__ = . ; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------Start----------------------------------------- - */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------End----------------------------------------- - */ - LONG(0) ; - __DTOR_END__ = . ; - . = ALIGN(8); - } > pfls - /* - * DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the - * beginning of the section, so we begin them at 0. - */ - /* - * DWARF 1 - */ - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* - * GNU DWARF 1 extensions - */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* - * DWARF 1.1 and DWARF 2 - */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* - * DWARF 2 - */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_ranges 0 : { *(.debug_ranges) } - /* - * SGI/MIPS DWARF 2 extensions - */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* - * Optional sections that may only appear when relocating. - */ - /* - * Optional sections that may appear regardless of relocating. - */ - .version_info 0 : { *(.version_info) } - .boffs 0 : { KEEP (*(.boffs)) } -} diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user deleted file mode 100644 index 98393894ed55b..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include "arch/board/board_memorymap.h" - -/* Default linker script, for normal executables */ -OUTPUT_FORMAT("elf32-tricore") -OUTPUT_ARCH("tricore") - -LCF_PFLASH_USER_START = GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID); -LCF_PFLASH_USER_SIZE = GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID); -LCF_DLMU_USER_START = GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID); -LCF_DLMU_USER_SIZE = GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID); -LCF_USTACK_START = GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID); -LCF_USTACK_SIZE = GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID); - -MEMORY -{ - upfls (rx!p): org = LCF_PFLASH_USER_START, len = LCF_PFLASH_USER_SIZE - upfls_nc (rx!p): org = NC_START(LCF_PFLASH_USER_START), len = LCF_PFLASH_USER_SIZE - - cpu_udlmu (w!xp): org = LCF_DLMU_USER_START, len = LCF_DLMU_USER_SIZE - cpu_udlmu_nc (w!xp): org = NC_START(LCF_DLMU_USER_START), len = LCF_DLMU_USER_SIZE - - ustack (w!xp): org = LCF_USTACK_START, len = LCF_USTACK_SIZE -} - -/* map cached and non cached addresses */ -REGION_MIRROR("upfls", "upfls_nc") -REGION_MIRROR("cpu_udlmu", "cpu_udlmu_nc") - -/*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/ - -/*Code Sections, selectable by toolchain*/ -CORE_ID = GLOBAL; -SECTIONS -{ - .userspace : ALIGN(64) - { - _suserspace = ABSOLUTE(.); - KEEP(*(.userspace)) - . = ALIGN(64); /* userspace align to 64 to keep the address continuous for MBF */ - _euserspace = ABSOLUTE(.); - } > upfls - - CORE_SEC(.text) : FLAGS(axl) - { - _stext = ABSOLUTE(.); - *(.text) - *(.text.*) - *(.zrodata) - *(.zrodata.*) - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.gcc_except_table) - *(.gnu.linkonce.t.*) - *(.gnu.warning) /* .gnu.warning sections are handled specially by elf32.em. */ - . = ALIGN(4); - _etext = ABSOLUTE(.); - } > upfls - - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - - /* - * C++ exception handling tables. NOTE: gcc emits .eh_frame - * sections when compiling C sources with debugging enabled (-g). - * If you can be sure that your final application consists - * exclusively of C objects (i.e., no C++ objects), you may use - * the -R option of the "strip" and "objcopy" utilities to remove - * the .eh_frame section from the executable. - */ - .eh_frame_hdr : ALIGN(8) - { - KEEP (*(.eh_frame_hdr)) - . = ALIGN(8); - } > upfls - - .eh_frame : ALIGN(8) - { - __EH_FRAME_BEGIN__ = . ; - KEEP (*(.eh_frame)) - __EH_FRAME_END__ = . ; - . = ALIGN(8); - } > upfls - - /* - * Constructors and destructors. - */ - .ctors : FLAGS(ar) - { - _sinit = ABSOLUTE(.); - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------Start----------------------------------------- - */ - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - /* - * Code executed before calling main extra section for C++ constructor init - * -------------------------End----------------------------------------- - */ - _einit = ABSOLUTE(.); - . = ALIGN(8); - } > upfls - .dtors : FLAGS(ar) - { - __DTOR_LIST__ = . ; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------Start----------------------------------------- - */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* - * Code executed before calling main extra section for C++ destructor init - * -------------------------End----------------------------------------- - */ - LONG(0) ; - __DTOR_END__ = . ; - . = ALIGN(8); - } > upfls - - _eronly = ABSOLUTE(.); - - /* - * DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the - * beginning of the section, so we begin them at 0. - */ - /* - * DWARF 1 - */ - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* - * GNU DWARF 1 extensions - */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* - * DWARF 1.1 and DWARF 2 - */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* - * DWARF 2 - */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_ranges 0 : { *(.debug_ranges) } - /* - * SGI/MIPS DWARF 2 extensions - */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* - * Optional sections that may only appear when relocating. - */ - /* - * Optional sections that may appear regardless of relocating. - */ - .version_info 0 : { *(.version_info) } - .boffs 0 : { KEEP (*(.boffs)) } -} - -/*Far Data Sections, selectable by toolchain*/ -CORE_ID = GLOBAL; -SECTIONS -{ - CORE_SEC(.stack) (NOLOAD) : FLAGS(aw) - { - *(.dtcm_stack) - *(.dtcm_stack.*) - } > ustack - - CORE_SEC(.data) : FLAGS(awzl) - { - _sdata = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.zdata) - *(.zdata.*) - *(.gnu.linkonce.d.*) - *(.gnu.linkonce.z.*) - . = ALIGN(2); - _edata = ABSOLUTE(.); - } > cpu_udlmu AT> upfls - - CORE_SEC(.bss) (NOLOAD): FLAGS(awz) - { - _sbss = ABSOLUTE(.); - *(.bss) - *(.bss.*) - *(.zbss) - *(.zbss.*) - *(.bbss) - *(.bbss.*) - *(.gnu.linkonce.zb.*) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > cpu_udlmu - - .heap (NOLOAD) : FLAGS(aw) - { - _sheap = ABSOLUTE(.); - _eheap = ABSOLUTE(LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE); - } > cpu_udlmu - - _sdata_pflash = LOADADDR(.data); -} - -#if CONFIG_CPU_COREID == 5 -/* This sections is added to reserve last 4 bytes of flash in core5's user - * space. This is because the car's diagnostic service will query this area, - * and if the area has been erased but not written to, the query will cause - * an exception. Since the page size of pflash is 32 bytes, we reserve 32 - * bytes instead of 4 bytes. - */ - -CORE_ID = GLOBAL; -SECTIONS -{ - .flash_reserve (LCF_PFLASH_USER_START + LCF_PFLASH_USER_SIZE - 32) : { - . = ALIGN(32); - FILL(0x55); - . = . + 28; - LONG(0x55555555); - } > upfls -} -#endif diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel deleted file mode 100644 index 79dc34e38912f..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel +++ /dev/null @@ -1,639 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include "arch/board/board_memorymap.h" - -#define __JOIN2(x,y) x##y -#define JOIN2(x,y) __JOIN2(x,y) -#define __JOIN3(x,y,z) x##y##z -#define JOIN3(x,y,z) __JOIN3(x,y,z) -#define __JOIN4(x,y,z,w) x##y##z##w -#define JOIN4(x,y,z,w) __JOIN4(x,y,z,w) - -#ifdef USE_PREFIX -# define K_PREFIX(x) kernel_##x -# define K_PREFIX_COREID_LST(x) JOIN3(kernel_, x, CONFIG_CPU_COREID) -# define K_PREFIX_COREID_MID(x,y) JOIN4(kernel_, x, CONFIG_CPU_COREID, y) -#else -# define K_PREFIX(x) x -# define K_PREFIX_COREID_LST(x) JOIN2(x, CONFIG_CPU_COREID) -# define K_PREFIX_COREID_MID(x,y) JOIN3(x, CONFIG_CPU_COREID, y) -#endif - -#define LCF_PFLASH_KERNEL_START GENERATE_CORE_PFLASH_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_PFLASH_KERNEL_SIZE GENERATE_CORE_PFLASH_KERNEL_SIZE(CONFIG_CPU_COREID) -#define LCF_DSPR_KERNEL_START GENERATE_CORE_DSPR_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_DSPR_KERNEL_SIZE GENERATE_CORE_DSPR_KERNEL_SIZE(CONFIG_CPU_COREID) -#define LCF_PSPR_KERNEL_START GENERATE_CORE_PSPR_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_PSPR_KERNEL_SIZE GENERATE_CORE_PSPR_KERNEL_SIZE(CONFIG_CPU_COREID) -#define LCF_DLMU_KERNEL_START GENERATE_CORE_DLMU_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_DLMU_KERNEL_SIZE GENERATE_CORE_DLMU_KERNEL_SIZE(CONFIG_CPU_COREID) -#define LCF_KSTACK_START GENERATE_CORE_STACK_KERNEL_START(CONFIG_CPU_COREID) -#define LCF_KSTACK_SIZE GENERATE_CORE_STACK_KERNEL_SIZE(CONFIG_CPU_COREID) - -#if CONFIG_CPU_COREID != 0 -#define LCF_SYSLOG_START JOIN3(AURIX_RPTUN_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_START) -#define LCF_SYSLOG_SIZE JOIN3(AURIX_RPTUN_CORE0CORE, CONFIG_CPU_COREID, _SYSLOG_SIZE) -#endif - -#define LCF_CSA_SIZE 40k -#define LCF_USTACK_SIZE CONFIG_IDLETHREAD_STACKSIZE -#define LCF_ISTACK_SIZE CONFIG_ARCH_INTERRUPTSTACK - -#define LCF_HEAP_SIZE 4k - -#define LCF_CPU0 0 -#define LCF_CPU1 1 -#define LCF_CPU2 2 -#define LCF_CPU3 3 -#define LCF_CPU4 4 -#define LCF_CPU5 5 - -/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/ -#define LCF_DEFAULT_HOST LCF_CPU0 - -#define LCF_CSA_OFFSET (LCF_DSPR_KERNEL_SIZE - 1k - LCF_CSA_SIZE) -#define LCF_ISTACK_OFFSET (LCF_CSA_OFFSET - 256 - LCF_ISTACK_SIZE) -#define LCF_USTACK_OFFSET (LCF_ISTACK_OFFSET - 256 - LCF_USTACK_SIZE) -#define LCF_HEAP_OFFSET (LCF_USTACK_OFFSET - LCF_HEAP_SIZE) - -#define LCF_STARTPTR_CPU LCF_PFLASH_KERNEL_START -#define LCF_TRAPVEC_START (LCF_STARTPTR_CPU + 0x20) -#define LCF_INTVEC_START LCF_PFLASH_KERNEL_START - -#define LCF_STARTPTR_NC_CPU0 NC_START(CORE0_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU1 NC_START(CORE1_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU2 NC_START(CORE2_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU3 NC_START(CORE3_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU4 NC_START(CORE4_PFLASH_KERNEL_START) -#define LCF_STARTPTR_NC_CPU5 NC_START(CORE5_PFLASH_KERNEL_START) - -#define INTTAB (LCF_INTVEC_START) - -#define RESET CORE0_PFLASH_KERNEL_START - -#include "tc1v1_8.lsl" - -// Specify a multi-core processor environment (mpe) - -processor mpe -{ - derivative = tc4D; -} - -derivative tc4D -{ - core tc - { - architecture = TC1V1.8; - space_id_offset = 100; // add 100 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core vtc - { - architecture = TC1V1.8; - import tc; // add all address spaces of core tc to core vtc for linking and locating - } - - bus sri - { - mau = 8; - width = 32; - - // map shared addresses one-to-one to real cores and virtual cores - map (dest=bus:tc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - } - - memory dsram // Data Scratch Pad Ram - { - mau = 8; - size = LCF_DSPR_KERNEL_SIZE; - type = ram; - map (dest=bus:tc:fpi_bus, dest_offset=DSPR_LOCAL_START, size=LCF_DSPR_KERNEL_SIZE, priority=8); - map (dest=bus:sri, dest_offset=LCF_DSPR_KERNEL_START, size=LCF_DSPR_KERNEL_SIZE); - } - - memory psram // Program Scratch Pad Ram - { - mau = 8; - size = LCF_PSPR_KERNEL_SIZE; - type = ram; - map (dest=bus:tc:fpi_bus, dest_offset=PSPR_LOCAL_START, size=LCF_PSPR_KERNEL_SIZE, priority=8); - map (dest=bus:sri, dest_offset=LCF_PSPR_KERNEL_START, size=LCF_PSPR_KERNEL_SIZE); - } - - memory pfls - { - mau = 8; - size = LCF_PFLASH_KERNEL_SIZE; - type = rom; - map cached (dest=bus:sri, dest_offset=LCF_PFLASH_KERNEL_START, size=LCF_PFLASH_KERNEL_SIZE); - map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_PFLASH_KERNEL_START), reserved, size=LCF_PFLASH_KERNEL_SIZE); - } - - memory ucb - { - mau = 8; - size = 80K; - type = rom; - map (dest=bus:sri, dest_offset=0xae400000, reserved, size=80K); - } - - memory cpu_dlmu - { - mau = 8; - size = LCF_DLMU_KERNEL_SIZE; - type = ram; - map cached (dest=bus:sri, dest_offset=LCF_DLMU_KERNEL_START, size=LCF_DLMU_KERNEL_SIZE); - map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_KERNEL_START), reserved, size=LCF_DLMU_KERNEL_SIZE); - } - - memory kstack - { - mau = 8; - size = LCF_KSTACK_SIZE; - type = ram; - map not_cached (dest=bus:sri, dest_offset=LCF_KSTACK_START, size=LCF_KSTACK_SIZE); - } - -#if CONFIG_CPU_COREID != 0 - memory syslog - { - mau = 8; - size = LCF_SYSLOG_SIZE; - type = ram; - map not_cached (dest=bus:sri, dest_offset=LCF_SYSLOG_START, size=LCF_SYSLOG_SIZE); - } -#endif - - section_setup :vtc:linear - { - heap "heap1" (min_size = LCF_HEAP_SIZE, align = 4); - heap "heap2" (min_size = LCF_HEAP_SIZE, align = 4); - } - - section_setup :vtc:linear - { - start_address - ( -#if CONFIG_CPU_COREID == 0 - symbol = "_START" -#elif CONFIG_CPU_COREID == 1 - symbol = "_START1" -#elif CONFIG_CPU_COREID == 2 - symbol = "_START2" -#elif CONFIG_CPU_COREID == 3 - symbol = "_START3" -#elif CONFIG_CPU_COREID == 4 - symbol = "_START4" -#elif CONFIG_CPU_COREID == 5 - symbol = "_START5" -#endif - ); - } - - section_setup :vtc:linear - { - stack "ustack_tc" (min_size = 1k, fixed, align = 8); - stack "istack_tc" (min_size = 1k, fixed, align = 8); - } - - /*Section setup for the copy table*/ - section_setup :vtc:linear - { - copytable - ( - align = 4, - dest = linear, - table - { - symbol = "_lc_ub_table_tc"; - space = :tc:linear, :tc:abs24, :tc:abs18; - } - ); - } - - /*Sections located at absolute fixed address*/ - - section_layout :vtc:linear - { - /*Fixed memory Allocations for stack memory*/ - group (ordered) - { - group ustack(align = 8, run_addr = mem:dsram[LCF_USTACK_OFFSET]) - { - stack "ustack_tc" (size = LCF_USTACK_SIZE); - } - "__USTACK"= sizeof(group:ustack) > 0 ? "_lc_ue_ustack_tc" : 0; - "__USTACK_END"="_lc_gb_ustack"; - "__USTACK0_END"="_lc_gb_ustack"; - "__USTACK1_END"="_lc_gb_ustack"; - "__USTACK2_END"="_lc_gb_ustack"; - "__USTACK3_END"="_lc_gb_ustack"; - "__USTACK4_END"="_lc_gb_ustack"; - "__USTACK5_END"="_lc_gb_ustack"; - "__USTACK0":= "__USTACK"; - "__USTACK1":= "__USTACK"; - "__USTACK2":= "__USTACK"; - "__USTACK3":= "__USTACK"; - "__USTACK4":= "__USTACK"; - "__USTACK5":= "__USTACK"; - - group istack(align = 8, run_addr = mem:dsram[LCF_ISTACK_OFFSET]) - { - stack "istack_tc" (size = LCF_ISTACK_SIZE); - } - "__ISTACK"= sizeof(group:istack) > 0 ? "_lc_ue_istack_tc" : 0; - "__ISTACK_END"="_lc_gb_istack"; - "__ISTACK0":="__ISTACK"; - "__ISTACK1":="__ISTACK"; - "__ISTACK2":="__ISTACK"; - "__ISTACK3":="__ISTACK"; - "__ISTACK4":="__ISTACK"; - "__ISTACK5":="__ISTACK"; - } - - /*Fixed memory Allocations for _START*/ - group (ordered) - { - group interface_const (run_addr=mem:pfls[0x0020]) - { - select "*.interface_const"; - } - "__IF_CONST" := addressof(group:interface_const); - "__START0" := CORE0_PFLASH_KERNEL_START; - "__START1" := CORE1_PFLASH_KERNEL_START; - "__START2" := CORE2_PFLASH_KERNEL_START; - "__START3" := CORE3_PFLASH_KERNEL_START; - "__START4" := CORE4_PFLASH_KERNEL_START; - "__START5" := CORE5_PFLASH_KERNEL_START; - } - - /*Fixed memory Allocations for Trap Vector Table*/ - group (ordered) - { - group trapvec_tc (align = 8, run_addr=LCF_TRAPVEC_START) - { - section "trapvec_tc" (size=0x100, attributes=rx, fill=0) - { -#if CONFIG_CPU_COREID == 0 - select "(.text.traptab_cpu0*)"; -#elif CONFIG_CPU_COREID == 1 - select "(.text.traptab_cpu1*)"; -#elif CONFIG_CPU_COREID == 2 - select "(.text.traptab_cpu2*)"; -#elif CONFIG_CPU_COREID == 3 - select "(.text.traptab_cpu3*)"; -#elif CONFIG_CPU_COREID == 4 - select "(.text.traptab_cpu4*)"; -#elif CONFIG_CPU_COREID == 5 - select "(.text.traptab_cpu5*)"; -#endif - } - } - "__TRAPTAB_CPU0" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU1" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU2" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU3" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU4" := LCF_TRAPVEC_START; - "__TRAPTAB_CPU5" := LCF_TRAPVEC_START; - } - - /*Fixed memory Allocations for Start up code*/ - group (ordered, attributes=rx) - { - group start_tc (run_addr=(LCF_STARTPTR_CPU)) - { -#if CONFIG_CPU_COREID == 0 - select "(.text.start*)"; -#elif CONFIG_CPU_COREID == 1 - select "(.text.start_cpu1*)"; -#elif CONFIG_CPU_COREID == 2 - select "(.text.start_cpu2*)"; -#elif CONFIG_CPU_COREID == 3 - select "(.text.start_cpu3*)"; -#elif CONFIG_CPU_COREID == 4 - select "(.text.start_cpu4*)"; -#elif CONFIG_CPU_COREID == 5 - select "(.text.start_cpu5*)"; -#endif - } - "__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 1; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 1; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU3" := 1; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU4" := 1; /* Not used */ - "__ENABLE_INDIVIDUAL_C_INIT_CPU5" := 1; /* Not used */ - } - - /*Fixed memory Allocations for Interrupt Vector Table*/ - group (ordered, attributes=rx) - { - group int_tab_tc (ordered) - { - group (run_addr=(INTTAB)+0x1FE0) select ".text.inttab0.intvec.0ff"; - } - "_lc_u_int_tab" = (LCF_INTVEC_START); - "__INTTAB_CPU0" = (LCF_INTVEC_START); - "__INTTAB_CPU1" = (LCF_INTVEC_START); - "__INTTAB_CPU2" = (LCF_INTVEC_START); - "__INTTAB_CPU3" = (LCF_INTVEC_START); - "__INTTAB_CPU4" = (LCF_INTVEC_START); - "__INTTAB_CPU5" = (LCF_INTVEC_START); - } - - /*Fixed memory Allocations for BMHD*/ - group (ordered) - { - group bmh_0_orig (run_addr=mem:ucb[0x4800]) - { - select ".rodata.bmhd_0_orig"; - } - group bmh_1_orig (run_addr=mem:ucb[0x5000]) - { - select ".rodata.bmhd_1_orig"; - } - group bmh_2_orig (run_addr=mem:ucb[0x5800]) - { - select ".rodata.bmhd_2_orig"; - } - group bmh_3_orig (run_addr=mem:ucb[0x6000]) - { - select ".rodata.bmhd_3_orig"; - } - group usercfg_0_org (run_addr=mem:ucb[0x8800]) - { - select ".rodata.usercfg_0_orig"; - } - group usercfg_0_cpy (run_addr=mem:ucb[0x9000]) - { - select ".rodata.usercfg_0_copy"; - } - } - } - - /*Near Abbsolute Addressable Data Sections*/ - section_layout :vtc:abs18 - { - /*Near Absolute Data, selectable with patterns and user defined sections*/ - group - { - group (ordered, attributes=rw, run_addr = mem:cpu_dlmu) - { - select "(.zdata.zlmudata|.zdata.zlmudata.*)"; - select "(.zbss.zlmubss|.zbss.zlmubss.*)"; - } - } - - /*Near Absolute Data, selectable by toolchain*/ - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) - { - group zdata(attributes=rw) - { - select "(.zdata|.zdata.*)"; - select "(.zbss|.zbss.*)"; - } - } - - /*Near Absolute Const, selectable with patterns and user defined sections*/ - group - { - group (ordered, contiguous, align = 4, attributes=r, run_addr=mem:pfls) - { -#if CONFIG_CPU_COREID == 0 - select ".zrodata.Ifx_Ssw_Tc?.*"; - select ".zrodata.Cpu?_Main.*"; -#elif CONFIG_CPU_COREID == 1 - select ".zrodata.Ifx_Ssw_Tc1.*"; - select ".zrodata.Cpu1_Main.*"; -#elif CONFIG_CPU_COREID == 2 - select ".zrodata.Ifx_Ssw_Tc2.*"; - select ".zrodata.Cpu2_Main.*"; -#elif CONFIG_CPU_COREID == 3 - select ".zrodata.Ifx_Ssw_Tc3.*"; - select ".zrodata.Cpu3_Main.*"; -#elif CONFIG_CPU_COREID == 4 - select ".zrodata.Ifx_Ssw_Tc4.*"; - select ".zrodata.Cpu4_Main.*"; -#elif CONFIG_CPU_COREID == 5 - select ".zrodata.Ifx_Ssw_Tc5.*"; - select ".zrodata.Cpu5_Main.*"; -#endif - /*Near Absolute Const, selectable by toolchain*/ - select "(.zrodata|.zrodata.*)"; - } - } - } - - /*Relative A0/A1/A8/A9 Addressable Sections*/ - section_layout :vtc:linear - { - /*Relative A0 Addressable Data, selectable by toolchain*/ - group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) - { - select "(.sdata|.sdata.*)"; - select "(.data_a0|.data_a0.*)"; - select "(.sbss|.sbss.*)"; - select "(.bss_a0|.bss_a0.*)"; - } - "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k; - "__A0_MEM" = "_SMALL_DATA_"; - - /*Relative A1 Addressable Const, selectable by toolchain*/ - /*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/ - group a1 (ordered, align = 4, attributes=r, run_addr=mem:pfls) - { - select "(.srodata|.srodata.*)"; - select "(.ldata|.ldata.*)"; - select "(.rodata_a1|.rodata_a1.*)"; - } - "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k; - "__A1_MEM" = "_LITERAL_DATA_"; - - /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ - group a9 (ordered, align = 4, run_addr=mem:dsram) - { - select "(.a9sdata|.a9sdata.*)"; - select "(.data_a9|.data_a9.*)"; - select "(.a9sbss|.a9sbss.*)"; - select "(.bss_a9|.bss_a9.*)"; - } - "_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k; - "__A9_MEM" = "_A9_DATA_"; - - /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ - group a8 (ordered, align = 4, run_addr=mem:pfls) - { - select "(.a8srodata|.a8srodata.*)"; - select "(.rodata_a8|.rodata_a8.*)"; - } - "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k; - "__A8_MEM" = "_A8_DATA_"; - } - - /*kstack ram*/ - section_layout :vtc:linear - { - group kstack(ordered, contiguous, nocopy, run_addr=mem:kstack) - { - select "(.dtcm_stack|.dtcm_stack.*)"; - } - } - -#if CONFIG_CPU_COREID != 0 - /*syslog ram*/ - section_layout :vtc:linear - { - group syslog(ordered, contiguous, nocopy, run_addr=mem:syslog) - { - select "(.syslog|.syslog.*)"; - } - } -#endif - - /*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ - section_layout :vtc:linear - { - /*Far Data Sections, selectable with patterns and user defined sections*/ - - /*DSRAM sections*/ - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) - { - group (attributes=rw) - { - select ".data.Ifx_Ssw_Tc?.*"; - select ".data.Cpu?_Main.*"; - select ".bss.Ifx_Ssw_Tc?.*"; - select ".bss.Cpu?_Main.*"; - select ".bss.os_scheduletable_misc.*"; - select ".bss.iob_initialize.*"; - select "(.dspr_data|.dspr_data.*)"; - } - - group (attributes=rw, nocopy) - { - select "(.dspr_bss|.dspr_bss.*)"; - } - - /*Heap1*/ - group heap1(attributes=rw) - { - heap "heap1" (size = LCF_HEAP_SIZE); - } - "_sheap":="_lc_ub_heap1"; - "_eheap":="__USTACK_END"; - } - - /*LMU Data sections*/ - group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_dlmu/not_cached) - { - select "(.data.uncached.*)"; - select "(.bss.uncached.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr=mem:cpu_dlmu) - { - group lmubss(attributes=rw, nocopy) - { - select "(.lmubss_cpu?|.lmubss_cpu?.*)"; - } - - group data(attributes=rw) - { - select "(.data|.data.*)"; - select "(.bss|.bss.*)"; - } - - /*Heap2 allocation*/ - group heap2(attributes=rw) - { - heap "heap2" (size = LCF_HEAP_SIZE); - } - "__DLMUHEAP":="_lc_ge_data"; - "__DLMUHEAP_END":=LCF_DLMU_KERNEL_START + LCF_DLMU_KERNEL_SIZE; - } - - /*Far Const Sections, selectable with patterns and user defined sections*/ - group - { - group (ordered, align = 4, attributes=r, run_addr=mem:pfls) - { - select ".rodata.Ifx_Ssw_Tc?.*"; - select ".rodata.Cpu?_Main.*"; - } - } - - /*Far Const Sections, selectable by toolchain*/ - group (ordered, align = 4, run_addr=mem:pfls) - { - select "(.rodata|.rodata.*)"; - select "(.constant|.constant.*)"; - } - } - - /* PSRAM Code selections*/ - section_layout :vtc:linear - { - /*Code Sections, selectable with patterns and user defined sections*/ - group - { - /*Program Scratchpad Sections*/ - group - { - group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram) - { - select "(.text.aurix_mtd_flash|.text.aurix_mtd_flash.*)"; - select "(.text.aurix_mtd_partition|.text.aurix_mtd_partition.*)"; - } - } - } - } - - /* FLS Code selections*/ - section_layout :vtc:linear - { - /*Code Sections, selectable with patterns and user defined sections*/ - group - { - /*Cpu specific PFLASH Sections*/ - group - { - group (ordered, align = 4, attributes=rx, run_addr=mem:pfls) - { - select ".text.Ifx_Ssw_Tc?.*"; - select ".text.Cpu?_Main.*"; - select ".text.CompilerTasking.Ifx_C_Init"; - } - } - } - - /*Code Sections, selectable by toolchain*/ - group text(ordered, contiguous, fill = 0, run_addr=mem:pfls) - { - select "(.text|.text.*)"; - } - "_stext" = "_lc_gb_text"; - "_etext" = "_lc_ge_text"; - } -} diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user deleted file mode 100644 index 0bb924ba6891b..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user +++ /dev/null @@ -1,204 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc4da/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#include "arch/board/board_memorymap.h" - -#define LCF_PFLASH_USER_START GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID) -#define LCF_PFLASH_USER_SIZE GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID) -#define LCF_DLMU_USER_START GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID) -#define LCF_DLMU_USER_SIZE GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID) -#define LCF_USTACK_START GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID) -#define LCF_USTACK_SIZE GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID) - -#define LCF_HEAP_SIZE 4k - -#include "tc1v1_8.lsl" - -// Specify a multi-core processor environment (mpe) - -processor mpe -{ - derivative = tc4D; -} - -derivative tc4D -{ - core tc - { - architecture = TC1V1.8; - space_id_offset = 100; // add 100 to all space IDs in the architecture definition - copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections - } - - core vtc - { - architecture = TC1V1.8; - import tc; // add all address spaces of core tc to core vtc for linking and locating - } - - bus sri - { - mau = 8; - width = 32; - - // map shared addresses one-to-one to real cores and virtual cores - map (dest=bus:tc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); - } - - memory upfls - { - mau = 8; - size = LCF_PFLASH_USER_SIZE; - type = rom; - map cached (dest=bus:sri, dest_offset=LCF_PFLASH_USER_START, size=LCF_PFLASH_USER_SIZE); - map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_PFLASH_USER_START), reserved, size=LCF_PFLASH_USER_SIZE); - } - - memory cpu_udlmu - { - mau = 8; - size = LCF_DLMU_USER_SIZE; - type = ram; - map cached (dest=bus:sri, dest_offset=LCF_DLMU_USER_START, size=LCF_DLMU_USER_SIZE); - map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_USER_START), reserved, size=LCF_DLMU_USER_SIZE); - } - - memory ustack - { - mau = 8; - size = LCF_USTACK_SIZE; - type = ram; - map not_cached (dest=bus:sri, dest_offset=LCF_USTACK_START, size=LCF_USTACK_SIZE); - } - - /*Section setup for the copy table*/ - section_setup :vtc:linear - { - copytable - ( - align = 4, - dest = linear, - table - { - symbol = "_lc_ub_table_tc"; - space = :tc:linear, :tc:abs24, :tc:abs18; - } - ); - } - - section_setup :vtc:linear - { - heap "uheap" (min_size = LCF_HEAP_SIZE, align = 4); - } - - /* user stack section */ - section_layout :vtc:linear - { - group ustack(ordered, contiguous, nocopy, run_addr=mem:ustack) - { - select "(.dtcm_stack|.dtcm_stack.*)"; - } - } - - /*Sections located at absolute fixed address*/ - section_layout :vtc:linear - { - group userspace(ordered, run_addr=LCF_PFLASH_USER_START) - { - select "(.userspace|.userspace.*)"; - } - "_suserspace" = "_lc_gb_userspace"; - "_euserspace" = "_lc_ge_userspace"; - - group text(ordered, contiguous, fill = 0, run_addr=mem:upfls) - { - select "(.text|.text.*)"; - select "(.zrodata|.zrodata.*)"; - select "(.rodata|.rodata.*)"; - select "(.constant|.constant.*)"; - } - "_stext" = "_lc_gb_text"; - "_etext" = "_lc_ge_text"; - } - - /* Data & Bss section */ - section_layout :vtc:linear - { - group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu/not_cached) - { - select "(.data.uncached.*)"; - select "(.bss.uncached.*)"; - } - - group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu) - { - group udata - { - select "(.data|.data.*)"; - select "(.zdata|.zdata.*)"; - } - "_sdata" = "_lc_gb_udata"; - "_edata" = "_lc_ge_udata"; - - /* bss section */ - group ubss - { - select "(.bss|.bss.*)"; - select "(.zbss|.zbss.*)"; - select "(.bbss|.bbss.*)"; - } - "_sbss" = "_lc_gb_ubss"; - "_ebss" = "_lc_ge_ubss"; - - /* heap section */ - group uheap - { - heap "uheap" (size = LCF_HEAP_SIZE); - } - "_sheap" = "_ebss"; - "_eheap" = LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE; - } - - group udata_rom(ordered, contiguous, load_addr=mem:upfls) - { - select "(.data|.data.*)"; - select "(.zdata|.zdata.*)"; - } - "_sdata_pflash" = "_lc_gb_udata_rom"; - } -#if CONFIG_CPU_COREID == 5 - /* This sections is added to reserve last 4 bytes of flash in core5's user - * space. This is because the car's diagnostic service will query this area, - * and if the area has been erased but not written to, the query will cause - * an exception. Since the page size of pflash is 32 bytes, we reserve 32 - * bytes instead of 4 bytes. - */ - section_layout :vtc:linear - { - group flash_reserve(ordered, run_addr=LCF_PFLASH_USER_START + LCF_PFLASH_USER_SIZE - 32) - { - reserved "flash_reserve" ( size = 32, attributes = r, fill = 0x55 ); - } - } -#endif -} diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Make.defs b/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Make.defs deleted file mode 100644 index d015a3ceca651..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/scripts/Make.defs +++ /dev/null @@ -1,44 +0,0 @@ -############################################################################ -# boards/tricore/tc4da/triboard_tc4x9_com/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/tricore/src/tc4xx/Toolchain.defs - -ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - TRICORE_TOOLCHAIN := Tasking -else - TRICORE_TOOLCHAIN := Gnuc -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.kernel - -ifeq ($(CONFIG_BUILD_PROTECTED),y) - ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.user -endif - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/CMakeLists.txt b/boards/tricore/tc4da/triboard_tc4x9_com/src/CMakeLists.txt deleted file mode 100644 index 3ed0a4855edbb..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/src/CMakeLists.txt +++ /dev/null @@ -1,42 +0,0 @@ -# ############################################################################## -# boards/tricore/tc4da/triboard_tc4x9_com/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS tc4da_boardinit.c tc4da_bringup.c) - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_TRICORE_TOOLCHAIN_TASKING) - set(toolchain "Tasking") -else() - set(toolchain "Gnuc") -endif() - -set_property( - GLOBAL - PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.kernel") -if(CONFIG_BUILD_PROTECTED) - set_property( - GLOBAL - PROPERTY LD_SCRIPT_USER - "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.user") -endif() diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/Makefile b/boards/tricore/tc4da/triboard_tc4x9_com/src/Makefile deleted file mode 100644 index 30abecc8728ae..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/src/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -############################################################################ -# boards/tricore/tc4da/triboard_tc4x9_com/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = tc4da_boardinit.c tc4da_bringup.c - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da.h b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da.h deleted file mode 100644 index 9cb69f9b2b876..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_SRC_TC4DA_H -#define __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_SRC_TC4DA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Functions Definitions - ****************************************************************************/ - -/**************************************************************************** - * Name: tc4da_bringup - * - * Description: - * Bring up board features - * - ****************************************************************************/ - -#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) -int tc4da_bringup(void); -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_TRICORE_TC4DA_TRIBOARD_TC4X9_COM_SRC_TC4DA_H */ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_boardinit.c b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_boardinit.c deleted file mode 100644 index adfdb89a8bee9..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_boardinit.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_boardinit.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "chip.h" -#include "tc4da.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: tc4da_memory_initialize - * - * Description: - * All i.MX6 architectures must provide the following entry point. This - * entry point is called early in the initialization before memory has - * been configured. This board-specific function is responsible for - * configuring any on-board memories. - * - * Logic in tc4da_memory_initialize must be careful to avoid using any - * global variables because those will be uninitialized at the time this - * function is called. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void tc4da_memory_initialize(void) -{ - /* SDRAM was initialized by a bootloader in the supported configurations. */ -} - -/**************************************************************************** - * Name: tc4da_board_initialize - * - * Description: - * All i.MX6 architectures must provide the following entry point. This - * entry point is called in the initialization phase -- after - * tc4da_memory_initialize and after all memory has been configured and - * mapped but before any devices have been initialized. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void tc4da_board_initialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_intitialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board initialization */ - - tc4da_bringup(); -} -#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_bringup.c b/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_bringup.c deleted file mode 100644 index b802b389f038e..0000000000000 --- a/boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_bringup.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/tricore/tc4da/triboard_tc4x9_com/src/tc4da_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "tc4da.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: tc4da_bringup - * - * Description: - * Bring up board features - * - ****************************************************************************/ - -int tc4da_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_TMPFS - /* Mount the tmpfs file system */ - - ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", - CONFIG_LIBC_TMPDIR, ret); - } -#endif - - UNUSED(ret); - return OK; -} From 0aae4dfd609bcc700d4589d87e745a13606b4726 Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Fri, 15 May 2026 12:00:37 +0530 Subject: [PATCH 02/12] arch/tricore: switch Kconfig to family + chip selectors The arch code introduced in the following commits is organized by family: arch/tricore/src/tc3x and arch/tricore/src/tc4x hold the code shared across the TC3X and TC4X chip variants respectively. On AURIX all chips in a family share their ISA and peripherals, so the family-shared code is the bulk of the port. Restructure Kconfig to match: the user selects a family first (ARCH_CHIP_FAMILY_TC3X or ARCH_CHIP_FAMILY_TC4X) and then picks a chip inside it. The selectors then mirror the directory layout. Only the TC1.8 ISA has its own Kconfig symbol (TRICORE_TC18), which TC4X selects; TC3X runs as the !TRICORE_TC18 fallback in assembly. Co-Authored-By: Parthiban Nallathambi Signed-off-by: Saravanan Sekar --- .../platforms/tricore/tc3x/index.rst | 16 +++++ .../platforms/tricore/tc4x/index.rst | 17 +++++ arch/tricore/Kconfig | 63 +++++++++++++++---- arch/tricore/src/tc3x/Kconfig | 17 +++++ arch/tricore/src/tc4x/Kconfig | 17 +++++ 5 files changed, 119 insertions(+), 11 deletions(-) create mode 100644 Documentation/platforms/tricore/tc3x/index.rst create mode 100644 Documentation/platforms/tricore/tc4x/index.rst create mode 100644 arch/tricore/src/tc3x/Kconfig create mode 100644 arch/tricore/src/tc4x/Kconfig diff --git a/Documentation/platforms/tricore/tc3x/index.rst b/Documentation/platforms/tricore/tc3x/index.rst new file mode 100644 index 0000000000000..710ffee9b2d45 --- /dev/null +++ b/Documentation/platforms/tricore/tc3x/index.rst @@ -0,0 +1,16 @@ +========== +AURIX TC3X +========== + +NuttX support for the Infineon AURIX TC3X (TriCore TC1.6.2) family. + +The TC3X port covers SCU clock tree bring-up (PLL, CCU dividers, ENDINIT +password rotation), the IR/SRC interrupt routing, the System Timer (STM) +oneshot and ASCLIN-based UART. Boards select a particular TC3X variant +through ``CONFIG_TC3X_CHIP_*``. + +.. toctree:: + :maxdepth: 1 + :glob: + + */* diff --git a/Documentation/platforms/tricore/tc4x/index.rst b/Documentation/platforms/tricore/tc4x/index.rst new file mode 100644 index 0000000000000..efe15dd157701 --- /dev/null +++ b/Documentation/platforms/tricore/tc4x/index.rst @@ -0,0 +1,17 @@ +========== +AURIX TC4X +========== + +NuttX support for the Infineon AURIX TC4X (TriCore TC1.8) family. + +The TC4X port covers SCU clock tree bring-up (PLL, CCU dividers, +SafetyEndInit/CpuEndInit unlock), the IR/SRC interrupt routing +(SRPN equals the IRQ number), the System Timer (STM) oneshot and +ASCLIN-based UART. Boards select a particular TC4X variant through +``CONFIG_TC4X_CHIP_*``. + +.. toctree:: + :maxdepth: 1 + :glob: + + */* diff --git a/arch/tricore/Kconfig b/arch/tricore/Kconfig index a9beb4f81bfb3..bfe65093b7769 100644 --- a/arch/tricore/Kconfig +++ b/arch/tricore/Kconfig @@ -6,8 +6,16 @@ if ARCH_TRICORE comment "Tricore Options" -config ARCH_TC1V6 +config TRICORE_TC18 bool + default n + +choice + prompt "AURIX SoC Family" + default ARCH_CHIP_FAMILY_TC4X + +config ARCH_CHIP_FAMILY_TC3X + bool "AURIX Family TC3X" select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_PERF_EVENTS select ARCH_HAVE_POWEROFF @@ -15,10 +23,12 @@ config ARCH_TC1V6 select ARCH_HAVE_SETJMP select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET - default n + ---help--- + AURIX TC3X family (TriCore 1.6.2P). -config ARCH_TC1V8 - bool +config ARCH_CHIP_FAMILY_TC4X + bool "AURIX Family TC4X" + select TRICORE_TC18 select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_PERF_EVENTS select ARCH_HAVE_PERF_EVENTS_USER_ACCESS @@ -26,16 +36,47 @@ config ARCH_TC1V8 select ARCH_HAVE_SETJMP select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET - default n + ---help--- + AURIX TC4X family (TriCore 1.8P). + +endchoice + +config ARCH_CHIP + string + default "tc3x" if ARCH_CHIP_FAMILY_TC3X + default "tc4x" if ARCH_CHIP_FAMILY_TC4X config ARCH_FAMILY string - default "tc1v6" if ARCH_TC1V6 - default "tc1v8" if ARCH_TC1V8 + default "tc1v6" if ARCH_CHIP_FAMILY_TC3X + default "tc1v8" if ARCH_CHIP_FAMILY_TC4X + +choice + prompt "Tricore Toolchain Selection" + default TRICORE_TOOLCHAIN_GNUC + +config TRICORE_TOOLCHAIN_GNUC + bool "GNU GCC Toolchain" + select ARCH_TOOLCHAIN_GNU + ---help--- + Build with the AURIX GNU GCC toolchain (tricore-elf-gcc). + The toolchain binaries must be reachable on $PATH. + +config TRICORE_TOOLCHAIN_LLVM + bool "HighTec LLVM Toolchain" + ---help--- + Build with the HighTec LLVM/Clang toolchain (clang -target tricore). + The toolchain binaries must be reachable on $PATH and a valid + HighTec license must be reachable through $RLM_LICENSE. + +endchoice + +if ARCH_CHIP_FAMILY_TC3X +source "arch/tricore/src/tc3x/Kconfig" +endif -config CPU_COREID - int "TRICORE CPU CORE ID" - default 0 - range 0 6 +if ARCH_CHIP_FAMILY_TC4X +source "arch/tricore/src/tc4x/Kconfig" +endif endif # ARCH_TRICORE diff --git a/arch/tricore/src/tc3x/Kconfig b/arch/tricore/src/tc3x/Kconfig new file mode 100644 index 0000000000000..5f888349fa2b5 --- /dev/null +++ b/arch/tricore/src/tc3x/Kconfig @@ -0,0 +1,17 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "Infineon AURIX TC3X Chip" + +choice + prompt "Infineon AURIX TC3X Chip selection" + default TC3X_CHIP_TC375 + +config TC3X_CHIP_TC375 + bool "TC375 SoC" + ---help--- + Infineon AURIX TC375. + +endchoice diff --git a/arch/tricore/src/tc4x/Kconfig b/arch/tricore/src/tc4x/Kconfig new file mode 100644 index 0000000000000..f15917d3942c3 --- /dev/null +++ b/arch/tricore/src/tc4x/Kconfig @@ -0,0 +1,17 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "Infineon AURIX TC4X Chip" + +choice + prompt "Infineon AURIX TC4X Chip selection" + default TC4X_CHIP_TC4D7 + +config TC4X_CHIP_TC4D7 + bool "TC4D7 SoC" + ---help--- + Infineon AURIX TC4D7. + +endchoice From 47bab598ef1a9588d48a1724a0adc780f4b41f62 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Fri, 15 May 2026 12:00:53 +0530 Subject: [PATCH 03/12] arch/tricore: add GCC and HighTec LLVM toolchain support GCC and HighTec clang are the two toolchains that build the TriCore port today. GCC (tricore-elf-gcc, AURIX GCC) is the open toolchain published by Infineon. HighTec clang is the only LLVM build that currently targets TriCore and consumes a HighTec license at runtime. Wire each with a Kconfig selector and a matching dispatcher under Toolchain.defs and Toolchain.cmake so a board picks its toolchain once at configure time. The earlier Tasking dispatcher is removed in the same commit because the upstream port does not include a configuration that builds under Tasking. Co-Authored-By: Saravanan Sekar Signed-off-by: Parthiban Nallathambi --- arch/tricore/src/cmake/Toolchain.cmake | 6 +- arch/tricore/src/cmake/ToolchainGnuc.cmake | 8 +- arch/tricore/src/cmake/ToolchainLLVM.cmake | 115 +++++++++++++ arch/tricore/src/cmake/ToolchainTasking.cmake | 139 ---------------- arch/tricore/src/cmake/chip.cmake | 21 +++ arch/tricore/src/cmake/platform.cmake | 12 +- arch/tricore/src/common/Make.defs | 9 +- arch/tricore/src/common/Toolchain.defs | 17 +- arch/tricore/src/common/ToolchainLLVM.defs | 124 ++++++++++++++ arch/tricore/src/common/ToolchainTasking.defs | 155 ------------------ arch/tricore/src/{tc4xx => tc3x}/Make.defs | 4 +- .../src/{tc3xx => tc3x}/Toolchain.defs | 19 +-- arch/tricore/src/{tc3xx => tc4x}/Make.defs | 4 +- .../src/{tc4xx => tc4x}/Toolchain.defs | 21 +-- 14 files changed, 294 insertions(+), 360 deletions(-) create mode 100644 arch/tricore/src/cmake/ToolchainLLVM.cmake delete mode 100644 arch/tricore/src/cmake/ToolchainTasking.cmake create mode 100644 arch/tricore/src/common/ToolchainLLVM.defs delete mode 100644 arch/tricore/src/common/ToolchainTasking.defs rename arch/tricore/src/{tc4xx => tc3x}/Make.defs (95%) rename arch/tricore/src/{tc3xx => tc3x}/Toolchain.defs (64%) rename arch/tricore/src/{tc3xx => tc4x}/Make.defs (95%) rename arch/tricore/src/{tc4xx => tc4x}/Toolchain.defs (57%) diff --git a/arch/tricore/src/cmake/Toolchain.cmake b/arch/tricore/src/cmake/Toolchain.cmake index ad9195e5fc29f..f2a90d70e227e 100644 --- a/arch/tricore/src/cmake/Toolchain.cmake +++ b/arch/tricore/src/cmake/Toolchain.cmake @@ -22,9 +22,9 @@ # Toolchain -if(CONFIG_TRICORE_TOOLCHAIN_TASKING) - include(${CMAKE_CURRENT_LIST_DIR}/ToolchainTasking.cmake) -elseif(CONFIG_TRICORE_TOOLCHAIN_GNU) +if(CONFIG_TRICORE_TOOLCHAIN_LLVM) + include(${CMAKE_CURRENT_LIST_DIR}/ToolchainLLVM.cmake) +else() include(${CMAKE_CURRENT_LIST_DIR}/ToolchainGnuc.cmake) endif() diff --git a/arch/tricore/src/cmake/ToolchainGnuc.cmake b/arch/tricore/src/cmake/ToolchainGnuc.cmake index 627d9ba6e5c5c..9e0dc51e6e084 100644 --- a/arch/tricore/src/cmake/ToolchainGnuc.cmake +++ b/arch/tricore/src/cmake/ToolchainGnuc.cmake @@ -25,10 +25,10 @@ set(CMAKE_SYSTEM_NAME Generic) set(CMAKE_SYSTEM_VERSION 1) -if(CONFIG_ARCH_CHIP_TC3XX) - set(ARCH_SUBDIR tc3xx) -elseif(CONFIG_ARCH_CHIP_TC4XX) - set(ARCH_SUBDIR tc4xx) +if(CONFIG_ARCH_CHIP_FAMILY_TC3X) + set(ARCH_SUBDIR tc3x) +elseif(CONFIG_ARCH_CHIP_FAMILY_TC4X) + set(ARCH_SUBDIR tc4x) endif() include(${CMAKE_CURRENT_LIST_DIR}/chip.cmake) diff --git a/arch/tricore/src/cmake/ToolchainLLVM.cmake b/arch/tricore/src/cmake/ToolchainLLVM.cmake new file mode 100644 index 0000000000000..0261eafe01d8b --- /dev/null +++ b/arch/tricore/src/cmake/ToolchainLLVM.cmake @@ -0,0 +1,115 @@ +# ############################################################################## +# arch/tricore/src/cmake/ToolchainLLVM.cmake +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_VERSION 1) + +# CMake's compiler check links a test executable with linker flags it selects +# for the host's default ld. ld.lld rejects the GNU-ld-only +# --no-warn-rwx-segments option, so skip the link step entirely. + +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +if(CONFIG_ARCH_CHIP_FAMILY_TC3X) + set(ARCH_SUBDIR tc3x) +elseif(CONFIG_ARCH_CHIP_FAMILY_TC4X) + set(ARCH_SUBDIR tc4x) +endif() + +include(${CMAKE_CURRENT_LIST_DIR}/chip.cmake) + +set(CMAKE_ASM_COMPILER clang) +set(CMAKE_C_COMPILER clang) +set(CMAKE_CXX_COMPILER clang++) +set(CMAKE_STRIP llvm-strip --strip-unneeded) +set(CMAKE_OBJCOPY llvm-objcopy) +set(CMAKE_OBJDUMP llvm-objdump) + +set(CMAKE_LINKER clang) +set(CMAKE_LD clang) +set(CMAKE_AR llvm-ar) +set(CMAKE_NM llvm-nm) +set(CMAKE_RANLIB llvm-ranlib) + +set(CMAKE_C_ARCHIVE_CREATE " rcs ") +set(CMAKE_CXX_ARCHIVE_CREATE " rcs ") +set(CMAKE_ASM_ARCHIVE_CREATE " rcs ") + +add_compile_options(-fno-common) +add_compile_options(-Wall -Wshadow -Wundef) +add_compile_options(-Wno-unused-command-line-argument) +add_compile_options(-nostdlib) + +if(CONFIG_DEBUG_CUSTOMOPT) + add_compile_options(${CONFIG_DEBUG_OPTLEVEL}) +elseif(CONFIG_DEBUG_FULLOPT) + add_compile_options(-Os) +endif() + +if(NOT CONFIG_DEBUG_NOOPT) + add_compile_options(-fno-strict-aliasing) +endif() + +if(CONFIG_FRAME_POINTER) + add_compile_options(-fno-omit-frame-pointer -fno-optimize-sibling-calls) +else() + add_compile_options(-fomit-frame-pointer) +endif() + +if(CONFIG_DEBUG_OPT_UNUSED_SECTIONS) + add_link_options(-Wl,--gc-sections) + add_compile_options(-ffunction-sections -fdata-sections) +endif() + +if(CONFIG_DEBUG_LINK_WHOLE_ARCHIVE) + add_link_options(-Wl,--whole-archive) +endif() + +if(CONFIG_LTO_THIN) + add_compile_options(-flto=thin) +elseif(CONFIG_LTO_FULL) + add_compile_options(-flto) +endif() + +if(CONFIG_DEBUG_SYMBOLS) + add_compile_options(-g) +endif() + +add_compile_options(-Wno-attributes -Wno-unknown-pragmas + $<$:-Wstrict-prototypes>) + +if(CONFIG_CXX_STANDARD) + add_compile_options($<$:-std=${CONFIG_CXX_STANDARD}>) +endif() + +if(NOT CONFIG_LIBCXXTOOLCHAIN) + add_compile_options($<$:-nostdinc++>) +endif() + +if(NOT CONFIG_CXX_EXCEPTION) + add_compile_options($<$:-fno-exceptions> + $<$:-fcheck-new>) +endif() + +if(NOT CONFIG_CXX_RTTI) + add_compile_options($<$:-fno-rtti>) +endif() diff --git a/arch/tricore/src/cmake/ToolchainTasking.cmake b/arch/tricore/src/cmake/ToolchainTasking.cmake deleted file mode 100644 index 62f2cc24b6d46..0000000000000 --- a/arch/tricore/src/cmake/ToolchainTasking.cmake +++ /dev/null @@ -1,139 +0,0 @@ -# ############################################################################## -# arch/tricore/src/cmake/ToolchainTasking.cmake -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -# Toolchain - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_SYSTEM_VERSION 1) - -if(CONFIG_ARCH_CHIP_TC3XX) - set(ARCH_SUBDIR tc3xx) -elseif(CONFIG_ARCH_CHIP_TC4XX) - set(ARCH_SUBDIR tc4xx) -endif() - -include(chip.cmake) - -set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PREFIX}cctc) -set(CMAKE_C_COMPILER ${CMAKE_ASM_COMPILER}) -set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}cctc) -set(CMAKE_STRIP strip --strip-unneeded) -set(CMAKE_OBJCOPY echo) -set(CMAKE_OBJDUMP ${TOOLCHAIN_PREFIX}elfdump) - -set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}cctc) -set(CMAKE_LD ${TOOLCHAIN_PREFIX}cctc) -set(CMAKE_AR ${TOOLCHAIN_PREFIX}artc -r) -set(CMAKE_NM nm) -set(CMAKE_RANLIB ranlib) - -# override the ARCHIVE command - -set(CMAKE_C_ARCHIVE_CREATE " rcs ") -set(CMAKE_CXX_ARCHIVE_CREATE " rcs ") -set(CMAKE_ASM_ARCHIVE_CREATE " rcs ") - -# Architecture flags - -add_compile_options(--lsl-core=vtc) -add_compile_options(--iso=99) -add_compile_options(--language=+gcc,+volatile,-strings,-kanji) - -if(CONFIG_DEBUG_CUSTOMOPT) - add_compile_options(${CONFIG_DEBUG_OPTLEVEL}) -elseif(CONFIG_DEBUG_FULLOPT) - add_compile_options(-Os) -endif() - -# pragma align <4> (default: 0) - -add_compile_options(--align=4) - -# Always use 32-bit integers for enumeration - -add_compile_options(--integer-enumeration) - -# tradeoff between speed (-t0) and size (-t4) (default: 4) - -add_compile_options(--tradeoff=2) - -# enable symbolic debug information - -if(CONFIG_DEBUG_SYMBOLS) - add_compile_options(--debug-info=default) - add_compile_options(--keep-temporary-files) - add_compile_options(${CONFIG_DEBUG_SYMBOLS_LEVEL}) -endif() - -# merge source code with assembly output - -add_compile_options(--source) - -# generate alignment depending on assume_if hints - -add_compile_options(--branch-target-align) - -# cmake-format: off -# Since nuttx uses too many of GNU extensions in the implementation of -# FPU-related library functions, which is not supported in tasking, so currently -# we cannot use FPU-related configurations to manage it. -# -# Just set fp-model to Double Precision: -# --fp-model[=,...] floating-point model (default: cFlnrSTz) -# 0 alias for --fp-model=CFLNRStZ (strict) -# 1 alias for --fp-model=cFLNRSTZ (precise) -# 2 alias for --fp-model=cFlnrSTz (fast-dp) -# 3 alias for --fp-model=cflnrSTz (fast-sp) -# cmake-format: on - -add_compile_options(--fp-model=2) -add_link_options(--no-default-libraries) -add_link_options(--fp-model=2) -add_link_options(-lfp_fpu) - -add_link_options(--hex-format=s -Wl-OtxYcL -Wl-mcrfiklsmnoduq) -add_link_options(-lrt) - -# cmake-format: off -# ctc W500: ["stdio/lib_libvsprintf.c" 884/29] expression without effect -# ctc W507: ["mm_heap/mm_malloc.c" 238/64] variable "nodesize" is possibly uninitialized -# ctc W508: ["misc/lib_impure.c" 1/1] empty source file -# ctc W525: ["getopt.c" 678/3] discarded 'const' qualifier at assignment: conversion from char const * to char * -# ctc W527: ["stdlib/lib_strtold.c" 565/23] constant of type "double" saturated -# ctc W526: ["include/sys/epoll.h" 87/5] enumeration constant shall be representable as 'int' -# ctc W529: ["wchar/lib_mbrtowc.c" 88/35] overflow in constant expression of type "unsigned long int" -# ctc W544: ["wqueue/kwork_thread.c" 210/32] unreachable code -# ctc W549: ["unistd/lib_getopt_common.c" 544/15] condition is always true -# ctc W553: ["vfs/fs_fcntl.c" 231/7] no 'break' or comment before case label -# ctc W557: ["common/tricore_main.c" 58/11] possible infinite loop -# ctc W560: ["tmpfs/fs_tmpfs.c" 232/25] possible truncation at implicit conversion to type "unsigned short int" -# ctc W562: ["mm_heap/mm_memalign.c" 70/20] unary minus applied to unsigned value -# ctc W558: ["include/nuttx/power/regulator.h" 224/36] struct/union/enum definition in parameter declaration -# ctc W587: ["stdlib/lib_strtold.c" 571/23] underflow on constant of type "double" -# ctc W588: ["misc/lib_glob.c" 150/13] dead assignment to "i" eliminated -# ctc W589: ["inode/fs_inodesearch.c" 72/8] pointer assumed to be nonzero - test removed -# cmake-format: on - -set(TASKING_WARNINGS - 500,507,508,525,526,527,529,544,549,553,560,562,557,558,587,588,589) - -add_compile_options(--pass-c=--no-warnings=${TASKING_WARNINGS}) diff --git a/arch/tricore/src/cmake/chip.cmake b/arch/tricore/src/cmake/chip.cmake index 79cd5f0c4028e..d72250994192e 100644 --- a/arch/tricore/src/cmake/chip.cmake +++ b/arch/tricore/src/cmake/chip.cmake @@ -19,3 +19,24 @@ # the License. # # ############################################################################## + +set(PLATFORM_FLAGS) + +if(CONFIG_ARCH_CHIP_FAMILY_TC3X) + if(CONFIG_TRICORE_TOOLCHAIN_LLVM) + list(APPEND PLATFORM_FLAGS -march=tc162 -mcpu=tc3xx) + list(APPEND PLATFORM_FLAGS -Wno-error=implicit-function-declaration) + else() + list(APPEND PLATFORM_FLAGS -mtc162) + endif() +elseif(CONFIG_ARCH_CHIP_FAMILY_TC4X) + if(CONFIG_TRICORE_TOOLCHAIN_LLVM) + list(APPEND PLATFORM_FLAGS -march=tc18 -mcpu=tc4xx) + list(APPEND PLATFORM_FLAGS -Wno-error=implicit-function-declaration) + else() + list(APPEND PLATFORM_FLAGS -mtc18) + endif() +endif() + +add_compile_options(${PLATFORM_FLAGS}) +add_link_options(${PLATFORM_FLAGS}) diff --git a/arch/tricore/src/cmake/platform.cmake b/arch/tricore/src/cmake/platform.cmake index 42b9204485359..dc58e1e52bf2f 100644 --- a/arch/tricore/src/cmake/platform.cmake +++ b/arch/tricore/src/cmake/platform.cmake @@ -39,7 +39,7 @@ endforeach() separate_arguments(CMAKE_C_FLAG_ARGS NATIVE_COMMAND ${CMAKE_C_FLAGS}) -if(CONFIG_TRICORE_TOOLCHAIN_GNU) +if(CONFIG_TRICORE_TOOLCHAIN_GNUC) nuttx_find_toolchain_lib() if(CONFIG_LIBM_TOOLCHAIN) nuttx_find_toolchain_lib(libm.a) @@ -56,14 +56,6 @@ if(CONFIG_TRICORE_TOOLCHAIN_GNU) if(CONFIG_COVERAGE_TOOLCHAIN) nuttx_find_toolchain_lib(libgcov.a) endif() - - set(PREPROCESS ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} -E -P -x c) endif() -if(CONFIG_TRICORE_TOOLCHAIN_TASKING) - find_program(TASKING_COMPILER_PATH ctc) - get_filename_component(C_COMPILER_DIR ${TASKING_COMPILER_PATH} DIRECTORY) - set(PREPROCESS - ${TOOLCHAIN_PREFIX}ctc ${CMAKE_C_FLAG_ARGS} -E - -I${TOOLCHAIN_PREFIX}/../include.lsl -I${C_COMPILER_DIR}/../include.lsl) -endif() +set(PREPROCESS ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} -E -P -x c) diff --git a/arch/tricore/src/common/Make.defs b/arch/tricore/src/common/Make.defs index 0b961757673ba..0dc13a047ad51 100644 --- a/arch/tricore/src/common/Make.defs +++ b/arch/tricore/src/common/Make.defs @@ -37,19 +37,14 @@ CMN_CSRCS += tricore_nputs.c CMN_CSRCS += tricore_registerdump.c CMN_CSRCS += tricore_releasestack.c CMN_CSRCS += tricore_saveusercontext.c +CMN_CSRCS += tricore_schedulesigaction.c +CMN_CSRCS += tricore_sigdeliver.c CMN_CSRCS += tricore_stackframe.c CMN_CSRCS += tricore_svcall.c CMN_CSRCS += tricore_tcbinfo.c CMN_CSRCS += tricore_trapcall.c CMN_CSRCS += tricore_usestack.c -ifeq ($(CONFIG_ENABLE_ALL_SIGNALS),y) -CMN_CSRCS += tricore_schedulesigaction.c tricore_sigdeliver.c -endif - ifeq ($(CONFIG_SPINLOCK),y) CMN_CSRCS += tricore_testset.c endif - -CFLAGS += -DIFX_CFG_EXTEND_TRAP_HOOKS -CFLAGS += -DIFX_USE_SW_MANAGED_INT diff --git a/arch/tricore/src/common/Toolchain.defs b/arch/tricore/src/common/Toolchain.defs index b58f486284b25..92cecfa19c502 100644 --- a/arch/tricore/src/common/Toolchain.defs +++ b/arch/tricore/src/common/Toolchain.defs @@ -20,17 +20,14 @@ # ############################################################################ -ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - include $(TOPDIR)/arch/tricore/src/common/ToolchainTasking.defs +ifeq ($(CONFIG_TRICORE_TOOLCHAIN_LLVM),y) + include $(TOPDIR)/arch/tricore/src/common/ToolchainLLVM.defs else include $(TOPDIR)/arch/tricore/src/common/ToolchainGnuc.defs endif -ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - undefine PREPROCESS - define PREPROCESS - $(ECHO_BEGIN)"CPP: $1->$2 " - $(CPP) $(CPPFLAGS) $1 > $2 - $(ECHO_END) - endef -endif \ No newline at end of file +# Shared AURIX peripheral headers (asclin, gpio, ...) live under +# arch/tricore/src/aurix. Expose them to board sources via ARCHINCLUDES +# so that boards/Board.mk-driven compiles can find them. + +ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)aurix diff --git a/arch/tricore/src/common/ToolchainLLVM.defs b/arch/tricore/src/common/ToolchainLLVM.defs new file mode 100644 index 0000000000000..e12b89d319ada --- /dev/null +++ b/arch/tricore/src/common/ToolchainLLVM.defs @@ -0,0 +1,124 @@ +############################################################################ +# arch/tricore/src/common/ToolchainLLVM.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL) +else ifeq ($(CONFIG_DEBUG_FULLOPT),y) + ARCHOPTIMIZATION += -Os +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += -fno-strict-aliasing +endif + +ifeq ($(CONFIG_FRAME_POINTER),y) + ARCHOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls +else + ARCHOPTIMIZATION += -fomit-frame-pointer +endif + +ifeq ($(CONFIG_STACK_CANARIES),y) + ARCHOPTIMIZATION += $(patsubst "%",%,$(CONFIG_STACK_CANARIES_LEVEL)) +endif + +ifeq ($(CONFIG_STACK_USAGE),y) + ARCHOPTIMIZATION += -fstack-usage +endif + +ifneq ($(CONFIG_STACK_USAGE_WARNING),0) + ARCHOPTIMIZATION += -Wstack-usage=$(CONFIG_STACK_USAGE_WARNING) +endif + +ifeq ($(CONFIG_LTO_THIN),y) + ARCHOPTIMIZATION += -flto=thin +else ifeq ($(CONFIG_LTO_FULL),y) + ARCHOPTIMIZATION += -flto +endif + +CC = $(CROSSDEV)clang +CXX = $(CROSSDEV)clang++ +CPP = $(CROSSDEV)clang -E -P -x c +LD = $(CROSSDEV)clang +STRIP = $(CROSSDEV)llvm-strip --strip-unneeded +AR = $(CROSSDEV)llvm-ar rcs +UNAR = $(CROSSDEV)llvm-ar x +NM = $(CROSSDEV)llvm-nm +OBJCOPY = $(CROSSDEV)llvm-objcopy +OBJDUMP = $(CROSSDEV)llvm-objdump +RANLIB = $(CROSSDEV)llvm-ranlib + +ARCHOPTIMIZATION += -fno-builtin +ARCHOPTIMIZATION += -fno-common -Wall -Wshadow -Wundef + +ARCHCFLAGS += -Wstrict-prototypes -Wno-attributes -Wno-unknown-pragmas +ARCHCFLAGS += -Wno-unused-command-line-argument +ARCHCXXFLAGS += -Wno-attributes -Wno-unknown-pragmas +ARCHCXXFLAGS += -Wno-unused-command-line-argument + +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + +ifneq ($(CONFIG_CXX_STANDARD),) + ARCHCXXFLAGS += -std=$(CONFIG_CXX_STANDARD) +endif + +ifneq ($(CONFIG_CXX_EXCEPTION),y) + ARCHCXXFLAGS += -fno-exceptions -fcheck-new +endif + +ifneq ($(CONFIG_CXX_RTTI),y) + ARCHCXXFLAGS += -fno-rtti +endif + +LDFLAGS += -nostdlib + +ifeq ($(CONFIG_DEBUG_OPT_UNUSED_SECTIONS),y) + LDFLAGS += --gc-sections + ARCHOPTIMIZATION += -ffunction-sections -fdata-sections +endif + +ifeq ($(CONFIG_DEBUG_LINK_WHOLE_ARCHIVE),y) + LDFLAGS += --whole-archive +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION += $(CONFIG_DEBUG_SYMBOLS_LEVEL) +endif + +COMPILER_RT_LIB = $(shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name) + +ifneq ($(COMPILER_RT_LIB),) + EXTRA_LIBS += $(COMPILER_RT_LIB) +endif + +ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) + EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) +endif + +ifeq ($(CONFIG_LIBSUPCXX),y) + EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) +endif + +ifeq ($(CONFIG_LIBCXXTOOLCHAIN),y) + EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libc++.a)) +endif diff --git a/arch/tricore/src/common/ToolchainTasking.defs b/arch/tricore/src/common/ToolchainTasking.defs deleted file mode 100644 index 9ea13cc3ca17f..0000000000000 --- a/arch/tricore/src/common/ToolchainTasking.defs +++ /dev/null @@ -1,155 +0,0 @@ -############################################################################ -# arch/tricore/src/common/ToolchainTasking.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -# -# Supported toolchains -# -# Each toolchain definition should set: -# -# CROSSDEV The GNU toolchain triple (command prefix) -# ARCHCPUFLAGS CPU-specific flags selecting the instruction set -# FPU options, etc. -# ARCHOPTIMIZATION The optimization level that results in -# reliable code generation. -# - -ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) - ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL) -else ifeq ($(CONFIG_DEBUG_FULLOPT),y) - ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) - ARCHOPTIMIZATION += -Oz - else - ARCHOPTIMIZATION += -Os - endif -endif - -# Tasking toolchain - -TASKING_COMPILER_PATH := $(shell which ctc) -C_COMPILER_DIR := $(dir $(TASKING_COMPILER_PATH)) - -CC = cctc -CXX = cctc -CPP = ctc -E -I$(C_COMPILER_DIR)/../include.lsl -LD = cctc -STRIP = strip --strip-unneeded -AR = artc -r -UNAR = artc -x -NM = nm -OBJCOPY = echo -OBJDUMP = elfdump - -ARCHOPTIMIZATION += --lsl-core=vtc -LDFLAGS += --lsl-core=vtc -ARCHOPTIMIZATION += --iso=99 -ARCHOPTIMIZATION += --language=+gcc,+volatile,-strings,-kanji - -# pragma align <4> (default: 0) - -ARCHOPTIMIZATION += --align=4 - -# Always use 32-bit integers for enumeration - -ARCHOPTIMIZATION += --integer-enumeration - -# tradeoff between speed (-t0) and size (-t4) (default: 4) - -ARCHOPTIMIZATION += --tradeoff=2 - -# enable symbolic debug information - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION += --debug-info=default - ARCHOPTIMIZATION += --keep-temporary-files - ARCHOPTIMIZATION += $(CONFIG_DEBUG_SYMBOLS_LEVEL) -endif - -# merge source code with assembly output - -ARCHOPTIMIZATION += --source - -# generate alignment depending on assume_if hints - -ARCHOPTIMIZATION += --branch-target-align - - -# Since nuttx uses too many of GNU extensions in the implementation of -# FPU-related library functions, which is not supported in tasking, -# so currently we cannot use FPU-related configurations to manage it. -# -# Just set fp-model to Double Precision: -# --fp-model[=,...] floating-point model (default: cFlnrSTz) -# 0 alias for --fp-model=CFLNRStZ (strict) -# 1 alias for --fp-model=cFLNRSTZ (precise) -# 2 alias for --fp-model=cFlnrSTz (fast-dp) -# 3 alias for --fp-model=cflnrSTz (fast-sp) - -ARCHOPTIMIZATION += --fp-model=2 -LDFLAGS += --no-default-libraries -LDFLAGS += --fp-model=2 -LDFLAGS += -lfp_fpu - -LDFLAGS += -Wl-OtxYcL -Wl-mcrfiklsmnoduq -LDFLAGS += -lrt - -ifeq ($(CONFIG_INTELHEX_BINARY),y) - LDFLAGS += -Wl-o${TOPDIR}/nuttx.hex:IHEX:4 --hex-format=s -endif - -ifeq ($(CONFIG_MOTOROLA_SREC),y) - LDFLAGS += -Wl-o${TOPDIR}/nuttx.srec:SREC:4 -endif - -# ctc W500: ["stdio/lib_libvsprintf.c" 884/29] expression without effect -# ctc W507: ["mm_heap/mm_malloc.c" 238/64] variable "nodesize" is possibly uninitialized -# ctc W508: ["misc/lib_impure.c" 1/1] empty source file -# ctc W525: ["getopt.c" 678/3] discarded 'const' qualifier at assignment: conversion from char const * to char * -# ctc W527: ["stdlib/lib_strtold.c" 565/23] constant of type "double" saturated -# ctc W526: ["include/sys/epoll.h" 87/5] enumeration constant shall be representable as 'int' -# ctc W529: ["wchar/lib_mbrtowc.c" 88/35] overflow in constant expression of type "unsigned long int" -# ctc W544: ["wqueue/kwork_thread.c" 210/32] unreachable code -# ctc W549: ["unistd/lib_getopt_common.c" 544/15] condition is always true -# ctc W553: ["vfs/fs_fcntl.c" 231/7] no 'break' or comment before case label -# ctc W557: ["common/tricore_main.c" 58/11] possible infinite loop -# ctc W560: ["tmpfs/fs_tmpfs.c" 232/25] possible truncation at implicit conversion to type "unsigned short int" -# ctc W562: ["mm_heap/mm_memalign.c" 70/20] unary minus applied to unsigned value -# ctc W558: ["include/nuttx/power/regulator.h" 224/36] struct/union/enum definition in parameter declaration -# ctc W587: ["stdlib/lib_strtold.c" 571/23] underflow on constant of type "double" -# ctc W588: ["misc/lib_glob.c" 150/13] dead assignment to "i" eliminated -# ctc W589: ["inode/fs_inodesearch.c" 72/8] pointer assumed to be nonzero - test removed - -TASKING_WARNINGS = 500,507,508,525,526,527,529,544,549,553,560,562,557,558,587,588,589 - -ARCHOPTIMIZATION += --pass-c=--no-warnings=$(TASKING_WARNINGS) - -# Loadable module definitions - -CMODULEFLAGS = $(CFLAGS) -fvisibility=hidden -LDMODULEFLAGS = -r -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/elf/gnu-elf.ld) - -# ELF module definitions - -CELFFLAGS = $(CFLAGS) -fvisibility=hidden -CXXELFFLAGS = $(CXXFLAGS) -fvisibility=hidden - -LDELFFLAGS = -r -e _start -LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)libs$(DELIM)libc$(DELIM)elf$(DELIM)gnu-elf.ld) diff --git a/arch/tricore/src/tc4xx/Make.defs b/arch/tricore/src/tc3x/Make.defs similarity index 95% rename from arch/tricore/src/tc4xx/Make.defs rename to arch/tricore/src/tc3x/Make.defs index 2363894a66b6f..25bc0b9430028 100644 --- a/arch/tricore/src/tc4xx/Make.defs +++ b/arch/tricore/src/tc3x/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/tricore/src/tc4xx/Make.defs +# arch/tricore/src/tc3x/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -20,4 +20,4 @@ # ############################################################################ -VPATH += tc4xx +VPATH += tc3x diff --git a/arch/tricore/src/tc3xx/Toolchain.defs b/arch/tricore/src/tc3x/Toolchain.defs similarity index 64% rename from arch/tricore/src/tc3xx/Toolchain.defs rename to arch/tricore/src/tc3x/Toolchain.defs index ee16fc33bdf08..09ffd4cab64d3 100644 --- a/arch/tricore/src/tc3xx/Toolchain.defs +++ b/arch/tricore/src/tc3x/Toolchain.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/tricore/src/tc3xx/Toolchain.defs +# arch/tricore/src/tc3x/Toolchain.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -20,18 +20,11 @@ # ############################################################################ -ifeq ($(CONFIG_ARCH_CHIP_TC397),y) - ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - ARCHCPUFLAGS += --cpu=tc39xb - LDFLAGS += -Ctc39xb - else - ARCHCPUFLAGS += -mcpu=tc39xx - ARCHCPUFLAGS += -mtc162 - endif - - ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Std - ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Platform - ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc3xx/Configurations +ifeq ($(CONFIG_TRICORE_TOOLCHAIN_LLVM),y) +ARCHCPUFLAGS += -march=tc162 -mcpu=tc3xx +ARCHCPUFLAGS += -Wno-error=implicit-function-declaration +else +ARCHCPUFLAGS += -mtc162 endif include $(TOPDIR)/arch/tricore/src/common/Toolchain.defs diff --git a/arch/tricore/src/tc3xx/Make.defs b/arch/tricore/src/tc4x/Make.defs similarity index 95% rename from arch/tricore/src/tc3xx/Make.defs rename to arch/tricore/src/tc4x/Make.defs index 1671f0458f852..8f2fb7a97aaa0 100644 --- a/arch/tricore/src/tc3xx/Make.defs +++ b/arch/tricore/src/tc4x/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/tricore/src/tc3xx/Make.defs +# arch/tricore/src/tc4x/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -20,4 +20,4 @@ # ############################################################################ -VPATH += tc3xx +VPATH += tc4x diff --git a/arch/tricore/src/tc4xx/Toolchain.defs b/arch/tricore/src/tc4x/Toolchain.defs similarity index 57% rename from arch/tricore/src/tc4xx/Toolchain.defs rename to arch/tricore/src/tc4x/Toolchain.defs index 9eff515a24377..65fde836ccb53 100644 --- a/arch/tricore/src/tc4xx/Toolchain.defs +++ b/arch/tricore/src/tc4x/Toolchain.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/tricore/src/tc4xx/Toolchain.defs +# arch/tricore/src/tc4x/Toolchain.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -20,20 +20,11 @@ # ############################################################################ -ifeq ($(CONFIG_ARCH_CHIP_TC4XX),y) - ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - ARCHCPUFLAGS += --misrac-version=2004 --user-mode=hypervisor - ARCHCPUFLAGS += --default-near-size=0 - LDFLAGS += -Ctc4dx - else - ARCHCPUFLAGS += -mcpu=tc4DAx - ARCHCPUFLAGS += -mtc18 -endif - - ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/iLLD/TC4xx/Tricore/Cpu/Std - ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Platform - ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Platform/Compilers - ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Configurations +ifeq ($(CONFIG_TRICORE_TOOLCHAIN_LLVM),y) +ARCHCPUFLAGS += -march=tc18 -mcpu=tc4xx +ARCHCPUFLAGS += -Wno-error=implicit-function-declaration +else +ARCHCPUFLAGS += -mtc18 endif include $(TOPDIR)/arch/tricore/src/common/Toolchain.defs From 2de45536eee4bc4b60383489c13e341640a472e5 Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Fri, 15 May 2026 12:01:41 +0530 Subject: [PATCH 04/12] arch/tricore: add TriCore architecture support Add TriCore architecture port supporting the TC1.6P core (AURIX TC3X family) and the TC1.8P core (AURIX TC4X family) from Infineon. Includes reset vector, context switching using TriCore upper and lower context save areas (CSA), interrupt management with the BIV vector table, trap and exception handling with the BTV vector table, syscall interface, and linker scripts for both GCC and HighTec clang. The TC3X and TC4X families share the same trap and interrupt model, so the core paths sit under arch/tricore/src/common and serve both families. Watchdog disable diverges between the families (ENDINIT password rotation on TC3X, CCU on TC4X) and lives in small per-family helpers under tc3x/ and tc4x/. Co-Authored-By: Parthiban Nallathambi Signed-off-by: Saravanan Sekar --- arch/tricore/include/arch.h | 134 ++++- arch/tricore/include/barriers.h | 17 +- arch/tricore/include/inttypes.h | 18 +- arch/tricore/include/irq.h | 242 +++------ arch/tricore/include/limits.h | 1 - arch/tricore/include/syscall.h | 167 +------ arch/tricore/include/tc3x/irq.h | 38 ++ arch/tricore/include/tc4x/irq.h | 45 ++ arch/tricore/src/common/CMakeLists.txt | 20 +- arch/tricore/src/common/Make.defs | 7 + arch/tricore/src/common/tricore-llvm.ld | 147 ++++++ arch/tricore/src/common/tricore.ld | 150 ++++++ .../tricore/src/common/tricore_allocateheap.c | 9 +- arch/tricore/src/common/tricore_backtrace.c | 32 +- arch/tricore/src/common/tricore_checkstack.c | 18 +- arch/tricore/src/common/tricore_compiler.c | 55 +++ arch/tricore/src/common/tricore_createstack.c | 88 +--- arch/tricore/src/common/tricore_csa.c | 32 +- arch/tricore/src/common/tricore_doirq.c | 56 ++- arch/tricore/src/common/tricore_exit.c | 12 +- arch/tricore/src/common/tricore_getintstack.c | 2 +- arch/tricore/src/common/tricore_head.S | 211 ++++++++ arch/tricore/src/common/tricore_idle.c | 27 +- arch/tricore/src/common/tricore_initialize.c | 70 ++- .../tricore/src/common/tricore_initialstate.c | 3 +- arch/tricore/src/common/tricore_internal.h | 152 ++---- arch/tricore/src/common/tricore_interrupt.S | 55 +++ arch/tricore/src/common/tricore_irq.c | 264 ++-------- arch/tricore/src/common/tricore_irq.h | 119 +++++ arch/tricore/src/common/tricore_lib.S | 174 +++++++ arch/tricore/src/common/tricore_nputs.c | 6 + .../tricore/src/common/tricore_registerdump.c | 137 ++---- .../tricore/src/common/tricore_releasestack.c | 2 +- .../src/common/tricore_saveusercontext.c | 35 +- .../src/common/tricore_schedulesigaction.c | 82 +++- arch/tricore/src/common/tricore_sigdeliver.c | 6 +- arch/tricore/src/common/tricore_stackframe.c | 4 +- arch/tricore/src/common/tricore_svcall.c | 78 +-- .../src/common/tricore_switchcontext.c | 33 +- arch/tricore/src/common/tricore_testset.c | 21 +- arch/tricore/src/common/tricore_trap.S | 67 +++ arch/tricore/src/common/tricore_trapcall.c | 460 +++++------------- arch/tricore/src/common/tricore_usestack.c | 20 +- arch/tricore/src/tc3x/Make.defs | 2 + arch/tricore/src/tc3x/tc3x_watchdog.c | 128 +++++ arch/tricore/src/tc4x/Make.defs | 2 + arch/tricore/src/tc4x/tc4x_watchdog.c | 92 ++++ 47 files changed, 2080 insertions(+), 1460 deletions(-) create mode 100644 arch/tricore/include/tc3x/irq.h create mode 100644 arch/tricore/include/tc4x/irq.h create mode 100644 arch/tricore/src/common/tricore-llvm.ld create mode 100644 arch/tricore/src/common/tricore.ld create mode 100644 arch/tricore/src/common/tricore_compiler.c create mode 100644 arch/tricore/src/common/tricore_head.S create mode 100644 arch/tricore/src/common/tricore_interrupt.S create mode 100644 arch/tricore/src/common/tricore_irq.h create mode 100644 arch/tricore/src/common/tricore_lib.S create mode 100644 arch/tricore/src/common/tricore_trap.S create mode 100644 arch/tricore/src/tc3x/tc3x_watchdog.c create mode 100644 arch/tricore/src/tc4x/tc4x_watchdog.c diff --git a/arch/tricore/include/arch.h b/arch/tricore/include/arch.h index 8d022db95656b..3e2488271a260 100644 --- a/arch/tricore/include/arch.h +++ b/arch/tricore/include/arch.h @@ -20,10 +20,6 @@ * ****************************************************************************/ -/* This file should never be included directly but, rather, - * only indirectly through nuttx/arch.h - */ - #ifndef __ARCH_TRICORE_INCLUDE_ARCH_H #define __ARCH_TRICORE_INCLUDE_ARCH_H @@ -42,13 +38,131 @@ * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Public Types - ****************************************************************************/ +#define TRICORE_CPU_VCON0 0xb000 +#define TRICORE_CPU_PCXI 0xfe00 +#define TRICORE_CPU_PSW 0xfe04 +#define TRICORE_CPU_CORE_ID 0xfe1c +#define TRICORE_CPU_BIV 0xfe20 +#define TRICORE_CPU_BTV 0xfe24 +#define TRICORE_CPU_ISP 0xfe28 +#define TRICORE_CPU_FCX 0xfe38 +#define TRICORE_CPU_LCX 0xfe3c -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ +#define TRICORE_CFG_SSW_PSW_DEFAULT 0x980 +#define TRICORE_CPU_CORE_ID_MASK GENMASK(2, 0) + +/* Upper CSA */ + +#define REG_UPCXI 0 +#define REG_PSW 1 +#define REG_A10 2 +#define REG_UA11 3 +#define REG_D8 4 +#define REG_D9 5 +#define REG_D10 6 +#define REG_D11 7 +#define REG_A12 8 +#define REG_A13 9 +#define REG_A14 10 +#define REG_A15 11 +#define REG_D12 12 +#define REG_D13 13 +#define REG_D14 14 +#define REG_D15 15 + +/* Lower CSA */ + +#define REG_LPCXI 0 +#define REG_LA11 1 +#define REG_A2 2 +#define REG_A3 3 +#define REG_D0 4 +#define REG_D1 5 +#define REG_D2 6 +#define REG_D3 7 +#define REG_A4 8 +#define REG_A5 9 +#define REG_A6 10 +#define REG_A7 11 +#define REG_D4 12 +#define REG_D5 13 +#define REG_D6 14 +#define REG_D7 15 + +#define REG_RA REG_UA11 +#define REG_SP REG_A10 +#define REG_UPC REG_UA11 +#define REG_PC REG_UA11 + +#define REG_LPC REG_LA11 + +#define TC_CONTEXT_REGS (16) + +#define XCPTCONTEXT_REGS (TC_CONTEXT_REGS) +#define XCPTCONTEXT_SIZE (sizeof(void *) * TC_CONTEXT_REGS) + +/* PSW: Program Status Word Register */ + +#define PSW_CDE (1 << 7) /* Bits 7: Call Depth Count Enable */ +#define PSW_IS (1 << 9) /* Bits 9: Interrupt Stack Control */ +#define PSW_IO (10) /* Bits 10-11: Access Privilege Level Control (I/O Privilege) */ +# define PSW_IO_USER0 (0 << PSW_IO) +# define PSW_IO_USER1 (1 << PSW_IO) +# define PSW_IO_SUPERVISOR (2 << PSW_IO) + +/* PCXI: Previous Context Information and Pointer Register */ + +#define PCXI_UL (1 << 20) /* Bits 20: Upper or Lower Context Tag */ +#define PCXI_PIE (1 << 21) /* Bits 21: Previous Interrupt Enable */ + +/* FCX: Free CSA List Head Pointer Register */ + +#define FCX_FCXO (0) /* Bits 0-15: FCX Offset Address */ +#define FCX_FCXS (16) /* Bits 16-19: FCX Segment Address */ +#define FCX_FCXO_MASK (0xffff << FCX_FCXO) +#define FCX_FCXS_MASK (0xf << FCX_FCXS) +#define FCX_FREE (FCX_FCXS_MASK | FCX_FCXO_MASK) /* Free CSA manipulation */ + +/* Address <--> Context Save Areas */ + +#define tricore_csa2addr(csa) ((uintptr_t *)((((csa) & 0x000f0000) << 12) \ + | (((csa) & 0x0000ffff) << 6))) +#define tricore_addr2csa(addr) ((uintptr_t)(((((uintptr_t)(addr)) & 0xf0000000) >> 12) \ + | (((uintptr_t)(addr) & 0x003fffc0) >> 6))) + +#ifndef __ASSEMBLY__ +struct xcptcontext +{ + uintptr_t *saved_regs; + uintptr_t *regs; +}; +#endif /* __ASSEMBLY__ */ + +#define TRICORE_CFG_SSW_CSA_BOOT_PTR_START (0x7010ec00) +#define TRICORE_CFG_SSW_CSA_USTACK_PTR (0x7010eb00) +#define TRICORE_CFG_DSPR0_START (0x70000000) + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) +# define TRICORE_IR_LASR_ADDR (0xf4430c20) +# define TRICORE_IR_LASR_TOS_STRIDE (0x34) +# define TRICORE_IR_LASR_PIPN_WIDTH (11) +#elif defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) + /* TC3x INT_CHx_LASR: 0xf0037204 + CH_index * 0x10. */ + +# define TRICORE_IR_LASR_ADDR (0xf0037204) +# define TRICORE_IR_LASR_TOS_STRIDE (0x10) +# define TRICORE_IR_LASR_PIPN_WIDTH (10) +#endif + +#ifndef __ASSEMBLY__ +#define TRICORE_MTCR(reg, val) { __asm__ __volatile__ ("dsync" : : : "memory"); \ + __asm__ __volatile__ ("mtcr %0,%1"::"i"(reg),"d"(val): "memory"); \ + __asm__ __volatile__ ("isync" : : : "memory");} + +#define TRICORE_MFCR(reg, val) {__asm__ __volatile__ ("mfcr %0,%1": "=d"(val) :"i"(reg): "memory");} +#define TRICORE_IRQ_ENABLE() { __asm__ __volatile__ ("enable" : : : "memory"); } +#define TRICORE_IRQ_DISABLE() { __asm__ __volatile__ ("disable" : : : "memory"); } +#endif /* __ASSEMBLY__ */ #ifdef __cplusplus #define EXTERN extern "C" diff --git a/arch/tricore/include/barriers.h b/arch/tricore/include/barriers.h index b50bc7f464aaa..95438172ce26a 100644 --- a/arch/tricore/include/barriers.h +++ b/arch/tricore/include/barriers.h @@ -1,6 +1,8 @@ /**************************************************************************** * arch/tricore/include/barriers.h * + * SPDX-License-Identifier: Apache-2.0 + * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The @@ -19,13 +21,18 @@ ****************************************************************************/ #ifndef __ARCH_TRICORE_INCLUDE_BARRIERS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + #define __ARCH_TRICORE_INCLUDE_BARRIERS_H -#define UP_DSB() __dsync() -#define UP_DMB() asm volatile ("" : : : "memory") -#define UP_RMB() asm volatile ("" : : : "memory") -#define UP_WMB() asm volatile ("" : : : "memory") -#define UP_ISB() __isync() +#define UP_DSB() __asm__ __volatile__ ("dsync" : : : "memory") +#define UP_DMB() __asm__ __volatile__ ("":::"memory") +#define UP_RMB() __asm__ __volatile__ ("":::"memory") +#define UP_WMB() __asm__ __volatile__ ("":::"memory") +#define UP_ISB() __asm__ __volatile__ ("isync" : : : "memory") #endif /* __ARCH_TRICORE_INCLUDE_BARRIERS_H */ diff --git a/arch/tricore/include/inttypes.h b/arch/tricore/include/inttypes.h index 5e762312f1fd1..c1ea00072ec81 100644 --- a/arch/tricore/include/inttypes.h +++ b/arch/tricore/include/inttypes.h @@ -41,28 +41,28 @@ #define PRId32 "ld" #define PRId64 "lld" -#define PRIdPTR "d" +#define PRIdPTR "ld" #define PRIi8 "i" #define PRIi16 "i" #define PRIi32 "li" #define PRIi64 "lli" -#define PRIiPTR "i" +#define PRIiPTR "li" #define PRIo8 "o" #define PRIo16 "o" #define PRIo32 "lo" #define PRIo64 "llo" -#define PRIoPTR "o" +#define PRIoPTR "lo" #define PRIu8 "u" #define PRIu16 "u" #define PRIu32 "lu" #define PRIu64 "llu" -#define PRIuPTR "u" +#define PRIuPTR "lu" #define PRIx8 "x" #define PRIx16 "x" @@ -83,35 +83,35 @@ #define SCNd32 "ld" #define SCNd64 "lld" -#define SCNdPTR "d" +#define SCNdPTR "ld" #define SCNi8 "hhi" #define SCNi16 "hi" #define SCNi32 "li" #define SCNi64 "lli" -#define SCNiPTR "i" +#define SCNiPTR "li" #define SCNo8 "hho" #define SCNo16 "ho" #define SCNo32 "lo" #define SCNo64 "llo" -#define SCNoPTR "o" +#define SCNoPTR "lo" #define SCNu8 "hhu" #define SCNu16 "hu" #define SCNu32 "lu" #define SCNu64 "llu" -#define SCNuPTR "u" +#define SCNuPTR "lu" #define SCNx8 "hhx" #define SCNx16 "hx" #define SCNx32 "lx" #define SCNx64 "llx" -#define SCNxPTR "x" +#define SCNxPTR "lx" #define INT8_C(x) x #define INT16_C(x) x diff --git a/arch/tricore/include/irq.h b/arch/tricore/include/irq.h index f4109c6f5bd72..c15e8359ec2bb 100644 --- a/arch/tricore/include/irq.h +++ b/arch/tricore/include/irq.h @@ -34,7 +34,6 @@ #include #ifndef __ASSEMBLY__ # include -# include #endif /* Include NuttX-specific IRQ definitions */ @@ -43,106 +42,22 @@ /* Include chip-specific IRQ definitions (including IRQ numbers) */ -#include #include -#include +#include + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) +# include +#elif defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) +# include +#endif /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ -/* Address <--> Context Save Areas */ - -#define tricore_csa2addr(csa) ((uintptr_t *)((((csa) & 0x000F0000) << 12) \ - | (((csa) & 0x0000FFFF) << 6))) -#define tricore_addr2csa(addr) ((uintptr_t)(((((uintptr_t)(addr)) & 0xF0000000) >> 12) \ - | (((uintptr_t)(addr) & 0x003FFFC0) >> 6))) - -/* Upper CSA */ - -#define REG_UPCXI 0 -#define REG_PSW 1 -#define REG_A10 2 -#define REG_UA11 3 -#define REG_D8 4 -#define REG_D9 5 -#define REG_D10 6 -#define REG_D11 7 -#define REG_A12 8 -#define REG_A13 9 -#define REG_A14 10 -#define REG_A15 11 -#define REG_D12 12 -#define REG_D13 13 -#define REG_D14 14 -#define REG_D15 15 - -/* Lower CSA */ - -#define REG_LPCXI 0 -#define REG_LA11 1 -#define REG_A2 2 -#define REG_A3 3 -#define REG_D0 4 -#define REG_D1 5 -#define REG_D2 6 -#define REG_D3 7 -#define REG_A4 8 -#define REG_A5 9 -#define REG_A6 10 -#define REG_A7 11 -#define REG_D4 12 -#define REG_D5 13 -#define REG_D6 14 -#define REG_D7 15 - -#define REG_RA REG_UA11 -#define REG_SP REG_A10 -#define REG_UPC REG_UA11 - -#define REG_LPC REG_LA11 - -#define TC_CONTEXT_REGS (16) -#define TC_CONTEXT_SIZE (sizeof(void *) * TC_CONTEXT_REGS) - -#define XCPTCONTEXT_REGS (TC_CONTEXT_REGS * 2) -#define XCPTCONTEXT_SIZE (sizeof(void *) * XCPTCONTEXT_REGS) - -#define NR_IRQS (2048) - -/* PSW: Program Status Word Register */ - -#define PSW_CDE (1 << 7) /* Bits 7: Call Depth Count Enable */ -#define PSW_IS (1 << 9) /* Bits 9: Interrupt Stack Control */ -#define PSW_IO (10) /* Bits 10-11: Access Privilege Level Control (I/O Privilege) */ -# define PSW_IO_USER0 (0 << PSW_IO) -# define PSW_IO_USER1 (1 << PSW_IO) -# define PSW_IO_SUPERVISOR (2 << PSW_IO) - -/* PCXI: Previous Context Information and Pointer Register */ - -#define PCXI_UL (1 << 20) /* Bits 20: Upper or Lower Context Tag */ -#define PCXI_PIE (1 << 21) /* Bits 21: Previous Interrupt Enable */ - -/* FCX: Free CSA List Head Pointer Register */ - -#define FCX_FCXO (0) /* Bits 0-15: FCX Offset Address */ -#define FCX_FCXS (16) /* Bits 16-19: FCX Segment Address */ -#define FCX_FCXO_MASK (0xffff << FCX_FCXO) -#define FCX_FCXS_MASK (0xf << FCX_FCXS) -#define FCX_FREE (FCX_FCXS_MASK | FCX_FCXO_MASK) /* Free CSA manipulation */ - -#define TRICORE_SRCNUM_PER_GPSR 8 -#define TRICORE_SRC2IRQ(src_addr) \ - (((uintptr_t)(src_addr) - (uintptr_t)&MODULE_SRC) / 4) -#define TRICORE_GPSR_IRQNUM(src_cpu, dest_cpu) \ - TRICORE_SRC2IRQ(&SRC_GPSR00 + src_cpu * 8 + dest_cpu) - -/* For use with EABI and floating point, the stack must be aligned to 8-byte - * addresses. - */ - -#define STACKFRAME_ALIGN 8 +#ifndef STACKFRAME_ALIGN +# define STACKFRAME_ALIGN 8 +#endif /* FPU registers */ @@ -159,59 +74,38 @@ #ifndef __ASSEMBLY__ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif /**************************************************************************** - * Public Types + * Pre-processor Definitions ****************************************************************************/ -struct xcptcontext +#define EXTERN extern "C" +extern "C" { -#ifdef CONFIG_ENABLE_ALL_SIGNALS - /* These are saved copies of the context used during - * signal processing. - */ - - uintptr_t *saved_regs; +#else +#define EXTERN extern #endif - /* Register save area with XCPTCONTEXT_SIZE, only valid when: - * 1.The task isn't running or - * 2.The task is interrupted - * otherwise task is running, and regs contain the stale value. - */ - - uintptr_t *regs; -}; /**************************************************************************** * Public Data ****************************************************************************/ -/* g_interrupt_context store irq status */ +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * g_current_regs for portability. + */ -EXTERN volatile bool g_interrupt_context[CONFIG_SMP_NCPUS]; +/* For the case of architectures with multiple CPUs, then there must be one + * such value for each processor that can receive an interrupt. + */ -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ +EXTERN volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; /**************************************************************************** - * Name: up_cpu_index - * - * Description: - * Return the real core number regardless CONFIG_SMP setting - * + * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_ARCH_HAVE_MULTICPU -int up_cpu_index(void) noinstrument_function; -#endif /* CONFIG_ARCH_HAVE_MULTICPU */ - /**************************************************************************** * Name: up_irq_enable * @@ -223,65 +117,60 @@ int up_cpu_index(void) noinstrument_function; void up_irq_enable(void); /**************************************************************************** - * Inline functions + * Inline Functions ****************************************************************************/ noinstrument_function static inline_function uintptr_t up_getsp(void) { -#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING - return (uintptr_t)__get_sp(); -#else - return (uintptr_t)__builtin_frame_address(0); -#endif + return __builtin_frame_address(0); } /**************************************************************************** * Name: up_irq_save * * Description: - * Disable interrupts and return the previous value of the mstatus register + * Disable interrupts and return the previous PSW.IE state. * ****************************************************************************/ +#define TRICORE_IRQ_DISABLE_AND_SAVE(x) \ + __asm__ __volatile__("disable %0":"=d"(x)) +#define TRICORE_IRQ_RESTORE(x) \ + __asm__ __volatile__("restore %0"::"d"(x)) + noinstrument_function static inline_function irqstate_t up_irq_save(void) { - return __disable_and_save(); + irqstate_t state; + TRICORE_IRQ_DISABLE_AND_SAVE(state); + return state; } /**************************************************************************** * Name: up_irq_restore * * Description: - * Restore the value of the mstatus register + * Restore the previous PSW.IE state from up_irq_save(). * ****************************************************************************/ noinstrument_function static inline_function void up_irq_restore(irqstate_t flags) { - __restore(flags); + TRICORE_IRQ_RESTORE(flags); } /**************************************************************************** * Inline Functions ****************************************************************************/ -/**************************************************************************** - * Name: up_set_interrupt_context - * - * Description: - * Set the interrupt handler context. - * - ****************************************************************************/ +static inline_function uintptr_t *up_current_regs(void) +{ + return (uintptr_t *)g_current_regs[0]; +} -noinstrument_function -static inline_function void up_set_interrupt_context(bool flag) +static inline_function void up_set_current_regs(uintptr_t *regs) { -#ifdef CONFIG_SMP - g_interrupt_context[up_this_cpu()] = flag; -#else - g_interrupt_context[0] = flag; -#endif + g_current_regs[0] = regs; } /**************************************************************************** @@ -296,16 +185,9 @@ static inline_function void up_set_interrupt_context(bool flag) noinstrument_function static inline_function bool up_interrupt_context(void) { -#ifdef CONFIG_SMP - irqstate_t flags = up_irq_save(); - bool ret = g_interrupt_context[up_this_cpu()]; - - up_irq_restore(flags); + bool ret = up_current_regs() != NULL; return ret; -#else - return g_interrupt_context[0]; -#endif } /**************************************************************************** @@ -314,41 +196,27 @@ static inline_function bool up_interrupt_context(void) static inline_function uintptr_t up_getusrsp(void *regs) { - uintptr_t *csaregs = (uintptr_t *)regs; + uintptr_t *csa = regs; - if (csaregs[REG_LPCXI] & PCXI_UL) + while (((uintptr_t)csa & PCXI_UL) == 0) { - csaregs = tricore_csa2addr(csaregs[REG_LPCXI]); + csa = tricore_csa2addr((uintptr_t)csa); + csa = (uintptr_t *)csa[0]; } - else - { - csaregs += TC_CONTEXT_REGS; - } - - return csaregs[REG_SP]; -} -#endif /* __ASSEMBLY__ */ - -/**************************************************************************** - * Name: up_switch_context - ****************************************************************************/ + csa = tricore_csa2addr((uintptr_t)csa); -#define up_switch_context(tcb, rtcb) \ - do { \ - if (!up_interrupt_context()) \ - { \ - sys_call0(SYS_switch_context); \ - } \ - UNUSED(rtcb); \ - } while (0) + return csa[REG_SP]; +} /**************************************************************************** * Name: up_getusrpc ****************************************************************************/ #define up_getusrpc(regs) \ - (((uint32_t *)((regs) ? (regs) : running_regs()))[REG_UPC]) + (((uintptr_t *)((regs) ? (regs) : running_regs()))[REG_PC]) + +#endif /* __ASSEMBLY__ */ #undef EXTERN #ifdef __cplusplus diff --git a/arch/tricore/include/limits.h b/arch/tricore/include/limits.h index 9ae86fd940438..31482b9cf7e0a 100644 --- a/arch/tricore/include/limits.h +++ b/arch/tricore/include/limits.h @@ -30,7 +30,6 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ - #define CHAR_BIT 8 #define SCHAR_MIN (-SCHAR_MAX - 1) #define SCHAR_MAX 127 diff --git a/arch/tricore/include/syscall.h b/arch/tricore/include/syscall.h index 208ef318ecdae..4710985e5505c 100644 --- a/arch/tricore/include/syscall.h +++ b/arch/tricore/include/syscall.h @@ -38,7 +38,7 @@ #endif /**************************************************************************** - * Pre-processor Prototypes + * Pre-processor Definitions ****************************************************************************/ #define SYS_syscall 0x00 @@ -58,8 +58,6 @@ # define CONFIG_SYS_RESERVED 4 #endif -/* Cortex-M system calls ****************************************************/ - /* SYS call 1: * * void tricore_fullcontextrestore(uint32_t *restoreregs) noreturn_function; @@ -118,10 +116,6 @@ #define SYS_signal_handler_return (7) #endif /* !CONFIG_BUILD_FLAT */ -/**************************************************************************** - * Public Types - ****************************************************************************/ - /**************************************************************************** * Inline functions ****************************************************************************/ @@ -132,24 +126,6 @@ static inline uintptr_t sys_call0(unsigned int nbr) { -#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING - register long reg0; - - __asm volatile - ( - "mov d8, %0 \n\t" - : - : "d"(nbr) - : "d8" - ); - __asm volatile - ( - "syscall %1" - : "=d"(reg0) - : "i"(SYS_syscall), "d"(nbr) - : "memory", "a11" - ); -#else register long reg0 __asm__("d8") = (long)(nbr); __asm__ __volatile__ @@ -159,7 +135,6 @@ static inline uintptr_t sys_call0(unsigned int nbr) : "i"(SYS_syscall), "d"(reg0) : "memory", "a11" ); -#endif return reg0; } @@ -168,25 +143,6 @@ static inline uintptr_t sys_call0(unsigned int nbr) static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1) { -#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING - register long reg0; - - __asm volatile - ( - "mov d8, %0 \n\t" - "mov d9, %1 \n\t" - : - : "d"(nbr), "d"(parm1) - : "d8", "d9" - ); - __asm volatile - ( - "syscall %1" - : "=d"(reg0) - : "i"(SYS_syscall) - : "memory", "a11" - ); -#else register long reg0 __asm__("d8") = (long)(nbr); register long reg1 __asm__("d9") = (long)(parm1); @@ -197,7 +153,6 @@ static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1) : "i"(SYS_syscall), "d"(reg0), "d"(reg1) : "memory", "a11" ); -#endif return reg0; } @@ -207,26 +162,6 @@ static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1) static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, uintptr_t parm2) { -#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING - register long reg0; - - __asm volatile - ( - "mov d8, %0 \n\t" - "mov d9, %1 \n\t" - "mov d10, %2 \n\t" - : - : "d"(nbr), "d"(parm1), "d"(parm2) - : "d8", "d9", "d10" - ); - __asm volatile - ( - "syscall %1" - : "=d"(reg0) - : "i"(SYS_syscall) - : "memory", "a11" - ); -#else register long reg0 __asm__("d8") = (long)(nbr); register long reg2 __asm__("d10") = (long)(parm2); register long reg1 __asm__("d9") = (long)(parm1); @@ -238,7 +173,6 @@ static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, : "i"(SYS_syscall), "d"(reg0), "d"(reg1), "d"(reg2) : "memory", "a11" ); -#endif return reg0; } @@ -248,27 +182,6 @@ static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3) { -#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING - register long reg0; - - __asm volatile - ( - "mov d8, %0 \n\t" - "mov d9, %1 \n\t" - "mov d10, %2 \n\t" - "mov d11, %3 \n\t" - : - : "d"(nbr), "d"(parm1), "d"(parm2), "d"(parm3) - : "d8", "d9", "d10", "d11" - ); - __asm volatile - ( - "syscall %1" - : "=d"(reg0) - : "i"(SYS_syscall) - : "memory", "a11" - ); -#else register long reg0 __asm__("d8") = (long)(nbr); register long reg3 __asm__("d11") = (long)(parm3); register long reg2 __asm__("d10") = (long)(parm2); @@ -281,7 +194,6 @@ static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, : "i"(SYS_syscall), "d"(reg0), "d"(reg1), "d"(reg2), "d"(reg3) : "memory", "a11" ); -#endif return reg0; } @@ -292,28 +204,6 @@ static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3, uintptr_t parm4) { -#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING - register long reg0; - - __asm volatile - ( - "mov d8, %0 \n\t" - "mov d9, %1 \n\t" - "mov d10, %2 \n\t" - "mov d11, %3 \n\t" - "mov d12, %4 \n\t" - : - : "d"(nbr), "d"(parm1), "d"(parm2), "d"(parm3), "d"(parm4) - : "d8", "d9", "d10", "d11", "d12" - ); - __asm volatile - ( - "syscall %1" - : "=d"(reg0) - : "i"(SYS_syscall) - : "memory", "a11" - ); -#else register long reg0 __asm__("d8") = (long)(nbr); register long reg4 __asm__("d12") = (long)(parm4); register long reg3 __asm__("d11") = (long)(parm3); @@ -328,7 +218,6 @@ static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, "d"(reg3), "d"(reg4) : "memory", "a11" ); -#endif return reg0; } @@ -339,29 +228,6 @@ static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3, uintptr_t parm4, uintptr_t parm5) { -#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING - register long reg0; - - __asm volatile - ( - "mov d8, %0 \n\t" - "mov d9, %1 \n\t" - "mov d10, %2 \n\t" - "mov d11, %3 \n\t" - "mov d12, %4 \n\t" - "mov d13, %5 \n\t" - : - : "d"(nbr), "d"(parm1), "d"(parm2), "d"(parm3), "d"(parm4), "d"(parm5) - : "d8", "d9", "d10", "d11", "d12", "d13" - ); - __asm volatile - ( - "syscall %1" - : "=d"(reg0) - : "i"(SYS_syscall) - : "memory", "a11" - ); -#else register long reg0 __asm__("d8") = (long)(nbr); register long reg5 __asm__("d13") = (long)(parm5); register long reg4 __asm__("d12") = (long)(parm4); @@ -377,7 +243,6 @@ static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, "d"(reg3), "d"(reg4), "d"(reg5) : "memory", "a11" ); -#endif return reg0; } @@ -389,31 +254,6 @@ static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1, uintptr_t parm4, uintptr_t parm5, uintptr_t parm6) { -#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING - register long reg0; - - __asm volatile - ( - "mov d8, %0 \n\t" - "mov d9, %1 \n\t" - "mov d10, %2 \n\t" - "mov d11, %3 \n\t" - "mov d12, %4 \n\t" - "mov d13, %5 \n\t" - "mov d14, %6 \n\t" - : - : "d"(nbr), "d"(parm1), "d"(parm2), - "d"(parm3), "d"(parm4), "d"(parm5), "d"(parm6) - : "d8", "d9", "d10", "d11", "d12", "d13", "d14" - ); - __asm volatile - ( - "syscall %1" - : "=d"(reg0) - : "i"(SYS_syscall) - : "memory", "a11" - ); -#else register long reg0 __asm__("d8") = (long)(nbr); register long reg6 __asm__("d14") = (long)(parm6); register long reg5 __asm__("d13") = (long)(parm5); @@ -430,15 +270,10 @@ static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1, "d"(reg3), "d"(reg4), "d"(reg5), "d"(reg6) : "memory", "a11" ); -#endif return reg0; } -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/tricore/include/tc3x/irq.h b/arch/tricore/include/tc3x/irq.h new file mode 100644 index 0000000000000..281f4925a5670 --- /dev/null +++ b/arch/tricore/include/tc3x/irq.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/tricore/include/tc3x/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_TRICORE_INCLUDE_TC3X_IRQ_H +#define __ARCH_TRICORE_INCLUDE_TC3X_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#define NR_IRQS 2048 + +#endif /* __ARCH_TRICORE_INCLUDE_TC3X_IRQ_H */ diff --git a/arch/tricore/include/tc4x/irq.h b/arch/tricore/include/tc4x/irq.h new file mode 100644 index 0000000000000..498ce171b29ad --- /dev/null +++ b/arch/tricore/include/tc4x/irq.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/tricore/include/tc4x/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_TRICORE_INCLUDE_TC4X_IRQ_H +#define __ARCH_TRICORE_INCLUDE_TC4X_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ +#define NR_IRQS 2048 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#endif /* __ARCH_TRICORE_INCLUDE_TC4X_IRQ_H */ diff --git a/arch/tricore/src/common/CMakeLists.txt b/arch/tricore/src/common/CMakeLists.txt index 1bbf4a0426231..796a4773ff183 100644 --- a/arch/tricore/src/common/CMakeLists.txt +++ b/arch/tricore/src/common/CMakeLists.txt @@ -24,6 +24,7 @@ set(SRCS tricore_allocateheap.c tricore_backtrace.c tricore_checkstack.c + tricore_compiler.c tricore_createstack.c tricore_csa.c tricore_exit.c @@ -36,26 +37,25 @@ set(SRCS tricore_registerdump.c tricore_releasestack.c tricore_saveusercontext.c + tricore_schedulesigaction.c + tricore_sigdeliver.c tricore_stackframe.c + tricore_stm.c tricore_svcall.c + tricore_switchcontext.c tricore_tcbinfo.c tricore_trapcall.c - tricore_usestack.c) - -if(CONFIG_ENABLE_ALL_SIGNALS) - list(APPEND SRCS tricore_schedulesigaction.c tricore_sigdeliver.c) -endif() + tricore_usestack.c + tricore_interrupt.S + tricore_trap.S + tricore_lib.S) if(CONFIG_SPINLOCK) list(APPEND SRCS tricore_testset.c) endif() -set(IFXFLAGS -DIFX_CFG_EXTEND_TRAP_HOOKS -DIFX_USE_SW_MANAGED_INT) - target_sources(arch PRIVATE ${SRCS}) -target_sources(nuttx PRIVATE tricore_doirq.c) -target_compile_options(arch PRIVATE ${IFXFLAGS}) -target_compile_options(nuttx PRIVATE ${IFXFLAGS}) +target_sources(nuttx PRIVATE tricore_doirq.c tricore_head.S) target_include_directories( nuttx SYSTEM PRIVATE ${CMAKE_SOURCE_DIR}/include ${CMAKE_BINARY_DIR}/include ${CMAKE_BINARY_DIR}/include_arch) diff --git a/arch/tricore/src/common/Make.defs b/arch/tricore/src/common/Make.defs index 0dc13a047ad51..01e179624315f 100644 --- a/arch/tricore/src/common/Make.defs +++ b/arch/tricore/src/common/Make.defs @@ -20,11 +20,17 @@ # ############################################################################ +HEAD_ASRC += tricore_head.S HEAD_CSRC += tricore_doirq.c +CMN_ASRCS += tricore_interrupt.S +CMN_ASRCS += tricore_trap.S +CMN_ASRCS += tricore_lib.S + CMN_CSRCS += tricore_allocateheap.c CMN_CSRCS += tricore_backtrace.c CMN_CSRCS += tricore_checkstack.c +CMN_CSRCS += tricore_compiler.c CMN_CSRCS += tricore_createstack.c CMN_CSRCS += tricore_csa.c CMN_CSRCS += tricore_exit.c @@ -41,6 +47,7 @@ CMN_CSRCS += tricore_schedulesigaction.c CMN_CSRCS += tricore_sigdeliver.c CMN_CSRCS += tricore_stackframe.c CMN_CSRCS += tricore_svcall.c +CMN_CSRCS += tricore_switchcontext.c CMN_CSRCS += tricore_tcbinfo.c CMN_CSRCS += tricore_trapcall.c CMN_CSRCS += tricore_usestack.c diff --git a/arch/tricore/src/common/tricore-llvm.ld b/arch/tricore/src/common/tricore-llvm.ld new file mode 100644 index 0000000000000..72fedc345cde4 --- /dev/null +++ b/arch/tricore/src/common/tricore-llvm.ld @@ -0,0 +1,147 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore-llvm.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH("tricore") +ENTRY(__start) +EXTERN(__start) + +CONFIG_TRICORE_CSA_COUNT = 512; +CONFIG_TRICORE_INITIAL_STACK_SIZE = 512; +CONFIG_TRICORE_INITIAL_STACK_OFFSET = 0xEB00; + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) +__HEAP_SIZE = (512 * 1024); +#else +__HEAP_SIZE = (64 * 1024); +#endif + +MEMORY +{ + dsram (rw): ORIGIN = 0x70000000, LENGTH = 240K + psram (rwx): ORIGIN = 0x70100000, LENGTH = 64K +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) + dlmu (rw): ORIGIN = 0x90000000, LENGTH = 512K +#else + dlmu (rw): ORIGIN = 0x90000000, LENGTH = 96K +#endif + pflash (rx): ORIGIN = 0x80000000, LENGTH = 4M +} + +REGION_ALIAS("CODE_MEM", pflash) +REGION_ALIAS("DATA_MEM", dsram) +REGION_ALIAS("BSS_MEM", dsram) +REGION_ALIAS("CSA_MEM", dsram) +REGION_ALIAS("HEAP_MEM", dlmu) +REGION_ALIAS("PSRAM_MEM", psram) + +SECTIONS +{ + .start : + { + KEEP(*(.start)) + . = ALIGN(4); + } > CODE_MEM + + .traptab : + { + KEEP(*(.traptab)) + . = ALIGN(256); + } > CODE_MEM + + .ivtab : + { + KEEP(*(.ivtab)) + . = ALIGN(4); + } > CODE_MEM + + .text : + { + KEEP(*(.text)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + . = ALIGN(2); + } > CODE_MEM + + .data : ALIGN(4) + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > DATA_MEM AT> CODE_MEM + _data_flash = LOADADDR(.data); + + .psram_base ALIGN(8) (NOLOAD) : + { + . += CONFIG_TRICORE_INITIAL_STACK_OFFSET; + __PSRAM_USTACK = .; + . += CONFIG_TRICORE_INITIAL_STACK_SIZE; + __PSRAM_BOOT_CSA = .; + } > PSRAM_MEM + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > BSS_MEM + + .ustack ALIGN(8) (NOLOAD) : + { + . += CONFIG_IDLETHREAD_STACKSIZE; + __USTACK = .; + } > BSS_MEM + +#if defined(CONFIG_ARCH_INTERRUPTSTACK) + .istack ALIGN(8) (NOLOAD) : + { + . += CONFIG_ARCH_INTERRUPTSTACK; + __istack = .; + } > BSS_MEM +#endif + + .csa (NOLOAD) : ALIGN(64) + { + __CSA_BEGIN = .; + . += CONFIG_TRICORE_CSA_COUNT * 64; + __CSA_END = .; + } > CSA_MEM + __CSA_SIZE = __CSA_END - __CSA_BEGIN; + + .heap (NOLOAD) : ALIGN(8) + { + _sheap = .; + . += __HEAP_SIZE; + _eheap = .; + } > HEAP_MEM + _heap_size = _sheap - _eheap; +} diff --git a/arch/tricore/src/common/tricore.ld b/arch/tricore/src/common/tricore.ld new file mode 100644 index 0000000000000..9b8c79963caf0 --- /dev/null +++ b/arch/tricore/src/common/tricore.ld @@ -0,0 +1,150 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH("tricore") +ENTRY(__start) +EXTERN(__start) + +__USTACK_SIZE = 2K; +CONFIG_TRICORE_CSA_COUNT = 1024; +CONFIG_TRICORE_INITIAL_STACK_OFFSET = 0xEB00; +CONFIG_TRICORE_INITIAL_STACK_SIZE = 512; + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) +__HEAP_SIZE = 512K; +#else +__HEAP_SIZE = 64K; +#endif + +MEMORY +{ + dsram0 (w!xp): ORIGIN = 0x70000000, LENGTH = 240K + psram0 (wx!p): ORIGIN = 0x70100000, LENGTH = 64K +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) + dlmu (wr!xp): ORIGIN = 0x90000000, LENGTH = 512K +#else + dlmu (wr!xp): ORIGIN = 0x90000000, LENGTH = 96K +#endif + pflash0 (rx!p): ORIGIN = 0x80000000, LENGTH = 4M +} + +REGION_ALIAS("CODE_MEM", pflash0) +REGION_ALIAS("DATA_MEM", dsram0) +REGION_ALIAS("BSS_MEM", dsram0) +REGION_ALIAS("CSA_MEM", dsram0) +REGION_ALIAS("HEAP_MEM", dlmu) + +SECTIONS +{ + .start : + { + KEEP(*(.start)) + . = ALIGN(4); + } > CODE_MEM + + .traptab : + { + KEEP(*(.traptab)) + . = ALIGN(4); + } > CODE_MEM + + .ivtab : + { + KEEP(*(.ivtab)) + . = ALIGN(4); + } > CODE_MEM + + .text : + { + KEEP(*(.text)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + . = ALIGN(2); + } > CODE_MEM + + .data : + { + . = ALIGN(4); + _sdata = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(4); + _edata = .; + } > DATA_MEM AT> CODE_MEM + _data_load = LOADADDR(.data); + + .bss . : + { + . = ALIGN(4); + _sbss = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } > BSS_MEM + _data_flash = LOADADDR(.data); + + .ustack : ALIGN(8) FLAGS(aw) + { + . += __USTACK_SIZE; + __USTACK = .; + } > BSS_MEM + + .istack : ALIGN(8) FLAGS(aw) + { + . += CONFIG_ARCH_INTERRUPTSTACK; + __istack = .; + } > BSS_MEM + + .csa : ALIGN(64) FLAGS(aw) + { + __CSA_BEGIN = .; + . += CONFIG_TRICORE_CSA_COUNT * 64; + __CSA_END = .; + } > CSA_MEM + __CSA_SIZE = __CSA_END - __CSA_BEGIN; + + .psram_base (NOLOAD) : ALIGN(8) + { + . += CONFIG_TRICORE_INITIAL_STACK_OFFSET; + __PSRAM_USTACK = .; + . += CONFIG_TRICORE_INITIAL_STACK_SIZE; + __PSRAM_BOOT_CSA = .; + } > psram0 + + .heap : ALIGN(8) FLAGS(aw) + { + _sheap = .; + . += __HEAP_SIZE; + _eheap = .; + } > HEAP_MEM + _heap_size = _sheap - _eheap; + + /DISCARD/ : { *(.comment) } + /DISCARD/ : { *(.callinfo) } +} diff --git a/arch/tricore/src/common/tricore_allocateheap.c b/arch/tricore/src/common/tricore_allocateheap.c index bdc31d7270e7e..15e33a3c61c13 100644 --- a/arch/tricore/src/common/tricore_allocateheap.c +++ b/arch/tricore/src/common/tricore_allocateheap.c @@ -27,11 +27,6 @@ #include #include -#include - -#include -#include -#include #include "tricore_internal.h" @@ -68,6 +63,6 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) { - *heap_start = _sheap; - *heap_size = (size_t)((uintptr_t)_eheap - (uintptr_t)_sheap); + *heap_start = (void *)_sheap; + *heap_size = (size_t)((uint32_t)_eheap - (uint32_t)_sheap); } diff --git a/arch/tricore/src/common/tricore_backtrace.c b/arch/tricore/src/common/tricore_backtrace.c index 5649af87ed950..50924c67d8328 100644 --- a/arch/tricore/src/common/tricore_backtrace.c +++ b/arch/tricore/src/common/tricore_backtrace.c @@ -25,9 +25,7 @@ ****************************************************************************/ #include - #include - #include "sched/sched.h" #include "tricore_internal.h" @@ -44,34 +42,29 @@ ****************************************************************************/ nosanitize_address -static int backtrace(uintptr_t pcxi, void **buffer, - int size, int *skip) +static int backtrace(uintptr_t pcxi, void **buffer, int size, int *skip) { - uintptr_t *csa; int i = 0; - for (; i < size && (pcxi & FCX_FREE) != 0; ) + for (; ((pcxi & FCX_FREE) != 0U) && (i < size); ) { + uintptr_t *csa; + csa = tricore_csa2addr(pcxi); if (csa == NULL) { break; } - if ((pcxi & PCXI_UL) != 0) + if ((pcxi & PCXI_UL) != 0U) { - if (csa[REG_UA11] == 0) - { - break; - } - if ((*skip)-- <= 0) { buffer[i++] = (void *)csa[REG_UA11]; } } - pcxi = csa[REG_UPCXI]; + pcxi = csa[0]; } return i; @@ -114,11 +107,10 @@ static int backtrace(uintptr_t pcxi, void **buffer, * ****************************************************************************/ -int up_backtrace(struct tcb_s *tcb, - void **buffer, int size, int skip) +int up_backtrace(struct tcb_s *tcb, void **buffer, int size, int skip) { struct tcb_s *rtcb = running_task(); - int ret = 0; + int ret; if (size <= 0 || !buffer) { @@ -127,12 +119,14 @@ int up_backtrace(struct tcb_s *tcb, if (tcb == NULL || tcb == rtcb) { - ret = backtrace(__mfcr(CPU_PCXI), buffer, size, &skip); + uintptr_t pcxi; + TRICORE_MFCR(TRICORE_CPU_PCXI, pcxi); + ret = backtrace(pcxi, buffer, size, &skip); } else { - uintptr_t *regs = tcb->xcp.regs; - ret = backtrace(regs[REG_LPCXI], buffer, size, &skip); + ret = backtrace(tricore_addr2csa(tcb->xcp.regs), + buffer, size, &skip); } return ret; diff --git a/arch/tricore/src/common/tricore_checkstack.c b/arch/tricore/src/common/tricore_checkstack.c index 77a4653e032fc..05dcc87ab9eb7 100644 --- a/arch/tricore/src/common/tricore_checkstack.c +++ b/arch/tricore/src/common/tricore_checkstack.c @@ -30,12 +30,7 @@ #include #include #include -#include -#include -#include - -#include "sched/sched.h" #include "tricore_internal.h" #ifdef CONFIG_STACK_COLORATION @@ -79,21 +74,20 @@ size_t tricore_stack_check(uintptr_t alloc, size_t size) /* Get aligned addresses of the top and bottom of the stack */ - start = STACKFRAME_ALIGN_UP((uintptr_t)alloc); - end = STACKFRAME_ALIGN_DOWN((uintptr_t)alloc + size); + start = STACK_ALIGN_UP((uintptr_t)alloc); + end = STACK_ALIGN_DOWN((uintptr_t)alloc + size); /* Get the adjusted size based on the top and bottom of the stack */ size = end - start; - /* RISC-V uses a push-down stack: the stack grows toward lower addresses - * in memory. We need to start at the lowest address in the stack memory - * allocation and search to higher addresses. The first word we encounter - * that does not have the magic value is the high water mark. + /* TriCore uses a push-down stack: the stack grows toward lower addresses + * in memory. Search from the lowest address upward; the first word that + * does not have the magic value is the high-water mark. */ for (ptr = (uint32_t *)start, mark = (size >> 2); - mark > 0 && *ptr == STACK_COLOR; + *ptr == STACK_COLOR && mark > 0; ptr++, mark--); /* Return our guess about how much stack space was used */ diff --git a/arch/tricore/src/common/tricore_compiler.c b/arch/tricore/src/common/tricore_compiler.c new file mode 100644 index 0000000000000..ea77958bf0a83 --- /dev/null +++ b/arch/tricore/src/common/tricore_compiler.c @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_compiler.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void up_regs_memcpy(void *dest, void *src, size_t count) +{ + memcpy(dest, src, count); +} + +#ifdef CONFIG_TRICORE_TOOLCHAIN_LLVM + +void __memcpy_assume_aligned(void *dst, const void *src, size_t n) +{ + if (n == 4) + { + *(uint32_t *)dst = *(uint32_t *)src; + return; + } + + memcpy(dst, src, n); +} + +#endif /* CONFIG_TRICORE_TOOLCHAIN_LLVM */ diff --git a/arch/tricore/src/common/tricore_createstack.c b/arch/tricore/src/common/tricore_createstack.c index ad7a6a93a7056..d16ae9cbb86f4 100644 --- a/arch/tricore/src/common/tricore_createstack.c +++ b/arch/tricore/src/common/tricore_createstack.c @@ -28,15 +28,13 @@ #include #include -#include #include -#include +#include -#include #include -#include #include -#include +#include +#include #include @@ -44,49 +42,9 @@ * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: up_create_stack - * - * Description: - * Allocate a stack for a new thread and setup up stack-related information - * in the TCB. - * - * The following TCB fields must be initialized by this function: - * - * - adj_stack_size: Stack size after adjustment for hardware, processor, - * etc. This value is retained only for debug purposes. - * - stack_alloc_ptr: Pointer to allocated stack - * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and - * Arguments has been removed from the stack allocation. - * - * Input Parameters: - * - tcb: The TCB of new task - * - stack_size: The requested stack size. At least this much - * must be allocated. - * - ttype: The thread type. This may be one of following (defined in - * include/nuttx/sched.h): - * - * TCB_FLAG_TTYPE_TASK Normal user task - * TCB_FLAG_TTYPE_PTHREAD User pthread - * TCB_FLAG_TTYPE_KERNEL Kernel thread - * - * This thread type is normally available in the flags field of the TCB, - * however, there are certain contexts where the TCB may not be fully - * initialized when up_create_stack is called. - * - * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect - * how the stack is allocated. For example, kernel thread stacks should - * be allocated from protected kernel memory. Stacks for user tasks and - * threads must come from memory that is accessible to user code. - * - ****************************************************************************/ - int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) { #ifdef CONFIG_TLS_ALIGNED - /* The allocated stack size must not exceed the maximum possible for the - * TLS feature. - */ DEBUGASSERT(stack_size <= TLS_MAXSTACK); if (stack_size >= TLS_MAXSTACK) @@ -95,11 +53,6 @@ int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) } #endif - /* Is there already a stack allocated of a different size? Because of - * alignment issues, stack_size might erroneously appear to be of a - * different size. Fortunately, this is not a critical operation. - */ - if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size) { /* Yes.. Release the old stack */ @@ -111,11 +64,6 @@ int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) if (!tcb->stack_alloc_ptr) { - /* Allocate the stack. If DEBUG is enabled (but not stack debug), - * then create a zeroed stack to make stack dumps easier to trace. - * If TLS is enabled, then we must allocate aligned stacks. - */ - #ifdef CONFIG_TLS_ALIGNED #ifdef CONFIG_MM_KERNEL_HEAP /* Use the kernel allocator if this is a kernel thread */ @@ -166,19 +114,9 @@ int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) uintptr_t top_of_stack; size_t size_of_stack; - /* RISC-V uses a push-down stack: the stack grows toward lower - * addresses in memory. The stack pointer register points to the - * lowest, valid working address (the "top" of the stack). Items on - * the stack are referenced as positive word offsets from SP. - */ - top_of_stack = (uintptr_t)tcb->stack_alloc_ptr + stack_size; - /* The RISC-V stack must be aligned at 128-bit (16-byte) boundaries. - * If necessary top_of_stack must be rounded down to the next boundary. - */ - - top_of_stack = STACKFRAME_ALIGN_DOWN(top_of_stack); + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); size_of_stack = top_of_stack - (uintptr_t)tcb->stack_alloc_ptr; /* Save the adjusted stack values in the struct tcb_s */ @@ -187,14 +125,11 @@ int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_size = size_of_stack; #ifdef CONFIG_STACK_COLORATION - /* If stack debug is enabled, then fill the stack with a - * recognizable value that we can use later to test for high - * water marks. - */ tricore_stack_color(tcb->stack_base_ptr, tcb->adj_stack_size); #endif /* CONFIG_STACK_COLORATION */ + tcb->flags |= TCB_FLAG_FREE_STACK; return OK; @@ -203,14 +138,6 @@ int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) return ERROR; } -/**************************************************************************** - * Name: tricore_stack_color - * - * Description: - * Write a well know value into the stack - * - ****************************************************************************/ - #ifdef CONFIG_STACK_COLORATION void tricore_stack_color(void *stackbase, size_t nbytes) { @@ -221,9 +148,10 @@ void tricore_stack_color(void *stackbase, size_t nbytes) /* Take extra care that we do not write outside the stack boundaries */ - stkptr = (uint32_t *)STACKFRAME_ALIGN_UP((uintptr_t)stackbase); + stkptr = (uint32_t *)STACK_ALIGN_UP((uintptr_t)stackbase); if (nbytes == 0) /* 0: colorize the running stack */ + { stkend = up_getsp(); if (stkend > (uintptr_t)&sp) @@ -236,7 +164,7 @@ void tricore_stack_color(void *stackbase, size_t nbytes) stkend = (uintptr_t)stackbase + nbytes; } - stkend = STACKFRAME_ALIGN_DOWN(stkend); + stkend = STACK_ALIGN_DOWN(stkend); nwords = (stkend - (uintptr_t)stkptr) >> 2; /* Set the entire stack to the coloration value */ diff --git a/arch/tricore/src/common/tricore_csa.c b/arch/tricore/src/common/tricore_csa.c index d68ea4ae215f6..478ab676adb29 100644 --- a/arch/tricore/src/common/tricore_csa.c +++ b/arch/tricore/src/common/tricore_csa.c @@ -31,6 +31,7 @@ #include #include +#include #include #include @@ -49,32 +50,27 @@ uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp, { uintptr_t *plcsa; uintptr_t *pucsa; + uint32_t val; + irqstate_t flags; - plcsa = (uintptr_t *)tricore_csa2addr(__mfcr(CPU_FCX)); - - /* DSYNC instruction should be executed immediately prior to the MTCR */ - - __dsync(); + TRICORE_IRQ_DISABLE_AND_SAVE(flags); + TRICORE_MFCR(TRICORE_CPU_FCX, val); + plcsa = (uintptr_t *)tricore_csa2addr(val); pucsa = (uintptr_t *)tricore_csa2addr(plcsa[REG_UPCXI]); - __mtcr(CPU_FCX, pucsa[REG_UPCXI]); - - /* ISYNC instruction executed immediately following MTCR */ + TRICORE_MTCR(TRICORE_CPU_FCX, pucsa[REG_UPCXI]); - __isync(); + TRICORE_IRQ_RESTORE(flags); - memset(pucsa, 0, TC_CONTEXT_SIZE); - memset(plcsa, 0, TC_CONTEXT_SIZE); + memset(pucsa, 0, XCPTCONTEXT_SIZE); + memset(plcsa, 0, XCPTCONTEXT_SIZE); pucsa[REG_SP] = sp; pucsa[REG_PSW] = psw; - - /* Save the task entry point */ - pucsa[REG_UPC] = pc; - plcsa[REG_LPC] = pc; + plcsa[REG_LPC] = pc; plcsa[REG_LPCXI] = (PCXI_UL | tricore_addr2csa(pucsa)); if (!irqsave) @@ -82,7 +78,7 @@ uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp, plcsa[REG_LPCXI] |= PCXI_PIE; } - return plcsa; + return (uintptr_t *)tricore_addr2csa(plcsa); } /**************************************************************************** @@ -140,7 +136,7 @@ void tricore_reclaim_csa(uintptr_t pcxi) /* Look up the current free CSA head. */ - free = __mfcr(CPU_FCX); + TRICORE_MFCR(TRICORE_CPU_FCX, free); /* Join the current Free onto the Tail of what is being reclaimed. */ @@ -148,5 +144,5 @@ void tricore_reclaim_csa(uintptr_t pcxi) /* Move the head of the reclaimed into the Free. */ - __mtcr(CPU_FCX, head); + TRICORE_MTCR(TRICORE_CPU_FCX, head); } diff --git a/arch/tricore/src/common/tricore_doirq.c b/arch/tricore/src/common/tricore_doirq.c index 19f01934dee8d..1bcca0b0344e3 100644 --- a/arch/tricore/src/common/tricore_doirq.c +++ b/arch/tricore/src/common/tricore_doirq.c @@ -34,8 +34,6 @@ #include #include -#include - #include #include "tricore_internal.h" @@ -44,45 +42,50 @@ * Public Functions ****************************************************************************/ -IFX_INTERRUPT_INTERNAL(tricore_doirq, 0, 255) +void __attribute__((interrupt_handler)) tricore_isr_handler(int irq) { - struct tcb_s **running_task = &g_running_tasks[this_cpu()]; - struct tcb_s *tcb = this_task(); + struct tcb_s *running_task = g_running_tasks[this_cpu()]; + struct tcb_s *tcb; #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else - Ifx_CPU_ICR icr; uintptr_t *regs; - icr.U = __mfcr(CPU_ICR); - regs = tricore_csa2addr(__mfcr(CPU_PCXI)); + TRICORE_MFCR(TRICORE_CPU_PCXI, regs); - if (*running_task != NULL) + if (running_task != NULL) { - (*running_task)->xcp.regs = regs; + running_task->xcp.regs = regs; } board_autoled_on(LED_INIRQ); /* Nested interrupts are not supported */ - DEBUGASSERT(!up_interrupt_context()); + DEBUGASSERT(up_current_regs() == NULL); - /* Set irq flag */ + /* Current regs non-zero indicates that we are processing an interrupt; + * current_regs is also used to manage interrupt level context switches. + */ - up_set_interrupt_context(true); + up_set_current_regs(regs); /* Deliver the IRQ */ - tricore_ack_irq(NDX_TO_IRQ(icr.B.CCPN)); + irq_dispatch(irq, regs); - irq_dispatch(NDX_TO_IRQ(icr.B.CCPN), regs); - - /* Check for a context switch. */ + /* Check for a context switch. If a context switch occurred, then + * g_current_regs will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ - if (*running_task != tcb) + if (regs != up_current_regs()) { + tcb = this_task(); + #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously * running task is closed down gracefully (data caches dump, @@ -91,33 +94,34 @@ IFX_INTERRUPT_INTERNAL(tricore_doirq, 0, 255) */ addrenv_switch(tcb); - tcb = this_task(); #endif /* Update scheduler parameters */ - nxsched_switch_context(*running_task, tcb); + nxsched_switch_context(running_task, tcb); /* Record the new "running" task when context switch occurred. * g_running_tasks[] is only used by assertion logic for reporting * crashes. */ - *running_task = tcb; + running_task = tcb; + g_running_tasks[this_cpu()] = running_task; - __mtcr(CPU_PCXI, tricore_addr2csa(tcb->xcp.regs)); - __isync(); + TRICORE_MTCR(TRICORE_CPU_PCXI, (uintptr_t)up_current_regs()); } - /* Set irq flag */ + /* Set current_regs to NULL to indicate that we are no longer in an + * interrupt handler. + */ - up_set_interrupt_context(false); + up_set_current_regs(NULL); /* running_task->xcp.regs is about to become invalid * and will be marked as NULL to avoid misusage. */ - (*running_task)->xcp.regs = NULL; + running_task->xcp.regs = NULL; board_autoled_off(LED_INIRQ); #endif } diff --git a/arch/tricore/src/common/tricore_exit.c b/arch/tricore/src/common/tricore_exit.c index 1c796373ba263..ffa58ddc38154 100644 --- a/arch/tricore/src/common/tricore_exit.c +++ b/arch/tricore/src/common/tricore_exit.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include @@ -56,17 +56,25 @@ void up_exit(int status) { + struct tcb_s *tcb = this_task(); + /* Destroy the task at the head of the ready to run list. */ nxtask_exit(); + /* Now, perform the context switch to the new ready-to-run task at the + * head of the list. + */ + + tcb = this_task(); + /* Scheduler parameters will update inside syscall */ g_running_tasks[this_cpu()] = NULL; /* Then switch contexts */ - tricore_fullcontextrestore(); + tricore_fullcontextrestore(tcb->xcp.regs); /* tricore_fullcontextrestore() should not return but could if the software * interrupts are disabled. diff --git a/arch/tricore/src/common/tricore_getintstack.c b/arch/tricore/src/common/tricore_getintstack.c index 5647e8380cad5..ea2ace9f299c1 100644 --- a/arch/tricore/src/common/tricore_getintstack.c +++ b/arch/tricore/src/common/tricore_getintstack.c @@ -41,6 +41,6 @@ #if CONFIG_ARCH_INTERRUPTSTACK > 3 uintptr_t up_get_intstackbase(int cpu) { - return (uintptr_t)g_intstackalloc; + return (uintptr_t)__istack; } #endif diff --git a/arch/tricore/src/common/tricore_head.S b/arch/tricore/src/common/tricore_head.S new file mode 100644 index 0000000000000..377cb2317f10f --- /dev/null +++ b/arch/tricore/src/common/tricore_head.S @@ -0,0 +1,211 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_head.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +#define PSW_CDE (1 << 7) +#define PSW_GW (1 << 8) +#define PSW_IS (1 << 9) +#define PSW_IO_SV (2 << 10) + +#define PSW_DEFAULT (PSW_CDE | PSW_GW | PSW_IO_SV) +#define PSW_DEFAULT_IS (PSW_DEFAULT | PSW_IS) + + .extern btv_vector + .extern biv_vector + .extern tricore_wdt_disable + .extern up_clockconfig + .extern tricore_start + + .extern tricore_endinit_disable + .extern tricore_endinit_enable + .extern tricore_safety_endinit_enable + +#if defined(CONFIG_TRICORE_TC18) + .extern tricore_virt_disable +#endif + +.macro encode_csa_link addr_reg, tmp1, tmp2 + extr.u \tmp1, \addr_reg, 6, 16 + extr.u \tmp2, \addr_reg, 12, 20 + insert \addr_reg, \tmp2, \tmp1, 0, 16 +.endm + + /* Reset Entry Point */ + .section .start, "ax" + .global __start + .type __start, %function + +__start: + movh.a %a15, hi:__start_stage2 + lea %a15, [%a15], lo:__start_stage2 + ji %a15 + + .section .text, "ax" + .type __start_stage2, %function + +__start_stage2: + + /* Disable endinit protection */ + jl tricore_endinit_disable + + movh.a %a10, hi:__PSRAM_USTACK + lea %a10, [%a10], lo:__PSRAM_USTACK + + /* Trap vector table (BTV) */ + mov %d15, lo:btv_vector + addih %d15, %d15, hi:btv_vector + mtcr TRICORE_CPU_BTV, %d15 + isync + + /* Boot CSA in PSPR0 */ + movh.a %a15, hi:__PSRAM_BOOT_CSA + lea %a15, [%a15], lo:__PSRAM_BOOT_CSA + + mov.d %d15, %a15 + encode_csa_link %d15, %d14, %d13 + mtcr TRICORE_CPU_FCX, %d15 + isync + +#if defined(CONFIG_TRICORE_TC18) + + /* virt_disable ends in rfh; only CPU 0 has the hypervisor context */ + mfcr %d4, TRICORE_CPU_CORE_ID + extr.u %d4, %d4, 0, 3 + jnz %d4, skip_virt_disable + + /* Disable Virtualization */ + call tricore_virt_disable + + /* Re-init trap table setup because clobbered BTV and FCX after RFH */ + mov %d15, lo:btv_vector + addih %d15, %d15, hi:btv_vector + mtcr TRICORE_CPU_BTV, %d15 + + movh.a %a15, hi:__PSRAM_BOOT_CSA + lea %a15, [%a15], lo:__PSRAM_BOOT_CSA + mov.d %d15, %a15 + encode_csa_link %d15, %d14, %d13 + mtcr TRICORE_CPU_FCX, %d15 + isync + +skip_virt_disable: + +#endif /* CONFIG_TRICORE_TC18 */ + +#if defined(CONFIG_ARCH_INTERRUPTSTACK) + /* Setup PSW */ + mov %d15, lo:PSW_DEFAULT + mtcr TRICORE_CPU_PSW, %d15 + isync + + /* PSW.IS = 0, enable ISP stack */ + mov %d15, lo:__istack + addih %d15, %d15, hi:__istack + mtcr TRICORE_CPU_ISP, %d15 + isync +#else + /* PSW.IS = 0, enable user stack */ + mov %d15, lo:PSW_DEFAULT_IS + mtcr TRICORE_CPU_PSW, %d15 + isync +#endif + + /* Stack pointer -> DSPR0 (final user stack) */ + movh.a %a10, hi:__USTACK + lea %a10, [%a10], lo:__USTACK + + /* Initialize context save areas */ + movh.a %a15, hi:__CSA_BEGIN + lea %a15, [%a15], lo:__CSA_BEGIN + movh.a %a14, hi:__CSA_END + lea %a14, [%a14], lo:__CSA_END + + /* Encode first entry -> FCX */ + mov.d %d15, %a15 + encode_csa_link %d15, %d14, %d13 + mtcr TRICORE_CPU_FCX, %d15 + isync + + /* Build free list */ +csa_loop: + addi %d15, %d15, 1 + st.w [%a15], %d15 + lea %a15, [%a15], 64 + jne.a %a15, %a14, csa_loop + + /* Store LCX with 3 less entries for context depletion trap */ + addi %d15, %d15, -3 + mtcr TRICORE_CPU_LCX, %d15 + isync + + /* Copy .data from flash (LMA) to RAM (VMA) */ + movh.a %a0, hi:_data_flash + lea %a0, [%a0], lo:_data_flash + movh.a %a1, hi:_sdata + lea %a1, [%a1], lo:_sdata + movh.a %a2, hi:_edata + lea %a2, [%a2], lo:_edata + jeq.a %a1, %a2, skip_data + +copy_data: + ld.w %d0, [%a0+] + st.w [%a1+], %d0 + jne.a %a1, %a2, copy_data + +skip_data: + + /* clear bss */ + movh.a %a0, hi:_sbss + lea %a0, [%a0], lo:_sbss + movh.a %a1, hi:_ebss + lea %a1, [%a1], lo:_ebss + jeq.a %a0, %a1, skip_bss + mov %d0, 0 + +clear_bss: + st.w [%a0+], %d0 + jne.a %a0, %a1, clear_bss + +skip_bss: + + /* Interrupt vector table setup */ + mov %d15, lo:biv_vector + addih %d15, %d15, hi:biv_vector + mtcr TRICORE_CPU_BIV, %d15 + isync + + /* Re-enable endinit protection */ + jl tricore_endinit_enable + jl tricore_safety_endinit_enable + + /* Disable watchdog */ + call tricore_wdt_disable + + mfcr %d4, TRICORE_CPU_CORE_ID + extr.u %d4, %d4, 0, 3 + jnz %d4, skip_clockconfig + call up_clockconfig + mfcr %d4, TRICORE_CPU_CORE_ID + extr.u %d4, %d4, 0, 3 +skip_clockconfig: + j tricore_start diff --git a/arch/tricore/src/common/tricore_idle.c b/arch/tricore/src/common/tricore_idle.c index 4f654f55b246f..960b2aebab6cb 100644 --- a/arch/tricore/src/common/tricore_idle.c +++ b/arch/tricore/src/common/tricore_idle.c @@ -28,7 +28,6 @@ #include #include #include -#include #include "tricore_internal.h" @@ -36,41 +35,17 @@ * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when there is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - void up_idle(void) { #if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ nxsched_process_timer(); #else - /* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - #ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY board_autoled_off(LED_CPU); #endif - /* This would be an appropriate place to put some MCU-specific logic to - * sleep in a reduced power mode until an interrupt occurs to save power - */ - - Ifx_Ssw_infiniteLoop(); + __asm__ __volatile__ ("enable\n\twait" ::: "memory"); #endif } diff --git a/arch/tricore/src/common/tricore_initialize.c b/arch/tricore/src/common/tricore_initialize.c index 86880f2c3a24b..823a9c7e6c05d 100644 --- a/arch/tricore/src/common/tricore_initialize.c +++ b/arch/tricore/src/common/tricore_initialize.c @@ -26,8 +26,7 @@ #include #include -#include -#include +#include #include "tricore_internal.h" @@ -35,54 +34,43 @@ * Public Data ****************************************************************************/ -/* g_interrupt_context store irq status */ - -volatile bool g_interrupt_context[CONFIG_SMP_NCPUS]; +volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; /**************************************************************************** - * Public Functions + * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: up_initialize - * - * Description: - * up_initialize will be called once during OS initialization after the - * basic OS services have been initialized. The architecture specific - * details of initializing the OS will be handled here. Such things as - * setting up interrupt service routines, starting the clock, and - * registering device drivers are some of the things that are different - * for each processor and hardware platform. - * - * up_initialize is called after the OS initialized but before the user - * initialization logic has been started and before the libraries have - * been initialized. OS services and driver services are available. - * - ****************************************************************************/ - -void up_initialize(void) +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 +static inline void up_color_intstack(void) { -#ifdef CONFIG_ARCH_PERF_EVENTS - up_perf_init((void *)IFX_CFG_CPU_CLOCK_FREQUENCY); -#endif - - tricore_trapinit(); + uint32_t *ptr = (uint32_t *)g_intstackalloc; + ssize_t size; -#ifdef CONFIG_ARCH_ICACHE - up_enable_icache(); + for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); + size > 0; + size -= sizeof(uint32_t)) + { + *ptr++ = INTSTACK_COLOR; + } +} +#else +# define up_color_intstack() #endif -#ifdef CONFIG_ARCH_DCACHE - up_enable_dcache(); -#endif +/**************************************************************************** + * Public Functions + ****************************************************************************/ - /* Initialize the serial device driver */ +void up_initialize(void) +{ + up_color_intstack(); -#ifdef USE_SERIALDRIVER - tricore_serialinit(); -#endif + aurix_earlyserialinit(); + aurix_serialinit(); +} -#ifdef CONFIG_ARCH_HAVE_DEBUG - tricore_init_dbgmonitor(); -#endif +void tricore_start(int current_cpu) +{ + (void)current_cpu; + nx_start(); } diff --git a/arch/tricore/src/common/tricore_initialstate.c b/arch/tricore/src/common/tricore_initialstate.c index fcd0bb8c079e5..d9843c6e4c66f 100644 --- a/arch/tricore/src/common/tricore_initialstate.c +++ b/arch/tricore/src/common/tricore_initialstate.c @@ -66,7 +66,7 @@ void up_initial_state(struct tcb_s *tcb) if (tcb->pid == IDLE_PROCESS_ID) { - tcb->stack_alloc_ptr = (void *)((uintptr_t)g_idle_topstack - + tcb->stack_alloc_ptr = (void *)((uint8_t *)__USTACK - CONFIG_IDLETHREAD_STACKSIZE); tcb->stack_base_ptr = tcb->stack_alloc_ptr; tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE; @@ -79,6 +79,7 @@ void up_initial_state(struct tcb_s *tcb) tricore_stack_color(tcb->stack_alloc_ptr, 0); #endif /* CONFIG_STACK_COLORATION */ + return; } diff --git a/arch/tricore/src/common/tricore_internal.h b/arch/tricore/src/common/tricore_internal.h index ac8aab260dd6b..205b965374d2b 100644 --- a/arch/tricore/src/common/tricore_internal.h +++ b/arch/tricore/src/common/tricore_internal.h @@ -31,28 +31,14 @@ #ifndef __ASSEMBLY__ # include -# include +/* # include */ +# include # include # include # include -# include -# include -# include -# include #endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define SCU_FREQUENCY 100000000UL - -/* Determine which (if any) console driver to use. If a console is enabled - * and no other console device is specified, then a serial console is - * assumed. - */ - #ifndef CONFIG_DEV_CONSOLE # undef USE_SERIALDRIVER # undef USE_EARLYSERIALINIT @@ -69,36 +55,31 @@ # elif defined(CONFIG_RPMSG_UART_CONSOLE) # undef USE_SERIALDRIVER # undef USE_EARLYSERIALINIT -# elif defined(CONFIG_RPMSG_UART_RAW_CONSOLE) -# undef USE_SERIALDRIVER -# undef USE_EARLYSERIALINIT # else # define USE_SERIALDRIVER 1 # define USE_EARLYSERIALINIT 1 # endif #endif -/* If some other device is used as the console, then the serial driver may - * still be needed. Let's assume that if the upper half serial driver is - * built, then the lower half will also be needed. There is no need for - * the early serial initialization in this case. - */ - #if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL) # define USE_SERIALDRIVER 1 #endif +/* STACK_ALIGNMENT, STACK_ALIGN_MASK, STACK_ALIGN_UP/DOWN come from + * which derives them from STACKFRAME_ALIGN. + */ + /* Check if an interrupt stack size is configured */ #ifndef CONFIG_ARCH_INTERRUPTSTACK # define CONFIG_ARCH_INTERRUPTSTACK 0 #endif -#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACKFRAME_ALIGN_MASK) +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ -/* This is the value used to mark the stack for subsequent stack monitoring - * logic. - */ +#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK) #define STACK_COLOR 0xdeadbeef #define INTSTACK_COLOR 0xdeadbeef @@ -120,62 +101,39 @@ #define modreg32(v,m,a) putreg32((getreg32(a) & ~(m)) | ((v) & (m)), (a)) #define modreg64(v,m,a) putreg64((getreg64(a) & ~(m)) | ((v) & (m)), (a)) -#define tricore_fullcontextrestore() sys_call0(SYS_restore_context) +/* Context switching */ -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -typedef void (*up_vector_t)(void); +#ifndef tricore_fullcontextrestore +# define tricore_fullcontextrestore(restoreregs) \ + sys_call1(SYS_restore_context, (uintptr_t)restoreregs); +#else +extern void tricore_fullcontextrestore(uintptr_t *restoreregs); #endif -/**************************************************************************** - * Public Data - ****************************************************************************/ +#ifndef tricore_switchcontext +# define tricore_switchcontext(saveregs, restoreregs) \ + sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs); +#else +extern void tricore_switchcontext(uintptr_t **saveregs, + uintptr_t *restoreregs); +#endif #ifndef __ASSEMBLY__ - -/* This is the beginning of heap as provided from up_head.S. This is the - * first address in DRAM after the loaded program+bss+idle stack. The - * end of the heap is CONFIG_RAM_END - */ - -extern uintptr_t __USTACK0_END[]; -extern uintptr_t __USTACK0[]; -#define g_idle_topstack __USTACK0 - -/* Address of the saved user stack pointer */ - -#if CONFIG_ARCH_INTERRUPTSTACK > 3 -extern uintptr_t __ISTACK0_END[]; -extern uintptr_t __ISTACK0[]; -#define g_intstackalloc __ISTACK0_END -#define g_intstacktop __ISTACK0 +typedef void (*up_vector_t)(void); #endif -/* These symbols are setup by the linker script. */ - -extern uintptr_t _sheap[]; /* Start of .heap */ -extern uintptr_t _eheap[]; /* End+1 of .heap */ +extern uintptr_t _sheap[]; +extern uintptr_t _eheap[]; +extern uintptr_t __USTACK[]; +#if defined(CONFIG_ARCH_INTERRUPTSTACK) +extern uintptr_t __istack[]; #endif -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Interrupt ****************************************************************/ +/* Macros to handle saving and restoring interrupt state. */ -void tricore_ack_irq(int irq); +#define tricore_savestate(regs) (regs = up_current_regs()) +#define tricore_restorestate(regs) (up_set_current_regs(regs)) /* Signal handling **********************************************************/ @@ -185,7 +143,6 @@ void tricore_sigdeliver(void); void tricore_svcall(volatile void *trap); void tricore_trapcall(volatile void *trap); -void tricore_trapinit(void); /* Context Save Areas *******************************************************/ @@ -193,39 +150,34 @@ uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp, uintptr_t psw, bool irqsave); void tricore_reclaim_csa(uintptr_t pcxi); -/* Low level serial output **************************************************/ - -void tricore_lowputc(char ch); -void tricore_lowputs(const char *str); - -#ifdef USE_SERIALDRIVER -void tricore_serialinit(void); -#endif +/* Debug ********************************************************************/ -#ifdef USE_EARLYSERIALINIT -void tricore_earlyserialinit(void); +#ifdef CONFIG_STACK_COLORATION +size_t tricore_stack_check(uintptr_t alloc, size_t size); +void tricore_stack_color(void *stackbase, size_t nbytes); #endif -/* FPU **********************************************************************/ +void tricore_endinit_disable(void); +void tricore_endinit_enable(void); +void tricore_safety_endinit_enable(void); +void tricore_wdt_disable(void); +void up_clockconfig(void); -#ifdef CONFIG_ARCH_HAVE_FPU -void tricore_fpuinit(void); +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) +void aurix_cpu_endinit_enable(bool enable); +void aurix_safety_endinit_enable(bool enable); #endif -#ifdef CONFIG_ARCH_HAVE_DEBUG -int tricore_init_dbgmonitor(void); -#endif - -/* System Timer *************************************************************/ +void aurix_earlyserialinit(void); +void aurix_serialinit(void); -struct oneshot_lowerhalf_s * -tricore_systimer_initialize(volatile void *tbase, int irq, uint64_t freq); - -/* Debug ********************************************************************/ +void board_aurix_setup_serial_pin(int idx); -#ifdef CONFIG_STACK_COLORATION -size_t tricore_stack_check(uintptr_t alloc, size_t size); -void tricore_stack_color(void *stackbase, size_t nbytes); +#ifdef CONFIG_TRICORE_FLASH_MTD +struct mtd_dev_s; +struct mtd_dev_s *tricore_flash_initialize(void); +void tricore_flash_get_last_dmu_state(uint32_t *err, uint32_t *status, + uint32_t *phase); #endif #endif /* __ARCH_TRICORE_SRC_COMMON_TRICORE_INTERNAL_H */ diff --git a/arch/tricore/src/common/tricore_interrupt.S b/arch/tricore/src/common/tricore_interrupt.S new file mode 100644 index 0000000000000..cbfe5f86fa7ac --- /dev/null +++ b/arch/tricore/src/common/tricore_interrupt.S @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_interrupt.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + .section .ivtab, "ax", %progbits + .globl biv_vector + .type biv_vector, %object + .p2align 5 + +biv_vector: + .set N, 255 + + .rept N +1: + svlcx + j _isr_wrapper + + .space (32 - (.-1b)) + .endr + +_isr_wrapper: + mov %d14, lo:TRICORE_IR_LASR_ADDR + addih %d14, %d14, hi:TRICORE_IR_LASR_ADDR + + mfcr %d15, TRICORE_CPU_CORE_ID + extr.u %d15, %d15, 0, 3 + madd %d14, %d14, %d15, TRICORE_IR_LASR_TOS_STRIDE + + mov.a %a2, %d14 + ld.w %d15, [%a2] + extr.u %d15, %d15, 16, TRICORE_IR_LASR_PIPN_WIDTH + + mov %d4, %d15 + movh.a %a14, hi:tricore_isr_handler + lea %a14, [%a14]lo:tricore_isr_handler + ji %a14 diff --git a/arch/tricore/src/common/tricore_irq.c b/arch/tricore/src/common/tricore_irq.c index 072e33ab18a43..5be235d742c54 100644 --- a/arch/tricore/src/common/tricore_irq.c +++ b/arch/tricore/src/common/tricore_irq.c @@ -28,266 +28,104 @@ #include #include -#include +#include #include +#include #include -#include +#include +#include "tricore_irq.h" #include "tricore_internal.h" -#include "IfxSrc.h" -#include "IfxCpu.h" -#include "IfxInt_reg.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** - * Name: tricore_color_intstack - * - * Description: - * Set the interrupt stack to a value so that later we can determine how - * much stack space was used by interrupt handling logic - * + * Public Functions ****************************************************************************/ -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 -static inline void tricore_color_intstack(void) +static inline uint32_t tricore_srcr_read(int irq) { - uint32_t *ptr = (uint32_t *)g_intstackalloc; - ssize_t size; - - for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); - size > 0; - size -= sizeof(uint32_t)) - { - *ptr++ = INTSTACK_COLOR; - } + return getreg32(TRICORE_IR_GET_SRC(irq)); } -#else -# define tricore_color_intstack() -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ -static spinlock_t g_irqlock = SP_UNLOCKED; -static int g_irqmap_count = 1; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#ifdef CONFIG_ARCH_HAVE_IRQTRIGGER -/**************************************************************************** - * Name: tricore_gpsrinitialize - * - * Description: - * Perform gpsr initialization for the CPU - * - ****************************************************************************/ - -static void tricore_gpsrinitialize(void) +static inline void tricore_srcr_write(int irq, uint32_t val) { - volatile Ifx_SRC_SRCR *src = &SRC_GPSR00 + up_cpu_index(); - int i; - - /* Cpux gpsr init */ - - for (i = 0; i < 6; i++) - { -#ifdef CONFIG_ARCH_CHIP_TC3XX - IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(), - IRQ_TO_NDX(TRICORE_SRC2IRQ(src))); -#else - IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(), - IRQ_TO_NDX(TRICORE_SRC2IRQ(src)), - IfxSrc_VmId_none); -#endif - - src += TRICORE_SRCNUM_PER_GPSR; - } - - /* Cpucs gpsr init */ - -#ifndef CONFIG_ARCH_CHIP_TC3XX - src = &SRC_GPSR6_SR0 + up_cpu_index(); - IfxSrc_init(src, IfxSrc_Tos_cpu0 + up_cpu_index(), - IRQ_TO_NDX(TRICORE_SRC2IRQ(src)), - IfxSrc_VmId_none); -#endif + putreg32(val, TRICORE_IR_GET_SRC(irq)); } -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irq_enable - * - * Description: - * Enable interrupts globally. - * - ****************************************************************************/ void up_irq_enable(void) { - IfxCpu_enableInterrupts(); + TRICORE_IRQ_ENABLE(); } -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - void up_irqinitialize(void) { -#ifdef CONFIG_ARCH_HAVE_IRQTRIGGER - tricore_gpsrinitialize(); -#endif - - tricore_color_intstack(); - up_irq_enable(); + TRICORE_IRQ_ENABLE(); } -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - void up_disable_irq(int irq) { - volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; - Ifx_SRC_SRCR srctmp; + uint32_t regval = tricore_srcr_read(irq); - IfxSrc_disable(src); - - /* Clear, keep SRPN */ - - srctmp.U = 0U; - srctmp.B.TOS = ~0; - srctmp.B.SRPN = src->B.SRPN; - src->U = srctmp.U; + regval &= ~SRCR_SRE; + tricore_srcr_write(irq, regval); } -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - void up_enable_irq(int irq) { - volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; - -#ifdef CONFIG_ARCH_CHIP_TC3XX - IfxSrc_init(src, IfxSrc_Tos_cpu0, IRQ_TO_NDX(irq)); -#else - IfxSrc_init(src, IfxSrc_Tos_cpu0, IRQ_TO_NDX(irq), IfxSrc_VmId_none); -#endif - - IfxSrc_enable(src); -} - -/**************************************************************************** - * Name: up_affinity_irq - * - * Description: - * Set an IRQ affinity by software. - * - ****************************************************************************/ - -void up_affinity_irq(int irq, cpu_set_t cpuset) -{ - volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; - int irq_prio = src->B.SRPN; - - IfxSrc_disable(src); + uint32_t regval = tricore_srcr_read(irq); - /* Only support interrupt routing mode 0, - * so routing to the first cpu in cpuset. - */ + regval |= SRCR_CLRR | SRCR_IOVCLR; -#ifdef CONFIG_ARCH_CHIP_TC3XX - IfxSrc_init(src, ffs(cpuset) - 1, irq_prio); -#else - IfxSrc_init(src, ffs(cpuset) - 1, irq_prio, IfxSrc_VmId_none); +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) + regval |= SRCR_SWSCLR; #endif - IfxSrc_enable(src); -} + regval &= ~SRCR_SRPN_MASK; + regval |= ((uint32_t)irq << SRCR_SRPN_SHIFT) & SRCR_SRPN_MASK; -/**************************************************************************** - * Name: tricore_ack_irq - * - * Description: - * Acknowledge the IRQ - * - ****************************************************************************/ + regval &= ~SRCR_TOS_MASK; + regval |= (TRICORE_DEFAULT_IR_TOS << SRCR_TOS_SHIFT) & SRCR_TOS_MASK; -void tricore_ack_irq(int irq) -{ - volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; - IfxSrc_clearRequest(src); + regval |= SRCR_SRE; + tricore_srcr_write(irq, regval); } #ifdef CONFIG_ARCH_HAVE_IRQTRIGGER -/**************************************************************************** - * Name: up_trigger_irq - * - * Description: - * Trigger an IRQ by software. May not be supported by all architectures. - * - ****************************************************************************/ - void up_trigger_irq(int irq, cpu_set_t cpuset) { - volatile Ifx_INT_SRB *srb = &INT_SRB0 + up_cpu_index(); - srb->U = cpuset; + uint32_t regval; + + (void)cpuset; + + regval = tricore_srcr_read(irq); + regval |= SRCR_SETR; + tricore_srcr_write(irq, regval); } -#endif -/**************************************************************************** - * Name: up_irq_to_ndx - * - * Description: - * Irq to ndx - * - ****************************************************************************/ +#endif /* CONFIG_ARCH_HAVE_IRQTRIGGER */ -int up_irq_to_ndx(int irq) +void up_affinity_irq(int irq, cpu_set_t cpuset) { - volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; - Ifx_SRC_SRCR srctmp; - irqstate_t flags; - int ndx; + uint32_t regval; + + up_disable_irq(irq); - ndx = src->B.SRPN; - if (ndx != 0) - { - return ndx; - } + regval = tricore_srcr_read(irq); + regval &= ~SRCR_TOS_MASK; + regval |= ((uint32_t)cpuset << SRCR_TOS_SHIFT) & SRCR_TOS_MASK; + tricore_srcr_write(irq, regval); - flags = spin_lock_irqsave(&g_irqlock); - ndx = src->B.SRPN; - if (ndx == 0) - { - ndx = g_irqmap_count++; - g_irqrevmap[ndx] = irq; - srctmp.U = src->U; - srctmp.B.SRPN = ndx; - src->U = srctmp.U; - } + up_enable_irq(irq); +} + +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regval; - spin_unlock_irqrestore(&g_irqlock, flags); + regval = tricore_srcr_read(irq); + regval &= ~SRCR_SRPN_MASK; + regval |= ((uint32_t)priority << SRCR_SRPN_SHIFT) & SRCR_SRPN_MASK; + tricore_srcr_write(irq, regval); - return ndx; + return 0; } diff --git a/arch/tricore/src/common/tricore_irq.h b/arch/tricore/src/common/tricore_irq.h new file mode 100644 index 0000000000000..159d47a5c78ce --- /dev/null +++ b/arch/tricore/src/common/tricore_irq.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_COMMON_TRICORE_IRQ_H +#define __ARCH_TRICORE_SRC_COMMON_TRICORE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NR_IRQS 2048 + +#define TRICORE_DEFAULT_IR_PRIO 255 +#define TRICORE_DEFAULT_IR_TOS 0 + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) +# define TRICORE_IR_INT_BASE 0xf4430000 +# define TRICORE_IR_SRC_BASE 0xf4432000 +# define TRICORE_STM_BASE_SRN 8 +#elif defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) +# define TRICORE_IR_INT_BASE 0xf0037000 +# define TRICORE_IR_SRC_BASE 0xf0038000 +# define TRICORE_STM_BASE_SRN 192 +#endif + +#define TRICORE_IR_GET_SRC(irq) (TRICORE_IR_SRC_BASE + ((irq) * 4)) + +#define SRCR_SRPN_SHIFT 0 +#define SRCR_SRPN_MASK (0xff << SRCR_SRPN_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) + +# define SRCR_VM_SHIFT 8 +# define SRCR_VM_MASK (0x7 << SRCR_VM_SHIFT) + +# define SRCR_CS BIT(11) + +# define SRCR_TOS_SHIFT 12 +# define SRCR_TOS_MASK (0xf << SRCR_TOS_SHIFT) + +# define SRCR_SRE BIT(23) +# define SRCR_SRR BIT(24) +# define SRCR_CLRR BIT(25) +# define SRCR_SETR BIT(26) +# define SRCR_IOV BIT(27) +# define SRCR_IOVCLR BIT(28) + +# define TRICORE_IR_LASR_OFFSET 0x0c20 +# define TRICORE_IR_LASR_STRIDE 0x34 +# define TRICORE_IR_LASR_PIPN_SHIFT 16 +# define TRICORE_IR_LASR_PIPN_MASK (0x7ff << TRICORE_IR_LASR_PIPN_SHIFT) + +# define TRICORE_IR_GET_TOS(coreid) (coreid) + +#elif defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) + +# define SRCR_SRE (1u << 10) + +# define SRCR_TOS_SHIFT 11 +# define SRCR_TOS_MASK (0x7 << SRCR_TOS_SHIFT) + +# define SRCR_ECC_SHIFT 16 +# define SRCR_ECC_MASK (0x1f << SRCR_ECC_SHIFT) + +# define SRCR_SRR BIT(24) +# define SRCR_CLRR BIT(25) +# define SRCR_SETR BIT(26) +# define SRCR_IOV BIT(27) +# define SRCR_IOVCLR BIT(28) +# define SRCR_SWS BIT(29) +# define SRCR_SWSCLR BIT(30) + +# define TRICORE_IR_LASR_OFFSET 0x204 +# define TRICORE_IR_LASR_STRIDE 0x10 +# define TRICORE_IR_LASR_PIPN_SHIFT 16 +# define TRICORE_IR_LASR_PIPN_MASK (0x3ff << TRICORE_IR_LASR_PIPN_SHIFT) + +# define TRICORE_IR_GET_TOS(coreid) ((coreid) == 0 ? 0 : (coreid) + 1) + +#endif + +#define TRICORE_IR_LASR(tos) \ + (TRICORE_IR_INT_BASE + TRICORE_IR_LASR_OFFSET + \ + ((tos) * TRICORE_IR_LASR_STRIDE)) + +#define TRICORE_STM_IR_OFFSET 0x20 +#define TRICORE_STM_IR_CPUw_SRx(w, x) \ + (TRICORE_IR_SRC_BASE + TRICORE_STM_IR_OFFSET + \ + ((w) * 0x40) + ((x) * 0x4)) +#define TRICORE_STM_IR_CPU0_SR(x) TRICORE_STM_IR_CPUw_SRx(0, (x)) +#define TRICORE_STM_IR_SRN(x) (TRICORE_STM_BASE_SRN + (x)) + +#endif /* __ARCH_TRICORE_SRC_COMMON_TRICORE_IRQ_H */ diff --git a/arch/tricore/src/common/tricore_lib.S b/arch/tricore/src/common/tricore_lib.S new file mode 100644 index 0000000000000..5d0215d5565f3 --- /dev/null +++ b/arch/tricore/src/common/tricore_lib.S @@ -0,0 +1,174 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_lib.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + + .global tricore_endinit_disable + .global tricore_endinit_enable + .global tricore_safety_endinit_enable + +#if defined(CONFIG_TRICORE_TC18) +#define CPU_PROTSFR 0xF880E080 + + .type tricore_endinit_disable, %function +tricore_endinit_disable: + mfcr %d4, TRICORE_CPU_CORE_ID + extr.u %d4, %d4, 0, 3 + sh %d4, %d4, 18 + movh.a %a15, hi:CPU_PROTSFR + lea %a15, [%a15], lo:CPU_PROTSFR + addsc.a %a15, %a15, %d4, 0 + + ld.w %d15, [%a15] + extr.u %d15, %d15, 0, 3 + jlt.u %d15, 3, already_config + + /* Transition: Run -> Config (unlock) */ + insert %d15, %d15, 9, 0, 16 + st.w [%a15], %d15 + dsync + +already_config: + ji %a11 + + .type tricore_endinit_enable, %function +tricore_endinit_enable: + mfcr %d4, TRICORE_CPU_CORE_ID + extr.u %d4, %d4, 0, 3 + sh %d4, %d4, 18 + movh.a %a15, hi:CPU_PROTSFR + lea %a15, [%a15], lo:CPU_PROTSFR + addsc.a %a15, %a15, %d4, 0 + + ld.w %d15, [%a15] + extr.u %d15, %d15, 0, 3 + jge.u %d15, 2, already_locked + + /* Transition: Config -> Run (lock) */ + insert %d15, %d15, 12, 0, 16 + st.w [%a15], %d15 + dsync + +already_locked: + ji %a11 + + .type tricore_safety_endinit_enable, %function +tricore_safety_endinit_enable: + ji %a11 + + /* Virtualization disable */ + + .global tricore_virt_disable + .type tricore_virt_disable, %function +tricore_virt_disable: + mov %d15, 0 + mtcr TRICORE_CPU_VCON0, %d15 + + mov %d15, 0xB00 + mtcr TRICORE_CPU_PSW, %d15 + isync + + rfh + +#else /* TC1.6 (AURIX TC3x) */ + +/* TC1.6 (AURIX TC3x) -- WDT-based endinit */ + +#define SCU_BASE 0xF0036000 +#define WDTCPU0CON0 (SCU_BASE + 0x024C) +#define WDTSCON0 (SCU_BASE + 0x02A8) + + .type tricore_endinit_disable, %function +tricore_endinit_disable: + mfcr %d4, TRICORE_CPU_CORE_ID + extr.u %d4, %d4, 0, 3 + jne %d4, 6, 1f + mov %d4, 5 +1: + sh %d5, %d4, 1 + add %d4, %d5, %d4 + movh.a %a15, hi:WDTCPU0CON0 + lea %a15, [%a15], lo:WDTCPU0CON0 + addsc.a %a15, %a15, %d4, 2 + + /* Read current WDT register, invert password bits */ + ld.w %d15, [%a15] + xor %d15, %d15, 0xFC + + insert %d15, %d15, 1, 0, 2 + st.w [%a15], %d15 + + insert %d15, %d15, 2, 0, 2 + st.w [%a15], %d15 + dsync + + ji %a11 + + .type tricore_endinit_enable, %function +tricore_endinit_enable: + mfcr %d4, TRICORE_CPU_CORE_ID + extr.u %d4, %d4, 0, 3 + jne %d4, 6, 1f + mov %d4, 5 +1: + sh %d5, %d4, 1 + add %d4, %d5, %d4 + movh.a %a15, hi:WDTCPU0CON0 + lea %a15, [%a15], lo:WDTCPU0CON0 + addsc.a %a15, %a15, %d4, 2 + + /* Read current WDT register, invert password bits */ + ld.w %d15, [%a15] + xor %d15, %d15, 0xFC + + insert %d15, %d15, 1, 0, 2 + st.w [%a15], %d15 + + insert %d15, %d15, 3, 0, 2 + st.w [%a15], %d15 + dsync + + ji %a11 + + .type tricore_safety_endinit_enable, %function +tricore_safety_endinit_enable: + mfcr %d4, TRICORE_CPU_CORE_ID + extr.u %d4, %d4, 0, 3 + jnz %d4, _safety_endinit_skip + + movh.a %a15, hi:WDTSCON0 + lea %a15, [%a15], lo:WDTSCON0 + + ld.w %d15, [%a15] + xor %d15, %d15, 0xFC + + insert %d15, %d15, 1, 0, 2 + st.w [%a15], %d15 + + insert %d15, %d15, 3, 0, 2 + st.w [%a15], %d15 + dsync + +_safety_endinit_skip: + ji %a11 + +#endif /* CONFIG_TRICORE_TC18 */ diff --git a/arch/tricore/src/common/tricore_nputs.c b/arch/tricore/src/common/tricore_nputs.c index 32e1557b91206..7d5ed5f56f396 100644 --- a/arch/tricore/src/common/tricore_nputs.c +++ b/arch/tricore/src/common/tricore_nputs.c @@ -26,11 +26,17 @@ #include #include +#include /**************************************************************************** * Public Functions ****************************************************************************/ +void weak_function up_putc(int ch) +{ + (void)ch; +} + /**************************************************************************** * Name: up_nputs * diff --git a/arch/tricore/src/common/tricore_registerdump.c b/arch/tricore/src/common/tricore_registerdump.c index 44ff3aa8bdfd2..22c90296248da 100644 --- a/arch/tricore/src/common/tricore_registerdump.c +++ b/arch/tricore/src/common/tricore_registerdump.c @@ -28,10 +28,11 @@ #include #include -#include +#include #include #include +#include #include "tricore_internal.h" @@ -39,108 +40,52 @@ * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: tricore_dump_upcsa - ****************************************************************************/ - -void tricore_dump_upcsa(volatile uint32_t *regs) -{ - _alert("UPCXI:%-13.8" PRIX32 "PSW:%-15.8" PRIX32 - "SP:%-16.8" PRIX32 "A11:%-15.8" PRIX32 "\n", - regs[REG_UPCXI], regs[REG_PSW], regs[REG_A10], regs[REG_UA11]); - _alert("D8:%-16.8" PRIX32 "D9:%-16.8" PRIX32 - "D10:%-15.8" PRIX32 "D11:%-15.8" PRIX32 "\n", - regs[REG_D8], regs[REG_D9], regs[REG_D10], regs[REG_D11]); - _alert("A12:%-15.8" PRIX32 "A13:%-15.8" PRIX32 - "A14:%-15.8" PRIX32 "A15:%-15.8" PRIX32 "\n", - regs[REG_A12], regs[REG_A13], regs[REG_A14], regs[REG_A15]); - _alert("D12:%-15.8" PRIX32 "D13:%-15.8" PRIX32 - "D14:%-15.8" PRIX32 "D15:%-15.8" PRIX32 "\n\n", - regs[REG_D12], regs[REG_D13], regs[REG_D14], regs[REG_D15]); -} - -/**************************************************************************** - * Name: tricore_dump_lowcsa - ****************************************************************************/ - -void tricore_dump_lowcsa(volatile uint32_t *regs) -{ - _alert("LPCXI:%-13.8" PRIX32 "PC:%-16.8" PRIX32 - "A2:%-16.8" PRIX32 "A3:%-16.8" PRIX32 "\n", - regs[REG_LPCXI] | PCXI_UL, regs[REG_LA11], - regs[REG_A2], regs[REG_A3]); - _alert("D0:%-16.8" PRIX32 "D1:%-16.8" PRIX32 - "D2:%-16.8" PRIX32 "D3:%-16.8" PRIX32 "\n", - regs[REG_D0], regs[REG_D1], regs[REG_D2], regs[REG_D3]); - _alert("A4:%-16.8" PRIX32 "A5:%-16.8" PRIX32 - "A6:%-16.8" PRIX32 "A7:%-16.8" PRIX32 "\n", - regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]); - _alert("D4:%-16.8" PRIX32 "D5:%-16.8" PRIX32 - "D6:%-16.8" PRIX32 "D7:%-16.8" PRIX32 "\n\n", - regs[REG_D4], regs[REG_D5], regs[REG_D6], regs[REG_D7]); -} - -/**************************************************************************** - * Name: tricore_dump_trapctrl - ****************************************************************************/ - -void tricore_dump_trapctrl(void) -{ - _alert("PSTR:%-14.8" PRIX32 "DSTR:%-14.8" PRIX32 - "DATR:%-14.8" PRIX32 "DEADD:%-13.8" PRIX32 "\n\n", - (uint32_t)__mfcr(CPU_PSTR), (uint32_t)__mfcr(CPU_DSTR), - (uint32_t)__mfcr(CPU_DATR), (uint32_t)__mfcr(CPU_DEADD)); -} - -/**************************************************************************** - * Name: tricore_dump_csachain - ****************************************************************************/ - -void tricore_dump_csachain(uintptr_t pcxi) -{ - while (pcxi & FCX_FREE) - { - if (pcxi & PCXI_UL) - { - tricore_dump_upcsa((uint32_t *)tricore_csa2addr(pcxi)); - } - else - { - tricore_dump_lowcsa((uint32_t *)tricore_csa2addr(pcxi)); - } - - pcxi = tricore_csa2addr(pcxi)[0]; - } -} - /**************************************************************************** * Name: up_dump_register + * + * Description: + * Dump the contents of all general-purpose registers from the saved + * context. The supplied pointer points at the lower CSA captured by + * svlcx in the trap entry path. The upper CSA (containing a10-a15, + * d8-d15, PSW) is reached through the PCXI chain field of the lower + * CSA. + * ****************************************************************************/ void up_dump_register(void *dumpregs) { - volatile uint32_t *regs = dumpregs; - - tricore_dump_lowcsa(regs); + uintptr_t *lower = dumpregs; + uintptr_t *upper; - tricore_dump_upcsa(regs + TC_CONTEXT_REGS); - - tricore_dump_trapctrl(); -} - -/**************************************************************************** - * Name: up_regs_memcpy - ****************************************************************************/ - -void up_regs_memcpy(FAR void *dest, FAR void *src, size_t count) -{ - int csa_size = TC_CONTEXT_REGS * sizeof(uintptr_t); - int csa_num = count / csa_size; - - while (csa_num--) + if (lower == NULL) { - memcpy(dest, src, csa_size); - dest = (char *)dest + csa_size; - src = tricore_csa2addr(((uintptr_t *)src)[REG_LPCXI]); + return; } + + upper = tricore_csa2addr(lower[REG_LPCXI]); + + lowsyslog("A2: %08lx A3: %08lx A4: %08lx A5: %08lx\n", + (unsigned long)lower[REG_A2], (unsigned long)lower[REG_A3], + (unsigned long)lower[REG_A4], (unsigned long)lower[REG_A5]); + lowsyslog("A6: %08lx A7: %08lx A10: %08lx A11: %08lx\n", + (unsigned long)lower[REG_A6], (unsigned long)lower[REG_A7], + (unsigned long)upper[REG_A10], (unsigned long)upper[REG_UA11]); + lowsyslog("A12: %08lx A13: %08lx A14: %08lx A15: %08lx\n", + (unsigned long)upper[REG_A12], (unsigned long)upper[REG_A13], + (unsigned long)upper[REG_A14], (unsigned long)upper[REG_A15]); + lowsyslog("D0: %08lx D1: %08lx D2: %08lx D3: %08lx\n", + (unsigned long)lower[REG_D0], (unsigned long)lower[REG_D1], + (unsigned long)lower[REG_D2], (unsigned long)lower[REG_D3]); + lowsyslog("D4: %08lx D5: %08lx D6: %08lx D7: %08lx\n", + (unsigned long)lower[REG_D4], (unsigned long)lower[REG_D5], + (unsigned long)lower[REG_D6], (unsigned long)lower[REG_D7]); + lowsyslog("D8: %08lx D9: %08lx D10: %08lx D11: %08lx\n", + (unsigned long)upper[REG_D8], (unsigned long)upper[REG_D9], + (unsigned long)upper[REG_D10], (unsigned long)upper[REG_D11]); + lowsyslog("D12: %08lx D13: %08lx D14: %08lx D15: %08lx\n", + (unsigned long)upper[REG_D12], (unsigned long)upper[REG_D13], + (unsigned long)upper[REG_D14], (unsigned long)upper[REG_D15]); + lowsyslog("PC: %08lx SP: %08lx PSW: %08lx PCXI:%08lx\n", + (unsigned long)upper[REG_UPC], (unsigned long)upper[REG_SP], + (unsigned long)upper[REG_PSW], (unsigned long)upper[REG_UPCXI]); } diff --git a/arch/tricore/src/common/tricore_releasestack.c b/arch/tricore/src/common/tricore_releasestack.c index 2ed948a62f0e5..bd70973a48f9b 100644 --- a/arch/tricore/src/common/tricore_releasestack.c +++ b/arch/tricore/src/common/tricore_releasestack.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/arch/tricore/src/common/tricore_saveusercontext.c b/arch/tricore/src/common/tricore_saveusercontext.c index 25a46f8201753..18e32f6e63925 100644 --- a/arch/tricore/src/common/tricore_saveusercontext.c +++ b/arch/tricore/src/common/tricore_saveusercontext.c @@ -26,16 +26,16 @@ #include +#include + +#include + #include "tricore_internal.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -51,29 +51,10 @@ int up_saveusercontext(void *saveregs) { uintptr_t *regs; - uintptr_t pcxi; - int csa_size = TC_CONTEXT_REGS * sizeof(uintptr_t); - - pcxi = __mfcr(CPU_PCXI); - regs = tricore_csa2addr(pcxi); - memcpy((char *)saveregs + csa_size, regs, csa_size); - - /* to unify the trap processing, extra save lowcsa */ - - __asm("svlcx"); - - regs = tricore_csa2addr(__mfcr(CPU_PCXI)); - memcpy(saveregs, regs, csa_size); - - /* lowcsa[REG_LPCXI] saves the upcsa's pcxi, but if lowcsa and upcsa is - * stored at continuous addresses, pcxi has no meaning. Use PCXI_UL - * without marking whether it is lowcsa or upcsa, but to mark whether - * lowcsa and upcsa is stored at continuous addresses. - */ - - ((uintptr_t *)saveregs)[REG_LPCXI] = pcxi & (~PCXI_UL); - - __asm("rslcx"); + uint32_t val; + TRICORE_MFCR(TRICORE_CPU_FCX, val); + regs = tricore_csa2addr(val); + memcpy(saveregs, regs, XCPTCONTEXT_SIZE); return 0; } diff --git a/arch/tricore/src/common/tricore_schedulesigaction.c b/arch/tricore/src/common/tricore_schedulesigaction.c index 1912371318706..ffac299f1ac3b 100644 --- a/arch/tricore/src/common/tricore_schedulesigaction.c +++ b/arch/tricore/src/common/tricore_schedulesigaction.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include @@ -80,19 +80,79 @@ void up_schedule_sigaction(struct tcb_s *tcb) { - /* Save the context registers. These will be - * restored by the signal trampoline after the signals have - * been delivered. + /* First, handle some special cases when the signal is + * being delivered to the currently executing task. */ - tcb->xcp.saved_regs = tcb->xcp.regs; + if (tcb == this_task()) + { + /* CASE 1: We are not in an interrupt handler and + * a task is signalling itself for some reason. + */ - /* Create a new CSA for signal delivery. The new context - * will borrow the process stack of the current tcb. + if (up_current_regs() == NULL) + { + /* In this case just deliver the signal now. */ + + (tcb->sigdeliver)(tcb); + tcb->sigdeliver = NULL; + } + + /* CASE 2: We are in an interrupt handler AND the + * interrupted task is the same as the one that + * must receive the signal, then we will have to modify + * the return state as well as the state in the TCB. + * + * Hmmm... there looks like a latent bug here: The following + * logic would fail in the strange case where we are in an + * interrupt handler, the thread is signalling itself, but + * a context switch to another task has occurred so that + * g_current_regs does not refer to the thread of this_task()! + */ + + else + { + /* Save the context registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tricore_savestate(tcb->xcp.saved_regs); + + /* Create a new CSA for signal delivery. The new context + * will borrow the process stack of the current tcb. + */ + + up_set_current_regs(tricore_alloc_csa((uintptr_t) + tricore_sigdeliver, + STACK_ALIGN_DOWN(up_getusrsp(tcb->xcp.regs)), + PSW_IO_SUPERVISOR | PSW_CDE, true)); + } + } + + /* Otherwise, we are (1) signaling a task is not running + * from an interrupt handler or (2) we are not in an + * interrupt handler and the running task is signalling + * some non-running task. */ - tcb->xcp.regs = tricore_alloc_csa((uintptr_t)tricore_sigdeliver, - STACKFRAME_ALIGN_DOWN - (up_getusrsp(tcb->xcp.regs)), - PSW_IO_SUPERVISOR | PSW_CDE, true); + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + /* Save the current register context location */ + + tcb->xcp.saved_regs = tcb->xcp.regs; + + /* Create a new CSA for signal delivery. The new context + * will borrow the process stack of the current tcb. + */ + + tcb->xcp.regs = tricore_alloc_csa((uintptr_t)tricore_sigdeliver, + STACK_ALIGN_DOWN(up_getusrsp(tcb->xcp.regs)), + PSW_IO_SUPERVISOR | PSW_CDE, true); + } } diff --git a/arch/tricore/src/common/tricore_sigdeliver.c b/arch/tricore/src/common/tricore_sigdeliver.c index c2e7e8c8e8c5a..cc29a06ea2922 100644 --- a/arch/tricore/src/common/tricore_sigdeliver.c +++ b/arch/tricore/src/common/tricore_sigdeliver.c @@ -29,12 +29,11 @@ #include #include #include +#include -#include #include #include #include -#include #include "sched/sched.h" #include "tricore_internal.h" @@ -116,6 +115,5 @@ void tricore_sigdeliver(void) board_autoled_off(LED_SIGNAL); - rtcb->xcp.regs = regs; - tricore_fullcontextrestore(); + tricore_fullcontextrestore(regs); } diff --git a/arch/tricore/src/common/tricore_stackframe.c b/arch/tricore/src/common/tricore_stackframe.c index 95e3fce96f8d8..da553c93ec404 100644 --- a/arch/tricore/src/common/tricore_stackframe.c +++ b/arch/tricore/src/common/tricore_stackframe.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include @@ -76,7 +76,7 @@ void *up_stack_frame(struct tcb_s *tcb, size_t frame_size) /* Align the frame_size */ - frame_size = STACKFRAME_ALIGN_UP(frame_size); + frame_size = STACK_ALIGN_UP(frame_size); /* Is there already a stack allocated? Is it big enough? */ diff --git a/arch/tricore/src/common/tricore_svcall.c b/arch/tricore/src/common/tricore_svcall.c index 02a639038b9a0..36ebf40791f69 100644 --- a/arch/tricore/src/common/tricore_svcall.c +++ b/arch/tricore/src/common/tricore_svcall.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include @@ -56,53 +56,73 @@ void tricore_svcall(volatile void *trap) { - struct tcb_s **running_task = &g_running_tasks[this_cpu()]; - struct tcb_s *tcb = this_task(); + uintptr_t pcxi; uintptr_t *regs; uint32_t cmd; - regs = (uintptr_t *)__mfcr(CPU_PCXI); + TRICORE_MFCR(TRICORE_CPU_PCXI, pcxi) - /* DSYNC instruction should be executed immediately prior to the MTCR */ + regs = tricore_csa2addr(pcxi); - __dsync(); - - regs = tricore_csa2addr((uintptr_t)regs); - - /* Set irq flag */ - - up_set_interrupt_context(true); + up_set_current_regs(regs); cmd = regs[REG_D8]; - if (cmd != SYS_restore_context) - { - (*running_task)->xcp.regs = tricore_csa2addr(regs[REG_UPCXI]); - } - else - { - tricore_reclaim_csa(regs[REG_UPCXI]); - } - /* Handle the SVCall according to the command in R0 */ switch (cmd) { - case SYS_switch_context: - nxsched_switch_context(*running_task, tcb); + /* R0=SYS_restore_context: This a restore context command: + * + * void tricore_fullcontextrestore(uint32_t *restoreregs) + * noreturn_function; + * + * At this point, the following values are saved in context: + * + * R0 = SYS_restore_context + * R1 = restoreregs + * + * In this case, we simply need to set g_current_regs to restore + * register area referenced in the saved R1. context == g_current_regs + * is the normal exception return. By setting g_current_regs = + * context[R1], we force the return to the saved context referenced + * in R1. + */ case SYS_restore_context: - *running_task = tcb; - regs[REG_UPCXI] = tricore_addr2csa(tcb->xcp.regs); - __isync(); + { + tricore_reclaim_csa(regs[REG_UPCXI]); + up_set_current_regs((uintptr_t *)regs[REG_D9]); + } + break; + + case SYS_switch_context: + { + *(uintptr_t **)regs[REG_D9] = (uintptr_t *)regs[REG_UPCXI]; + up_set_current_regs((uintptr_t *)regs[REG_D10]); + } break; default: - svcerr("ERROR: Bad SYS call: %d\n", (int)regs[REG_D0]); + { + svcerr("ERROR: Bad SYS call: %d\n", (int)regs[REG_D0]); + } break; } - /* Set irq flag */ + if (regs != up_current_regs()) + { + /* Record the new "running" task when context switch occurred. + * g_running_tasks[] is only used by assertion logic for reporting + * crashes. + */ + + g_running_tasks[this_cpu()] = this_task(); + + regs[REG_UPCXI] = (uintptr_t)up_current_regs(); + + __asm__ __volatile__ ("isync" : : : "memory"); + } - up_set_interrupt_context(false); + up_set_current_regs(NULL); } diff --git a/arch/tricore/src/common/tricore_switchcontext.c b/arch/tricore/src/common/tricore_switchcontext.c index 5fb7ad5112fb8..47aefd036eb54 100644 --- a/arch/tricore/src/common/tricore_switchcontext.c +++ b/arch/tricore/src/common/tricore_switchcontext.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include @@ -59,10 +59,39 @@ void up_switch_context(struct tcb_s *tcb, struct tcb_s *rtcb) { - if (!up_interrupt_context()) + /* Are we in an interrupt handler? */ + + if (up_current_regs()) { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + tricore_savestate(rtcb->xcp.regs); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + tricore_restorestate(tcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Update scheduler parameters */ + + nxsched_switch_context(rtcb, tcb); + /* Then switch contexts */ tricore_switchcontext(&rtcb->xcp.regs, tcb->xcp.regs); + + /* tricore_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ } } diff --git a/arch/tricore/src/common/tricore_testset.c b/arch/tricore/src/common/tricore_testset.c index e660ad72d80ba..67f033f42e2c6 100644 --- a/arch/tricore/src/common/tricore_testset.c +++ b/arch/tricore/src/common/tricore_testset.c @@ -35,6 +35,24 @@ * Public Functions ****************************************************************************/ +/* Atomic compare-and-swap helper using the TriCore cmpswap.w instruction. + * If *address equals condition, the swap happens; in either case the + * previous value of *address is returned. + */ + +inline unsigned int tricore_cmpswap(unsigned int volatile *address, + unsigned int value, + unsigned int condition) +{ + unsigned long long reg64 = value | (unsigned long long)condition << 32; + + __asm__ __volatile__ ("cmpswap.w [%[addr]]0, %A[reg]" + : [reg] "+d" (reg64) + : [addr] "a" (address) + : "memory"); + return reg64; +} + /**************************************************************************** * Name: up_testset * @@ -58,6 +76,5 @@ spinlock_t up_testset(volatile spinlock_t *lock) { /* Perform the compare and set operation */ - return Ifx__cmpAndSwap((volatile void *)lock, SP_LOCKED, SP_UNLOCKED); + return tricore_cmpswap((volatile void *)lock, SP_LOCKED, SP_UNLOCKED); } - diff --git a/arch/tricore/src/common/tricore_trap.S b/arch/tricore/src/common/tricore_trap.S new file mode 100644 index 0000000000000..58d3c8c8c615b --- /dev/null +++ b/arch/tricore/src/common/tricore_trap.S @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_trap.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + + .section .traptab, "ax", %progbits + .global btv_vector + .type btv_vector, %object + .p2align 8 + + .macro TRAP_SLOT I, handler +1: + mov %d4, \I + mov %d5, %d15 + movh.a %a2, hi:\handler + lea %a2, [%a2]lo:\handler + ji %a2 + .space (32 - (.-1b)) + .endm + +btv_vector: + TRAP_SLOT 0, tricore_trap_dispatch + TRAP_SLOT 1, tricore_trap_dispatch + TRAP_SLOT 2, tricore_trap_dispatch + TRAP_SLOT 3, tricore_trap_dispatch + TRAP_SLOT 4, tricore_trap_dispatch + TRAP_SLOT 5, tricore_trap_dispatch + TRAP_SLOT 6, tricore_svcall_local + TRAP_SLOT 7, tricore_trap_dispatch + + .text + .p2align 2 + + .global tricore_trap_dispatch + .type tricore_trap_dispatch, %function +tricore_trap_dispatch: + svlcx + call tricore_trap_handler + rslcx + rfe + + .global tricore_svcall_local + .type tricore_svcall_local, %function +tricore_svcall_local: + svlcx + call tricore_svcall + rslcx + rfe diff --git a/arch/tricore/src/common/tricore_trapcall.c b/arch/tricore/src/common/tricore_trapcall.c index 673819e2bf10d..d5a5f49a609c0 100644 --- a/arch/tricore/src/common/tricore_trapcall.c +++ b/arch/tricore/src/common/tricore_trapcall.c @@ -26,392 +26,178 @@ #include +#include #include -#include #include -#include -#include +#include -#include -#include -#include -#include +#include +#include +#include #include "tricore_internal.h" -#include "IfxCpu_Trap.h" - /**************************************************************************** - * Private Data + * Pre-processor Definitions ****************************************************************************/ -static IfxCpu_Trap g_trapinfo; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void tricore_trapinfo(volatile void *trap) +enum tricore_trap_class { - IfxCpu_Trap *ctrap = (IfxCpu_Trap *)trap; - - g_trapinfo.tCpu = ctrap->tCpu; - g_trapinfo.tClass = ctrap->tClass; - g_trapinfo.tId = ctrap->tId; - g_trapinfo.tAddr = ctrap->tAddr; -} + TRICORE_CLASS_MMU, + TRICORE_CLASS_IP, + TRICORE_CLASS_IE, + TRICORE_CLASS_CTX, + TRICORE_CLASS_BUS, + TRICORE_CLASS_ASSERT, + TRICORE_CLASS_SYSCALL, + TRICORE_CLASS_NMI +}; /**************************************************************************** - * Public Functions + * Private Data ****************************************************************************/ -int weak_function tricore_nmitrap(uint32_t tid, void *context, void *arg) -{ - _alert("PANIC!!! NMI Trap:\n"); - _alert("\tClass %d TID: %d regs: %p\n", - IfxCpu_Trap_Class_nonMaskableInterrupt, tid, context); - - up_irq_save(); - PANIC_WITH_REGS("panic", context); - return OK; -} +/* Trap description tables indexed by trap class and TIN. + * For classes where TIN numbering starts at 1, index 0 is reserved. + */ -int tricore_mmutrap(uint32_t tid, void *context, void *arg) +static const char * const g_trap_class0[] = { - _alert("PANIC!!! MMU Trap:\n"); - _alert("\tClass %d TID: %" PRId32 " regs: %p\n", - IfxCpu_Trap_Class_memoryManagement, - tid, context); - - _alert("MMU Trap Reason:\n"); - if (tid == IfxCpu_Trap_MemoryManagement_Id_virtualAddressFill) - { - _alert("\tVirtual Address Fill\n"); - } + "Virtual Address Fill", + "Virtual Address Protection", +}; - if (tid == IfxCpu_Trap_MemoryManagement_Id_virtualAddressProtection) - { - _alert("\tVirtual Address Protection\n"); - } - - up_irq_save(); - PANIC_WITH_REGS("panic", context); - return OK; -} - -int tricore_internalprotrape(uint32_t tid, void *context, void *arg) +static const char * const g_trap_class1[] = { - _alert("PANIC!!! Internal Protection Trap:\n"); - _alert("\tClass %d TID: %" PRId32 " regs: %p\n", - IfxCpu_Trap_Class_internalProtection, tid, context); - - _alert("Internal Protection Reason:\n"); - if (tid == IfxCpu_Trap_InternalProtection_Id_privilegeViolation) - { - _alert("\tPrivileged Instruction\n"); - } - - if (tid == IfxCpu_Trap_InternalProtection_Id_memoryProtectionRead) - { - _alert("\tMemory Protection Read\n"); - } - - if (tid == IfxCpu_Trap_InternalProtection_Id_memoryProtectionWrite) - { - _alert("\tMemory Proteciton Write\n"); - } - - if (tid == IfxCpu_Trap_InternalProtection_Id_memoryProtectionExecute) - { - _alert("\tMemory Protection Execution\n"); - } - - if (tid == - IfxCpu_Trap_InternalProtection_Id_memoryProtectionPeripheralAccess) - { - _alert("\tMemory Protection Peripheral Access\n"); - } - - if (tid == IfxCpu_Trap_InternalProtection_Id_memoryProtectionNullAddress) - { - _alert("\tMemory Protection Null Address\n"); - } - - if (tid == IfxCpu_Trap_InternalProtection_Id_globalRegisterWriteProtection) - { - _alert("\tGlobal Register Write Protection\n"); - } - - up_irq_save(); - PANIC_WITH_REGS("panic", context); - return OK; -} - -int tricore_insterrorstrap(uint32_t tid, void *context, void *arg) + "Reserved", + "Privileged Instruction", + "Memory Protection Read", + "Memory Protection Write", + "Memory Protection Execute", + "Memory Protection Peripheral Access", + "Memory Protection Null Address", + "Global Register Write Protection", +}; + +static const char * const g_trap_class2[] = { - _alert("PANIC!!! Instruction Errors Trap:\n"); - _alert("\tClass %d TID: %" PRId32 " regs: %p\n", - IfxCpu_Trap_Class_instructionErrors, tid, context); - - _alert("Instruction Errors Trap Reason:\n"); - if (tid == IfxCpu_Trap_InstructionErrors_Id_illegalOpcode) - { - _alert("\tIllegal Opcode\n"); - } - - if (tid == IfxCpu_Trap_InstructionErrors_Id_unimplementedOpcode) - { - _alert("\tUnimplemented Opcode\n"); - } - - if (tid == IfxCpu_Trap_InstructionErrors_Id_invalidOperand) - { - _alert("\tInvalid Operand Specification\n"); - } - - if (tid == IfxCpu_Trap_InstructionErrors_Id_dataAddressAlignment) - { - _alert("\tData Address Alignment\n"); - } - - if (tid == IfxCpu_Trap_InstructionErrors_Id_invalidMemoryAddress) - { - _alert("\tInvalid Local Memory Address\n"); - } - -#ifdef CONFIG_ARCH_TC1V8 - if (tid == - IfxCpu_Trap_InstructionErrors_Id_CoprocessorTrapSynchronousError) - { - _alert("\tCoprocessor Trap Synchronous Error\n"); -# ifdef CONFIG_ARCH_HAVE_FPU - _alert("\tFPU_SYNC_TRAP:%" PRIX32 "\n\n", - (uint32_t)__mfcr(FPU_SYNC_TRAP_REG)); - __mtcr(FPU_SYNC_TRAP_REG, - __mfcr(FPU_SYNC_TRAP_REG) | (1U << FPU_TRAP_TCL_SHIFT)); -# endif - } -#endif - - up_irq_save(); - PANIC_WITH_REGS("panic", context); - return OK; -} - -int tricore_contexmnttrap(uint32_t tid, void *context, void *arg) + "Reserved", + "Illegal Opcode", + "Unimplemented Opcode", + "Invalid Operand specification", + "Data Address Alignment", + "Invalid Local Memory Address", +}; + +static const char * const g_trap_class3[] = { - _alert("PANIC!!! Context Management Trap:\n"); - _alert("\tClass %d TID: %" PRId32 " regs: %p\n", - IfxCpu_Trap_Class_contextManagement, tid, context); - - _alert("Context Management Reason:\n"); - if (tid == IfxCpu_Trap_ContextManagement_Id_freeContextListDepletion) - { - _alert("\tFree Context List Depletion\n"); - } - - if (tid == IfxCpu_Trap_ContextManagement_Id_callDepthOverflow) - { - _alert("\tCall Depth Overflow\n"); - } - - if (tid == IfxCpu_Trap_ContextManagement_Id_callDepthUnderflow) - { - _alert("\tCall Depth Underflow\n"); - } - - if (tid == IfxCpu_Trap_ContextManagement_Id_freeContextListUnderflow) - { - _alert("\tFree Context List Underflow\n"); - } - - if (tid == IfxCpu_Trap_ContextManagement_Id_callStackUnderflow) - { - _alert("\tCall Stack Underflow\n"); - } - - if (tid == IfxCpu_Trap_ContextManagement_Id_contextType) - { - _alert("\tContext Type\n"); - } - - if (tid == IfxCpu_Trap_ContextManagement_Id_nestingError) - { - _alert("\tNesting Error:RFE with non-zero call depth\n"); - } - - up_irq_save(); - PANIC_WITH_REGS("panic", context); - return OK; -} - -int tricore_bustrap(uint32_t tid, void *context, void *arg) + "Reserved", + "Free Context List Depletion (FCX = LCX)", + "Call Depth Overflow", + "Call Depth Underflow", + "Free Context List Underflow (FCX = 0)", + "Call Stack Underflow (PCX = 0)", + "Context Type (PCXI.UL wrong)", + "Nesting Error: RFE with non-zero call depth", +}; + +static const char * const g_trap_class4[] = { - _alert("PANIC!!! System Bus Trap:\n"); - _alert("\tClass %d TID: %" PRId32 " regs: %p\n", IfxCpu_Trap_Class_bus, - tid, context); - - _alert("System Bus Reason:\n"); - if (tid == IfxCpu_Trap_Bus_Id_programFetchSynchronousError) - { - _alert("\tProgram Fetch Synchronous Error\n"); - } - - if (tid == IfxCpu_Trap_Bus_Id_dataAccessSynchronousError) - { - _alert("\tData Access Synchronous Error\n"); - } - - if (tid == IfxCpu_Trap_Bus_Id_dataAccessAsynchronousError) - { - _alert("\tData Access Asysnchronous Error\n"); - } + "Reserved", + "Program Fetch Synchronous Error", + "Data Access Synchronous Error", + "Data Access Asynchronous Error", + "Coprocessor Trap Asynchronous Error", + "Program Memory Integrity Error", + "Data Memory Integrity Error", + "Temporal Asynchronous Error", +}; + +static const char * const g_trap_class5[] = +{ + "Reserved", + "Arithmetic Overflow", + "Sticky Arithmetic Overflow", +}; - if (tid == IfxCpu_Trap_Bus_Id_CoprocessorTrapAsynchronousError) - { - _alert("\tCoprocessor Trap Asynchronous Error\n"); -#ifdef CONFIG_ARCH_HAVE_FPU - _alert("\tFPU_ASYNC_TRAP:%" PRIX32 "\n\n", - (uint32_t)__mfcr(FPU_ASYNC_TRAP_REG)); - __mtcr(FPU_ASYNC_TRAP_REG, - __mfcr(FPU_ASYNC_TRAP_REG) | (1U << FPU_TRAP_TCL_SHIFT)); -#endif - } +static const char * const g_trap_class6[] = +{ + "System Call", +}; - if (tid == IfxCpu_Trap_Bus_Id_programMemoryIntegrityError) - { - _alert("\tProgram Memory Integrity Error\n"); - } +static const char * const g_trap_class7[] = +{ + "Non-Maskable Interrupt", +}; - if (tid == IfxCpu_Trap_Bus_Id_dataMemoryIntegrityError) - { - _alert("\tData Memory Integrity Error\n"); - } +static const char * const * const g_trap_class_str[] = +{ + g_trap_class0, g_trap_class1, g_trap_class2, g_trap_class3, + g_trap_class4, g_trap_class5, g_trap_class6, g_trap_class7, +}; - if (tid == IfxCpu_Trap_Bus_Id_temporalAsynchronousError) - { - _alert("\tTemporal Asynchronous Error\n"); - } +static const uint8_t g_trap_class_tin_count[] = +{ + sizeof(g_trap_class0) / sizeof(g_trap_class0[0]), + sizeof(g_trap_class1) / sizeof(g_trap_class1[0]), + sizeof(g_trap_class2) / sizeof(g_trap_class2[0]), + sizeof(g_trap_class3) / sizeof(g_trap_class3[0]), + sizeof(g_trap_class4) / sizeof(g_trap_class4[0]), + sizeof(g_trap_class5) / sizeof(g_trap_class5[0]), + sizeof(g_trap_class6) / sizeof(g_trap_class6[0]), + sizeof(g_trap_class7) / sizeof(g_trap_class7[0]), +}; - up_irq_save(); - PANIC_WITH_REGS("panic", context); - return OK; -} +/**************************************************************************** + * Private Functions + ****************************************************************************/ -int tricore_assertiontrap(uint32_t tid, void *context, void *arg) +static const char *tricore_trap_cause_str(uint32_t tclass, uint32_t tin) { - _alert("PANIC!!! Assertion Trap:\n"); - _alert("\tClass %d TID: %" PRId32 " regs: %p\n", - IfxCpu_Trap_Class_assertion, - tid, context); - - _alert("System Bus Reason:\n"); - if (tid == IfxCpu_Trap_Assertion_Id_arithmeticOverflow) + if (tclass >= sizeof(g_trap_class_str) / sizeof(g_trap_class_str[0])) { - _alert("\tArithmetic Overflow\n"); + return "Unknown Trap Class"; } - if (tid == IfxCpu_Trap_Assertion_Id_stickyArithmeticOverflow) + if (tin >= g_trap_class_tin_count[tclass]) { - _alert("\tSticky Arithmetic Overflow\n"); + return "Unknown TIN"; } - up_irq_save(); - PANIC_WITH_REGS("panic", context); - return OK; + return g_trap_class_str[tclass][tin]; } /**************************************************************************** - * Name: tricore_trapcall + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_trap_handler * * Description: - * This is Trap exception handler + * This is the common Trap exception handler. It is invoked by the BTV + * trap stubs in tricore_trap.S after svlcx has saved the lower context. + * The current PCXI therefore points at the just-saved lower CSA whose + * PCXI field chains back to the upper CSA pushed by hardware on trap + * entry. * ****************************************************************************/ -void tricore_trapcall(volatile void *trap) +void tricore_trap_handler(uint32_t tclass, uint32_t tin) { uintptr_t *regs; uintptr_t pcxi; - IfxCpu_Trap *ctrap = (IfxCpu_Trap *)trap; - IfxCpu_Trap_Class tclass = (IfxCpu_Trap_Class)ctrap->tClass; - unsigned int tid = ctrap->tId; - - tricore_trapinfo(trap); - - regs = tricore_csa2addr(__mfcr(CPU_PCXI)); - pcxi = regs[REG_UPCXI]; - regs = tricore_csa2addr(pcxi); - - if (!up_interrupt_context()) + if (tclass == TRICORE_CLASS_SYSCALL) { - /* Update the current task's regs */ - - g_running_tasks[this_cpu()]->xcp.regs = regs; - } - - up_set_interrupt_context(true); - - if (tclass == IfxCpu_Trap_Class_nonMaskableInterrupt) - { - tricore_nmitrap(tid, regs, NULL); - up_set_interrupt_context(false); + tricore_svcall(NULL); return; } - if (tclass == IfxCpu_Trap_Class_memoryManagement) - { - tricore_mmutrap(tid, regs, NULL); - return; - } - - if (tclass == IfxCpu_Trap_Class_internalProtection) - { - tricore_internalprotrape(tid, regs, NULL); - return; - } - - if (tclass == IfxCpu_Trap_Class_instructionErrors) - { - tricore_insterrorstrap(tid, regs, NULL); - return; - } - - if (tclass == IfxCpu_Trap_Class_contextManagement) - { - tricore_contexmnttrap(tid, regs, NULL); - return; - } - - if (tclass == IfxCpu_Trap_Class_bus) - { - tricore_bustrap(tid, regs, NULL); - return; - } - - if (tclass == IfxCpu_Trap_Class_assertion) - { - tricore_assertiontrap(tid, regs, NULL); - return; - } - - up_irq_save(); - PANIC_WITH_REGS("Trap", regs); -} - -/**************************************************************************** - * Function: tricore_trapinit - * - * Description: - * Trap init for tricore arch. - * - ****************************************************************************/ + TRICORE_MFCR(TRICORE_CPU_PCXI, pcxi); + regs = tricore_csa2addr(pcxi); -void tricore_trapinit(void) -{ -#ifdef CONFIG_COREDUMP - coredump_add_memory_region(&g_trapinfo, sizeof(g_trapinfo), - PF_REGISTER); -#endif + lowsyslog("TriCore Trap: Class %" PRIu32 " TIN %" PRIu32 " (%s)\n", + tclass, tin, tricore_trap_cause_str(tclass, tin)); + up_dump_register(regs); } diff --git a/arch/tricore/src/common/tricore_usestack.c b/arch/tricore/src/common/tricore_usestack.c index a8f3706a552bb..4cf21fc508fae 100644 --- a/arch/tricore/src/common/tricore_usestack.c +++ b/arch/tricore/src/common/tricore_usestack.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include @@ -76,20 +76,10 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) size_t size_of_stack; #ifdef CONFIG_TLS_ALIGNED - /* The allocated stack size must not exceed the maximum possible for the - * TLS feature. - */ - - DEBUGASSERT(stack_size <= TLS_MAXSTACK); - if (stack_size >= TLS_MAXSTACK) - { - stack_size = TLS_MAXSTACK; - } -#endif - /* Make certain that the user provided stack is properly aligned */ - DEBUGASSERT(((uintptr_t)stack & STACK_ALIGN_MASK) == 0); + DEBUGASSERT(((uintptr_t)stack & TLS_STACK_MASK) == 0); +#endif /* Is there already a stack allocated? */ @@ -103,9 +93,9 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) /* Save the new stack allocation */ tcb->stack_alloc_ptr = stack; - tcb->stack_base_ptr = (void *)STACKFRAME_ALIGN_UP((uintptr_t)stack); + tcb->stack_base_ptr = (void *)STACK_ALIGN_UP((uintptr_t)stack); - top_of_stack = STACKFRAME_ALIGN_DOWN((uintptr_t)stack + stack_size); + top_of_stack = STACK_ALIGN_DOWN((uintptr_t)stack + stack_size); size_of_stack = top_of_stack - (uintptr_t)tcb->stack_base_ptr; tcb->adj_stack_size = size_of_stack; diff --git a/arch/tricore/src/tc3x/Make.defs b/arch/tricore/src/tc3x/Make.defs index 25bc0b9430028..3d8de7c0607b0 100644 --- a/arch/tricore/src/tc3x/Make.defs +++ b/arch/tricore/src/tc3x/Make.defs @@ -20,4 +20,6 @@ # ############################################################################ +CHIP_CSRCS += tc3x_watchdog.c + VPATH += tc3x diff --git a/arch/tricore/src/tc3x/tc3x_watchdog.c b/arch/tricore/src/tc3x/tc3x_watchdog.c new file mode 100644 index 0000000000000..0f0f24810b448 --- /dev/null +++ b/arch/tricore/src/tc3x/tc3x_watchdog.c @@ -0,0 +1,128 @@ +/**************************************************************************** + * arch/tricore/src/tc3x/tc3x_watchdog.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "tricore_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TC3X_SCU_BASE 0xf0036000 +#define TC3X_WDTCPU0CON0 (TC3X_SCU_BASE + 0x024c) +#define TC3X_WDTSCON0 (TC3X_SCU_BASE + 0x02a8) +#define TC3X_WDTCPU0_CON1 (TC3X_SCU_BASE + 0x0250) +#define TC3X_WDTS_CON1 (TC3X_SCU_BASE + 0x02ac) + +#define TC3X_WDT_CON1_DR BIT(3) + +/* TC3X has cores 0/1/2; the CORE_ID register reports them at indices + * 0/1/2 plus a logical alias index 6. Remap index 6 to 5 so the WDT + * register stride math below works for all readings. + */ + +#define TC3X_CORE_ID_ALIAS_6 6 +#define TC3X_CORE_ID_REMAP_6 5 + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void wdt_modify(uintptr_t con0, bool endinit) +{ + uint32_t val = getreg32(con0); + uint32_t pw = ((val >> 2) & 0x3fff) ^ 0x003f; + uint32_t want = endinit ? BIT(0) : 0; + int i; + + /* Password access: LCK=1, ENDINIT=1 */ + + if (val & BIT(1)) + { + putreg32((val & 0xffff0000) | (pw << 2) | BIT(0), con0); + } + + /* Modify access: LCK=1, ENDINIT=desired */ + + putreg32((val & 0xffff0000) | (pw << 2) | BIT(1) | want, con0); + + for (i = 0; i < 10000; i++) + { + if ((getreg32(con0) & BIT(0)) == want) + { + break; + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void aurix_cpu_endinit_enable(bool enable) +{ + uint32_t core_id; + + TRICORE_MFCR(TRICORE_CPU_CORE_ID, core_id); + core_id &= TRICORE_CPU_CORE_ID_MASK; + + if (core_id == TC3X_CORE_ID_ALIAS_6) + { + core_id = TC3X_CORE_ID_REMAP_6; + } + + wdt_modify(TC3X_WDTCPU0CON0 + (core_id * 12), enable); +} + +void aurix_safety_endinit_enable(bool enable) +{ + wdt_modify(TC3X_WDTSCON0, enable); +} + +void tricore_wdt_disable(void) +{ + uint32_t core_id; + + TRICORE_MFCR(TRICORE_CPU_CORE_ID, core_id); + core_id &= TRICORE_CPU_CORE_ID_MASK; + + if (core_id == TC3X_CORE_ID_ALIAS_6) + { + core_id = TC3X_CORE_ID_REMAP_6; + } + + if (core_id == 0) + { + aurix_safety_endinit_enable(false); + putreg32(TC3X_WDT_CON1_DR, TC3X_WDTS_CON1); + aurix_safety_endinit_enable(true); + } + + aurix_cpu_endinit_enable(false); + putreg32(TC3X_WDT_CON1_DR, TC3X_WDTCPU0_CON1 + (core_id * 12)); + aurix_cpu_endinit_enable(true); +} diff --git a/arch/tricore/src/tc4x/Make.defs b/arch/tricore/src/tc4x/Make.defs index 8f2fb7a97aaa0..55697c423b826 100644 --- a/arch/tricore/src/tc4x/Make.defs +++ b/arch/tricore/src/tc4x/Make.defs @@ -20,4 +20,6 @@ # ############################################################################ +CHIP_CSRCS += tc4x_watchdog.c + VPATH += tc4x diff --git a/arch/tricore/src/tc4x/tc4x_watchdog.c b/arch/tricore/src/tc4x/tc4x_watchdog.c new file mode 100644 index 0000000000000..fb09ec2402e99 --- /dev/null +++ b/arch/tricore/src/tc4x/tc4x_watchdog.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * arch/tricore/src/tc4x/tc4x_watchdog.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TC4X_WDTCPU0_BASE 0xf0000018 +#define TC4X_WDTSYS_BASE 0xf0000184 +#define TC4X_WDT_CPU_STRIDE 0x30 +#define TC4X_WDT_CTRLA_OFF 0x24 +#define TC4X_WDT_CTRLB_OFF 0x28 +#define TC4X_WDT_CTRLA_LCK BIT(0) +#define TC4X_WDT_CTRLA_PW (0x7fu << 1) +#define TC4X_WDT_CTRLB_DR BIT(0) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void tc4x_wdt_block_disable(uintptr_t ctrla, uintptr_t ctrlb) +{ + uint32_t v = getreg32(ctrla); + + if (v & TC4X_WDT_CTRLA_LCK) + { + v &= ~TC4X_WDT_CTRLA_LCK; + v ^= TC4X_WDT_CTRLA_PW; + putreg32(v, ctrla); + } + + putreg32(TC4X_WDT_CTRLB_DR, ctrlb); + + v = getreg32(ctrla); + v |= TC4X_WDT_CTRLA_LCK; + putreg32(v, ctrla); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void tricore_wdt_disable(void) +{ + uint32_t cpu_id; + uintptr_t base; + + TRICORE_MFCR(TRICORE_CPU_CORE_ID, cpu_id); + cpu_id &= TRICORE_CPU_CORE_ID_MASK; + + base = TC4X_WDTCPU0_BASE + cpu_id * TC4X_WDT_CPU_STRIDE; + tc4x_wdt_block_disable(base + TC4X_WDT_CTRLA_OFF, + base + TC4X_WDT_CTRLB_OFF); + + if (cpu_id == 0) + { + tc4x_wdt_block_disable(TC4X_WDTSYS_BASE + TC4X_WDT_CTRLA_OFF, + TC4X_WDTSYS_BASE + TC4X_WDT_CTRLB_OFF); + } +} From 26f3d64373d60bc853ea38674ed23407147466ce Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Fri, 15 May 2026 12:03:25 +0530 Subject: [PATCH 05/12] arch/tricore: STM oneshot tick timer A tick source is required to drive the scheduler and any sleep or timeout primitive. The System Timer (STM) is always present on both AURIX families, runs from the SCU clock and has the resolution and range the scheduler expects, so it is the natural tick source for the port. Use the oneshot lower-half binding so the same driver serves tickless and periodic configurations without a second timer. Signed-off-by: Parthiban Nallathambi --- arch/tricore/src/common/Make.defs | 1 + arch/tricore/src/common/tricore_stm.c | 176 ++++++++++++++++++++++++++ arch/tricore/src/common/tricore_stm.h | 124 ++++++++++++++++++ 3 files changed, 301 insertions(+) create mode 100644 arch/tricore/src/common/tricore_stm.c create mode 100644 arch/tricore/src/common/tricore_stm.h diff --git a/arch/tricore/src/common/Make.defs b/arch/tricore/src/common/Make.defs index 01e179624315f..531a5fcb1019b 100644 --- a/arch/tricore/src/common/Make.defs +++ b/arch/tricore/src/common/Make.defs @@ -46,6 +46,7 @@ CMN_CSRCS += tricore_saveusercontext.c CMN_CSRCS += tricore_schedulesigaction.c CMN_CSRCS += tricore_sigdeliver.c CMN_CSRCS += tricore_stackframe.c +CMN_CSRCS += tricore_stm.c CMN_CSRCS += tricore_svcall.c CMN_CSRCS += tricore_switchcontext.c CMN_CSRCS += tricore_tcbinfo.c diff --git a/arch/tricore/src/common/tricore_stm.c b/arch/tricore/src/common/tricore_stm.c new file mode 100644 index 0000000000000..1ef6e1d80d798 --- /dev/null +++ b/arch/tricore/src/common/tricore_stm.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_stm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "tricore_irq.h" +#include "tricore_stm.h" +#include "tricore_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CYCLES_PER_SEC TRICORE_STM_FREQ +#define CYCLES_PER_TICK (CONFIG_USEC_PER_TICK * (CYCLES_PER_SEC / USEC_PER_SEC)) + +#define cycle_diff_t unsigned long + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint64_t g_last_count; +static uint64_t g_last_ticks; +static uint8_t g_core_id; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline uint64_t stm_get_time64(void) +{ +#if TRICORE_STM_HAS_64BIT_READ + return getreg64(TRICORE_STM_ABS(g_core_id)); +#else + uint64_t lo; + uint64_t hi; + + lo = (uint64_t)getreg32(TRICORE_STM_TIM0SV(g_core_id)); + hi = (uint64_t)getreg32(TRICORE_STM_CAPSV(g_core_id)); + + return (hi << 32) | lo; +#endif +} + +static inline void stm_set_compare(uint32_t cmp) +{ + putreg32(cmp, TRICORE_STM_CMP0(g_core_id, TRICORE_STM_DEFAULT)); +} + +static int tricore_timerisr(int irq, uint32_t *regs, void *arg) +{ + uint32_t val; + uint64_t now; + uint64_t dcycles; + uint32_t dticks; + uint64_t next; + + /* Clear the compare match interrupt */ + + val = getreg32(TRICORE_STM_ISCR(g_core_id, TRICORE_STM_DEFAULT)); + val |= TRICORE_STM_ISCR_CMP0IRR; + putreg32(val, TRICORE_STM_ISCR(g_core_id, TRICORE_STM_DEFAULT)); + + /* Calculate elapsed ticks */ + + now = stm_get_time64(); + dcycles = now - g_last_count; + dticks = (cycle_diff_t)dcycles / CYCLES_PER_TICK; + + g_last_count += (cycle_diff_t)dticks * CYCLES_PER_TICK; + g_last_ticks += dticks; + + next = g_last_count + CYCLES_PER_TICK; + stm_set_compare((uint32_t)next); + + nxsched_process_timer(); + + return 0; +} + +static inline unsigned int tricore_get_core_id(void) +{ + unsigned int id; + + TRICORE_MFCR(TRICORE_CPU_CORE_ID, id); + + return id & TRICORE_CPU_CORE_ID_MASK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * Initialize the STM as the system tick timer. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t val; + int stm_irq; + + g_core_id = tricore_get_core_id(); + stm_irq = TRICORE_STM_SRC_INDEX(g_core_id, TRICORE_STM_DEFAULT); + + val = getreg32(TRICORE_STM_CMCON(g_core_id, TRICORE_STM_DEFAULT)); + val &= ~(TRICORE_STM_CMCON_MSIZE0_MASK | TRICORE_STM_CMCON_MSTART0_MASK); + val |= (31u << TRICORE_STM_CMCON_MSIZE0_SHIFT); + putreg32(val, TRICORE_STM_CMCON(g_core_id, TRICORE_STM_DEFAULT)); + + /* Clear any pending compare interrupt */ + + val = getreg32(TRICORE_STM_ISCR(g_core_id, TRICORE_STM_DEFAULT)); + val |= TRICORE_STM_ISCR_CMP0IRR; + putreg32(val, TRICORE_STM_ISCR(g_core_id, TRICORE_STM_DEFAULT)); + + /* Snapshot current time for tick accounting */ + + g_last_ticks = stm_get_time64() / CYCLES_PER_TICK; + g_last_count = g_last_ticks * CYCLES_PER_TICK; + + val = getreg32(TRICORE_STM_ICR(g_core_id, TRICORE_STM_DEFAULT)); + val &= ~TRICORE_STM_ICR_CMP0OS; + val |= TRICORE_STM_ICR_CMP0EN; + putreg32(val, TRICORE_STM_ICR(g_core_id, TRICORE_STM_DEFAULT)); + +#ifdef CONFIG_DEBUG_FEATURES + /* Freeze STM on debug halt */ + + putreg32(TRICORE_STM_OCS_SUS_W, TRICORE_STM_OCS(g_core_id)); +#endif + + /* Attach and enable the timer interrupt */ + + irq_attach(stm_irq, (xcpt_t)tricore_timerisr, NULL); + stm_set_compare((uint32_t)g_last_count + (CYCLES_PER_TICK * 5)); + up_enable_irq(stm_irq); +} diff --git a/arch/tricore/src/common/tricore_stm.h b/arch/tricore/src/common/tricore_stm.h new file mode 100644 index 0000000000000..50e685ef4bcae --- /dev/null +++ b/arch/tricore/src/common/tricore_stm.h @@ -0,0 +1,124 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_stm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_COMMON_TRICORE_STM_H +#define __ARCH_TRICORE_SRC_COMMON_TRICORE_STM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) + +#define TRICORE_STM_CPU_BASE 0xf8800000 +#define TRICORE_STM_CPU_STRIDE 0x40000 + +#define TRICORE_STM_DEFAULT 2 + +#define TRICORE_STM_BASE(core) (TRICORE_STM_CPU_BASE + (core * TRICORE_STM_CPU_STRIDE)) + +#define TRICORE_STM_ABS(core) (TRICORE_STM_BASE(core) + 0x20) +#define TRICORE_STM_OCS(core) (TRICORE_STM_BASE(core) + 0x04) + +#define TRICORE_STM_VM_BANK(core, stm) \ + (TRICORE_STM_BASE(core) + ((stm >> 1) * 0x20)) + +#define TRICORE_STM_CMP0(core, stm) (TRICORE_STM_VM_BANK(core, stm) + 0x100) +#define TRICORE_STM_CMP1(core, stm) (TRICORE_STM_VM_BANK(core, stm) + 0x104) +#define TRICORE_STM_CMCON(core, stm) (TRICORE_STM_VM_BANK(core, stm) + 0x108) +#define TRICORE_STM_ICR(core, stm) (TRICORE_STM_VM_BANK(core, stm) + 0x10c) +#define TRICORE_STM_ISCR(core, stm) (TRICORE_STM_VM_BANK(core, stm) + 0x110) +#define TRICORE_STM_ISR(core, stm) (TRICORE_STM_VM_BANK(core, stm) + 0x114) + +#define TRICORE_STM_SRC_INDEX(core, stm) (8 + stm) + +#define TRICORE_STM_FREQ (500 * 1000 * 1000) +#define TRICORE_STM_HAS_64BIT_READ 1 + +#elif defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) + +#define TRICORE_STM_PERIPH_BASE 0xf0001000 +#define TRICORE_STM_PERIPH_STRIDE 0x100 + +#define TRICORE_STM_DEFAULT 0 + +#define TRICORE_STM_BASE(core) \ + (TRICORE_STM_PERIPH_BASE + ((core) * TRICORE_STM_PERIPH_STRIDE)) + +#define TRICORE_STM_TIM0(core) (TRICORE_STM_BASE(core) + 0x10) +#define TRICORE_STM_TIM0SV(core) (TRICORE_STM_BASE(core) + 0x50) +#define TRICORE_STM_CAPSV(core) (TRICORE_STM_BASE(core) + 0x54) + +#define TRICORE_STM_CLC(core) (TRICORE_STM_BASE(core) + 0x00) +#define TRICORE_STM_OCS(core) (TRICORE_STM_BASE(core) + 0xe8) + +#define TRICORE_STM_CMP0(core, stm) (TRICORE_STM_BASE(core) + 0x30) +#define TRICORE_STM_CMP1(core, stm) (TRICORE_STM_BASE(core) + 0x34) +#define TRICORE_STM_CMCON(core, stm) (TRICORE_STM_BASE(core) + 0x38) +#define TRICORE_STM_ICR(core, stm) (TRICORE_STM_BASE(core) + 0x3c) +#define TRICORE_STM_ISCR(core, stm) (TRICORE_STM_BASE(core) + 0x40) + +#define TRICORE_STM_SRC_BASE 192 +#define TRICORE_STM_SRC_INDEX(core, stm) \ + (TRICORE_STM_SRC_BASE + (core) * 2) + +#define TRICORE_STM_FREQ (100 * 1000 * 1000) + +#define TRICORE_STM_HAS_64BIT_READ 0 +#endif + +#define TRICORE_STM_CMCON_MSIZE0_SHIFT 0 +#define TRICORE_STM_CMCON_MSIZE0_MASK GENMASK(4, 0) +#define TRICORE_STM_CMCON_MSTART0_SHIFT 8 +#define TRICORE_STM_CMCON_MSTART0_MASK GENMASK(12, 8) + +#define TRICORE_STM_CMCON_MSIZE1_SHIFT 16 +#define TRICORE_STM_CMCON_MSIZE1_MASK GENMASK(20, 16) +#define TRICORE_STM_CMCON_MSTART1_SHIFT 24 +#define TRICORE_STM_CMCON_MSTART1_MASK GENMASK(28, 24) + +#define TRICORE_STM_ICR_CMP0EN BIT(0) +#define TRICORE_STM_ICR_CMP0OS BIT(1) +#define TRICORE_STM_ICR_CMP1EN BIT(4) +#define TRICORE_STM_ICR_CMP1OS BIT(5) + +#define TRICORE_STM_ISCR_CMP0IRR BIT(0) +#define TRICORE_STM_ISCR_CMP0IRS BIT(1) +#define TRICORE_STM_ISCR_CMP1IRR BIT(2) +#define TRICORE_STM_ISCR_CMP1IRS BIT(3) + +#define TRICORE_STM_ISR_CMP0IR BIT(0) +#define TRICORE_STM_ISR_CMP1IR BIT(1) + +#define TRICORE_STM_CLC_DISR BIT(0) +#define TRICORE_STM_CLC_DISS BIT(1) + +#define TRICORE_STM_OCS_SUS_W 0x12000000 + +#endif /* __ARCH_TRICORE_SRC_COMMON_TRICORE_STM_H */ From a72966a8e3ae16514d3af19c3849870e84bb1cfb Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Fri, 15 May 2026 12:03:37 +0530 Subject: [PATCH 06/12] arch/tc3x: clock tree and ENDINIT password rotation The SCU PLL has to be brought up at boot so peripherals run at their intended rate. UART baud, STM tick interval and every other timed peripheral derive from the SCU clock tree, so the port configures the PLL before any driver starts. The TC3X SCU registers that select the PLL source and dividers are write-protected by the SCU watchdog ENDINIT bit, which is itself guarded by a per-watchdog password. Without rotating the password and clearing ENDINIT, the clock writes are silently dropped and the PLL never reaches the requested frequency. Signed-off-by: Saravanan Sekar --- .../platforms/tricore/tc3x/index.rst | 66 ++- .../src/{tc3xx => tc3x}/CMakeLists.txt | 6 +- arch/tricore/src/tc3x/Make.defs | 1 + arch/tricore/src/tc3x/hardware/tc3x_clock.h | 315 ++++++++++++++ arch/tricore/src/tc3x/tc3x_clockconfig.c | 403 ++++++++++++++++++ 5 files changed, 785 insertions(+), 6 deletions(-) rename arch/tricore/src/{tc3xx => tc3x}/CMakeLists.txt (88%) create mode 100644 arch/tricore/src/tc3x/hardware/tc3x_clock.h create mode 100644 arch/tricore/src/tc3x/tc3x_clockconfig.c diff --git a/Documentation/platforms/tricore/tc3x/index.rst b/Documentation/platforms/tricore/tc3x/index.rst index 710ffee9b2d45..abb734317175b 100644 --- a/Documentation/platforms/tricore/tc3x/index.rst +++ b/Documentation/platforms/tricore/tc3x/index.rst @@ -2,12 +2,68 @@ AURIX TC3X ========== -NuttX support for the Infineon AURIX TC3X (TriCore TC1.6.2) family. +NuttX support for the Infineon AURIX TC3X (TriCore TC1.6.2P) family. -The TC3X port covers SCU clock tree bring-up (PLL, CCU dividers, ENDINIT -password rotation), the IR/SRC interrupt routing, the System Timer (STM) -oneshot and ASCLIN-based UART. Boards select a particular TC3X variant -through ``CONFIG_TC3X_CHIP_*``. +The TC3X port covers: + +- SCU clock tree bring-up (PLL, CCU dividers, ENDINIT password rotation). +- IR/SRC interrupt routing and ICR-driven priority arbitration. +- System Timer (STM) periodic tick. +- ASCLIN-based UART (NSH console). +- GPIO pinmuxing through the AURIX layer. + +Boards select a particular TC3X variant through ``CONFIG_TC3X_CHIP_*``. + +Memory map (TC375 CPU0 view) +============================ + +================= ============ ================================= +Region Base Size / notes +================= ============ ================================= +PFLASH (uncached) 0x80000000 4 MiB (program flash) +PFLASH (cached) 0xA0000000 4 MiB (alias of PFLASH) +DSPR0 0x70000000 240 KiB (CPU0 data scratch-pad) +PSPR0 0x70100000 64 KiB (CPU0 program scratch-pad) +LMU0 0x90000000 96 KiB (local memory unit) +================= ============ ================================= + +NuttX places the boot image in PFLASH starting at 0x80000000 (entry +``__start``). CPU0's data, BSS and CSA pool live in DSPR0; the +interrupt stack lives in PSPR0; the heap lives in LMU0. + +Interrupt Router mapping +======================== + +The Interrupt Router (IR) on TC3X exposes SRC registers at +``0xF0038000 + 4*SRN`` and CPU latched-active-service registers at +``0xF0037000 + LASR_offset``. + +Peripherals used in the upstream port: + +================ ======= ========================================= +Peripheral SRN Default NuttX IRQ (Kconfig) +================ ======= ========================================= +ASCLIN0 TX 20 ``CONFIG_TRICORE_UART0_TXIRQ`` = 20 +ASCLIN0 RX 21 ``CONFIG_TRICORE_UART0_RXIRQ`` = 21 +ASCLIN0 ER 22 ``CONFIG_TRICORE_UART0_ERIRQ`` = 22 +ASCLIN1 TX 23 ``CONFIG_TRICORE_UART1_TXIRQ`` = 23 +ASCLIN1 RX 24 ``CONFIG_TRICORE_UART1_RXIRQ`` = 24 +ASCLIN1 ER 25 ``CONFIG_TRICORE_UART1_ERIRQ`` = 25 +STM0 SR0/SR1 192/193 (per-CPU; CPU0 only in this port) +================ ======= ========================================= + +ENDINIT password rotation +========================= + +TC3X SCU registers are write-protected by a CPU-wide ENDINIT and a +separate Safety ENDINIT. Each unlock writes the inverted password to +the matching WDT...CON0 register. The port uses direct SFR access for +the rotation; no iLLD password helper is linked in. See +``arch/tricore/src/tc3x/tc3x_endinit.c`` and the corresponding +TC3X System Control Unit chapter in the AURIX TC3xx User Manual. + +Supported boards +================ .. toctree:: :maxdepth: 1 diff --git a/arch/tricore/src/tc3xx/CMakeLists.txt b/arch/tricore/src/tc3x/CMakeLists.txt similarity index 88% rename from arch/tricore/src/tc3xx/CMakeLists.txt rename to arch/tricore/src/tc3x/CMakeLists.txt index b21d9f0465783..38ca5fbc37972 100644 --- a/arch/tricore/src/tc3xx/CMakeLists.txt +++ b/arch/tricore/src/tc3x/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# arch/tricore/src/tc3xx/CMakeLists.txt +# arch/tricore/src/tc3x/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -19,3 +19,7 @@ # the License. # # ############################################################################## + +set(SRCS tc3x_clockconfig.c tc3x_watchdog.c) + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/tricore/src/tc3x/Make.defs b/arch/tricore/src/tc3x/Make.defs index 3d8de7c0607b0..f1d1a105b08a9 100644 --- a/arch/tricore/src/tc3x/Make.defs +++ b/arch/tricore/src/tc3x/Make.defs @@ -20,6 +20,7 @@ # ############################################################################ +CHIP_CSRCS += tc3x_clockconfig.c CHIP_CSRCS += tc3x_watchdog.c VPATH += tc3x diff --git a/arch/tricore/src/tc3x/hardware/tc3x_clock.h b/arch/tricore/src/tc3x/hardware/tc3x_clock.h new file mode 100644 index 0000000000000..6a08aefd6e837 --- /dev/null +++ b/arch/tricore/src/tc3x/hardware/tc3x_clock.h @@ -0,0 +1,315 @@ +/**************************************************************************** + * arch/tricore/src/tc3x/hardware/tc3x_clock.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_CLOCK_H +#define __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_CLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TC3X_SCU_BASE 0xf0036000 +#define TC3X_REG32(off) (*(volatile uint32_t *)(TC3X_SCU_BASE + (off))) + +#define TC3X_CLOCK_OSCCON_OFFSET 0x0010 +#define TC3X_CLOCK_SYSPLLSTAT_OFFSET 0x0014 +#define TC3X_CLOCK_SYSPLLCON0_OFFSET 0x0018 +#define TC3X_CLOCK_SYSPLLCON1_OFFSET 0x001c +#define TC3X_CLOCK_SYSPLLCON2_OFFSET 0x0020 +#define TC3X_CLOCK_PERPLLSTAT_OFFSET 0x0024 +#define TC3X_CLOCK_PERPLLCON0_OFFSET 0x0028 +#define TC3X_CLOCK_PERPLLCON1_OFFSET 0x002c +#define TC3X_CLOCK_CCUCON0_OFFSET 0x0030 +#define TC3X_CLOCK_CCUCON1_OFFSET 0x0034 +#define TC3X_CLOCK_FDR_OFFSET 0x0038 +#define TC3X_CLOCK_EXTCON_OFFSET 0x003c +#define TC3X_CLOCK_CCUCON2_OFFSET 0x0040 +#define TC3X_CLOCK_CCUCON3_OFFSET 0x0044 +#define TC3X_CLOCK_CCUCON4_OFFSET 0x0048 +#define TC3X_CLOCK_CCUCON5_OFFSET 0x004c + +/* Per-CPU dividers */ + +#define TC3X_CLOCK_CCUCON6_OFFSET 0x0080 /* CPU0DIV */ +#define TC3X_CLOCK_CCUCON7_OFFSET 0x0084 /* CPU1DIV */ +#define TC3X_CLOCK_CCUCON8_OFFSET 0x0088 /* CPU2DIV */ +#define TC3X_CLOCK_CCUCON9_OFFSET 0x008c /* CPU3DIV */ +#define TC3X_CLOCK_CCUCON10_OFFSET 0x0090 /* CPU4DIV */ +#define TC3X_CLOCK_CCUCON11_OFFSET 0x0094 /* CPU5DIV */ + +#define TC3X_CLOCK_OSCCON TC3X_REG32(TC3X_CLOCK_OSCCON_OFFSET) +#define TC3X_CLOCK_SYSPLLSTAT TC3X_REG32(TC3X_CLOCK_SYSPLLSTAT_OFFSET) +#define TC3X_CLOCK_SYSPLLCON0 TC3X_REG32(TC3X_CLOCK_SYSPLLCON0_OFFSET) +#define TC3X_CLOCK_SYSPLLCON1 TC3X_REG32(TC3X_CLOCK_SYSPLLCON1_OFFSET) +#define TC3X_CLOCK_SYSPLLCON2 TC3X_REG32(TC3X_CLOCK_SYSPLLCON2_OFFSET) +#define TC3X_CLOCK_PERPLLSTAT TC3X_REG32(TC3X_CLOCK_PERPLLSTAT_OFFSET) +#define TC3X_CLOCK_PERPLLCON0 TC3X_REG32(TC3X_CLOCK_PERPLLCON0_OFFSET) +#define TC3X_CLOCK_PERPLLCON1 TC3X_REG32(TC3X_CLOCK_PERPLLCON1_OFFSET) +#define TC3X_CLOCK_CCUCON0 TC3X_REG32(TC3X_CLOCK_CCUCON0_OFFSET) +#define TC3X_CLOCK_CCUCON1 TC3X_REG32(TC3X_CLOCK_CCUCON1_OFFSET) +#define TC3X_CLOCK_FDR TC3X_REG32(TC3X_CLOCK_FDR_OFFSET) +#define TC3X_CLOCK_EXTCON TC3X_REG32(TC3X_CLOCK_EXTCON_OFFSET) +#define TC3X_CLOCK_CCUCON2 TC3X_REG32(TC3X_CLOCK_CCUCON2_OFFSET) +#define TC3X_CLOCK_CCUCON3 TC3X_REG32(TC3X_CLOCK_CCUCON3_OFFSET) +#define TC3X_CLOCK_CCUCON4 TC3X_REG32(TC3X_CLOCK_CCUCON4_OFFSET) +#define TC3X_CLOCK_CCUCON5 TC3X_REG32(TC3X_CLOCK_CCUCON5_OFFSET) +#define TC3X_CLOCK_CCUCON6 TC3X_REG32(TC3X_CLOCK_CCUCON6_OFFSET) + +#define TC3X_OSCCON_PLLLV BIT(1) +#define TC3X_OSCCON_OSCRES BIT(2) +#define TC3X_OSCCON_GAINSEL_SHIFT 3 +#define TC3X_OSCCON_GAINSEL_MASK GENMASK(4, 3) +#define TC3X_OSCCON_MODE_SHIFT 5 +#define TC3X_OSCCON_MODE_MASK GENMASK(6, 5) +#define TC3X_OSCCON_SHBY BIT(7) +#define TC3X_OSCCON_PLLHV BIT(8) +#define TC3X_OSCCON_HYSEN BIT(9) +#define TC3X_OSCCON_HYSCTL_SHIFT 10 +#define TC3X_OSCCON_HYSCTL_MASK GENMASK(11, 10) +#define TC3X_OSCCON_AMPCTL_SHIFT 12 +#define TC3X_OSCCON_AMPCTL_MASK GENMASK(13, 12) +#define TC3X_OSCCON_OSCVAL_SHIFT 16 +#define TC3X_OSCCON_OSCVAL_MASK GENMASK(20, 16) +#define TC3X_OSCCON_APREN BIT(23) +#define TC3X_OSCCON_CAP0EN BIT(24) +#define TC3X_OSCCON_CAP1EN BIT(25) +#define TC3X_OSCCON_CAP2EN BIT(26) +#define TC3X_OSCCON_CAP3EN BIT(27) + +/* MODE encodings */ + +#define TC3X_OSCCON_MODE_XTAL (0u << TC3X_OSCCON_MODE_SHIFT) +#define TC3X_OSCCON_MODE_DISABLED (1u << TC3X_OSCCON_MODE_SHIFT) +#define TC3X_OSCCON_MODE_EXTCLK (2u << TC3X_OSCCON_MODE_SHIFT) +#define TC3X_OSCCON_MODE_OFF (3u << TC3X_OSCCON_MODE_SHIFT) + +#define TC3X_SYSPLLSTAT_PWDSTAT BIT(1) +#define TC3X_SYSPLLSTAT_LOCK BIT(2) +#define TC3X_SYSPLLSTAT_K2RDY BIT(5) +#define TC3X_SYSPLLSTAT_MODRUN BIT(7) + +#define TC3X_SYSPLLCON0_MODEN BIT(2) +#define TC3X_SYSPLLCON0_NDIV_SHIFT 9 +#define TC3X_SYSPLLCON0_NDIV_MASK GENMASK(15, 9) +#define TC3X_SYSPLLCON0_PLLPWD BIT(16) +#define TC3X_SYSPLLCON0_RESLD BIT(18) +#define TC3X_SYSPLLCON0_PDIV_SHIFT 24 +#define TC3X_SYSPLLCON0_PDIV_MASK GENMASK(26, 24) +#define TC3X_SYSPLLCON0_INSEL_SHIFT 30 +#define TC3X_SYSPLLCON0_INSEL_MASK GENMASK(31, 30) + +/* INSEL encodings */ + +#define TC3X_SYSPLLCON0_INSEL_FBACK (0 << TC3X_SYSPLLCON0_INSEL_SHIFT) +#define TC3X_SYSPLLCON0_INSEL_FOSC (1 << TC3X_SYSPLLCON0_INSEL_SHIFT) +#define TC3X_SYSPLLCON0_INSEL_SYSCLK (2 << TC3X_SYSPLLCON0_INSEL_SHIFT) + +#define TC3X_SYSPLLCON1_K2DIV_SHIFT 0 +#define TC3X_SYSPLLCON1_K2DIV_MASK GENMASK(2, 0) + +#define TC3X_PERPLLSTAT_PWDSTAT BIT(1) +#define TC3X_PERPLLSTAT_LOCK BIT(2) +#define TC3X_PERPLLSTAT_K3RDY BIT(4) +#define TC3X_PERPLLSTAT_K2RDY BIT(5) + +#define TC3X_PERPLLCON0_DIVBY BIT(0) +#define TC3X_PERPLLCON0_NDIV_SHIFT 9 +#define TC3X_PERPLLCON0_NDIV_MASK GENMASK(15, 9) +#define TC3X_PERPLLCON0_PLLPWD BIT(16) +#define TC3X_PERPLLCON0_RESLD BIT(18) +#define TC3X_PERPLLCON0_PDIV_SHIFT 24 +#define TC3X_PERPLLCON0_PDIV_MASK GENMASK(26, 24) + +#define TC3X_PERPLLCON1_K2DIV_SHIFT 0 +#define TC3X_PERPLLCON1_K2DIV_MASK GENMASK(2, 0) +#define TC3X_PERPLLCON1_K3DIV_SHIFT 8 +#define TC3X_PERPLLCON1_K3DIV_MASK GENMASK(10, 8) + +#define TC3X_CCUCON0_STMDIV_SHIFT 0 +#define TC3X_CCUCON0_STMDIV_MASK GENMASK(3, 0) +#define TC3X_CCUCON0_GTMDIV_SHIFT 4 +#define TC3X_CCUCON0_GTMDIV_MASK GENMASK(7, 4) +#define TC3X_CCUCON0_SRIDIV_SHIFT 8 +#define TC3X_CCUCON0_SRIDIV_MASK GENMASK(11, 8) +#define TC3X_CCUCON0_LPDIV_SHIFT 12 +#define TC3X_CCUCON0_LPDIV_MASK GENMASK(14, 12) +#define TC3X_CCUCON0_SPBDIV_SHIFT 16 +#define TC3X_CCUCON0_SPBDIV_MASK GENMASK(19, 16) +#define TC3X_CCUCON0_BBBDIV_SHIFT 20 +#define TC3X_CCUCON0_BBBDIV_MASK GENMASK(23, 20) +#define TC3X_CCUCON0_FSIDIV_SHIFT 24 +#define TC3X_CCUCON0_FSIDIV_MASK GENMASK(25, 24) +#define TC3X_CCUCON0_FSI2DIV_SHIFT 26 +#define TC3X_CCUCON0_FSI2DIV_MASK GENMASK(27, 26) +#define TC3X_CCUCON0_CLKSEL_SHIFT 28 +#define TC3X_CCUCON0_CLKSEL_MASK GENMASK(29, 28) +#define TC3X_CCUCON0_UP BIT(30) +#define TC3X_CCUCON0_LCK BIT(31) + +/* CLKSEL encodings */ + +#define TC3X_CCUCON0_CLKSEL_FBACK (0 << TC3X_CCUCON0_CLKSEL_SHIFT) +#define TC3X_CCUCON0_CLKSEL_PLL (1 << TC3X_CCUCON0_CLKSEL_SHIFT) + +#define TC3X_CCUCON1_MCANDIV_SHIFT 0 +#define TC3X_CCUCON1_MCANDIV_MASK GENMASK(3, 0) +#define TC3X_CCUCON1_CLKSELMCAN_SHIFT 4 +#define TC3X_CCUCON1_CLKSELMCAN_MASK GENMASK(5, 4) +#define TC3X_CCUCON1_PLL1DIVDIS BIT(7) +#define TC3X_CCUCON1_I2CDIV_SHIFT 8 +#define TC3X_CCUCON1_I2CDIV_MASK GENMASK(11, 8) +#define TC3X_CCUCON1_MSCDIV_SHIFT 16 +#define TC3X_CCUCON1_MSCDIV_MASK GENMASK(19, 16) +#define TC3X_CCUCON1_CLKSELMSC_SHIFT 20 +#define TC3X_CCUCON1_CLKSELMSC_MASK GENMASK(21, 20) +#define TC3X_CCUCON1_QSPIDIV_SHIFT 24 +#define TC3X_CCUCON1_QSPIDIV_MASK GENMASK(27, 24) +#define TC3X_CCUCON1_CLKSELQSPI_SHIFT 28 +#define TC3X_CCUCON1_CLKSELQSPI_MASK GENMASK(29, 28) +#define TC3X_CCUCON1_LCK BIT(31) + +/* CLKSELMCAN encodings */ + +#define TC3X_CLKSEL_MCAN_OFF 0 +#define TC3X_CLKSEL_MCAN_FMCANI 1 +#define TC3X_CLKSEL_MCAN_FOSC 2 + +/* CLKSELMSC / CLKSELQSPI encodings */ + +#define TC3X_CLKSEL_OFF 0 +#define TC3X_CLKSEL_SRC1 1 +#define TC3X_CLKSEL_SRC2 2 + +/* CLKSELASCLINS encodings (in CCUCON2) */ + +#define TC3X_CLKSEL_ASCLINS_OFF 0 +#define TC3X_CLKSEL_ASCLINS_FASCLINSI 1 +#define TC3X_CLKSEL_ASCLINS_FOSC 2 + +#define TC3X_CCUCON2_ASCLINFDIV_SHIFT 0 +#define TC3X_CCUCON2_ASCLINFDIV_MASK GENMASK(3, 0) +#define TC3X_CCUCON2_ASCLINSDIV_SHIFT 8 +#define TC3X_CCUCON2_ASCLINSDIV_MASK GENMASK(11, 8) +#define TC3X_CCUCON2_CLKSELASCLINS_SHIFT 12 +#define TC3X_CCUCON2_CLKSELASCLINS_MASK GENMASK(13, 12) +#define TC3X_CCUCON2_EBUPERON BIT(24) +#define TC3X_CCUCON2_ERAYPERON BIT(25) +#define TC3X_CCUCON2_HSPDMPERON BIT(26) +#define TC3X_CCUCON2_LCK BIT(31) + +#define TC3X_CCUCON5_GETHDIV_SHIFT 0 +#define TC3X_CCUCON5_GETHDIV_MASK GENMASK(3, 0) +#define TC3X_CCUCON5_MCANHDIV_SHIFT 4 +#define TC3X_CCUCON5_MCANHDIV_MASK GENMASK(7, 4) +#define TC3X_CCUCON5_ADASDIV_SHIFT 8 +#define TC3X_CCUCON5_ADASDIV_MASK GENMASK(11, 8) +#define TC3X_CCUCON5_UP BIT(30) +#define TC3X_CCUCON5_LCK BIT(31) + +#define TC3X_CCUCONx_CPUDIV_SHIFT 0 +#define TC3X_CCUCONx_CPUDIV_MASK GENMASK(5, 0) + +#define TC3X_EXTCON_EN0 BIT(0) +#define TC3X_EXTCON_SEL0_SHIFT 2 +#define TC3X_EXTCON_SEL0_MASK GENMASK(5, 2) +#define TC3X_EXTCON_EN1 BIT(16) +#define TC3X_EXTCON_NSEL BIT(17) +#define TC3X_EXTCON_SEL1_SHIFT 18 +#define TC3X_EXTCON_SEL1_MASK GENMASK(21, 18) +#define TC3X_EXTCON_DIV1_SHIFT 24 +#define TC3X_EXTCON_DIV1_MASK GENMASK(31, 24) + +/* EXTCLK0 SEL0 source encodings */ + +enum tc3x_extclk0_sel +{ + TC3X_EXTCLK0_FOUT = 0x0, + TC3X_EXTCLK0_FPLL0 = 0x1, + TC3X_EXTCLK0_FPLL1 = 0x2, + TC3X_EXTCLK0_FOSC = 0x3, + TC3X_EXTCLK0_FBACK = 0x4, + TC3X_EXTCLK0_FPLL2 = 0x5, + TC3X_EXTCLK0_FBBB = 0x6, + TC3X_EXTCLK0_FSRI = 0x8, + TC3X_EXTCLK0_FSPB = 0x9, + TC3X_EXTCLK0_FFSI = 0xa, + TC3X_EXTCLK0_FSTM = 0xb, + TC3X_EXTCLK0_FGTM = 0xc, + TC3X_EXTCLK0_FFSI2 = 0xe, +}; + +#define TC3X_FBACK_HZ 100000000u /* 100 MHz backup clock */ +#define TC3X_FOSC_HZ 20000000u /* 20 MHz external crystal */ + +/* SYSPLL: fDCO = 20 * 30 / 1 = 600 MHz */ + +#define TC3X_SYSPLL_PDIV 1u +#define TC3X_SYSPLL_NDIV 30u +#define TC3X_SYSPLL_K2DIV 2u +#define TC3X_SYSPLL_K2DIV_INIT 6u + +/* PERPLL: fDCO = 20 * 32 / 1 = 640 MHz */ + +#define TC3X_PERPLL_PDIV 1u +#define TC3X_PERPLL_NDIV 32u +#define TC3X_PERPLL_K2DIV 2u +#define TC3X_PERPLL_K3DIV 2u +#define TC3X_PERPLL_DIVBY 0u + +/* PLL1DIVDIS: 0 -> fsource1 = fPLL1/2 = 160 MHz */ + +#define TC3X_PLL1DIVDIS 0u + +#define TC3X_FSOURCE0_HZ 300000000 +#define TC3X_FSOURCE1_HZ 160000000 +#define TC3X_FSOURCE2_HZ 200000000 + +#define TC3X_FSRI_TARGET_HZ 300000000 +#define TC3X_FSPB_TARGET_HZ 100000000 +#define TC3X_FBBB_TARGET_HZ 150000000 +#define TC3X_FSTM_TARGET_HZ 100000000 +#define TC3X_FFSI_TARGET_HZ 100000000 +#define TC3X_FFSI2_TARGET_HZ 300000000 + +#define TC3X_FGETH_TARGET_HZ 150000000 +#define TC3X_FMCANH_TARGET_HZ 100000000 +#define TC3X_FADAS_TARGET_HZ 300000000 + +#define TC3X_FMCANI_TARGET_HZ 80000000 + +#define TC3X_FQSPI_TARGET_HZ 200000000 +#define TC3X_FMSC_TARGET_HZ 200000000 +#define TC3X_FI2C_TARGET_HZ 66666667 + +#define TC3X_FASCLINF_TARGET_HZ 200000000 /* 200 MHz */ + +#define TC3X_FASCLINS_TARGET_HZ 80000000 /* 80 MHz */ + +#define TC3X_FGTM_TARGET_HZ 200000000 /* 200 MHz */ + +#endif /* __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_CLOCK_H */ diff --git a/arch/tricore/src/tc3x/tc3x_clockconfig.c b/arch/tricore/src/tc3x/tc3x_clockconfig.c new file mode 100644 index 0000000000000..6edafda6fda80 --- /dev/null +++ b/arch/tricore/src/tc3x/tc3x_clockconfig.c @@ -0,0 +1,403 @@ +/**************************************************************************** + * arch/tricore/src/tc3x/tc3x_clockconfig.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include "tricore_internal.h" + +#include "hardware/tc3x_clock.h" + +#ifndef DIV_ROUND_UP +# define DIV_ROUND_UP(n, d) (((n) + (d) - 1u) / (d)) +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FIELD_PREP(mask, shift, val) (((uint32_t)(val) << (shift)) & (mask)) +#define REGADDR(off) (TC3X_SCU_BASE + (off)) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +static inline void tc3x_busywait(unsigned int loops) +{ + volatile unsigned int i; + for (i = 0; i < loops; i++) + { + __asm__ __volatile__("nop"); + } +} + +static inline void tc3x_ccucon0_wait_unlocked(void) +{ + while (getreg32(REGADDR(TC3X_CLOCK_CCUCON0_OFFSET)) & TC3X_CCUCON0_LCK) + { + __asm__ __volatile__("nop"); + } +} + +static inline void tc3x_ccucon_wait_unlocked(uint32_t offset) +{ + while (getreg32(REGADDR(offset)) & BIT(31)) + { + __asm__ __volatile__("nop"); + } +} + +static void tc3x_osc_init(void) +{ + uint32_t addr = REGADDR(TC3X_CLOCK_OSCCON_OFFSET); + uint32_t val; + uint32_t oscval; + + oscval = (TC3X_FOSC_HZ / 1000000u) - 15u; + + val = getreg32(addr); + val &= ~(TC3X_OSCCON_MODE_MASK | TC3X_OSCCON_OSCVAL_MASK | + TC3X_OSCCON_GAINSEL_MASK); + val |= TC3X_OSCCON_MODE_XTAL; + val |= FIELD_PREP(TC3X_OSCCON_OSCVAL_MASK, + TC3X_OSCCON_OSCVAL_SHIFT, + oscval); + val |= FIELD_PREP(TC3X_OSCCON_GAINSEL_MASK, + TC3X_OSCCON_GAINSEL_SHIFT, + 3u); + + aurix_safety_endinit_enable(false); + putreg32(val, addr); + aurix_safety_endinit_enable(true); + + while (1) + { + val = getreg32(addr); + if ((val & TC3X_OSCCON_PLLHV) && (val & TC3X_OSCCON_PLLLV)) + { + break; + } + + tc3x_busywait(100); + } +} + +static void tc3x_syspll_init(void) +{ + uint32_t con0 = REGADDR(TC3X_CLOCK_SYSPLLCON0_OFFSET); + uint32_t con1 = REGADDR(TC3X_CLOCK_SYSPLLCON1_OFFSET); + uint32_t stat = REGADDR(TC3X_CLOCK_SYSPLLSTAT_OFFSET); + uint32_t val; + + val = TC3X_SYSPLLCON0_INSEL_FOSC; + val |= FIELD_PREP(TC3X_SYSPLLCON0_PDIV_MASK, + TC3X_SYSPLLCON0_PDIV_SHIFT, + TC3X_SYSPLL_PDIV - 1u); + val |= FIELD_PREP(TC3X_SYSPLLCON0_NDIV_MASK, + TC3X_SYSPLLCON0_NDIV_SHIFT, + TC3X_SYSPLL_NDIV - 1u); + val |= TC3X_SYSPLLCON0_PLLPWD; + val |= TC3X_SYSPLLCON0_RESLD; + + aurix_safety_endinit_enable(false); + putreg32(val, con0); + aurix_safety_endinit_enable(true); + + val = FIELD_PREP(TC3X_SYSPLLCON1_K2DIV_MASK, + TC3X_SYSPLLCON1_K2DIV_SHIFT, + TC3X_SYSPLL_K2DIV_INIT - 1u); + + aurix_safety_endinit_enable(false); + putreg32(val, con1); + aurix_safety_endinit_enable(true); + + while (!(getreg32(stat) & TC3X_SYSPLLSTAT_LOCK)) + { + tc3x_busywait(10); + } +} + +static void tc3x_perpll_init(void) +{ + uint32_t con0 = REGADDR(TC3X_CLOCK_PERPLLCON0_OFFSET); + uint32_t con1 = REGADDR(TC3X_CLOCK_PERPLLCON1_OFFSET); + uint32_t stat = REGADDR(TC3X_CLOCK_PERPLLSTAT_OFFSET); + uint32_t val; + + val = 0; + if (TC3X_PERPLL_DIVBY) + { + val |= TC3X_PERPLLCON0_DIVBY; + } + + val |= FIELD_PREP(TC3X_PERPLLCON0_PDIV_MASK, + TC3X_PERPLLCON0_PDIV_SHIFT, + TC3X_PERPLL_PDIV - 1u); + val |= FIELD_PREP(TC3X_PERPLLCON0_NDIV_MASK, + TC3X_PERPLLCON0_NDIV_SHIFT, + TC3X_PERPLL_NDIV - 1u); + val |= TC3X_PERPLLCON0_PLLPWD; + val |= TC3X_PERPLLCON0_RESLD; + + aurix_safety_endinit_enable(false); + putreg32(val, con0); + aurix_safety_endinit_enable(true); + + val = 0; + val |= FIELD_PREP(TC3X_PERPLLCON1_K2DIV_MASK, + TC3X_PERPLLCON1_K2DIV_SHIFT, + TC3X_PERPLL_K2DIV - 1u); + val |= FIELD_PREP(TC3X_PERPLLCON1_K3DIV_MASK, + TC3X_PERPLLCON1_K3DIV_SHIFT, + TC3X_PERPLL_K3DIV - 1u); + + aurix_safety_endinit_enable(false); + putreg32(val, con1); + aurix_safety_endinit_enable(true); + + while (!(getreg32(stat) & TC3X_PERPLLSTAT_LOCK)) + { + tc3x_busywait(10); + } +} + +static void tc3x_ccu_set_dividers(void) +{ + uint32_t fsource0 = TC3X_FSOURCE0_HZ; + uint32_t fsource1 = TC3X_FSOURCE1_HZ; + uint32_t fsource2 = TC3X_FSOURCE2_HZ; + + uint32_t fsri_div; + uint32_t fspb_div; + uint32_t fbbb_div; + uint32_t fstm_div; + uint32_t fgeth_div; + uint32_t fmcanh_div; + uint32_t fadas_div; + + uint32_t fmcani_div; + uint32_t fi2c_div; + uint32_t fmsc_div; + uint32_t fqspi_div; + uint32_t fasclinf_div; + uint32_t fasclinsi_div; + + uint32_t val; + + /* System domain from fsource0 (300 MHz) */ + + fsri_div = DIV_ROUND_UP(fsource0, TC3X_FSRI_TARGET_HZ) & 0xfu; + fspb_div = DIV_ROUND_UP(fsource0, TC3X_FSPB_TARGET_HZ) & 0xfu; + fbbb_div = DIV_ROUND_UP(fsource0, TC3X_FBBB_TARGET_HZ) & 0xfu; + fstm_div = DIV_ROUND_UP(fsource0, TC3X_FSTM_TARGET_HZ) & 0xfu; + fgeth_div = DIV_ROUND_UP(fsource0, TC3X_FGETH_TARGET_HZ) & 0xfu; + fmcanh_div = DIV_ROUND_UP(fsource0, TC3X_FMCANH_TARGET_HZ) & 0xfu; + fadas_div = DIV_ROUND_UP(fsource0, TC3X_FADAS_TARGET_HZ) & 0xfu; + + /* Peripheral from fsource1 (160 MHz) */ + + fmcani_div = DIV_ROUND_UP(fsource1, TC3X_FMCANI_TARGET_HZ) & 0xfu; + fasclinsi_div = DIV_ROUND_UP(fsource1, TC3X_FASCLINS_TARGET_HZ) & 0xfu; + + /* Peripheral from fsource2 (200 MHz) */ + + fqspi_div = DIV_ROUND_UP(fsource2, TC3X_FQSPI_TARGET_HZ) & 0xfu; + fmsc_div = DIV_ROUND_UP(fsource2, TC3X_FMSC_TARGET_HZ) & 0xfu; + fi2c_div = DIV_ROUND_UP(fsource2, TC3X_FI2C_TARGET_HZ) & 0xfu; + fasclinf_div = DIV_ROUND_UP(fsource2, TC3X_FASCLINF_TARGET_HZ) & 0xfu; + + val = 0; + val |= FIELD_PREP(TC3X_CCUCON0_STMDIV_MASK, + TC3X_CCUCON0_STMDIV_SHIFT, + fstm_div); + val |= FIELD_PREP(TC3X_CCUCON0_GTMDIV_MASK, + TC3X_CCUCON0_GTMDIV_SHIFT, + 1u); + val |= FIELD_PREP(TC3X_CCUCON0_SRIDIV_MASK, + TC3X_CCUCON0_SRIDIV_SHIFT, + fsri_div); + val |= FIELD_PREP(TC3X_CCUCON0_SPBDIV_MASK, + TC3X_CCUCON0_SPBDIV_SHIFT, + fspb_div); + val |= FIELD_PREP(TC3X_CCUCON0_BBBDIV_MASK, + TC3X_CCUCON0_BBBDIV_SHIFT, + fbbb_div); + val |= FIELD_PREP(TC3X_CCUCON0_FSIDIV_MASK, + TC3X_CCUCON0_FSIDIV_SHIFT, + 3u); + val |= FIELD_PREP(TC3X_CCUCON0_FSI2DIV_MASK, + TC3X_CCUCON0_FSI2DIV_SHIFT, + 1u); + + tc3x_ccucon0_wait_unlocked(); + aurix_safety_endinit_enable(false); + putreg32(val, REGADDR(TC3X_CLOCK_CCUCON0_OFFSET)); + aurix_safety_endinit_enable(true); + + val = 0; + val |= FIELD_PREP(TC3X_CCUCON5_GETHDIV_MASK, + TC3X_CCUCON5_GETHDIV_SHIFT, + fgeth_div); + val |= FIELD_PREP(TC3X_CCUCON5_MCANHDIV_MASK, + TC3X_CCUCON5_MCANHDIV_SHIFT, + fmcanh_div); + val |= FIELD_PREP(TC3X_CCUCON5_ADASDIV_MASK, + TC3X_CCUCON5_ADASDIV_SHIFT, + fadas_div); + val |= TC3X_CCUCON5_UP; + + aurix_safety_endinit_enable(false); + putreg32(val, REGADDR(TC3X_CLOCK_CCUCON5_OFFSET)); + aurix_safety_endinit_enable(true); + + tc3x_ccucon0_wait_unlocked(); + + val = 0; + val |= FIELD_PREP(TC3X_CCUCON1_MCANDIV_MASK, + TC3X_CCUCON1_MCANDIV_SHIFT, + fmcani_div); + val |= FIELD_PREP(TC3X_CCUCON1_CLKSELMCAN_MASK, + TC3X_CCUCON1_CLKSELMCAN_SHIFT, + TC3X_CLKSEL_MCAN_FMCANI); + val |= FIELD_PREP(TC3X_CCUCON1_I2CDIV_MASK, + TC3X_CCUCON1_I2CDIV_SHIFT, + fi2c_div); + val |= FIELD_PREP(TC3X_CCUCON1_MSCDIV_MASK, + TC3X_CCUCON1_MSCDIV_SHIFT, + fmsc_div); + val |= FIELD_PREP(TC3X_CCUCON1_CLKSELMSC_MASK, + TC3X_CCUCON1_CLKSELMSC_SHIFT, + TC3X_CLKSEL_SRC2); + val |= FIELD_PREP(TC3X_CCUCON1_QSPIDIV_MASK, + TC3X_CCUCON1_QSPIDIV_SHIFT, + fqspi_div); + val |= FIELD_PREP(TC3X_CCUCON1_CLKSELQSPI_MASK, + TC3X_CCUCON1_CLKSELQSPI_SHIFT, + TC3X_CLKSEL_SRC2); + + if (TC3X_PLL1DIVDIS) + { + val |= TC3X_CCUCON1_PLL1DIVDIS; + } + + tc3x_ccucon_wait_unlocked(TC3X_CLOCK_CCUCON1_OFFSET); + aurix_safety_endinit_enable(false); + putreg32(val, REGADDR(TC3X_CLOCK_CCUCON1_OFFSET)); + aurix_safety_endinit_enable(true); + tc3x_ccucon_wait_unlocked(TC3X_CLOCK_CCUCON1_OFFSET); + + val = 0; + val |= FIELD_PREP(TC3X_CCUCON2_ASCLINFDIV_MASK, + TC3X_CCUCON2_ASCLINFDIV_SHIFT, + fasclinf_div); + val |= FIELD_PREP(TC3X_CCUCON2_ASCLINSDIV_MASK, + TC3X_CCUCON2_ASCLINSDIV_SHIFT, + fasclinsi_div); + val |= FIELD_PREP(TC3X_CCUCON2_CLKSELASCLINS_MASK, + TC3X_CCUCON2_CLKSELASCLINS_SHIFT, + TC3X_CLKSEL_ASCLINS_FASCLINSI); + val |= TC3X_CCUCON2_EBUPERON; + val |= TC3X_CCUCON2_ERAYPERON; + val |= TC3X_CCUCON2_HSPDMPERON; + + tc3x_ccucon_wait_unlocked(TC3X_CLOCK_CCUCON2_OFFSET); + aurix_safety_endinit_enable(false); + putreg32(val, REGADDR(TC3X_CLOCK_CCUCON2_OFFSET)); + aurix_safety_endinit_enable(true); + tc3x_ccucon_wait_unlocked(TC3X_CLOCK_CCUCON2_OFFSET); +} + +static void tc3x_ccu_select_clock(uint32_t clksel) +{ + uint32_t addr = REGADDR(TC3X_CLOCK_CCUCON0_OFFSET); + uint32_t val; + + tc3x_ccucon0_wait_unlocked(); + + val = getreg32(addr); + val &= ~(TC3X_CCUCON0_CLKSEL_MASK | TC3X_CCUCON0_UP); + val |= FIELD_PREP(TC3X_CCUCON0_CLKSEL_MASK, + TC3X_CCUCON0_CLKSEL_SHIFT, + clksel); + val |= TC3X_CCUCON0_UP; + + aurix_safety_endinit_enable(false); + putreg32(val, addr); + aurix_safety_endinit_enable(true); + + tc3x_ccucon0_wait_unlocked(); +} + +static void tc3x_syspll_k2_step(void) +{ + uint32_t con1 = REGADDR(TC3X_CLOCK_SYSPLLCON1_OFFSET); + uint32_t stat = REGADDR(TC3X_CLOCK_SYSPLLSTAT_OFFSET); + + static const uint32_t k2_steps[] = + { + 4u, /* fPLL0 = 150 MHz */ + + 3u, /* fPLL0 = 200 MHz */ + + 2u, /* fPLL0 = 300 MHz */ + }; + + unsigned int i; + + for (i = 0; i < sizeof(k2_steps) / sizeof(k2_steps[0]); i++) + { + uint32_t k2div_val = k2_steps[i] - 1u; + + while (!(getreg32(stat) & TC3X_SYSPLLSTAT_K2RDY)) + { + __asm__ __volatile__("nop"); + } + + aurix_safety_endinit_enable(false); + putreg32(k2div_val, con1); + aurix_safety_endinit_enable(true); + + tc3x_busywait(50000); + } + + while (!(getreg32(stat) & TC3X_SYSPLLSTAT_K2RDY)) + { + __asm__ __volatile__("nop"); + } +} + +void up_clockconfig(void) +{ + tc3x_osc_init(); + tc3x_syspll_init(); + tc3x_perpll_init(); + tc3x_ccu_set_dividers(); + tc3x_ccu_select_clock(1u); + tc3x_syspll_k2_step(); +} From dd7852785a46704a29271474732212c42f8a21d6 Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Fri, 15 May 2026 12:03:47 +0530 Subject: [PATCH 07/12] arch/tc4x: clock support The SCU PLL has to be brought up at boot so peripherals run at their intended rate. TC4X configures the PLL and clock tree through the Clock Control Unit (CCU). Signed-off-by: Saravanan Sekar --- .../platforms/tricore/tc4x/index.rst | 78 +- .../src/{tc4xx => tc4x}/CMakeLists.txt | 6 +- arch/tricore/src/tc4x/Make.defs | 1 + arch/tricore/src/tc4x/hardware/tc4x_clock.h | 399 ++++++++++ arch/tricore/src/tc4x/tc4x_clockconfig.c | 687 ++++++++++++++++++ 5 files changed, 1164 insertions(+), 7 deletions(-) rename arch/tricore/src/{tc4xx => tc4x}/CMakeLists.txt (88%) create mode 100644 arch/tricore/src/tc4x/hardware/tc4x_clock.h create mode 100644 arch/tricore/src/tc4x/tc4x_clockconfig.c diff --git a/Documentation/platforms/tricore/tc4x/index.rst b/Documentation/platforms/tricore/tc4x/index.rst index efe15dd157701..96f734768379b 100644 --- a/Documentation/platforms/tricore/tc4x/index.rst +++ b/Documentation/platforms/tricore/tc4x/index.rst @@ -2,13 +2,79 @@ AURIX TC4X ========== -NuttX support for the Infineon AURIX TC4X (TriCore TC1.8) family. +NuttX support for the Infineon AURIX TC4X (TriCore TC1.8P) family. -The TC4X port covers SCU clock tree bring-up (PLL, CCU dividers, -SafetyEndInit/CpuEndInit unlock), the IR/SRC interrupt routing -(SRPN equals the IRQ number), the System Timer (STM) oneshot and -ASCLIN-based UART. Boards select a particular TC4X variant through -``CONFIG_TC4X_CHIP_*``. +The TC4X port covers: + +- SCU clock tree bring-up (PLL, CCU dividers, Safety/CPU ENDINIT + unlock). +- IR/SRC interrupt routing (SRPN equals the NuttX IRQ number). +- System Timer (STM) periodic tick (64-bit ABS). +- ASCLIN-based UART (NSH console). +- GPIO pinmuxing through the AURIX layer. + +Boards select a particular TC4X variant through ``CONFIG_TC4X_CHIP_*``. + +Memory map (TC4D7 CPU0 view) +============================ + +================= ============ ================================= +Region Base Size / notes +================= ============ ================================= +PFLASH (uncached) 0x80000000 4 MiB (program flash, CPU0 bank) +PFLASH (cached) 0xA0000000 4 MiB (alias of PFLASH) +DSPR0 0x70000000 240 KiB (CPU0 data scratch-pad) +PSPR0 0x70100000 64 KiB (CPU0 program scratch-pad) +DLMU0 0x90000000 512 KiB (distributed LMU, CPU0) +LMU0 0x90400000 5 MiB (local memory unit) +================= ============ ================================= + +NuttX places the boot image in PFLASH starting at 0x80000000 (entry +``__start``). CPU0's data, BSS and CSA pool live in DSPR0; the +interrupt stack lives in PSPR0; the heap lives in LMU0. + +Interrupt Router mapping +======================== + +The TC4X Interrupt Router exposes SRC registers at +``0xF4432000 + 4*SRN`` and per-CPU LASR registers at +``0xF4430000 + 0x0C20 + tos*0x34``. ``SRPN`` (Service Request Priority +Number) equals the NuttX IRQ number; no remapping is performed. + +Peripherals used in the upstream port: + +================ ==== ========================================= +Peripheral SRN Default NuttX IRQ (Kconfig) +================ ==== ========================================= +ASCLIN0 RX 172 ``CONFIG_TRICORE_UART0_RXIRQ`` = 172 +ASCLIN0 TX 173 ``CONFIG_TRICORE_UART0_TXIRQ`` = 173 +ASCLIN0 ER 174 ``CONFIG_TRICORE_UART0_ERIRQ`` = 174 +ASCLIN1 RX 175 ``CONFIG_TRICORE_UART1_RXIRQ`` = 175 +ASCLIN1 TX 176 ``CONFIG_TRICORE_UART1_TXIRQ`` = 176 +ASCLIN1 ER 177 ``CONFIG_TRICORE_UART1_ERIRQ`` = 177 +STM0 SR0/SR1 8/9 (per-CPU; CPU0 only in this port) +================ ==== ========================================= + +Clock tree +========== + +The TC4X CCU clock tree is configured by +``arch/tricore/src/tc4x/tc4x_clockconfig.c``. The implementation +brings up the external oscillator, RAMP, SYSPLL and PERPLL, then +programs SYSCCUCON0/1 and PERCCUCON0/1 to produce the target divider +ratios documented in ``arch/tricore/src/tc4x/hardware/tc4x_clock.h``. + +ENDINIT unlock +============== + +TC4X folds the ENDINIT password sequence into the clock configuration +itself rather than using a separate WDT password helper. A single +direct-SFR routine in ``tc4x_clockconfig.c`` performs the required +Safety ENDINIT and CPU ENDINIT unlock/lock dance around every SCU +register write. + +Supported boards +================ .. toctree:: :maxdepth: 1 diff --git a/arch/tricore/src/tc4xx/CMakeLists.txt b/arch/tricore/src/tc4x/CMakeLists.txt similarity index 88% rename from arch/tricore/src/tc4xx/CMakeLists.txt rename to arch/tricore/src/tc4x/CMakeLists.txt index 1da5dfad24c3d..7c9e611742e29 100644 --- a/arch/tricore/src/tc4xx/CMakeLists.txt +++ b/arch/tricore/src/tc4x/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# arch/tricore/src/tc4xx/CMakeLists.txt +# arch/tricore/src/tc4x/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -19,3 +19,7 @@ # the License. # # ############################################################################## + +set(SRCS tc4x_clockconfig.c tc4x_watchdog.c) + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/tricore/src/tc4x/Make.defs b/arch/tricore/src/tc4x/Make.defs index 55697c423b826..7b46a9de6826d 100644 --- a/arch/tricore/src/tc4x/Make.defs +++ b/arch/tricore/src/tc4x/Make.defs @@ -20,6 +20,7 @@ # ############################################################################ +CHIP_CSRCS += tc4x_clockconfig.c CHIP_CSRCS += tc4x_watchdog.c VPATH += tc4x diff --git a/arch/tricore/src/tc4x/hardware/tc4x_clock.h b/arch/tricore/src/tc4x/hardware/tc4x_clock.h new file mode 100644 index 0000000000000..78adf47c1b012 --- /dev/null +++ b/arch/tricore/src/tc4x/hardware/tc4x_clock.h @@ -0,0 +1,399 @@ +/**************************************************************************** + * arch/tricore/src/tc4x/hardware/tc4x_clock.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_CLOCK_H +#define __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_CLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Base + 32-bit accessor */ + +#define TC4X_CLOCK_BASE 0xf0064000u /* CCU base */ + +#define TC4X_REG32(off) (*(volatile uint32_t *)(TC4X_CLOCK_BASE + (off))) + +#define TC4X_CLOCK_OSCCON_OFFSET 0x0100u +#define TC4X_CLOCK_OSCMON1_OFFSET 0x0508u + +#define TC4X_CLOCK_RAMPCON0_OFFSET 0x0200u +#define TC4X_CLOCK_RAMPSTAT_OFFSET 0x020cu + +#define TC4X_CLOCK_SYSPLLCON0_OFFSET 0x0300u +#define TC4X_CLOCK_SYSPLLCON1_OFFSET 0x0304u +#define TC4X_CLOCK_SYSPLLSTAT_OFFSET 0x030cu + +#define TC4X_CLOCK_PERPLLCON0_OFFSET 0x0380u +#define TC4X_CLOCK_PERPLLCON1_OFFSET 0x0384u +#define TC4X_CLOCK_PERPLLSTAT_OFFSET 0x038cu + +#define TC4X_CLOCK_CCUCON_OFFSET 0x0400u +#define TC4X_CLOCK_CCUSTAT_OFFSET 0x0404u + +#define TC4X_CLOCK_SYSCCUCON0_OFFSET 0x0410u +#define TC4X_CLOCK_SYSCCUCON1_OFFSET 0x0414u +#define TC4X_CLOCK_PERCCUCON0_OFFSET 0x0420u +#define TC4X_CLOCK_PERCCUCON1_OFFSET 0x0424u + +#define TC4X_CLOCK_OSCCON TC4X_REG32(TC4X_CLOCK_OSCCON_OFFSET) +#define TC4X_CLOCK_OSCMON1 TC4X_REG32(TC4X_CLOCK_OSCMON1_OFFSET) + +#define TC4X_CLOCK_RAMPCON0 TC4X_REG32(TC4X_CLOCK_RAMPCON0_OFFSET) +#define TC4X_CLOCK_RAMPSTAT TC4X_REG32(TC4X_CLOCK_RAMPSTAT_OFFSET) + +#define TC4X_CLOCK_SYSPLLCON0 TC4X_REG32(TC4X_CLOCK_SYSPLLCON0_OFFSET) +#define TC4X_CLOCK_SYSPLLCON1 TC4X_REG32(TC4X_CLOCK_SYSPLLCON1_OFFSET) +#define TC4X_CLOCK_SYSPLLSTAT TC4X_REG32(TC4X_CLOCK_SYSPLLSTAT_OFFSET) + +#define TC4X_CLOCK_PERPLLCON0 TC4X_REG32(TC4X_CLOCK_PERPLLCON0_OFFSET) +#define TC4X_CLOCK_PERPLLCON1 TC4X_REG32(TC4X_CLOCK_PERPLLCON1_OFFSET) +#define TC4X_CLOCK_PERPLLSTAT TC4X_REG32(TC4X_CLOCK_PERPLLSTAT_OFFSET) + +#define TC4X_CLOCK_CCUCON TC4X_REG32(TC4X_CLOCK_CCUCON_OFFSET) +#define TC4X_CLOCK_CCUSTAT TC4X_REG32(TC4X_CLOCK_CCUSTAT_OFFSET) + +#define TC4X_CLOCK_SYSCCUCON0 TC4X_REG32(TC4X_CLOCK_SYSCCUCON0_OFFSET) +#define TC4X_CLOCK_SYSCCUCON1 TC4X_REG32(TC4X_CLOCK_SYSCCUCON1_OFFSET) +#define TC4X_CLOCK_PERCCUCON0 TC4X_REG32(TC4X_CLOCK_PERCCUCON0_OFFSET) +#define TC4X_CLOCK_PERCCUCON1 TC4X_REG32(TC4X_CLOCK_PERCCUCON1_OFFSET) + +/* OSCCON fields */ + +#define TC4X_OSCCON_MODE_SHIFT 8 +#define TC4X_OSCCON_MODE_MASK GENMASK(10, 8) +#define TC4X_OSCCON_INSEL_SHIFT 24 +#define TC4X_OSCCON_INSEL_MASK GENMASK(25, 24) + +/* Convenient mode / input encodings */ + +#define TC4X_OSCCON_MODE_EXTCLK (0u << TC4X_OSCCON_MODE_SHIFT) +#define TC4X_OSCCON_MODE_XTAL (1u << TC4X_OSCCON_MODE_SHIFT) +#define TC4X_OSCCON_INSEL_XTAL (1u << TC4X_OSCCON_INSEL_SHIFT) + +/* OSCMON1 fields */ + +#define TC4X_OSCMON1_OSCVAL_SHIFT 0 +#define TC4X_OSCMON1_OSCVAL_MASK GENMASK(6, 0) +#define TC4X_OSCMON1_SMONEN BIT(8) /* sys PLL osc monitor enable */ +#define TC4X_OSCMON1_PMONEN BIT(24) /* per PLL osc monitor enable */ + +/* RAMPCON0 fields */ + +#define TC4X_RAMPCON0_UFL_SHIFT 0 +#define TC4X_RAMPCON0_UFL_MASK GENMASK(9, 0) +#define TC4X_RAMPCON0_CMD_SHIFT 16 +#define TC4X_RAMPCON0_CMD_MASK GENMASK(18, 16) +#define TC4X_RAMPCON0_PWR BIT(19) + +/* Command encodings */ + +#define TC4X_RAMPCON0_CMD_NONE (0u << TC4X_RAMPCON0_CMD_SHIFT) +#define TC4X_RAMPCON0_CMD_TOP (1u << TC4X_RAMPCON0_CMD_SHIFT) +#define TC4X_RAMPCON0_CMD_BOTTOM (2u << TC4X_RAMPCON0_CMD_SHIFT) + +/* RAMPSTAT fields */ + +#define TC4X_RAMPSTAT_FSTAT_SHIFT 16 +#define TC4X_RAMPSTAT_FSTAT GENMASK(17, 16) +#define TC4X_RAMPSTAT_SSTAT GENMASK(21, 20) +#define TC4X_RAMPSTAT_ACTIVE_SHIFT 23 +#define TC4X_RAMPSTAT_ACTIVE BIT(23) +#define TC4X_RAMPSTAT_FLLLOCK_SHIFT 24 +#define TC4X_RAMPSTAT_FLLLOCK BIT(24) + +/* SYSPLLCON0 fields */ + +#define TC4X_SYSPLLCON0_PLLPWR BIT(0) +#define TC4X_SYSPLLCON0_RESLD BIT(1) +#define TC4X_SYSPLLCON0_NDIV_SHIFT 8 +#define TC4X_SYSPLLCON0_NDIV_MASK GENMASK(14, 8) +#define TC4X_SYSPLLCON0_PDIV_SHIFT 16 +#define TC4X_SYSPLLCON0_PDIV_MASK GENMASK(18, 16) + +/* SYSPLLCON1 fields */ + +#define TC4X_SYSPLLCON1_K2DIV_SHIFT 0 +#define TC4X_SYSPLLCON1_K2DIV_MASK GENMASK(3, 0) +#define TC4X_SYSPLLCON1_K2PREDIV_SHIFT 4 +#define TC4X_SYSPLLCON1_K2PREDIV_MASK GENMASK(5, 4) +#define TC4X_SYSPLLCON1_K3DIV_SHIFT 8 +#define TC4X_SYSPLLCON1_K3DIV_MASK GENMASK(10, 8) +#define TC4X_SYSPLLCON1_K3PREDIV_SHIFT 12 +#define TC4X_SYSPLLCON1_K3PREDIV_MASK GENMASK(15, 12) + +/* PERPLLCON0 fields */ + +#define TC4X_PERPLLCON0_PLLPWR BIT(0) +#define TC4X_PERPLLCON0_RESLD BIT(1) +#define TC4X_PERPLLCON0_NDIV_SHIFT 8 +#define TC4X_PERPLLCON0_NDIV_MASK GENMASK(14, 8) +#define TC4X_PERPLLCON0_PDIV_SHIFT 16 +#define TC4X_PERPLLCON0_PDIV_MASK GENMASK(18, 16) + +/* PERPLLCON1 fields */ + +#define TC4X_PERPLLCON1_K2DIV_SHIFT 0 +#define TC4X_PERPLLCON1_K2DIV_MASK GENMASK(3, 0) +#define TC4X_PERPLLCON1_K2PREDIV_SHIFT 4 +#define TC4X_PERPLLCON1_K2PREDIV_MASK GENMASK(5, 4) +#define TC4X_PERPLLCON1_K3DIV_SHIFT 8 +#define TC4X_PERPLLCON1_K3DIV_MASK GENMASK(10, 8) +#define TC4X_PERPLLCON1_K3PREDIV_SHIFT 12 +#define TC4X_PERPLLCON1_K3PREDIV_MASK GENMASK(15, 12) +#define TC4X_PERPLLCON1_K4DIV_SHIFT 16 +#define TC4X_PERPLLCON1_K4DIV_MASK GENMASK(18, 16) +#define TC4X_PERPLLCON1_K4PREDIV_SHIFT 20 +#define TC4X_PERPLLCON1_K4PREDIV_MASK GENMASK(21, 20) + +/* SYSPLLSTAT / PERPLLSTAT common bits */ + +#define TC4X_PLLSTAT_PWRSTAT BIT(0) +#define TC4X_PLLSTAT_PLLLOCK_SHIFT 1 +#define TC4X_PLLSTAT_PLLLOCK BIT(1) + +/* CCUCON fields */ + +#define TC4X_CCUCON_CLKSELS_SHIFT 0 +#define TC4X_CCUCON_CLKSELS_MASK GENMASK(1, 0) +#define TC4X_CCUCON_CLKSELP_SHIFT 16 +#define TC4X_CCUCON_CLKSELP_MASK GENMASK(16, 16) + +/* Common source encodings (same for SYSCLK and PERCLK) */ + +enum tc4x_clk_source +{ + TC4X_CLK_SOURCE_PLL = 0, /* SYS: PLL0, PER: PERPLL */ + + TC4X_CLK_SOURCE_FBACK = 1, /* backup clock */ + + TC4X_CLK_SOURCE_FRAMP = 2, /* ramp oscillator */ +}; + +enum tc4x_rootclk_domain +{ + TC4X_ROOTCLK_SYS, + TC4X_ROOTCLK_PER, +}; + +/* CCUSTAT fields */ + +#define TC4X_CCUSTAT_LCK BIT(31) + +/* SYSCCUCON0 fields */ + +#define TC4X_SYSCCUCON0_SPBDIV_SHIFT 0 +#define TC4X_SYSCCUCON0_SPBDIV_MASK GENMASK(3, 0) +#define TC4X_SYSCCUCON0_CPBDIV_SHIFT 4 +#define TC4X_SYSCCUCON0_CPBDIV_MASK GENMASK(7, 4) +#define TC4X_SYSCCUCON0_TPBDIV_SHIFT 8 +#define TC4X_SYSCCUCON0_TPBDIV_MASK GENMASK(11, 8) +#define TC4X_SYSCCUCON0_SRIDIV_SHIFT 12 +#define TC4X_SYSCCUCON0_SRIDIV_MASK GENMASK(15, 12) +#define TC4X_SYSCCUCON0_FSIDIV_SHIFT 16 +#define TC4X_SYSCCUCON0_FSIDIV_MASK GENMASK(19, 16) +#define TC4X_SYSCCUCON0_FSI2DIV BIT(20) +#define TC4X_SYSCCUCON0_STMDIV_SHIFT 24 +#define TC4X_SYSCCUCON0_STMDIV_MASK GENMASK(27, 24) +#define TC4X_SYSCCUCON0_LPDIV BIT(28) +#define TC4X_SYSCCUCON0_UP BIT(30) + +/* SYSCCUCON1 fields */ + +#define TC4X_SYSCCUCON1_GETHDIV_SHIFT 0 +#define TC4X_SYSCCUCON1_GETHDIV_MASK GENMASK(3, 0) +#define TC4X_SYSCCUCON1_EGTMDIV_SHIFT 12 +#define TC4X_SYSCCUCON1_EGTMDIV_MASK GENMASK(15, 12) +#define TC4X_SYSCCUCON1_MCANHDIV_SHIFT 16 +#define TC4X_SYSCCUCON1_MCANHDIV_MASK GENMASK(19, 16) +#define TC4X_SYSCCUCON1_LETHDIV_SHIFT 20 +#define TC4X_SYSCCUCON1_LETHDIV_MASK GENMASK(23, 20) +#define TC4X_SYSCCUCON1_CANXLHDIV_SHIFT 24 +#define TC4X_SYSCCUCON1_CANXLHDIV_MASK GENMASK(27, 24) +#define TC4X_SYSCCUCON1_UP BIT(30) + +/* PERCCUCON0 fields */ + +#define TC4X_PERCCUCON0_MCANDIV_SHIFT 0 +#define TC4X_PERCCUCON0_MCANDIV_MASK GENMASK(3, 0) +#define TC4X_PERCCUCON0_CLKSELMCAN_SHIFT 4 +#define TC4X_PERCCUCON0_CLKSELMCAN_MASK GENMASK(5, 4) +#define TC4X_PERCCUCON0_MSCDIV_SHIFT 8 +#define TC4X_PERCCUCON0_MSCDIV_MASK GENMASK(11, 8) +#define TC4X_PERCCUCON0_CLKSELMSC_SHIFT 12 +#define TC4X_PERCCUCON0_CLKSELMSC_MASK GENMASK(13, 12) +#define TC4X_PERCCUCON0_QSPIDIV_SHIFT 16 +#define TC4X_PERCCUCON0_QSPIDIV_MASK GENMASK(19, 16) +#define TC4X_PERCCUCON0_CLKSELQSPI_SHIFT 20 +#define TC4X_PERCCUCON0_CLKSELQSPI_MASK GENMASK(21, 20) +#define TC4X_PERCCUCON0_I2CDIV_SHIFT 24 +#define TC4X_PERCCUCON0_I2CDIV_MASK GENMASK(27, 24) +#define TC4X_PERCCUCON0_PPUDIV_SHIFT 28 +#define TC4X_PERCCUCON0_PPUDIV_MASK GENMASK(31, 28) + +/* PERCCUCON1 fields */ + +/* CLKSEL encodings for PERCCUCON0/PERCCUCON1 (TC4Dx TRM, table SCU.CCU) */ + +#define TC4X_CLKSEL_MCAN_FOSC0 0u +#define TC4X_CLKSEL_MCAN_FSYS 1u +#define TC4X_CLKSEL_MCAN_FXBAR 2u +#define TC4X_CLKSEL_MCAN_FPLL1_K1 3u + +#define TC4X_CLKSEL_QSPI_FSPB 0u +#define TC4X_CLKSEL_QSPI_FSOURCE3 1u + +#define TC4X_CLKSEL_ASCLINS_FOSC0 1u + +#define TC4X_PERCCUCON1_ASCLINFDIV_SHIFT 0 +#define TC4X_PERCCUCON1_ASCLINFDIV_MASK GENMASK(3, 0) +#define TC4X_PERCCUCON1_XSPISLDIV_SHIFT 4 +#define TC4X_PERCCUCON1_XSPISLDIV_MASK GENMASK(7, 4) +#define TC4X_PERCCUCON1_ASCLINSDIV_SHIFT 8 +#define TC4X_PERCCUCON1_ASCLINSDIV_MASK GENMASK(11, 8) +#define TC4X_PERCCUCON1_CLKSELASCLINS_SHIFT 12 +#define TC4X_PERCCUCON1_CLKSELASCLINS_MASK GENMASK(13, 12) +#define TC4X_PERCCUCON1_CLKSELCANXL_SHIFT 14 +#define TC4X_PERCCUCON1_CLKSELCANXL_MASK GENMASK(15, 14) +#define TC4X_PERCCUCON1_ADCPERON BIT(16) +#define TC4X_PERCCUCON1_CANXLDIV_SHIFT 20 +#define TC4X_PERCCUCON1_CANXLDIV_MASK GENMASK(23, 20) +#define TC4X_PERCCUCON1_ERAYPERON BIT(24) +#define TC4X_PERCCUCON1_XSPIPERON BIT(25) +#define TC4X_PERCCUCON1_SDMMCPERON BIT(26) +#define TC4X_PERCCUCON1_HSCTPERON BIT(27) +#define TC4X_PERCCUCON1_LETH100PERON BIT(28) +#define TC4X_PERCCUCON1_UP BIT(30) + +#define TC4X_FBACK_HZ 100000000u /* 100 MHz backup clock */ +#define TC4X_FOSC_HZ 25000000u /* 25 MHz external crystal */ + +/* SYSPLL: fVCO = 25 MHz * 20 / 1 = 500 MHz, K2=1 => 500 MHz core */ + +#define TC4X_SYSPLL_PDIV 1u +#define TC4X_SYSPLL_NDIV 20u +#define TC4X_SYSPLL_K2DIV 1u +#define TC4X_SYSPLL_K2PREDIV 1u +#define TC4X_SYSPLL_K3DIV 1u +#define TC4X_SYSPLL_K3PREDIV 1u + +#define TC4X_SYSPLL_K2DIV_DEF 1u +#define TC4X_SYSPLL_K3DIV_DEF 1u +#define TC4X_SYSPLL_K3PREDIV_DEF 10u + +/* PERPLL: fVCO = 25 MHz * 32 / 1 = 800 MHz, K2=5 => 160 MHz */ + +#define TC4X_PERPLL_PDIV 1u +#define TC4X_PERPLL_NDIV 32u +#define TC4X_PERPLL_K2DIV 5u +#define TC4X_PERPLL_K2PREDIV 1u +#define TC4X_PERPLL_K3DIV 2u +#define TC4X_PERPLL_K3PREDIV 2u +#define TC4X_PERPLL_K4DIV 1u +#define TC4X_PERPLL_K4PREDIV 2u + +#define TC4X_PERPLL_K2DIV_DEF 1u +#define TC4X_PERPLL_K3DIV_DEF 1u +#define TC4X_PERPLL_K4DIV_DEF 1u + +#define TC4X_PERPLL_K2PREDIV_DEF 1u +#define TC4X_PERPLL_K3PREDIV_DEF 10u +#define TC4X_PERPLL_K4PREDIV_DEF 1u + +/* Target frequencies for key domains (unchanged) */ + +#define TC4X_EGTM_TARGET_HZ 500000000u /* 500 MHz */ +#define TC4X_FSRI_TARGET_HZ 500000000u /* 500 MHz */ +#define TC4X_FFSI_TARGET_HZ 100000000u /* 100 MHz */ +#define TC4X_FSPB_TARGET_HZ 100000000u /* 100 MHz */ +#define TC4X_FTPB_TARGET_HZ 250000000u /* 250 MHz */ +#define TC4X_FSTM_TARGET_HZ 500000000u /* 500 MHz */ +#define TC4X_FLETH_TARGET_HZ 125000000u /* 125 MHz */ +#define TC4X_FGETH_TARGET_HZ 250000000u /* 250 MHz */ +#define TC4X_CANXL_TARGET_HZ 250000000u /* 250 MHz */ +#define TC4X_MCANH_TARGET_HZ 100000000u /* 100 MHz */ +#define TC4X_MCANI_TARGET_HZ 80000000u /* 80 MHz */ +#define TC4X_ASCLINSI_TARGET_HZ 80000000u /* 80 MHz */ +#define TC4X_ASCLINF_TARGET_HZ 200000000u /* 200 MHz */ +#define TC4X_QSPI_TARGET_HZ 200000000u /* 200 MHz */ +#define TC4X_I2C_TARGET_HZ 66666667u /* 66.6 MHz */ +#define TC4X_PPU_TARGET_HZ 454545454u /* 45.45 MHz */ + +/* External clock control register (EXTCON) */ + +#define TC4X_CLOCK_EXTCON_OFFSET 0x0430u + +/* Accessor */ + +#define TC4X_CLOCK_EXTCON TC4X_REG32(TC4X_CLOCK_EXTCON_OFFSET) + +/* EXTCON bits */ + +#define TC4X_EXTCON_EN0 BIT(0) + +#define TC4X_EXTCON_SEL0_SHIFT 2 +#define TC4X_EXTCON_SEL0_MASK GENMASK(6, 2) + +/* SEL0 sources for EXTCLK0 (from UM) */ + +enum tc4x_extclk0_sel +{ + TC4X_EXTCLK0_FBACK = 0x00, + TC4X_EXTCLK0_FRAMP = 0x01, + TC4X_EXTCLK0_FOSC = 0x02, + TC4X_EXTCLK0_FPLL0 = 0x03, + TC4X_EXTCLK0_FPLL1 = 0x04, + TC4X_EXTCLK0_FPLL2 = 0x05, + TC4X_EXTCLK0_FPLL3 = 0x06, /* only if present */ + + TC4X_EXTCLK0_FFRAC = 0x07, + TC4X_EXTCLK0_FSPB = 0x08, + TC4X_EXTCLK0_FCPB = 0x09, /* if available */ + + TC4X_EXTCLK0_FTPB = 0x0a, + TC4X_EXTCLK0_FSRI = 0x0b, + TC4X_EXTCLK0_FFSI = 0x0c, + TC4X_EXTCLK0_FSTM = 0x0e, + TC4X_EXTCLK0_FGTM = 0x0f, /* if available */ + + TC4X_EXTCLK0_FEGTM = 0x10, /* if available */ + + TC4X_EXTCLK0_FGETH = 0x11, /* if available */ + + TC4X_EXTCLK0_FMCANH = 0x12, /* if available */ + + TC4X_EXTCLK0_FRCB = 0x15, /* if available */ + + TC4X_EXTCLK0_FLETH = 0x16, /* if available */ + + TC4X_EXTCLK0_FPPU = 0x17, /* async PPU only */ + + TC4X_EXTCLK0_FCANXLH = 0x18, /* if available */ +}; + +#endif /* __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_CLOCK_H */ diff --git a/arch/tricore/src/tc4x/tc4x_clockconfig.c b/arch/tricore/src/tc4x/tc4x_clockconfig.c new file mode 100644 index 0000000000000..2185c23b7e878 --- /dev/null +++ b/arch/tricore/src/tc4x/tc4x_clockconfig.c @@ -0,0 +1,687 @@ +/**************************************************************************** + * arch/tricore/src/tc4x/tc4x_clockconfig.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "tricore_internal.h" +#include "hardware/tc4x_clock.h" + +#ifndef DIV_ROUND_UP +# define DIV_ROUND_UP(n, d) (((n) + (d) - 1u) / (d)) +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void tc4x_busywait(unsigned int loops) +{ + volatile unsigned int i; + for (i = 0; i < loops; i++) + { + __asm__ __volatile__("nop"); + } +} + +/* Convenience: field prep without needing ffs() since we know SHIFT. */ + +#define FIELD_PREP(mask, shift, val) (((uint32_t)(val) << (shift)) & (mask)) +#define REGADDR(off) (TC4X_CLOCK_BASE + (off)) + +static inline void tc4x_ccu_wait_unlocked(void) +{ + while (getreg32(REGADDR(TC4X_CLOCK_CCUSTAT_OFFSET)) & TC4X_CCUSTAT_LCK) + { + __asm__ __volatile__("nop"); + } +} + +static void tc4x_osc_init(void) +{ + uint32_t addr; + uint32_t val; + + /* OSCCON: MODE = external clock, INSEL = XTAL input */ + + addr = REGADDR(TC4X_CLOCK_OSCCON_OFFSET); + val = getreg32(addr); + + val &= ~(TC4X_OSCCON_MODE_MASK | TC4X_OSCCON_INSEL_MASK); + val |= TC4X_OSCCON_MODE_EXTCLK; + val |= TC4X_OSCCON_INSEL_XTAL; + + tc4x_ccu_wait_unlocked(); + putreg32(val, addr); + + uint32_t mhz = TC4X_FOSC_HZ / 1000000u; + uint32_t oscval = 0; + + if (mhz > 15u) + { + oscval = mhz - 15u; + } + + val = FIELD_PREP(TC4X_OSCMON1_OSCVAL_MASK, + TC4X_OSCMON1_OSCVAL_SHIFT, + oscval); + + tc4x_ccu_wait_unlocked(); + putreg32(val, REGADDR(TC4X_CLOCK_OSCMON1_OFFSET)); + + /* Give oscillator some time to stabilise */ + + tc4x_busywait(100000); +} + +static void tc4x_syspll_init(void) +{ + uint32_t con0; + uint32_t con1; + uint32_t stat; + uint32_t val; + + con0 = REGADDR(TC4X_CLOCK_SYSPLLCON0_OFFSET); + con1 = REGADDR(TC4X_CLOCK_SYSPLLCON1_OFFSET); + stat = REGADDR(TC4X_CLOCK_SYSPLLSTAT_OFFSET); + + val = getreg32(con0); + val = ~TC4X_SYSPLLCON0_PLLPWR; + + tc4x_ccu_wait_unlocked(); + putreg32(val, con0); + + /* Wait for SYSPLL power status */ + + while ((getreg32(stat) & TC4X_PLLSTAT_PWRSTAT) != 0u) + { + } + + val = 0; + val |= FIELD_PREP(TC4X_SYSPLLCON1_K3PREDIV_MASK, + TC4X_SYSPLLCON1_K3PREDIV_SHIFT, + TC4X_SYSPLL_K3PREDIV_DEF); + + tc4x_ccu_wait_unlocked(); + modreg32(val, TC4X_SYSPLLCON1_K3PREDIV_MASK, con1); + + val = 0; + val |= FIELD_PREP(TC4X_SYSPLLCON1_K2DIV_MASK, + TC4X_SYSPLLCON1_K2DIV_SHIFT, + TC4X_SYSPLL_K2DIV_DEF); + val |= FIELD_PREP(TC4X_SYSPLLCON1_K3DIV_MASK, + TC4X_SYSPLLCON1_K3DIV_SHIFT, + TC4X_SYSPLL_K3DIV_DEF); + + tc4x_ccu_wait_unlocked(); + modreg32(val, + (TC4X_SYSPLLCON1_K2DIV_MASK | TC4X_SYSPLLCON1_K3DIV_MASK), con1); + + /* SYSPLL init */ + + val = 0; + val |= FIELD_PREP(TC4X_SYSPLLCON0_NDIV_MASK, + TC4X_SYSPLLCON0_NDIV_SHIFT, + TC4X_SYSPLL_NDIV - 1u); + val |= FIELD_PREP(TC4X_SYSPLLCON0_PDIV_MASK, + TC4X_SYSPLLCON0_PDIV_SHIFT, + TC4X_SYSPLL_PDIV - 1u); + val |= TC4X_SYSPLLCON0_PLLPWR; + val |= TC4X_SYSPLLCON0_RESLD; + + tc4x_ccu_wait_unlocked(); + putreg32(val, con0); + + /* Wait for SYSPLL power status */ + + while ((getreg32(stat) & TC4X_PLLSTAT_PWRSTAT) != 1u) + { + } + + tc4x_busywait(100); +} + +static void tc4x_perpll_init(void) +{ + uint32_t con0; + uint32_t con1; + uint32_t stat; + uint32_t val; + + con0 = REGADDR(TC4X_CLOCK_PERPLLCON0_OFFSET); + con1 = REGADDR(TC4X_CLOCK_PERPLLCON1_OFFSET); + stat = REGADDR(TC4X_CLOCK_PERPLLSTAT_OFFSET); + + val = getreg32(con0); + val = ~TC4X_PERPLLCON0_PLLPWR; + + tc4x_ccu_wait_unlocked(); + putreg32(val, con0); + + /* Wait for PERPLL power status */ + + while ((getreg32(stat) & TC4X_PLLSTAT_PWRSTAT) != 0u) + { + } + + val = 0; + val |= FIELD_PREP(TC4X_PERPLLCON1_K2PREDIV_MASK, + TC4X_PERPLLCON1_K2PREDIV_SHIFT, + TC4X_PERPLL_K2PREDIV_DEF); + val |= FIELD_PREP(TC4X_PERPLLCON1_K3PREDIV_MASK, + TC4X_PERPLLCON1_K3PREDIV_SHIFT, + TC4X_PERPLL_K3PREDIV_DEF); + val |= FIELD_PREP(TC4X_PERPLLCON1_K4PREDIV_MASK, + TC4X_PERPLLCON1_K4PREDIV_SHIFT, + TC4X_PERPLL_K4PREDIV_DEF); + tc4x_ccu_wait_unlocked(); + modreg32(val, + (TC4X_PERPLLCON1_K2PREDIV_MASK | + TC4X_PERPLLCON1_K3PREDIV_MASK | + TC4X_PERPLLCON1_K4PREDIV_MASK), con1); + + val = 0; + val |= FIELD_PREP(TC4X_PERPLLCON1_K2DIV_MASK, + TC4X_PERPLLCON1_K2DIV_SHIFT, + TC4X_PERPLL_K2DIV_DEF); + val |= FIELD_PREP(TC4X_PERPLLCON1_K3DIV_MASK, + TC4X_PERPLLCON1_K3DIV_SHIFT, + TC4X_PERPLL_K3DIV_DEF); + val |= FIELD_PREP(TC4X_PERPLLCON1_K4DIV_MASK, + TC4X_PERPLLCON1_K4DIV_SHIFT, + TC4X_PERPLL_K4DIV_DEF); + tc4x_ccu_wait_unlocked(); + modreg32(val, + (TC4X_PERPLLCON1_K2DIV_MASK | + TC4X_PERPLLCON1_K3DIV_MASK | + TC4X_PERPLLCON1_K4DIV_MASK), con1); + + val = 0; + val |= FIELD_PREP(TC4X_PERPLLCON0_NDIV_MASK, + TC4X_PERPLLCON0_NDIV_SHIFT, + TC4X_PERPLL_NDIV - 1u); + val |= FIELD_PREP(TC4X_PERPLLCON0_PDIV_MASK, + TC4X_PERPLLCON0_PDIV_SHIFT, + TC4X_PERPLL_PDIV - 1u); + val |= TC4X_PERPLLCON0_PLLPWR; + val |= TC4X_PERPLLCON0_RESLD; + + tc4x_ccu_wait_unlocked(); + putreg32(val, con0); + + /* Wait for PERPLL power status */ + + while ((getreg32(stat) & TC4X_PLLSTAT_PWRSTAT) != 1u) + { + } + + tc4x_busywait(100); +} + +static void tc4x_ccu_set_dividers(void) +{ + uint64_t sys_vco; + uint32_t fsource0; + uint64_t per_vco; + uint32_t fsource1; + uint32_t fsource2; + uint32_t fsourceppu; + + uint32_t fsri_div; + uint32_t fspb_div; + uint32_t ftpb_div; + uint32_t fstm_div; + uint32_t fleth_div; + uint32_t ffsi_div; + uint32_t fgeth_div; + uint32_t fegtm_div; + uint32_t fmcanh_div; + + uint32_t fmcani_div; + uint32_t fasclinf_div; + uint32_t fasclinsi_div; + uint32_t fqspi_div; + uint32_t fi2c_div; + + uint32_t fmcanxl_div; + uint32_t fppu_div; + uint32_t val; + + /* 500 Mhz */ + + sys_vco = (uint64_t)TC4X_FOSC_HZ * + (uint64_t)TC4X_SYSPLL_NDIV / + (uint64_t)TC4X_SYSPLL_PDIV; + + /* 500 Mhz */ + + fsource0 = (uint32_t)(sys_vco / + ((uint64_t)TC4X_SYSPLL_K2DIV * + (uint64_t)TC4X_SYSPLL_K2PREDIV)); + + /* 500 Mhz */ + + fsourceppu = (uint32_t)(sys_vco / + ((uint64_t)TC4X_SYSPLL_K3DIV * + (uint64_t)TC4X_SYSPLL_K3PREDIV)); + + /* 800 Mhz */ + + per_vco = (uint64_t)TC4X_FOSC_HZ * + (uint64_t)TC4X_PERPLL_NDIV / + (uint64_t)TC4X_PERPLL_PDIV; + + /* 160 Mhz */ + + fsource1 = (uint32_t)(per_vco / + ((uint64_t)TC4X_PERPLL_K2DIV * + (uint64_t)TC4X_PERPLL_K2PREDIV)); + + /* 200 Mhz */ + + fsource2 = (uint32_t)(per_vco / + ((uint64_t)TC4X_PERPLL_K3DIV * + (uint64_t)TC4X_PERPLL_K3PREDIV)); + + /* ---- System domain dividers from fsource0 (500 MHz) ---- */ + + fspb_div = DIV_ROUND_UP(fsource0, TC4X_FSPB_TARGET_HZ) & 0xfu; + fsri_div = DIV_ROUND_UP(fsource0, TC4X_FSRI_TARGET_HZ) & 0xfu; + ffsi_div = DIV_ROUND_UP(fsource0, TC4X_FFSI_TARGET_HZ) & 0xfu; + fstm_div = DIV_ROUND_UP(fsource0, TC4X_FSTM_TARGET_HZ) & 0xfu; + fgeth_div = DIV_ROUND_UP(fsource0, TC4X_FGETH_TARGET_HZ) & 0xfu; + fmcanh_div = DIV_ROUND_UP(fsource0, TC4X_MCANH_TARGET_HZ) & 0xfu; + fmcanxl_div = DIV_ROUND_UP(fsource0, TC4X_CANXL_TARGET_HZ) & 0xfu; + + ftpb_div = DIV_ROUND_UP(fsource0, TC4X_FTPB_TARGET_HZ) & 0xfu; + fleth_div = DIV_ROUND_UP(fsource0, TC4X_FLETH_TARGET_HZ) & 0xfu; + fegtm_div = DIV_ROUND_UP(fsource0, TC4X_EGTM_TARGET_HZ) & 0xfu; + + /* ---- Peripheral domain dividers from fsource1 (160 MHz) ---- */ + + fmcani_div = DIV_ROUND_UP(fsource1, TC4X_MCANI_TARGET_HZ) & 0xfu; + fasclinsi_div = DIV_ROUND_UP(fsource1, TC4X_ASCLINSI_TARGET_HZ) & 0xfu; + + /* ---- Peripheral domain dividers from fsource2 (200 MHz) ---- */ + + fi2c_div = DIV_ROUND_UP(fsource2, TC4X_I2C_TARGET_HZ) & 0xfu; + fasclinf_div = DIV_ROUND_UP(fsource2, TC4X_ASCLINF_TARGET_HZ) & 0xfu; + fqspi_div = DIV_ROUND_UP(fsource2, TC4X_QSPI_TARGET_HZ) & 0xfu; + + /* ---- Peripheral domain dividers from fsourceppu (500 MHz) ---- */ + + fppu_div = DIV_ROUND_UP(fsourceppu, TC4X_PPU_TARGET_HZ) & 0xfu; + + /* ---- Program SYSCCUCON0 ---- */ + + val = 0; + val |= FIELD_PREP(TC4X_SYSCCUCON0_SPBDIV_MASK, + TC4X_SYSCCUCON0_SPBDIV_SHIFT, + fspb_div); + val |= FIELD_PREP(TC4X_SYSCCUCON0_TPBDIV_MASK, + TC4X_SYSCCUCON0_TPBDIV_SHIFT, + ftpb_div); + val |= FIELD_PREP(TC4X_SYSCCUCON0_SRIDIV_MASK, + TC4X_SYSCCUCON0_SRIDIV_SHIFT, + fsri_div); + val |= FIELD_PREP(TC4X_SYSCCUCON0_FSIDIV_MASK, + TC4X_SYSCCUCON0_FSIDIV_SHIFT, + ffsi_div); + val |= FIELD_PREP(TC4X_SYSCCUCON0_STMDIV_MASK, + TC4X_SYSCCUCON0_STMDIV_SHIFT, + fstm_div); + + val |= TC4X_SYSCCUCON0_FSI2DIV; + + /* LPDIV left at reset */ + + val |= TC4X_SYSCCUCON0_UP; + + tc4x_ccu_wait_unlocked(); + putreg32(val, REGADDR(TC4X_CLOCK_SYSCCUCON0_OFFSET)); + + /* ---- Program SYSCCUCON1 ---- */ + + val = getreg32(REGADDR(TC4X_CLOCK_SYSCCUCON1_OFFSET)); + val = 0; + val |= FIELD_PREP(TC4X_SYSCCUCON1_GETHDIV_MASK, + TC4X_SYSCCUCON1_GETHDIV_SHIFT, + fgeth_div); + val |= FIELD_PREP(TC4X_SYSCCUCON1_EGTMDIV_MASK, + TC4X_SYSCCUCON1_EGTMDIV_SHIFT, + fegtm_div); + val |= FIELD_PREP(TC4X_SYSCCUCON1_MCANHDIV_MASK, + TC4X_SYSCCUCON1_MCANHDIV_SHIFT, + fmcanh_div); + val |= FIELD_PREP(TC4X_SYSCCUCON1_LETHDIV_MASK, + TC4X_SYSCCUCON1_LETHDIV_SHIFT, + fleth_div); + val |= FIELD_PREP(TC4X_SYSCCUCON1_CANXLHDIV_MASK, + TC4X_SYSCCUCON1_CANXLHDIV_SHIFT, + fmcanxl_div); + val |= TC4X_SYSCCUCON1_UP; + + tc4x_ccu_wait_unlocked(); + putreg32(val, REGADDR(TC4X_CLOCK_SYSCCUCON1_OFFSET)); + + /* ---- Program PERCCUCON0 ---- */ + + tc4x_ccu_wait_unlocked(); + putreg32(0, REGADDR(TC4X_CLOCK_PERCCUCON0_OFFSET)); + val = getreg32(REGADDR(TC4X_CLOCK_PERCCUCON0_OFFSET)); + val |= FIELD_PREP(TC4X_PERCCUCON0_MCANDIV_MASK, + TC4X_PERCCUCON0_MCANDIV_SHIFT, + fmcani_div); + val |= FIELD_PREP(TC4X_PERCCUCON0_CLKSELMCAN_MASK, + TC4X_PERCCUCON0_CLKSELMCAN_SHIFT, + TC4X_CLKSEL_MCAN_FSYS); + + val |= FIELD_PREP(TC4X_PERCCUCON0_QSPIDIV_MASK, + TC4X_PERCCUCON0_QSPIDIV_SHIFT, + fqspi_div); + val |= FIELD_PREP(TC4X_PERCCUCON0_CLKSELQSPI_MASK, + TC4X_PERCCUCON0_CLKSELQSPI_SHIFT, + TC4X_CLKSEL_QSPI_FSPB); + + val |= FIELD_PREP(TC4X_PERCCUCON0_I2CDIV_MASK, + TC4X_PERCCUCON0_I2CDIV_SHIFT, + fi2c_div); + val |= FIELD_PREP(TC4X_PERCCUCON0_PPUDIV_MASK, + TC4X_PERCCUCON0_PPUDIV_SHIFT, + fppu_div); + + tc4x_ccu_wait_unlocked(); + putreg32(val, REGADDR(TC4X_CLOCK_PERCCUCON0_OFFSET)); + + /* ---- Program PERCCUCON1 ---- */ + + tc4x_ccu_wait_unlocked(); + putreg32(0, REGADDR(TC4X_CLOCK_PERCCUCON1_OFFSET)); + val = getreg32(REGADDR(TC4X_CLOCK_PERCCUCON1_OFFSET)); + val |= FIELD_PREP(TC4X_PERCCUCON1_ASCLINFDIV_MASK, + TC4X_PERCCUCON1_ASCLINFDIV_SHIFT, + fasclinf_div); + val |= FIELD_PREP(TC4X_PERCCUCON1_ASCLINSDIV_MASK, + TC4X_PERCCUCON1_ASCLINSDIV_SHIFT, + fasclinsi_div); + val |= FIELD_PREP(TC4X_PERCCUCON1_CLKSELASCLINS_MASK, + TC4X_PERCCUCON1_CLKSELASCLINS_SHIFT, + TC4X_CLKSEL_ASCLINS_FOSC0); + + tc4x_ccu_wait_unlocked(); + putreg32(val, REGADDR(TC4X_CLOCK_PERCCUCON1_OFFSET)); +} + +static void tc4x_set_rootclk_source(enum tc4x_rootclk_domain dom, + enum tc4x_clk_source src) +{ + uint32_t addr = REGADDR(TC4X_CLOCK_CCUCON_OFFSET); + uint32_t val = getreg32(addr); + + switch (dom) + { + case TC4X_ROOTCLK_SYS: + val &= ~TC4X_CCUCON_CLKSELS_MASK; + val |= FIELD_PREP(TC4X_CCUCON_CLKSELS_MASK, + TC4X_CCUCON_CLKSELS_SHIFT, + (uint32_t)src); + break; + + case TC4X_ROOTCLK_PER: + val &= ~TC4X_CCUCON_CLKSELP_MASK; + val |= FIELD_PREP(TC4X_CCUCON_CLKSELP_MASK, + TC4X_CCUCON_CLKSELP_SHIFT, + (uint32_t)src); + break; + } + + tc4x_ccu_wait_unlocked(); + putreg32(val, addr); +} + +static void tc4x_set_sysclk_source(enum tc4x_clk_source src) +{ + tc4x_set_rootclk_source(TC4X_ROOTCLK_SYS, src); +} + +static void tc4x_set_perclk_source(enum tc4x_clk_source src) +{ + tc4x_set_rootclk_source(TC4X_ROOTCLK_PER, src); +} + +static void tc4x_ramposc_init(void) +{ + uint32_t con; + uint32_t stat; + uint32_t val; + + con = REGADDR(TC4X_CLOCK_RAMPCON0_OFFSET); + val = getreg32(con); + + val |= TC4X_RAMPCON0_PWR; + + tc4x_ccu_wait_unlocked(); + putreg32(val, con); + + stat = REGADDR(TC4X_CLOCK_RAMPSTAT_OFFSET); + while (((getreg32(stat) & TC4X_RAMPSTAT_ACTIVE) >> + TC4X_RAMPSTAT_ACTIVE_SHIFT) != 1) + { + } + + while (!((getreg32(stat) & TC4X_RAMPSTAT_FSTAT) >> + TC4X_RAMPSTAT_FSTAT_SHIFT)) + { + } + + if (((getreg32(stat) & TC4X_RAMPSTAT_FSTAT) >> + TC4X_RAMPSTAT_FSTAT_SHIFT) != 1) + { + val = getreg32(con); + val |= TC4X_RAMPCON0_CMD_BOTTOM; + + tc4x_ccu_wait_unlocked(); + putreg32(val, con); + + while (getreg32(stat) & TC4X_RAMPSTAT_FLLLOCK) + { + } + } +} + +static void tc4x_ramposc_move(void) +{ + uint32_t con; + uint32_t stat; + uint32_t val; + + con = REGADDR(TC4X_CLOCK_RAMPCON0_OFFSET); + stat = REGADDR(TC4X_CLOCK_RAMPSTAT_OFFSET); + + val = getreg32(stat); + if ((val & TC4X_RAMPSTAT_ACTIVE) && + (val & TC4X_RAMPSTAT_SSTAT) && + ((val & TC4X_RAMPSTAT_FSTAT) >> TC4X_RAMPSTAT_FSTAT_SHIFT) != 1) + { + return; + } + + val = 0; + val |= TC4X_RAMPCON0_PWR; + val |= FIELD_PREP(TC4X_RAMPCON0_UFL_MASK, + TC4X_RAMPCON0_UFL_SHIFT, + 500); + val |= FIELD_PREP(TC4X_RAMPCON0_CMD_MASK, + TC4X_RAMPCON0_CMD_SHIFT, + 1); + + tc4x_ccu_wait_unlocked(); + putreg32(val, con); + tc4x_busywait(100000); +} + +static void tc4x_set_syspll_divider(void) +{ + uint32_t con1; + uint32_t val; + + con1 = REGADDR(TC4X_CLOCK_SYSPLLCON1_OFFSET); + + /* SYSPLL default */ + + val = 0; + val |= FIELD_PREP(TC4X_SYSPLLCON1_K3PREDIV_MASK, + TC4X_SYSPLLCON1_K3PREDIV_SHIFT, + 1); + + tc4x_ccu_wait_unlocked(); + modreg32(val, TC4X_SYSPLLCON1_K3PREDIV_MASK, con1); + tc4x_busywait(100); + + val = 0; + val |= FIELD_PREP(TC4X_SYSPLLCON1_K2DIV_MASK, + TC4X_SYSPLLCON1_K2DIV_SHIFT, + 0); + val |= FIELD_PREP(TC4X_SYSPLLCON1_K3DIV_MASK, + TC4X_SYSPLLCON1_K3DIV_SHIFT, + 0); + + tc4x_ccu_wait_unlocked(); + modreg32(val, + (TC4X_SYSPLLCON1_K2DIV_MASK | TC4X_SYSPLLCON1_K3DIV_MASK), con1); +} + +static void tc4x_set_perpll_divider(void) +{ + uint32_t con1; + uint32_t val; + + con1 = REGADDR(TC4X_CLOCK_PERPLLCON1_OFFSET); + + val = 0; + val |= FIELD_PREP(TC4X_PERPLLCON1_K2PREDIV_MASK, + TC4X_PERPLLCON1_K2PREDIV_SHIFT, + 0); + val |= FIELD_PREP(TC4X_PERPLLCON1_K3PREDIV_MASK, + TC4X_PERPLLCON1_K3PREDIV_SHIFT, + TC4X_PERPLL_K3PREDIV_DEF); + val |= FIELD_PREP(TC4X_PERPLLCON1_K4PREDIV_MASK, + TC4X_PERPLLCON1_K4PREDIV_SHIFT, + TC4X_PERPLL_K4PREDIV_DEF); + tc4x_ccu_wait_unlocked(); + modreg32(val, + (TC4X_PERPLLCON1_K2PREDIV_MASK | + TC4X_PERPLLCON1_K3PREDIV_MASK | + TC4X_PERPLLCON1_K4PREDIV_MASK), con1); + + val = 0; + val |= FIELD_PREP(TC4X_PERPLLCON1_K2DIV_MASK, + TC4X_PERPLLCON1_K2DIV_SHIFT, + TC4X_PERPLL_K2DIV - 1u); + val |= FIELD_PREP(TC4X_PERPLLCON1_K3DIV_MASK, + TC4X_PERPLLCON1_K3DIV_SHIFT, + TC4X_PERPLL_K3DIV - 1u); + val |= FIELD_PREP(TC4X_PERPLLCON1_K4DIV_MASK, + TC4X_PERPLLCON1_K4DIV_SHIFT, + TC4X_PERPLL_K4DIV - 1u); + tc4x_ccu_wait_unlocked(); + modreg32(val, + (TC4X_PERPLLCON1_K2DIV_MASK | + TC4X_PERPLLCON1_K3DIV_MASK | + TC4X_PERPLLCON1_K4DIV_MASK), con1); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void up_clockconfig(void) +{ + uint32_t stat; + uint32_t val; + + /* External oscillator */ + + tc4x_osc_init(); + + /* RAMP oscillator */ + + tc4x_ramposc_init(); + + /* SYSPLL */ + + tc4x_syspll_init(); + + /* PERPLL */ + + tc4x_perpll_init(); + + /* CCU dividers for CPU + bus + periph clocks */ + + tc4x_ccu_set_dividers(); + + /* RAMP oscillator move */ + + tc4x_ramposc_move(); + + stat = REGADDR(TC4X_CLOCK_RAMPSTAT_OFFSET); + val = getreg32(stat); + if (((val & TC4X_RAMPSTAT_FLLLOCK) >> TC4X_RAMPSTAT_FLLLOCK_SHIFT) != 1) + { + return; + } + + stat = REGADDR(TC4X_CLOCK_SYSPLLSTAT_OFFSET); + val = getreg32(stat); + if (((val & TC4X_PLLSTAT_PLLLOCK) >> TC4X_PLLSTAT_PLLLOCK_SHIFT) != 1) + { + return; + } + + stat = REGADDR(TC4X_CLOCK_PERPLLSTAT_OFFSET); + val = getreg32(stat); + if (((val & TC4X_PLLSTAT_PLLLOCK) >> TC4X_PLLSTAT_PLLLOCK_SHIFT) != 1) + { + return; + } + + /* SYSPLL divider */ + + tc4x_set_syspll_divider(); + + /* Select PLLs as clock sources */ + + tc4x_set_sysclk_source(TC4X_CLK_SOURCE_PLL); + + /* PERPLL divider */ + + tc4x_set_perpll_divider(); + tc4x_set_perclk_source(TC4X_CLK_SOURCE_PLL); +} From 84a1742d04752660c7cde143a38685553da2d002 Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Fri, 15 May 2026 12:04:38 +0530 Subject: [PATCH 08/12] arch/aurix: GPIO support Peripherals need their input and output pads muxed to the right alternate function before they can move signals. Add GPIO pinmux helpers for both AURIX families so peripheral drivers added later in the series can call aurix_config_gpio() at init time and then talk to the line. Signed-off-by: Saravanan Sekar --- arch/tricore/Kconfig | 2 + arch/tricore/src/CMakeLists.txt | 8 +- arch/tricore/src/Makefile | 59 +++--- arch/tricore/src/aurix/Kconfig | 16 ++ arch/tricore/src/aurix/tricore_gpio.h | 215 +++++++++++++++++++++ arch/tricore/src/tc3x/CMakeLists.txt | 2 +- arch/tricore/src/tc3x/Make.defs | 1 + arch/tricore/src/tc3x/hardware/tc3x_gpio.h | 33 ++++ arch/tricore/src/tc3x/hardware/tc3x_port.h | 72 +++++++ arch/tricore/src/tc3x/tc3x_gpio.c | 148 ++++++++++++++ arch/tricore/src/tc4x/CMakeLists.txt | 2 +- arch/tricore/src/tc4x/Make.defs | 1 + arch/tricore/src/tc4x/hardware/tc4x_gpio.h | 33 ++++ arch/tricore/src/tc4x/hardware/tc4x_port.h | 77 ++++++++ arch/tricore/src/tc4x/tc4x_gpio.c | 152 +++++++++++++++ 15 files changed, 783 insertions(+), 38 deletions(-) create mode 100644 arch/tricore/src/aurix/Kconfig create mode 100644 arch/tricore/src/aurix/tricore_gpio.h create mode 100644 arch/tricore/src/tc3x/hardware/tc3x_gpio.h create mode 100644 arch/tricore/src/tc3x/hardware/tc3x_port.h create mode 100644 arch/tricore/src/tc3x/tc3x_gpio.c create mode 100644 arch/tricore/src/tc4x/hardware/tc4x_gpio.h create mode 100644 arch/tricore/src/tc4x/hardware/tc4x_port.h create mode 100644 arch/tricore/src/tc4x/tc4x_gpio.c diff --git a/arch/tricore/Kconfig b/arch/tricore/Kconfig index bfe65093b7769..fba75a08afcc1 100644 --- a/arch/tricore/Kconfig +++ b/arch/tricore/Kconfig @@ -71,6 +71,8 @@ config TRICORE_TOOLCHAIN_LLVM endchoice +source "arch/tricore/src/aurix/Kconfig" + if ARCH_CHIP_FAMILY_TC3X source "arch/tricore/src/tc3x/Kconfig" endif diff --git a/arch/tricore/src/CMakeLists.txt b/arch/tricore/src/CMakeLists.txt index 9f2686a11cec4..c65ea8ee9cfcf 100644 --- a/arch/tricore/src/CMakeLists.txt +++ b/arch/tricore/src/CMakeLists.txt @@ -23,13 +23,15 @@ add_subdirectory(${ARCH_SUBDIR}) add_subdirectory(${NUTTX_CHIP_ABS_DIR} EXCLUDE_FROM_ALL exclude_chip) add_subdirectory(common) +add_subdirectory(aurix) # Include directories (before system ones) as PUBLIC so that it can be exposed # to libboard target_include_directories(arch BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} common - ${ARCH_SUBDIR}) + aurix ${ARCH_SUBDIR}) if(NOT CONFIG_BUILD_FLAT) - target_include_directories(arch_interface BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} - common ${ARCH_SUBDIR}) + target_include_directories( + arch_interface BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} common aurix + ${ARCH_SUBDIR}) endif() diff --git a/arch/tricore/src/Makefile b/arch/tricore/src/Makefile index e86d95bfa1f2d..812bd2d0382f1 100644 --- a/arch/tricore/src/Makefile +++ b/arch/tricore/src/Makefile @@ -21,21 +21,21 @@ ############################################################################ include $(TOPDIR)/Make.defs -include chip/Make.defs include common/Make.defs +include aurix/Make.defs -ifeq ($(CONFIG_ARCH_CHIP_TC3XX),y) -ARCH_SUBDIR = tc3xx -include $(ARCH_SUBDIR)/Make.defs -else ifeq ($(CONFIG_ARCH_CHIP_TC4XX),y) -ARCH_SUBDIR = tc4xx -include $(ARCH_SUBDIR)/Make.defs +ifeq ($(CONFIG_ARCH_CHIP_FAMILY_TC3X),y) +ARCH_SUBDIR = tc3x +else ifeq ($(CONFIG_ARCH_CHIP_FAMILY_TC4X),y) +ARCH_SUBDIR = tc4x endif +include $(ARCH_SUBDIR)/Make.defs + ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src -INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)aurix INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)$(ARCH_SUBDIR) INCLUDES += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)sched @@ -52,10 +52,12 @@ ifeq ($(CONFIG_SCHED_INSTRUMENTATION_SYSCALL),y) EXTRALINKCMDS += @$(TOPDIR)/syscall/syscall_wraps.ldcmd endif -# The "head" object +# The "head" objects +HEAD_AOBJ = $(HEAD_ASRC:.S=$(OBJEXT)) HEAD_COBJ = $(HEAD_CSRC:.c=$(OBJEXT)) -STARTUP_OBJS ?= $(HEAD_COBJ) +HEAD_OBJS = $(HEAD_AOBJ) $(HEAD_COBJ) +STARTUP_OBJS ?= $(HEAD_OBJS) # Flat build or kernel-mode objects @@ -96,26 +98,18 @@ $(foreach lib,$(notdir $(wildcard $(APPDIR)$(DELIM)staging$(DELIM)*$(LIBEXT))), EXTRA_LIBS := $(filter-out $(NAMEFULL_LIBS) $(NAMESPEC_LIBS),$(EXTRA_LIBS)) EXTRA_LIBS += $(wildcard $(APPDIR)$(DELIM)staging$(DELIM)*$(LIBEXT)) -ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) - LIBPATH_OPT = --library-directory= - SCRIPT_OPT = --lsl-file= - LIBRARY_OPT = -l -else - LDFLAGS := $(addprefix -Xlinker ,$(LDFLAGS)) - LDFLAGS += $(CFLAGS) +LDFLAGS := $(addprefix -Xlinker ,$(LDFLAGS)) +LDFLAGS += $(CFLAGS) - LIBPATH_OPT = -L - SCRIPT_OPT = -T - LIBRARY_OPT = -l -endif +LIBPATH_OPT = -L +SCRIPT_OPT = -T +LIBRARY_OPT = -l ARCHSCRIPT := $(call CONVERT_PATH,$(ARCHSCRIPT)) LDFLAGS += $(addprefix $(SCRIPT_OPT),$(addsuffix .tmp,$(ARCHSCRIPT))) $(EXTRALINKCMDS) -ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),) - LDSTARTGROUP ?= -Wl,--start-group - LDENDGROUP ?= -Wl,--end-group -endif +LDSTARTGROUP ?= -Wl,--start-group +LDENDGROUP ?= -Wl,--end-group LIBPATHS += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)staging) @@ -131,15 +125,15 @@ ifeq ($(BOARDMAKE),y) LDLIBS += $(LIBRARY_OPT)board endif -VPATH += chip VPATH += common +VPATH += aurix VPATH += $(ARCH_SUBDIR) -all: $(HEAD_COBJ) $(BIN) +all: $(HEAD_OBJS) $(BIN) .PHONY: board$(DELIM)libboard$(LIBEXT) -$(AOBJS) $(UAOBJS): %$(OBJEXT): %.S +$(AOBJS) $(UAOBJS) $(HEAD_AOBJ): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) $(COBJS) $(UCOBJS) $(HEAD_COBJ): %$(OBJEXT): %.c @@ -163,7 +157,7 @@ define LINK_ALLSYMS $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp --orderbyname $(CONFIG_SYMTAB_ORDEREDBYNAME) $(Q) $(call COMPILE, allsyms.tmp, allsyms$(OBJEXT), -x c) $(Q) $(LD) $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ - -o $(NUTTX) $(HEAD_COBJ) allsyms$(OBJEXT) $(EXTRA_OBJS) \ + -o $(NUTTX) $(HEAD_OBJS) allsyms$(OBJEXT) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) $(Q) $(call DELFILE, allsyms.tmp allsyms$(OBJEXT)) endef @@ -171,12 +165,12 @@ endef $(addsuffix .tmp,$(ARCHSCRIPT)): $(ARCHSCRIPT) $(call PREPROCESS, $(patsubst %.tmp,%,$@), $@) -nuttx$(EXEEXT): $(HEAD_COBJ) board$(DELIM)libboard$(LIBEXT) $(EXTRA_LIBS) $(addsuffix .tmp,$(ARCHSCRIPT)) +nuttx$(EXEEXT): $(HEAD_OBJS) board$(DELIM)libboard$(LIBEXT) $(EXTRA_LIBS) $(addsuffix .tmp,$(ARCHSCRIPT)) $(Q) echo "LD: nuttx" ifneq ($(CONFIG_ALLSYMS),y) $(Q) $(LD) $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ - -o $(NUTTX) $(HEAD_COBJ) $(EXTRA_OBJS) \ + -o $(NUTTX) $(HEAD_OBJS) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) else $(Q) # Link and generate default table @@ -213,7 +207,7 @@ makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) $(call CATFILE, Make.dep, $^) $(call DELFILE, $^) -.depend: Makefile chip$(DELIM)Make.defs $(SRCS) $(TOPDIR)$(DELIM).config +.depend: Makefile $(ARCH_SUBDIR)$(DELIM)Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif @@ -239,7 +233,6 @@ distclean:: clean ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board distclean endif - $(call DELFILE, $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/arch/tricore/src/aurix/Kconfig b/arch/tricore/src/aurix/Kconfig new file mode 100644 index 0000000000000..305b44dcbcdc4 --- /dev/null +++ b/arch/tricore/src/aurix/Kconfig @@ -0,0 +1,16 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +menu "AURIX peripheral selection" + +config TC4X_GPIO_ACCESS_GROUP + int "TC4X port access group" + default 0 + range 0 7 + depends on ARCH_CHIP_FAMILY_TC4X + ---help--- + Access group used to drive the per-port PORTPROT register. + +endmenu diff --git a/arch/tricore/src/aurix/tricore_gpio.h b/arch/tricore/src/aurix/tricore_gpio.h new file mode 100644 index 0000000000000..cffdcef55a559 --- /dev/null +++ b/arch/tricore/src/aurix/tricore_gpio.h @@ -0,0 +1,215 @@ +/**************************************************************************** + * arch/tricore/src/aurix/tricore_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Common GPIO pin encoding and API for Infineon AURIX TriCore. + * + * gpio_pinset_t bit layout: + * + * 31 30 29:27 26:24 23:16 15:12 11:10 9:8 7:4 3:0 + * OD INIT PD[2:0] PL[2:0] PORT ALTPULL MODE --- (rsvd) PIN + * + * OD - Open drain (1=open-drain, 0=push-pull) + * INIT - Initial output value (1=high, 0=low) + * PD[2:0] - Pad driver mode / strength (TC4x: 3 bits, TC3x: lower 2 bits) + * PL[2:0] - Pad level selection / voltage (TC4x: 3, TC3x: lower 2 bits) + * PORT - Port number (0 .. 40+) + * ALT/PULL - For output/periph: alternate function 0-15 + * For input: 0=tristate, 1=pull-down, 2=pull-up + * MODE - 0=input, 1=output, 2=peripheral + * PIN - Pin within port (0-15) + */ + +#ifndef __ARCH_TRICORE_SRC_AURIX_TRICORE_GPIO_H +#define __ARCH_TRICORE_SRC_AURIX_TRICORE_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIO_PIN_SHIFT 0 +#define GPIO_PIN_MASK GENMASK(3, 0) +#define GPIO_PIN0 0 +#define GPIO_PIN1 1 +#define GPIO_PIN2 2 +#define GPIO_PIN3 3 +#define GPIO_PIN4 4 +#define GPIO_PIN5 5 +#define GPIO_PIN6 6 +#define GPIO_PIN7 7 +#define GPIO_PIN8 8 +#define GPIO_PIN9 9 +#define GPIO_PIN10 10 +#define GPIO_PIN11 11 +#define GPIO_PIN12 12 +#define GPIO_PIN13 13 +#define GPIO_PIN14 14 +#define GPIO_PIN15 15 + +/* Mode: bits 11:10 */ +#define GPIO_MODE_SHIFT 10 +#define GPIO_MODE_MASK GENMASK(11, 10) +#define GPIO_INPUT (0u << GPIO_MODE_SHIFT) +#define GPIO_OUTPUT (1u << GPIO_MODE_SHIFT) +#define GPIO_PERIPH (2u << GPIO_MODE_SHIFT) + +#define GPIO_FUNCALT_SHIFT 12 +#define GPIO_FUNCALT_MASK GENMASK(15, 12) + +/* Output alternate function encodings */ +#define GPIO_ALT0 (0u << GPIO_FUNCALT_SHIFT) /* GPIO */ +#define GPIO_ALT1 (1u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT2 (2u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT3 (3u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT4 (4u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT5 (5u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT6 (6u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT7 (7u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT8 (8u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT9 (9u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT10 (10u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT11 (11u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT12 (12u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT13 (13u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT14 (14u << GPIO_FUNCALT_SHIFT) +#define GPIO_ALT15 (15u << GPIO_FUNCALT_SHIFT) + +/* Input pull resistor encodings */ +#define GPIO_PULL_NONE (0u << GPIO_FUNCALT_SHIFT) +#define GPIO_PULL_DOWN (1u << GPIO_FUNCALT_SHIFT) +#define GPIO_PULL_UP (2u << GPIO_FUNCALT_SHIFT) + +/* Port number: bits 23:16 */ +#define GPIO_PORT_SHIFT 16 +#define GPIO_PORT_MASK GENMASK(22, 16) +#define GPIO_PORT(n) ((uint32_t)(n) << GPIO_PORT_SHIFT) +#define GPIO_PORT0 0 +#define GPIO_PORT1 1 +#define GPIO_PORT2 2 +#define GPIO_PORT3 3 +#define GPIO_PORT4 4 +#define GPIO_PORT5 5 +#define GPIO_PORT6 6 +#define GPIO_PORT7 7 +#define GPIO_PORT8 8 +#define GPIO_PORT9 9 +#define GPIO_PORT10 10 +#define GPIO_PORT11 11 +#define GPIO_PORT12 12 +#define GPIO_PORT13 13 +#define GPIO_PORT14 14 +#define GPIO_PORT15 15 +#define GPIO_PORT16 16 +#define GPIO_PORT17 17 +#define GPIO_PORT18 18 +#define GPIO_PORT19 19 +#define GPIO_PORT20 20 +#define GPIO_PORT21 21 +#define GPIO_PORT22 22 +#define GPIO_PORT23 23 +#define GPIO_PORT24 24 +#define GPIO_PORT25 25 +#define GPIO_PORT26 26 +#define GPIO_PORT27 27 +#define GPIO_PORT28 28 +#define GPIO_PORT29 29 +#define GPIO_PORT30 30 +#define GPIO_PORT31 31 +#define GPIO_PORT32 32 +#define GPIO_PORT33 33 +#define GPIO_PORT34 34 +#define GPIO_PORT35 35 +#define GPIO_PORT36 36 +#define GPIO_PORT37 37 +#define GPIO_PORT38 38 +#define GPIO_PORT39 39 + +#define GPIO_PERIPH_OWN_PAD BIT(23) + +#define GPIO_PADLEVEL_SHIFT 24 +#define GPIO_PADLEVEL_MASK GENMASK(26, 24) + +#define GPIO_PL(n) ((uint32_t)(n) << GPIO_PADLEVEL_SHIFT) + +#define GPIO_PADDRV_SHIFT 27 +#define GPIO_PADDRV_MASK GENMASK(29, 27) + +#define GPIO_PD(n) ((uint32_t)(n) << GPIO_PADDRV_SHIFT) + +#define GPIO_OUTPUT_HIGH BIT(30) +#define GPIO_OUTPUT_LOW 0 + +#define GPIO_OPEN_DRAIN BIT(31) + +#define GPIO_GET_PIN(ps) (((ps) & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT) +#define GPIO_GET_PORT(ps) (((ps) & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT) +#define GPIO_GET_MODE(ps) ((ps) & GPIO_MODE_MASK) +#define GPIO_GET_FUNCALT(ps) (((ps) & GPIO_FUNCALT_MASK) >> GPIO_FUNCALT_SHIFT) +#define GPIO_GET_PADLEVEL(ps) (((ps) & GPIO_PADLEVEL_MASK) >> GPIO_PADLEVEL_SHIFT) +#define GPIO_GET_PADDRV(ps) (((ps) & GPIO_PADDRV_MASK) >> GPIO_PADDRV_SHIFT) +#define GPIO_IS_OUTPUT(ps) (GPIO_GET_MODE(ps) != GPIO_INPUT) +#define GPIO_IS_OPENDRAIN(ps) (!!((ps) & GPIO_OPEN_DRAIN)) +#define GPIO_IS_INIT_HIGH(ps) (!!((ps) & GPIO_OUTPUT_HIGH)) +#define GPIO_IS_PERIPH_OWN_PAD(ps) (!!((ps) & GPIO_PERIPH_OWN_PAD)) + +#define AURIX_GPIO(port_n, pin_n, mode, funcalt) \ + (GPIO_PORT(port_n) | (mode) | (funcalt) | ((pin_n) & GPIO_PIN_MASK)) + +#define AURIX_GPIO_FULL(port_n, pin_n, mode, funcalt, od, init, pd, pl, ph) \ + (GPIO_PORT(port_n) | (mode) | (funcalt) | ((pin_n) & GPIO_PIN_MASK) | \ + (od) | (init) | GPIO_PD(pd) | GPIO_PL(pl) | (ph)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef uint32_t gpio_pinset_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: aurix_config_gpio + * + * Description: + * Configure a GPIO pin based on pin-encoded description. + * + * Input Parameters: + * pinset - Encoded pin configuration + * + * Returned Value: + * 0 on success, negative errno on failure + * + ****************************************************************************/ + +int aurix_config_gpio(gpio_pinset_t pinset); + +#endif /* __ARCH_TRICORE_SRC_AURIX_TRICORE_GPIO_H */ diff --git a/arch/tricore/src/tc3x/CMakeLists.txt b/arch/tricore/src/tc3x/CMakeLists.txt index 38ca5fbc37972..383a3baa26045 100644 --- a/arch/tricore/src/tc3x/CMakeLists.txt +++ b/arch/tricore/src/tc3x/CMakeLists.txt @@ -20,6 +20,6 @@ # # ############################################################################## -set(SRCS tc3x_clockconfig.c tc3x_watchdog.c) +set(SRCS tc3x_clockconfig.c tc3x_gpio.c tc3x_watchdog.c) target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/tricore/src/tc3x/Make.defs b/arch/tricore/src/tc3x/Make.defs index f1d1a105b08a9..f784023ec7f43 100644 --- a/arch/tricore/src/tc3x/Make.defs +++ b/arch/tricore/src/tc3x/Make.defs @@ -21,6 +21,7 @@ ############################################################################ CHIP_CSRCS += tc3x_clockconfig.c +CHIP_CSRCS += tc3x_gpio.c CHIP_CSRCS += tc3x_watchdog.c VPATH += tc3x diff --git a/arch/tricore/src/tc3x/hardware/tc3x_gpio.h b/arch/tricore/src/tc3x/hardware/tc3x_gpio.h new file mode 100644 index 0000000000000..fdac1ceee73a2 --- /dev/null +++ b/arch/tricore/src/tc3x/hardware/tc3x_gpio.h @@ -0,0 +1,33 @@ +/**************************************************************************** + * arch/tricore/src/tc3x/hardware/tc3x_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_GPIO_H +#define __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "tricore_gpio.h" +#include "tc3x_port.h" + +#endif /* __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_GPIO_H */ diff --git a/arch/tricore/src/tc3x/hardware/tc3x_port.h b/arch/tricore/src/tc3x/hardware/tc3x_port.h new file mode 100644 index 0000000000000..9e984884dcc20 --- /dev/null +++ b/arch/tricore/src/tc3x/hardware/tc3x_port.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * arch/tricore/src/tc3x/hardware/tc3x_port.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_PORT_H +#define __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_PORT_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AURIX_PORT_BASE 0xf003a000 +#define AURIX_PORT_STRIDE 0x100 +#define AURIX_PORT_ADDR(n) (AURIX_PORT_BASE + \ + ((uint32_t)(n) * AURIX_PORT_STRIDE)) + +#define PORT_OUT_OFFSET 0x00 +#define PORT_OMR_OFFSET 0x04 +#define PORT_ID_OFFSET 0x08 +#define PORT_IOCR_OFFSET 0x10 +#define PORT_IOCR4_OFFSET 0x14 +#define PORT_IOCR8_OFFSET 0x18 +#define PORT_IOCR12_OFFSET 0x1c +#define PORT_IN_OFFSET 0x24 +#define PORT_PDR0_OFFSET 0x40 +#define PORT_PDR1_OFFSET 0x44 +#define PORT_ESR_OFFSET 0x50 +#define PORT_PDISC_OFFSET 0x60 +#define PORT_PCSR_OFFSET 0x64 +#define PORT_LPCR_OFFSET 0xa0 +#define PORT_ACCEN1_OFFSET 0xf8 +#define PORT_ACCEN0_OFFSET 0xfc + +#define PORT_IOCR_REG(pin) (PORT_IOCR_OFFSET + ((pin) / 4) * 4) +#define PORT_IOCR_PC_SHIFT(pin) (((pin) % 4) * 8 + 3) +#define PORT_IOCR_PC_MASK(pin) (0x1f << PORT_IOCR_PC_SHIFT(pin)) + +#define PORT_PC_INPUT 0x00 +#define PORT_PC_INPUT_PD 0x01 +#define PORT_PC_INPUT_PU 0x02 +#define PORT_PC_OUTPUT 0x10 +#define PORT_PC_OUTPUT_OD 0x18 +#define PORT_PC_OUTPUT_ALT(n) (0x10 | ((n) & 0x07)) + +#define PORT_PDR_REG(pin) (PORT_PDR0_OFFSET + ((pin) / 8) * 4) +#define PORT_PDR_SHIFT(pin) (((pin) % 8) * 4) +#define PORT_PDR_MASK(pin) (0x0f << PORT_PDR_SHIFT(pin)) + +#define PORT_PDR_VAL(pd, pl) (((pl) << 2) | (pd)) + +#define PORT_OMR_SET(pin) BIT(pin) +#define PORT_OMR_CLR(pin) BIT((pin) + 16) + +#endif /* __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_PORT_H */ diff --git a/arch/tricore/src/tc3x/tc3x_gpio.c b/arch/tricore/src/tc3x/tc3x_gpio.c new file mode 100644 index 0000000000000..658b11f85767c --- /dev/null +++ b/arch/tricore/src/tc3x/tc3x_gpio.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/tricore/src/tc3x/tc3x_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "tricore_gpio.h" +#include "tricore_internal.h" +#include "hardware/tc3x_port.h" + +static spinlock_t g_gpio_lock = SP_UNLOCKED; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline uintptr_t tc3x_port_base(uint32_t port) +{ + return AURIX_PORT_ADDR(port); +} + +static uint32_t tc3x_build_padcfg(gpio_pinset_t pinset) +{ + uint32_t mode = GPIO_GET_MODE(pinset); + uint32_t funcalt = GPIO_GET_FUNCALT(pinset); + uint32_t cfg; + + if (mode == GPIO_INPUT) + { + cfg = funcalt & 0x07; + } + else + { + cfg = PORT_PC_OUTPUT | (funcalt & 0x07); + + if (GPIO_IS_OPENDRAIN(pinset)) + { + cfg |= 0x08; + } + } + + return cfg; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: aurix_config_gpio + * + * Description: + * Configure a GPIO pin on TC3x. + * + ****************************************************************************/ + +int aurix_config_gpio(gpio_pinset_t pinset) +{ + irqstate_t flags; + uint32_t port = GPIO_GET_PORT(pinset); + uint32_t pin = GPIO_GET_PIN(pinset); + uintptr_t base = tc3x_port_base(port); + uint32_t cfg; + uint32_t iocr_off; + uint32_t iocr_shift; + uint32_t iocr_mask; + uint32_t pdr_off; + uint32_t pdr_shift; + uint32_t pdr_mask; + uint32_t pdr_val; + + if (pin > 15) + { + return -EINVAL; + } + + cfg = tc3x_build_padcfg(pinset); + + iocr_off = PORT_IOCR_REG(pin); + iocr_shift = PORT_IOCR_PC_SHIFT(pin); + iocr_mask = PORT_IOCR_PC_MASK(pin); + + pdr_off = PORT_PDR_REG(pin); + pdr_shift = PORT_PDR_SHIFT(pin); + pdr_mask = PORT_PDR_MASK(pin); + pdr_val = PORT_PDR_VAL(GPIO_GET_PADDRV(pinset) & 0x03, + GPIO_GET_PADLEVEL(pinset) & 0x03); + + flags = spin_lock_irqsave(&g_gpio_lock); + + if (GPIO_GET_MODE(pinset) != GPIO_INPUT) + { + if (GPIO_IS_INIT_HIGH(pinset)) + { + putreg32(PORT_OMR_SET(pin), base + PORT_OMR_OFFSET); + } + else + { + putreg32(PORT_OMR_CLR(pin), base + PORT_OMR_OFFSET); + } + } + + aurix_cpu_endinit_enable(false); + modreg32(pdr_val << pdr_shift, pdr_mask, base + pdr_off); + aurix_cpu_endinit_enable(true); + + if (GPIO_IS_PERIPH_OWN_PAD(pinset)) + { + aurix_safety_endinit_enable(false); + modreg32(BIT(pin), BIT(pin), base + PORT_PCSR_OFFSET); + aurix_safety_endinit_enable(true); + } + + modreg32(cfg << iocr_shift, iocr_mask, base + iocr_off); + + spin_unlock_irqrestore(&g_gpio_lock, flags); + + return OK; +} diff --git a/arch/tricore/src/tc4x/CMakeLists.txt b/arch/tricore/src/tc4x/CMakeLists.txt index 7c9e611742e29..319dec067733d 100644 --- a/arch/tricore/src/tc4x/CMakeLists.txt +++ b/arch/tricore/src/tc4x/CMakeLists.txt @@ -20,6 +20,6 @@ # # ############################################################################## -set(SRCS tc4x_clockconfig.c tc4x_watchdog.c) +set(SRCS tc4x_clockconfig.c tc4x_gpio.c tc4x_watchdog.c) target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/tricore/src/tc4x/Make.defs b/arch/tricore/src/tc4x/Make.defs index 7b46a9de6826d..9d7329c484c8b 100644 --- a/arch/tricore/src/tc4x/Make.defs +++ b/arch/tricore/src/tc4x/Make.defs @@ -21,6 +21,7 @@ ############################################################################ CHIP_CSRCS += tc4x_clockconfig.c +CHIP_CSRCS += tc4x_gpio.c CHIP_CSRCS += tc4x_watchdog.c VPATH += tc4x diff --git a/arch/tricore/src/tc4x/hardware/tc4x_gpio.h b/arch/tricore/src/tc4x/hardware/tc4x_gpio.h new file mode 100644 index 0000000000000..30337efc67853 --- /dev/null +++ b/arch/tricore/src/tc4x/hardware/tc4x_gpio.h @@ -0,0 +1,33 @@ +/**************************************************************************** + * arch/tricore/src/tc4x/hardware/tc4x_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_GPIO_H +#define __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "tricore_gpio.h" +#include "tc4x_port.h" + +#endif /* __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_GPIO_H */ diff --git a/arch/tricore/src/tc4x/hardware/tc4x_port.h b/arch/tricore/src/tc4x/hardware/tc4x_port.h new file mode 100644 index 0000000000000..41e8dfa1e198d --- /dev/null +++ b/arch/tricore/src/tc4x/hardware/tc4x_port.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/tricore/src/tc4x/hardware/tc4x_port.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_PORT_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_PORT_H + +#define AURIX_PORT_BASE 0xf003a000 +#define AURIX_PORT_STRIDE 0x400 +#define AURIX_PORT_ADDR(n) (AURIX_PORT_BASE + \ + ((uint32_t)(n) * AURIX_PORT_STRIDE)) + +#define PORT_ID_OFFSET 0x00 +#define PORT_RST_OFFSET 0x04 +#define PORT_WKEN_OFFSET 0x10 +#define PORT_WKSTS_OFFSET 0x14 +#define PORT_WKENSTS_OFFSET 0x18 +#define PORT_WKENSTSCLR_OFFSET 0x1c +#define PORT_OUT_OFFSET 0x20 +#define PORT_IN_OFFSET 0x24 +#define PORT_HWSELSTAT_OFFSET 0x28 +#define PORT_PDISC_OFFSET 0x2c +#define PORT_PROTSE_OFFSET 0x30 +#define PORT_PCSRSEL_OFFSET 0x34 +#define PORT_BGTRIM_OFFSET 0x38 +#define PORT_OMR_OFFSET 0x3c +#define PORT_OMCR_OFFSET 0x40 +#define PORT_OMSR_OFFSET 0x44 + +#define PORT_PADCFG_BASE 0x0300 +#define PORT_PADCFG_STRIDE 0x0010 +#define PORT_PADCFG_GPIO(pin) (PORT_PADCFG_BASE + \ + ((pin) * PORT_PADCFG_STRIDE) + 0x0) +#define PORT_PADCFG_DRVCFG(pin) (PORT_PADCFG_BASE + \ + ((pin) * PORT_PADCFG_STRIDE) + 0x4) + +#define PORT_ACCGRP_BASE 0x90 +#define PORT_ACCGRP_STRIDE 0x20 +#define PORT_ACCGRP_PROTE(grp) (PORT_ACCGRP_BASE + \ + ((grp) * PORT_ACCGRP_STRIDE) + 0x1c) + +#define PORT_DRVCFG_DIR BIT(0) +#define PORT_DRVCFG_OD BIT(1) +#define PORT_DRVCFG_MODE_SHIFT 4 +#define PORT_DRVCFG_MODE_MASK GENMASK(7, 4) +#define PORT_DRVCFG_PD_SHIFT 8 +#define PORT_DRVCFG_PD_MASK GENMASK(10, 8) +#define PORT_DRVCFG_PL_SHIFT 12 +#define PORT_DRVCFG_PL_MASK GENMASK(14, 12) + +#define PORT_OMR_SET(pin) BIT(pin) +#define PORT_OMR_CLR(pin) BIT((pin) + 16) + +#endif /* __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_PORT_H */ diff --git a/arch/tricore/src/tc4x/tc4x_gpio.c b/arch/tricore/src/tc4x/tc4x_gpio.c new file mode 100644 index 0000000000000..dfdbaa3975397 --- /dev/null +++ b/arch/tricore/src/tc4x/tc4x_gpio.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/tricore/src/tc4x/tc4x_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "tricore_gpio.h" +#include "tricore_internal.h" +#include "hardware/tc4x_port.h" + +#ifndef CONFIG_TC4X_GPIO_ACCESS_GROUP +# define CONFIG_TC4X_GPIO_ACCESS_GROUP 0 +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AURIX_PROT_STATE_RUN 0 +#define AURIX_PROT_STATE_CONFIG 1 +#define AURIX_PROT_SWEN BIT(3) + +static spinlock_t g_gpio_lock = SP_UNLOCKED; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +static inline uintptr_t tc4x_port_base(uint32_t port) +{ + return AURIX_PORT_ADDR(port); +} + +static void tc4x_prot_set_config(uintptr_t prot_addr) +{ + uint32_t val = getreg32(prot_addr); + + if ((val & 0x07) == AURIX_PROT_STATE_RUN) + { + putreg32(AURIX_PROT_STATE_CONFIG | AURIX_PROT_SWEN, prot_addr); + } +} + +static void tc4x_prot_set_run(uintptr_t prot_addr) +{ + putreg32(AURIX_PROT_STATE_RUN | AURIX_PROT_SWEN, prot_addr); +} + +static uint32_t tc4x_build_drvcfg(gpio_pinset_t pinset) +{ + uint32_t drvcfg = 0; + uint32_t mode = GPIO_GET_MODE(pinset); + uint32_t funcalt = GPIO_GET_FUNCALT(pinset); + + if (mode != GPIO_INPUT) + { + drvcfg |= PORT_DRVCFG_DIR; + } + + if (GPIO_IS_OPENDRAIN(pinset)) + { + drvcfg |= PORT_DRVCFG_OD; + } + + drvcfg |= (funcalt << PORT_DRVCFG_MODE_SHIFT) & PORT_DRVCFG_MODE_MASK; + + drvcfg |= (GPIO_GET_PADDRV(pinset) << PORT_DRVCFG_PD_SHIFT) + & PORT_DRVCFG_PD_MASK; + + drvcfg |= (GPIO_GET_PADLEVEL(pinset) << PORT_DRVCFG_PL_SHIFT) + & PORT_DRVCFG_PL_MASK; + + return drvcfg; +} + +int aurix_config_gpio(gpio_pinset_t pinset) +{ + irqstate_t flags; + uint32_t port = GPIO_GET_PORT(pinset); + uint32_t pin = GPIO_GET_PIN(pinset); + uintptr_t base = tc4x_port_base(port); + uintptr_t prot; + uint32_t drvcfg; + + if (pin > 15) + { + return -EINVAL; + } + + drvcfg = tc4x_build_drvcfg(pinset); + + flags = spin_lock_irqsave(&g_gpio_lock); + + if (GPIO_GET_MODE(pinset) == GPIO_OUTPUT) + { + if (GPIO_IS_INIT_HIGH(pinset)) + { + putreg32(PORT_OMR_SET(pin), base + PORT_OMR_OFFSET); + } + else + { + putreg32(PORT_OMR_CLR(pin), base + PORT_OMR_OFFSET); + } + } + + if (GPIO_IS_PERIPH_OWN_PAD(pinset)) + { + uintptr_t protse = base + PORT_PROTSE_OFFSET; + tc4x_prot_set_config(protse); + putreg32(BIT(pin), base + PORT_PCSRSEL_OFFSET); + tc4x_prot_set_run(protse); + } + + prot = base + PORT_ACCGRP_PROTE(CONFIG_TC4X_GPIO_ACCESS_GROUP); + tc4x_prot_set_config(prot); + + putreg32(drvcfg, base + PORT_PADCFG_DRVCFG(pin)); + tc4x_prot_set_run(prot); + + spin_unlock_irqrestore(&g_gpio_lock, flags); + + return OK; +} From a3ae64349b124d9f89c9edfb9994c3216a3472e1 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Fri, 15 May 2026 12:04:46 +0530 Subject: [PATCH 09/12] arch/aurix: ASCLIN UART driver Generic UART interface driver for the ASCLIN serial peripheral on the AURIX family. A single driver serves both TC3X and TC4X. Signed-off-by: Parthiban Nallathambi --- arch/tricore/src/aurix/CMakeLists.txt | 29 + arch/tricore/src/aurix/Kconfig | 125 +++ arch/tricore/src/aurix/Make.defs | 25 + arch/tricore/src/aurix/tricore_asclin.h | 248 +++++ arch/tricore/src/aurix/tricore_serial.c | 904 +++++++++++++++++++ arch/tricore/src/tc3x/hardware/tc3x_asclin.h | 65 ++ arch/tricore/src/tc4x/hardware/tc4x_asclin.h | 57 ++ 7 files changed, 1453 insertions(+) create mode 100644 arch/tricore/src/aurix/CMakeLists.txt create mode 100644 arch/tricore/src/aurix/Make.defs create mode 100644 arch/tricore/src/aurix/tricore_asclin.h create mode 100644 arch/tricore/src/aurix/tricore_serial.c create mode 100644 arch/tricore/src/tc3x/hardware/tc3x_asclin.h create mode 100644 arch/tricore/src/tc4x/hardware/tc4x_asclin.h diff --git a/arch/tricore/src/aurix/CMakeLists.txt b/arch/tricore/src/aurix/CMakeLists.txt new file mode 100644 index 0000000000000..7fbd4a2e423d5 --- /dev/null +++ b/arch/tricore/src/aurix/CMakeLists.txt @@ -0,0 +1,29 @@ +# ############################################################################## +# arch/tricore/src/aurix/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +if(CONFIG_TRICORE_UART0 OR CONFIG_TRICORE_UART1) + list(APPEND SRCS tricore_serial.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/tricore/src/aurix/Kconfig b/arch/tricore/src/aurix/Kconfig index 305b44dcbcdc4..908cc61cd688d 100644 --- a/arch/tricore/src/aurix/Kconfig +++ b/arch/tricore/src/aurix/Kconfig @@ -5,6 +5,131 @@ menu "AURIX peripheral selection" +config TRICORE_UART0 + bool "ASCLIN UART0" + default n + select UART0_SERIALDRIVER + ---help--- + Build the ASCLIN0 channel as a serial UART instance (ttyS0). + +if TRICORE_UART0 + +config TRICORE_UART0_TXIRQ + int "ASCLIN0 TX IRQ" + default 173 if ARCH_CHIP_FAMILY_TC4X + default 20 if ARCH_CHIP_FAMILY_TC3X + ---help--- + Service Request Node (SRN) for ASCLIN0 TX completion. + Defaults match the canonical mapping in the AURIX Interrupt + Router: 173 on TC4X and 20 on TC3X. + +config TRICORE_UART0_RXIRQ + int "ASCLIN0 RX IRQ" + default 172 if ARCH_CHIP_FAMILY_TC4X + default 21 if ARCH_CHIP_FAMILY_TC3X + ---help--- + Service Request Node (SRN) for ASCLIN0 RX events. + Defaults: 172 on TC4X, 21 on TC3X. + +config TRICORE_UART0_ERIRQ + int "ASCLIN0 ER IRQ" + default 174 if ARCH_CHIP_FAMILY_TC4X + default 22 if ARCH_CHIP_FAMILY_TC3X + ---help--- + Service Request Node (SRN) for ASCLIN0 framing/parity/overrun + errors. Defaults: 174 on TC4X, 22 on TC3X. + +endif + +config TRICORE_UART1 + bool "ASCLIN UART1" + default n + select UART1_SERIALDRIVER + ---help--- + Build the ASCLIN1 channel as a serial UART instance (ttyS1). + +if TRICORE_UART1 + +config TRICORE_UART1_TXIRQ + int "ASCLIN1 TX IRQ" + default 176 if ARCH_CHIP_FAMILY_TC4X + default 23 if ARCH_CHIP_FAMILY_TC3X + ---help--- + Service Request Node (SRN) for ASCLIN1 TX completion. + Defaults: 176 on TC4X, 23 on TC3X. + +config TRICORE_UART1_RXIRQ + int "ASCLIN1 RX IRQ" + default 175 if ARCH_CHIP_FAMILY_TC4X + default 24 if ARCH_CHIP_FAMILY_TC3X + ---help--- + Service Request Node (SRN) for ASCLIN1 RX events. + Defaults: 175 on TC4X, 24 on TC3X. + +config TRICORE_UART1_ERIRQ + int "ASCLIN1 ER IRQ" + default 177 if ARCH_CHIP_FAMILY_TC4X + default 25 if ARCH_CHIP_FAMILY_TC3X + ---help--- + Service Request Node (SRN) for ASCLIN1 framing/parity/overrun + errors. Defaults: 177 on TC4X, 25 on TC3X. + +endif + +config TRICORE_ASCLINF_FREQUENCY + int "ASCLIN fASCLIN clock frequency (Hz)" + default 200000000 if ARCH_CHIP_FAMILY_TC4X + default 100000000 if ARCH_CHIP_FAMILY_TC3X + depends on TRICORE_UART0 || TRICORE_UART1 + ---help--- + ASCLIN baud generator source clock (fASCLIN), in Hz. + +config TRICORE_ASCLIN_PRESCALER + int "ASCLIN baud prescaler" + default 1 + range 1 4096 + depends on TRICORE_UART0 || TRICORE_UART1 + ---help--- + Prescaler applied to fASCLIN before the BRG fractional divider. + +config TRICORE_ASCLIN_OVERSAMPLING + int "ASCLIN oversampling factor" + default 16 + range 4 16 + depends on TRICORE_UART0 || TRICORE_UART1 + ---help--- + Number of fASCLIN ticks per UART bit. The Stern-Brocot baud + generator targets this divisor; 16 is the AURIX default. + +config TRICORE_ASCLIN_SAMPLEPOINT + int "ASCLIN sample point within bit time" + default 8 + range 1 15 + depends on TRICORE_UART0 || TRICORE_UART1 + ---help--- + Oversample tick at which the receiver samples each RX bit. + Must be smaller than ASCLIN_OVERSAMPLING. + +config TRICORE_ASCLIN_MEDIAN_FILTER + int "ASCLIN 3-tap median filter on RX (0/1)" + default 1 + range 0 1 + depends on TRICORE_UART0 || TRICORE_UART1 + ---help--- + Enable the 3-tap median filter on the RX bit slicer. Use 1 + for noise-rejection on long cable runs, 0 to disable. + +config TRICORE_ASCLIN_CLK_SRC + int "ASCLIN clock source selector" + default 2 + range 0 4 + depends on TRICORE_UART0 || TRICORE_UART1 + ---help--- + ASCLIN CSR.CLKSEL value written to enable the module clock. + 0 = NOCLK (clock off), 2 = FASCLINF (fast ASCLIN clock, + default for the on-board console), 4 = FASCLINS (slow ASCLIN + clock). Values 1 and 3 are reserved. + config TC4X_GPIO_ACCESS_GROUP int "TC4X port access group" default 0 diff --git a/arch/tricore/src/aurix/Make.defs b/arch/tricore/src/aurix/Make.defs new file mode 100644 index 0000000000000..c9d896fb6c51c --- /dev/null +++ b/arch/tricore/src/aurix/Make.defs @@ -0,0 +1,25 @@ +############################################################################ +# arch/tricore/src/aurix/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifneq ($(CONFIG_TRICORE_UART0)$(CONFIG_TRICORE_UART1),) +CMN_CSRCS += tricore_serial.c +endif diff --git a/arch/tricore/src/aurix/tricore_asclin.h b/arch/tricore/src/aurix/tricore_asclin.h new file mode 100644 index 0000000000000..e18e28aec1808 --- /dev/null +++ b/arch/tricore/src/aurix/tricore_asclin.h @@ -0,0 +1,248 @@ +/**************************************************************************** + * arch/tricore/src/aurix/tricore_asclin.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_AURIX_TRICORE_ASCLIN_H +#define __ARCH_TRICORE_SRC_AURIX_TRICORE_ASCLIN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) +# include "hardware/tc4x_asclin.h" +#elif defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) +# include "hardware/tc3x_asclin.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +#define ASCLIN_REG(base, off) ((base) + (off)) + +#define ASCLIN_CLC_DISR BIT(0) +#define ASCLIN_CLC_DISS BIT(1) +#define ASCLIN_CLC_EDIS BIT(3) + +#define ASCLIN_IOCR_ALTI_SHIFT 0 +#define ASCLIN_IOCR_ALTI_MASK GENMASK(2, 0) +#define ASCLIN_IOCR_DEPTH_SHIFT 4 +#define ASCLIN_IOCR_DEPTH_MASK GENMASK(9, 4) +#define ASCLIN_IOCR_CTS_SHIFT 16 +#define ASCLIN_IOCR_CTS_MASK GENMASK(17, 16) +#define ASCLIN_IOCR_RCPOL BIT(25) +#define ASCLIN_IOCR_CPOL BIT(26) +#define ASCLIN_IOCR_SPOL BIT(27) +#define ASCLIN_IOCR_LB BIT(28) +#define ASCLIN_IOCR_CTSEN BIT(29) +#define ASCLIN_IOCR_RXM BIT(30) +#define ASCLIN_IOCR_TXM BIT(31) + +#define ASCLIN_IOCR_ALTI_A 0 +#define ASCLIN_IOCR_ALTI_B 1 +#define ASCLIN_IOCR_ALTI_C 2 +#define ASCLIN_IOCR_ALTI_D 3 +#define ASCLIN_IOCR_ALTI_E 4 +#define ASCLIN_IOCR_ALTI_F 5 +#define ASCLIN_IOCR_ALTI_G 6 +#define ASCLIN_IOCR_ALTI_H 7 + +#define ASCLIN_TXFIFOCON_FLUSH BIT(0) +#define ASCLIN_TXFIFOCON_ENO BIT(1) +#define ASCLIN_TXFIFOCON_FM_SHIFT 4 +#define ASCLIN_TXFIFOCON_FM_MASK GENMASK(5, 4) +#define ASCLIN_TXFIFOCON_INW_SHIFT 6 +#define ASCLIN_TXFIFOCON_INW_MASK GENMASK(7, 6) +#define ASCLIN_TXFIFOCON_INTLEVEL_SHIFT 8 +#define ASCLIN_TXFIFOCON_INTLEVEL_MASK GENMASK(11, 8) +#define ASCLIN_TXFIFOCON_FILL_SHIFT 16 +#define ASCLIN_TXFIFOCON_FILL_MASK GENMASK(20, 16) + +#define ASCLIN_TXFIFOCON_INW_1 (1 << ASCLIN_TXFIFOCON_INW_SHIFT) +#define ASCLIN_TXFIFOCON_FM_COMBINED (0 << ASCLIN_TXFIFOCON_FM_SHIFT) + +#define ASCLIN_RXFIFOCON_FLUSH BIT(0) +#define ASCLIN_RXFIFOCON_ENI BIT(1) +#define ASCLIN_RXFIFOCON_FM_SHIFT 4 +#define ASCLIN_RXFIFOCON_FM_MASK GENMASK(5, 4) +#define ASCLIN_RXFIFOCON_OUTW_SHIFT 6 +#define ASCLIN_RXFIFOCON_OUTW_MASK GENMASK(7, 6) +#define ASCLIN_RXFIFOCON_INTLEVEL_SHIFT 8 +#define ASCLIN_RXFIFOCON_INTLEVEL_MASK GENMASK(11, 8) +#define ASCLIN_RXFIFOCON_FILL_SHIFT 16 +#define ASCLIN_RXFIFOCON_FILL_MASK GENMASK(20, 16) +#define ASCLIN_RXFIFOCON_BUF BIT(31) + +#define ASCLIN_RXFIFOCON_OUTW_1 (1 << ASCLIN_RXFIFOCON_OUTW_SHIFT) + +#define ASCLIN_BITCON_PRESCALER_SHIFT 0 +#define ASCLIN_BITCON_PRESCALER_MASK GENMASK(11, 0) +#define ASCLIN_BITCON_OVERSAMPLING_SHIFT 16 +#define ASCLIN_BITCON_OVERSAMPLING_MASK GENMASK(19, 16) +#define ASCLIN_BITCON_SAMPLEPOINT_SHIFT 24 +#define ASCLIN_BITCON_SAMPLEPOINT_MASK GENMASK(27, 24) +#define ASCLIN_BITCON_SM BIT(31) + +#define ASCLIN_FRAMECON_IDLE_SHIFT 6 +#define ASCLIN_FRAMECON_IDLE_MASK GENMASK(8, 6) +#define ASCLIN_FRAMECON_STOP_SHIFT 9 +#define ASCLIN_FRAMECON_STOP_MASK GENMASK(11, 9) +#define ASCLIN_FRAMECON_LEAD_SHIFT 12 +#define ASCLIN_FRAMECON_LEAD_MASK GENMASK(14, 12) +#define ASCLIN_FRAMECON_MODE_SHIFT 16 +#define ASCLIN_FRAMECON_MODE_MASK GENMASK(17, 16) +#define ASCLIN_FRAMECON_MSB BIT(28) +#define ASCLIN_FRAMECON_CEN BIT(29) +#define ASCLIN_FRAMECON_PEN BIT(30) +#define ASCLIN_FRAMECON_ODD BIT(31) + +#define ASCLIN_FRAMECON_MODE_INIT (0 << ASCLIN_FRAMECON_MODE_SHIFT) +#define ASCLIN_FRAMECON_MODE_ASC (1 << ASCLIN_FRAMECON_MODE_SHIFT) +#define ASCLIN_FRAMECON_MODE_SPI (2 << ASCLIN_FRAMECON_MODE_SHIFT) +#define ASCLIN_FRAMECON_MODE_LIN (3 << ASCLIN_FRAMECON_MODE_SHIFT) + +#define ASCLIN_FRAMECON_STOP_1 (1 << ASCLIN_FRAMECON_STOP_SHIFT) +#define ASCLIN_FRAMECON_STOP_2 (2 << ASCLIN_FRAMECON_STOP_SHIFT) + +#define ASCLIN_DATCON_DATLEN_SHIFT 0 +#define ASCLIN_DATCON_DATLEN_MASK GENMASK(3, 0) +#define ASCLIN_DATCON_TRGSRC_SHIFT 8 +#define ASCLIN_DATCON_TRGSRC_MASK GENMASK(9, 8) + +#define ASCLIN_DATCON_DATLEN(n) (((n) - 1) & 0xf) + +#define ASCLIN_BRG_DENOMINATOR_SHIFT 0 +#define ASCLIN_BRG_DENOMINATOR_MASK GENMASK(11, 0) +#define ASCLIN_BRG_NUMERATOR_SHIFT 16 +#define ASCLIN_BRG_NUMERATOR_MASK GENMASK(27, 16) + +#define ASCLIN_BRG_VAL(num, den) ((((num) & 0xfff) << 16) | ((den) & 0xfff)) + +#define ASCLIN_FLAGS_TH BIT(0) +#define ASCLIN_FLAGS_TR BIT(1) +#define ASCLIN_FLAGS_RH BIT(2) +#define ASCLIN_FLAGS_RR BIT(3) +#define ASCLIN_FLAGS_FED BIT(5) +#define ASCLIN_FLAGS_RED BIT(6) +#define ASCLIN_FLAGS_TFE BIT(10) +#define ASCLIN_FLAGS_PE BIT(16) +#define ASCLIN_FLAGS_TC BIT(17) +#define ASCLIN_FLAGS_FE BIT(18) +#define ASCLIN_FLAGS_HT BIT(19) +#define ASCLIN_FLAGS_RT BIT(20) +#define ASCLIN_FLAGS_BD BIT(21) +#define ASCLIN_FLAGS_CE BIT(25) +#define ASCLIN_FLAGS_RFO BIT(26) +#define ASCLIN_FLAGS_RFU BIT(27) +#define ASCLIN_FLAGS_RFL BIT(28) +#define ASCLIN_FLAGS_TFO BIT(30) +#define ASCLIN_FLAGS_TFL BIT(31) + +#define ASCLIN_FLAGSCLEAR_THC BIT(0) +#define ASCLIN_FLAGSCLEAR_TRC BIT(1) +#define ASCLIN_FLAGSCLEAR_RHC BIT(2) +#define ASCLIN_FLAGSCLEAR_RRC BIT(3) +#define ASCLIN_FLAGSCLEAR_FEDC BIT(5) +#define ASCLIN_FLAGSCLEAR_REDC BIT(6) +#define ASCLIN_FLAGSCLEAR_TFEC BIT(10) +#define ASCLIN_FLAGSCLEAR_PEC BIT(16) +#define ASCLIN_FLAGSCLEAR_TCC BIT(17) +#define ASCLIN_FLAGSCLEAR_FEC BIT(18) +#define ASCLIN_FLAGSCLEAR_HTC BIT(19) +#define ASCLIN_FLAGSCLEAR_RTC BIT(20) +#define ASCLIN_FLAGSCLEAR_BDC BIT(21) +#define ASCLIN_FLAGSCLEAR_CEC BIT(25) +#define ASCLIN_FLAGSCLEAR_RFOC BIT(26) +#define ASCLIN_FLAGSCLEAR_RFUC BIT(27) +#define ASCLIN_FLAGSCLEAR_RFLC BIT(28) +#define ASCLIN_FLAGSCLEAR_TFOC BIT(30) +#define ASCLIN_FLAGSCLEAR_TFLC BIT(31) + +#define ASCLIN_FLAGSCLEAR_ALL_ERRS (ASCLIN_FLAGSCLEAR_PEC | \ + ASCLIN_FLAGSCLEAR_FEC | \ + ASCLIN_FLAGSCLEAR_BDC | \ + ASCLIN_FLAGSCLEAR_CEC | \ + ASCLIN_FLAGSCLEAR_RFOC | \ + ASCLIN_FLAGSCLEAR_RFUC | \ + ASCLIN_FLAGSCLEAR_TFOC) + +#define ASCLIN_FLAGSCLEAR_ALL (ASCLIN_FLAGSCLEAR_THC | \ + ASCLIN_FLAGSCLEAR_TRC | \ + ASCLIN_FLAGSCLEAR_RHC | \ + ASCLIN_FLAGSCLEAR_RRC | \ + ASCLIN_FLAGSCLEAR_FEDC | \ + ASCLIN_FLAGSCLEAR_REDC | \ + ASCLIN_FLAGSCLEAR_TFEC | \ + ASCLIN_FLAGSCLEAR_PEC | \ + ASCLIN_FLAGSCLEAR_TCC | \ + ASCLIN_FLAGSCLEAR_FEC | \ + ASCLIN_FLAGSCLEAR_HTC | \ + ASCLIN_FLAGSCLEAR_RTC | \ + ASCLIN_FLAGSCLEAR_BDC | \ + ASCLIN_FLAGSCLEAR_CEC | \ + ASCLIN_FLAGSCLEAR_RFOC | \ + ASCLIN_FLAGSCLEAR_RFUC | \ + ASCLIN_FLAGSCLEAR_RFLC | \ + ASCLIN_FLAGSCLEAR_TFOC | \ + ASCLIN_FLAGSCLEAR_TFLC) + +#define ASCLIN_FLAGSSET_THS BIT(0) +#define ASCLIN_FLAGSSET_TFLC BIT(31) + +#define ASCLIN_FLAGSENABLE_THE BIT(0) +#define ASCLIN_FLAGSENABLE_TRE BIT(1) +#define ASCLIN_FLAGSENABLE_RHE BIT(2) +#define ASCLIN_FLAGSENABLE_RRE BIT(3) +#define ASCLIN_FLAGSENABLE_FEDE BIT(5) +#define ASCLIN_FLAGSENABLE_REDE BIT(6) +#define ASCLIN_FLAGSENABLE_TFEE BIT(10) +#define ASCLIN_FLAGSENABLE_PEE BIT(16) +#define ASCLIN_FLAGSENABLE_TCE BIT(17) +#define ASCLIN_FLAGSENABLE_FEE BIT(18) +#define ASCLIN_FLAGSENABLE_BDE BIT(21) +#define ASCLIN_FLAGSENABLE_CEE BIT(25) +#define ASCLIN_FLAGSENABLE_RFOE BIT(26) +#define ASCLIN_FLAGSENABLE_RFUE BIT(27) +#define ASCLIN_FLAGSENABLE_RFLE BIT(28) +#define ASCLIN_FLAGSENABLE_TFOE BIT(30) +#define ASCLIN_FLAGSENABLE_TFLE BIT(31) + +#define ASCLIN_CSR_CLKSEL_SHIFT 0 +#define ASCLIN_CSR_CLKSEL_MASK GENMASK(4, 0) +#define ASCLIN_CSR_CON BIT(31) + +#define ASCLIN_CSR_CLKSEL_NONE 0x0 +#define ASCLIN_CSR_CLKSEL_FASCLINF 0x2 +#define ASCLIN_CSR_CLKSEL_FASCLINS 0x4 + +#define ASCLIN_FIFO_DEPTH 16 + +#define ASCLIN_TX_FILL(txfifocon) (((txfifocon) & ASCLIN_TXFIFOCON_FILL_MASK) >> \ + ASCLIN_TXFIFOCON_FILL_SHIFT) + +#define ASCLIN_RX_FILL(rxfifocon) (((rxfifocon) & ASCLIN_RXFIFOCON_FILL_MASK) >> \ + ASCLIN_RXFIFOCON_FILL_SHIFT) + +#endif /* __ARCH_TRICORE_SRC_AURIX_TRICORE_ASCLIN_H */ diff --git a/arch/tricore/src/aurix/tricore_serial.c b/arch/tricore/src/aurix/tricore_serial.c new file mode 100644 index 0000000000000..4ac9f1190d2aa --- /dev/null +++ b/arch/tricore/src/aurix/tricore_serial.c @@ -0,0 +1,904 @@ +/**************************************************************************** + * arch/tricore/src/aurix/tricore_serial.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "tricore_internal.h" +#include "tricore_asclin.h" + +#ifndef CONFIG_TRICORE_ASCLINF_FREQUENCY +# if defined(CONFIG_ARCH_CHIP_FAMILY_TC4X) +# define CONFIG_TRICORE_ASCLINF_FREQUENCY 200000000 +# elif defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) +# define CONFIG_TRICORE_ASCLINF_FREQUENCY 100000000 +# endif +#endif + +/* Default ASCLIN clock source selection */ +#ifndef CONFIG_TRICORE_ASCLIN_CLK_SRC +# define CONFIG_TRICORE_ASCLIN_CLK_SRC ASCLIN_CSR_CLKSEL_FASCLINF +#endif + +#ifndef CONFIG_TRICORE_ASCLIN_OVERSAMPLING +# define CONFIG_TRICORE_ASCLIN_OVERSAMPLING 16u +#endif + +#ifndef CONFIG_TRICORE_ASCLIN_SAMPLEPOINT +# define CONFIG_TRICORE_ASCLIN_SAMPLEPOINT 8u +#endif + +#ifndef CONFIG_TRICORE_ASCLIN_PRESCALER +# define CONFIG_TRICORE_ASCLIN_PRESCALER 1u +#endif + +#ifndef CONFIG_TRICORE_ASCLIN_MEDIAN_FILTER +# define CONFIG_TRICORE_ASCLIN_MEDIAN_FILTER 1u +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ASCLIN_CLK_TIMEOUT 100000u + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_TRICORE_UART0) +# define HAVE_SERIAL_CONSOLE 1 +# define CONSOLE_DEV g_uart0port +# define TTYS0_DEV g_uart0port +# ifdef CONFIG_TRICORE_UART1 +# define TTYS1_DEV g_uart1port +# endif +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_TRICORE_UART1) +# define HAVE_SERIAL_CONSOLE 1 +# define CONSOLE_DEV g_uart1port +# define TTYS0_DEV g_uart1port +# ifdef CONFIG_TRICORE_UART0 +# define TTYS1_DEV g_uart0port +# endif +#elif defined(CONFIG_TRICORE_UART0) +# define TTYS0_DEV g_uart0port +# ifdef CONFIG_TRICORE_UART1 +# define TTYS1_DEV g_uart1port +# endif +#elif defined(CONFIG_TRICORE_UART1) +# define TTYS0_DEV g_uart1port +#endif + +struct aurix_uart_config_s +{ + uintptr_t base; + uint32_t fclk; + uint32_t baud; + uint8_t clk_src; + uint8_t oversampling; + uint8_t samplepoint; + uint8_t prescaler_val; + uint8_t median_filter; + uint8_t data_bits; + uint8_t stop_bits; + uint8_t parity; + uint8_t rxirq; + uint8_t txirq; + uint8_t erirq; + uint8_t rx_alti; +}; + +struct aurix_uart_priv_s +{ + struct aurix_uart_config_s *config; + bool txint_enabled; + bool rxint_enabled; +}; + +static int aurix_setup(struct uart_dev_s *dev); +static void aurix_shutdown(struct uart_dev_s *dev); +static int aurix_attach(struct uart_dev_s *dev); +static void aurix_detach(struct uart_dev_s *dev); +static int aurix_interrupt(int irq, void *context, void *arg); +static int aurix_ioctl(struct file *filep, int cmd, unsigned long arg); +static int aurix_receive(struct uart_dev_s *dev, unsigned int *status); +static void aurix_rxint(struct uart_dev_s *dev, bool enable); +static bool aurix_rxavailable(struct uart_dev_s *dev); +static void aurix_send(struct uart_dev_s *dev, int ch); +static void aurix_txint(struct uart_dev_s *dev, bool enable); +static bool aurix_txready(struct uart_dev_s *dev); +static bool aurix_txempty(struct uart_dev_s *dev); + +static const struct uart_ops_s g_uart_ops = +{ + .setup = aurix_setup, + .shutdown = aurix_shutdown, + .attach = aurix_attach, + .detach = aurix_detach, + .ioctl = aurix_ioctl, + .receive = aurix_receive, + .rxint = aurix_rxint, + .rxavailable = aurix_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = aurix_send, + .txint = aurix_txint, + .txready = aurix_txready, + .txempty = aurix_txempty, +}; + +#ifdef CONFIG_TRICORE_UART0 + +static struct aurix_uart_config_s g_uart0_config = +{ + .base = TRICORE_ASCLIN_BASE(0), + .fclk = CONFIG_TRICORE_ASCLINF_FREQUENCY, + .baud = CONFIG_UART0_BAUD, + .clk_src = CONFIG_TRICORE_ASCLIN_CLK_SRC, + .oversampling = CONFIG_TRICORE_ASCLIN_OVERSAMPLING, + .samplepoint = CONFIG_TRICORE_ASCLIN_SAMPLEPOINT, + .prescaler_val = CONFIG_TRICORE_ASCLIN_PRESCALER, + .median_filter = CONFIG_TRICORE_ASCLIN_MEDIAN_FILTER, + .data_bits = CONFIG_UART0_BITS, + .stop_bits = CONFIG_UART0_2STOP ? 2 : 1, +#if defined(CONFIG_UART0_PARITY) && CONFIG_UART0_PARITY == 1 + .parity = 2, +#elif defined(CONFIG_UART0_PARITY) && CONFIG_UART0_PARITY == 2 + .parity = 1, +#else + .parity = 0, +#endif + .rxirq = CONFIG_TRICORE_UART0_RXIRQ, + .txirq = CONFIG_TRICORE_UART0_TXIRQ, + .erirq = CONFIG_TRICORE_UART0_ERIRQ, + + .rx_alti = ASCLIN_IOCR_ALTI_A, +}; + +static struct aurix_uart_priv_s g_uart0_priv = +{ + .config = &g_uart0_config, + .txint_enabled = false, + .rxint_enabled = false, +}; + +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; + +static uart_dev_t g_uart0port = +{ +#ifdef HAVE_SERIAL_CONSOLE + .isconsole = true, +#endif + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0_priv, +}; + +#endif /* CONFIG_TRICORE_UART0 */ + +#ifdef CONFIG_TRICORE_UART1 + +static struct aurix_uart_config_s g_uart1_config = +{ + .base = TRICORE_ASCLIN_BASE(1), + .fclk = CONFIG_TRICORE_ASCLINF_FREQUENCY, + .baud = CONFIG_UART1_BAUD, + .clk_src = CONFIG_TRICORE_ASCLIN_CLK_SRC, + .oversampling = CONFIG_TRICORE_ASCLIN_OVERSAMPLING, + .samplepoint = CONFIG_TRICORE_ASCLIN_SAMPLEPOINT, + .prescaler_val = CONFIG_TRICORE_ASCLIN_PRESCALER, + .median_filter = CONFIG_TRICORE_ASCLIN_MEDIAN_FILTER, + .data_bits = CONFIG_UART1_BITS, + .stop_bits = CONFIG_UART1_2STOP ? 2 : 1, +#if defined(CONFIG_UART1_PARITY) && CONFIG_UART1_PARITY == 1 + .parity = 2, +#elif defined(CONFIG_UART1_PARITY) && CONFIG_UART1_PARITY == 2 + .parity = 1, +#else + .parity = 0, +#endif + .rxirq = CONFIG_TRICORE_UART1_RXIRQ, + .txirq = CONFIG_TRICORE_UART1_TXIRQ, + .erirq = CONFIG_TRICORE_UART1_ERIRQ, + + .rx_alti = ASCLIN_IOCR_ALTI_A, +}; + +static struct aurix_uart_priv_s g_uart1_priv = +{ + .config = &g_uart1_config, + .txint_enabled = false, + .rxint_enabled = false, +}; + +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; + +static uart_dev_t g_uart1port = +{ +#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(HAVE_SERIAL_CONSOLE) + .isconsole = true, +#endif + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1_priv, +}; + +#endif /* CONFIG_TRICORE_UART1 */ + +static inline uintptr_t aurix_serialreg( + const struct aurix_uart_config_s *cfg, uint32_t offset) +{ + return cfg->base + offset; +} + +static inline uint32_t aurix_serialin( + const struct aurix_uart_config_s *cfg, uint32_t offset) +{ + return getreg32(aurix_serialreg(cfg, offset)); +} + +static inline void aurix_serialout( + const struct aurix_uart_config_s *cfg, uint32_t offset, uint32_t value) +{ + putreg32(value, aurix_serialreg(cfg, offset)); +} + +static inline void aurix_serialmod( + const struct aurix_uart_config_s *cfg, uint32_t offset, + uint32_t setbits, uint32_t clrbits) +{ + modreg32(setbits, setbits | clrbits, aurix_serialreg(cfg, offset)); +} + +static int aurix_asclin_wait_clk( + const struct aurix_uart_config_s *cfg, bool on) +{ + uint32_t timeout = ASCLIN_CLK_TIMEOUT; + + while (timeout--) + { + uint32_t csr = aurix_serialin(cfg, ASCLIN_CSR_OFFSET); + bool con = !!(csr & ASCLIN_CSR_CON); + if (con == on) + { + return OK; + } + } + + return -ETIMEDOUT; +} + +static int aurix_asclin_set_clk( + const struct aurix_uart_config_s *cfg, uint8_t clksel) +{ + aurix_serialout(cfg, ASCLIN_CSR_OFFSET, clksel); + return aurix_asclin_wait_clk(cfg, clksel != ASCLIN_CSR_CLKSEL_NONE); +} + +static void aurix_asclin_set_baudrate( + const struct aurix_uart_config_s *cfg) +{ + uint32_t fovs = cfg->baud * cfg->oversampling; + uint32_t fpd = cfg->fclk / cfg->prescaler_val; + + uint32_t n = fovs; + uint32_t d = fpd; + uint32_t h0 = 0; + uint32_t h1 = 1; + uint32_t k0 = 1; + uint32_t k1 = 0; + + while (d != 0) + { + uint32_t a = n / d; + uint32_t r = n - a * d; + uint32_t h2 = a * h1 + h0; + uint32_t k2 = a * k1 + k0; + + if (k2 > 4095u) + { + break; + } + + h0 = h1; + h1 = h2; + k0 = k1; + k1 = k2; + + n = d; + d = r; + } + + if (h1 == 0) + { + h1 = 1; + } + + if (k1 == 0) + { + k1 = 1; + } + + aurix_serialout(cfg, ASCLIN_BRG_OFFSET, ASCLIN_BRG_VAL(h1, k1)); +} + +static void aurix_asclin_set_bittime( + const struct aurix_uart_config_s *cfg) +{ + uint32_t val = 0; + + val |= ((cfg->prescaler_val - 1u) & 0xfffu) + << ASCLIN_BITCON_PRESCALER_SHIFT; + + val |= (((uint32_t)(cfg->oversampling - 1u)) & 0xfu) + << ASCLIN_BITCON_OVERSAMPLING_SHIFT; + + val |= ((uint32_t)cfg->samplepoint & 0xfu) + << ASCLIN_BITCON_SAMPLEPOINT_SHIFT; + + if (cfg->median_filter) + { + val |= ASCLIN_BITCON_SM; + } + + aurix_serialout(cfg, ASCLIN_BITCON_OFFSET, val); +} + +static void aurix_asclin_set_frame( + const struct aurix_uart_config_s *cfg) +{ + uint32_t framecon; + uint32_t datcon; + uint32_t txfifocon; + uint32_t rxfifocon; + + framecon = ASCLIN_FRAMECON_MODE_ASC; + + framecon |= ((uint32_t)cfg->stop_bits & 0x7u) + << ASCLIN_FRAMECON_STOP_SHIFT; + + if (cfg->parity != 0) + { + framecon |= ASCLIN_FRAMECON_PEN; + if (cfg->parity == 2) + { + framecon |= ASCLIN_FRAMECON_ODD; + } + } + + aurix_serialout(cfg, ASCLIN_FRAMECON_OFFSET, framecon); + + datcon = ASCLIN_DATCON_DATLEN(cfg->data_bits); + aurix_serialout(cfg, ASCLIN_DATCON_OFFSET, datcon); + + txfifocon = ASCLIN_TXFIFOCON_FLUSH + | ASCLIN_TXFIFOCON_ENO + | ASCLIN_TXFIFOCON_FM_COMBINED + | ASCLIN_TXFIFOCON_INW_1; + + aurix_serialout(cfg, ASCLIN_TXFIFOCON_OFFSET, txfifocon); + + rxfifocon = ASCLIN_RXFIFOCON_FLUSH + | ASCLIN_RXFIFOCON_ENI + | ASCLIN_RXFIFOCON_OUTW_1; + + aurix_serialout(cfg, ASCLIN_RXFIFOCON_OFFSET, rxfifocon); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +static int aurix_asclin_index(const struct aurix_uart_config_s *cfg) +{ + return (int)((cfg->base - TRICORE_ASCLIN_BASE(0)) / TRICORE_ASCLIN_STRIDE); +} + +static int aurix_asclin_init(const struct aurix_uart_config_s *cfg) +{ + int ret; + uint32_t val; + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) + aurix_cpu_endinit_enable(false); +#endif + + val = aurix_serialin(cfg, ASCLIN_CLC_OFFSET); + val &= ~ASCLIN_CLC_DISR; + aurix_serialout(cfg, ASCLIN_CLC_OFFSET, val); + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) + aurix_cpu_endinit_enable(true); +#endif + + uint32_t timeout = ASCLIN_CLK_TIMEOUT; + + while ((aurix_serialin(cfg, ASCLIN_CLC_OFFSET) & ASCLIN_CLC_DISS) && + timeout--); + + if (timeout == 0) + { + return -ETIMEDOUT; + } + + board_aurix_setup_serial_pin(aurix_asclin_index(cfg)); + + ret = aurix_asclin_set_clk(cfg, ASCLIN_CSR_CLKSEL_NONE); + if (ret < 0) + { + return ret; + } + + aurix_serialout(cfg, ASCLIN_FRAMECON_OFFSET, 0); + + aurix_asclin_set_bittime(cfg); + aurix_asclin_set_baudrate(cfg); + + val = (uint32_t)cfg->rx_alti & ASCLIN_IOCR_ALTI_MASK; + aurix_serialout(cfg, ASCLIN_IOCR_OFFSET, val); + + aurix_asclin_set_frame(cfg); + + aurix_serialout(cfg, ASCLIN_FLAGSENABLE_OFFSET, 0); + aurix_serialout(cfg, ASCLIN_FLAGSCLEAR_OFFSET, ASCLIN_FLAGSCLEAR_ALL); + + val = ASCLIN_FLAGSENABLE_PEE + | ASCLIN_FLAGSENABLE_FEE + | ASCLIN_FLAGSENABLE_RFOE + | ASCLIN_FLAGSENABLE_RFUE + | ASCLIN_FLAGSENABLE_TFOE; + aurix_serialout(cfg, ASCLIN_FLAGSENABLE_OFFSET, val); + + ret = aurix_asclin_set_clk(cfg, cfg->clk_src); + if (ret < 0) + { + return ret; + } + + return OK; +} + +static int aurix_setup(struct uart_dev_s *dev) +{ + struct aurix_uart_priv_s *priv = dev->priv; + + return aurix_asclin_init(priv->config); +} + +static void aurix_shutdown(struct uart_dev_s *dev) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + + aurix_serialout(cfg, ASCLIN_FLAGSENABLE_OFFSET, 0); + + aurix_asclin_set_clk(cfg, ASCLIN_CSR_CLKSEL_NONE); + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) + aurix_cpu_endinit_enable(false); +#endif + + aurix_serialmod(cfg, ASCLIN_CLC_OFFSET, ASCLIN_CLC_DISR, 0); + +#if defined(CONFIG_ARCH_CHIP_FAMILY_TC3X) + aurix_cpu_endinit_enable(true); +#endif +} + +static int aurix_attach(struct uart_dev_s *dev) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + int ret; + + ret = irq_attach(cfg->rxirq, aurix_interrupt, dev); + if (ret != OK) + { + return ret; + } + + ret = irq_attach(cfg->txirq, aurix_interrupt, dev); + if (ret != OK) + { + irq_detach(cfg->rxirq); + return ret; + } + + ret = irq_attach(cfg->erirq, aurix_interrupt, dev); + if (ret != OK) + { + irq_detach(cfg->rxirq); + irq_detach(cfg->txirq); + return ret; + } + + up_enable_irq(cfg->rxirq); + up_enable_irq(cfg->txirq); + up_enable_irq(cfg->erirq); + + return OK; +} + +static void aurix_detach(struct uart_dev_s *dev) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + + up_disable_irq(cfg->rxirq); + up_disable_irq(cfg->txirq); + up_disable_irq(cfg->erirq); + + irq_detach(cfg->rxirq); + irq_detach(cfg->txirq); + irq_detach(cfg->erirq); +} + +static int aurix_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + uint32_t flags; + + flags = aurix_serialin(cfg, ASCLIN_FLAGS_OFFSET); + + if (flags & ASCLIN_FLAGS_RFL) + { + aurix_serialout(cfg, ASCLIN_FLAGSCLEAR_OFFSET, + ASCLIN_FLAGSCLEAR_RFLC); + + uart_recvchars(dev); + } + + if (flags & ASCLIN_FLAGS_TFL) + { + aurix_serialout(cfg, ASCLIN_FLAGSCLEAR_OFFSET, + ASCLIN_FLAGSCLEAR_TFLC); + + uart_xmitchars(dev); + } + + if (flags & (ASCLIN_FLAGS_PE | ASCLIN_FLAGS_FE | ASCLIN_FLAGS_CE | + ASCLIN_FLAGS_RFO | ASCLIN_FLAGS_RFU)) + { + aurix_serialout(cfg, ASCLIN_FLAGSCLEAR_OFFSET, + ASCLIN_FLAGSCLEAR_ALL_ERRS); + } + + return OK; +} + +static int aurix_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + struct aurix_uart_priv_s *priv = dev->priv; + struct aurix_uart_config_s *cfg = + (struct aurix_uart_config_s *)priv->config; + int ret = OK; + + switch (cmd) + { + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + return -EINVAL; + } + + memset(termiosp, 0, sizeof(struct termios)); + + cfsetispeed(termiosp, cfg->baud); + cfsetospeed(termiosp, cfg->baud); + + switch (cfg->data_bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + case 6: + termiosp->c_cflag |= CS6; + break; + case 7: + termiosp->c_cflag |= CS7; + break; + default: + termiosp->c_cflag |= CS8; + break; + } + + if (cfg->parity == 1) + { + termiosp->c_cflag |= PARENB; + } + else if (cfg->parity == 2) + { + termiosp->c_cflag |= PARENB | PARODD; + } + + if (cfg->stop_bits >= 2) + { + termiosp->c_cflag |= CSTOPB; + } + } + break; + + case TCSETS: + case TCSETSW: + case TCSETSF: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + return -EINVAL; + } + + cfg->baud = cfgetospeed(termiosp); + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + cfg->data_bits = 5; + break; + case CS6: + cfg->data_bits = 6; + break; + case CS7: + cfg->data_bits = 7; + break; + default: + cfg->data_bits = 8; + break; + } + + if (termiosp->c_cflag & PARENB) + { + cfg->parity = (termiosp->c_cflag & PARODD) ? 2 : 1; + } + else + { + cfg->parity = 0; + } + + cfg->stop_bits = (termiosp->c_cflag & CSTOPB) ? 2 : 1; + + aurix_shutdown(dev); + aurix_setup(dev); + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +static int aurix_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + uint32_t flags; + int ch; + + ch = (int)(aurix_serialin(cfg, ASCLIN_RXDATA_OFFSET) & 0xff); + + flags = aurix_serialin(cfg, ASCLIN_FLAGS_OFFSET); + *status = flags & (ASCLIN_FLAGS_PE | ASCLIN_FLAGS_FE | + ASCLIN_FLAGS_RFO | ASCLIN_FLAGS_BD); + + return ch; +} + +static void aurix_rxint(struct uart_dev_s *dev, bool enable) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + irqstate_t flags; + + flags = enter_critical_section(); + + if (enable) + { + aurix_serialmod(cfg, ASCLIN_FLAGSENABLE_OFFSET, + ASCLIN_FLAGSENABLE_RFLE, 0); + } + else + { + aurix_serialmod(cfg, ASCLIN_FLAGSENABLE_OFFSET, + 0, ASCLIN_FLAGSENABLE_RFLE); + } + + priv->rxint_enabled = enable; + leave_critical_section(flags); +} + +static bool aurix_rxavailable(struct uart_dev_s *dev) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + uint32_t rxfifocon; + + rxfifocon = aurix_serialin(cfg, ASCLIN_RXFIFOCON_OFFSET); + return ASCLIN_RX_FILL(rxfifocon) > 0; +} + +static void aurix_send(struct uart_dev_s *dev, int ch) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + + aurix_serialout(cfg, ASCLIN_TXDATA_OFFSET, (uint32_t)(uint8_t)ch); +} + +static void aurix_txint(struct uart_dev_s *dev, bool enable) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + irqstate_t flags; + + flags = enter_critical_section(); + + if (enable) + { + aurix_serialmod(cfg, ASCLIN_FLAGSENABLE_OFFSET, + ASCLIN_FLAGSENABLE_TFLE, 0); + + uart_xmitchars(dev); + } + else + { + aurix_serialmod(cfg, ASCLIN_FLAGSENABLE_OFFSET, + 0, ASCLIN_FLAGSENABLE_TFLE); + } + + priv->txint_enabled = enable; + leave_critical_section(flags); +} + +static bool aurix_txready(struct uart_dev_s *dev) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + uint32_t txfifocon; + + txfifocon = aurix_serialin(cfg, ASCLIN_TXFIFOCON_OFFSET); + return ASCLIN_TX_FILL(txfifocon) < ASCLIN_FIFO_DEPTH; +} + +static bool aurix_txempty(struct uart_dev_s *dev) +{ + struct aurix_uart_priv_s *priv = dev->priv; + const struct aurix_uart_config_s *cfg = priv->config; + uint32_t txfifocon; + + txfifocon = aurix_serialin(cfg, ASCLIN_TXFIFOCON_OFFSET); + return ASCLIN_TX_FILL(txfifocon) == 0; +} + +static void aurix_lowputc(int ch) +{ +#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_TRICORE_UART1) + const struct aurix_uart_config_s *cfg = &g_uart1_config; +#elif defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_TRICORE_UART0) + const struct aurix_uart_config_s *cfg = &g_uart0_config; +#elif defined(CONFIG_TRICORE_UART0) + const struct aurix_uart_config_s *cfg = &g_uart0_config; +#elif defined(CONFIG_TRICORE_UART1) + const struct aurix_uart_config_s *cfg = &g_uart1_config; +#else + (void)ch; + return; +#endif + +#if defined(CONFIG_TRICORE_UART0) || defined(CONFIG_TRICORE_UART1) + uint32_t txfifocon; + + do + { + txfifocon = aurix_serialin(cfg, ASCLIN_TXFIFOCON_OFFSET); + } + while (ASCLIN_TX_FILL(txfifocon) >= ASCLIN_FIFO_DEPTH); + + aurix_serialout(cfg, ASCLIN_TXDATA_OFFSET, (uint32_t)(uint8_t)ch); +#endif +} + +#ifdef USE_SERIALDRIVER + +#ifdef USE_EARLYSERIALINIT +void aurix_earlyserialinit(void) +{ +#ifdef HAVE_SERIAL_CONSOLE + CONSOLE_DEV.isconsole = true; + aurix_setup(&CONSOLE_DEV); +#endif +} +#endif + +void aurix_serialinit(void) +{ +#ifdef HAVE_SERIAL_CONSOLE + uart_register("/dev/console", &CONSOLE_DEV); +#endif + +#ifdef TTYS0_DEV + uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +} + +#endif /* USE_SERIALDRIVER */ + +void up_putc(int ch) +{ + if (ch == '\n') + { + aurix_lowputc('\r'); + } + + aurix_lowputc(ch); +} + +void up_lowputc(int ch) +{ + up_putc(ch); +} diff --git a/arch/tricore/src/tc3x/hardware/tc3x_asclin.h b/arch/tricore/src/tc3x/hardware/tc3x_asclin.h new file mode 100644 index 0000000000000..82f52aa45cedd --- /dev/null +++ b/arch/tricore/src/tc3x/hardware/tc3x_asclin.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/tricore/src/tc3x/hardware/tc3x_asclin.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_ASCLIN_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_ASCLIN_H + +#define TRICORE_ASCLIN0_BASE 0xf0000600 +#define TRICORE_ASCLIN_STRIDE 0x100 +#define TRICORE_ASCLIN_BASE(n) ((n) <= 9 ? (TRICORE_ASCLIN0_BASE + ((uint32_t)(n) * TRICORE_ASCLIN_STRIDE)) \ + : (0xf02c0a00 + (((uint32_t)(n) - 10) * TRICORE_ASCLIN_STRIDE))) + +#define ASCLIN_CLC_OFFSET 0x00 +#define ASCLIN_IOCR_OFFSET 0x04 +#define ASCLIN_ID_OFFSET 0x08 +#define ASCLIN_TXFIFOCON_OFFSET 0x0c +#define ASCLIN_RXFIFOCON_OFFSET 0x10 +#define ASCLIN_BITCON_OFFSET 0x14 +#define ASCLIN_FRAMECON_OFFSET 0x18 +#define ASCLIN_DATCON_OFFSET 0x1c +#define ASCLIN_BRG_OFFSET 0x20 +#define ASCLIN_BRD_OFFSET 0x24 +#define ASCLIN_LINCON_OFFSET 0x28 +#define ASCLIN_LINBTIMER_OFFSET 0x2c +#define ASCLIN_LINHTIMER_OFFSET 0x30 +#define ASCLIN_FLAGS_OFFSET 0x34 +#define ASCLIN_FLAGSSET_OFFSET 0x38 +#define ASCLIN_FLAGSCLEAR_OFFSET 0x3c +#define ASCLIN_FLAGSENABLE_OFFSET 0x40 +#define ASCLIN_TXDATA_OFFSET 0x44 +#define ASCLIN_RXDATA_OFFSET 0x48 +#define ASCLIN_CSR_OFFSET 0x4c +#define ASCLIN_RXDATAD_OFFSET 0x50 + +#define ASCLIN_OCS_OFFSET 0xe8 +#define ASCLIN_KRSTCLR_OFFSET 0xec +#define ASCLIN_KRST1_OFFSET 0xf0 +#define ASCLIN_KRST0_OFFSET 0xf4 +#define ASCLIN_ACCEN1_OFFSET 0xf8 +#define ASCLIN_ACCEN0_OFFSET 0xfc + +#endif /* __ARCH_TRICORE_SRC_TC3X_HARDWARE_TC3X_ASCLIN_H */ diff --git a/arch/tricore/src/tc4x/hardware/tc4x_asclin.h b/arch/tricore/src/tc4x/hardware/tc4x_asclin.h new file mode 100644 index 0000000000000..bfe3122cc0900 --- /dev/null +++ b/arch/tricore/src/tc4x/hardware/tc4x_asclin.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/tricore/src/tc4x/hardware/tc4x_asclin.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_ASCLIN_H +#define __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_ASCLIN_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TRICORE_ASCLIN0_BASE 0xf46c0000 +#define TRICORE_ASCLIN_STRIDE 0x200 +#define TRICORE_ASCLIN_BASE(n) (TRICORE_ASCLIN0_BASE + ((uint32_t)(n) * TRICORE_ASCLIN_STRIDE)) + +#define ASCLIN_CLC_OFFSET 0x000 +#define ASCLIN_OCS_OFFSET 0x004 +#define ASCLIN_ID_OFFSET 0x008 +#define ASCLIN_IOCR_OFFSET 0x100 +#define ASCLIN_TXFIFOCON_OFFSET 0x104 +#define ASCLIN_RXFIFOCON_OFFSET 0x108 +#define ASCLIN_BITCON_OFFSET 0x10c +#define ASCLIN_FRAMECON_OFFSET 0x110 +#define ASCLIN_DATCON_OFFSET 0x114 +#define ASCLIN_BRG_OFFSET 0x118 +#define ASCLIN_BRD_OFFSET 0x11c +#define ASCLIN_LINCON_OFFSET 0x120 +#define ASCLIN_LINBTIMER_OFFSET 0x124 +#define ASCLIN_LINHTIMER_OFFSET 0x128 +#define ASCLIN_FLAGS_OFFSET 0x12c +#define ASCLIN_FLAGSSET_OFFSET 0x130 +#define ASCLIN_FLAGSCLEAR_OFFSET 0x134 +#define ASCLIN_FLAGSENABLE_OFFSET 0x138 +#define ASCLIN_CSR_OFFSET 0x13c +#define ASCLIN_TXDATA_OFFSET 0x140 +#define ASCLIN_RXDATA_OFFSET 0x160 +#define ASCLIN_RXDATAD_OFFSET 0x180 + +#endif /* __ARCH_TRICORE_SRC_TC4X_HARDWARE_TC4X_ASCLIN_H */ From ce795cd71ac59c2119c5262efc2613bdce164f45 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Fri, 15 May 2026 12:04:55 +0530 Subject: [PATCH 10/12] boards/tc3x: AURIX Lite Kit (TC375) TC375 Lite Kit board support for the AURIX TC3X family. Only UART is supported; NSH defconfigs provided for both GCC and HighTec clang toolchains. Signed-off-by: Parthiban Nallathambi --- .../tricore/tc3x/a2g-tc375-lite/index.rst | 75 ++++++++ boards/Kconfig | 11 ++ .../tc3x/a2g-tc375-lite/CMakeLists.txt | 23 +++ boards/tricore/tc3x/a2g-tc375-lite/Kconfig | 8 + .../a2g-tc375-lite/configs/nsh-llvm/defconfig | 42 +++++ .../tc3x/a2g-tc375-lite/configs/nsh/defconfig | 41 +++++ .../tc3x/a2g-tc375-lite/include/board.h | 31 ++++ .../tc3x/a2g-tc375-lite/scripts/Make.defs | 67 +++++++ .../a2g-tc375-lite/scripts/tricore-llvm.ld | 166 ++++++++++++++++++ .../tc3x/a2g-tc375-lite/src/CMakeLists.txt | 32 ++++ .../tricore/tc3x/a2g-tc375-lite/src/Makefile | 26 +++ .../tc3x/a2g-tc375-lite/src/tc375_appinit.c | 49 ++++++ 12 files changed, 571 insertions(+) create mode 100644 Documentation/platforms/tricore/tc3x/a2g-tc375-lite/index.rst create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/CMakeLists.txt create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/Kconfig create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/configs/nsh-llvm/defconfig create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/configs/nsh/defconfig create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/include/board.h create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/scripts/Make.defs create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/scripts/tricore-llvm.ld create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/src/CMakeLists.txt create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/src/Makefile create mode 100644 boards/tricore/tc3x/a2g-tc375-lite/src/tc375_appinit.c diff --git a/Documentation/platforms/tricore/tc3x/a2g-tc375-lite/index.rst b/Documentation/platforms/tricore/tc3x/a2g-tc375-lite/index.rst new file mode 100644 index 0000000000000..b0026699f87c1 --- /dev/null +++ b/Documentation/platforms/tricore/tc3x/a2g-tc375-lite/index.rst @@ -0,0 +1,75 @@ +================================ +KIT_A2G_TC375_LITE (AURIX TC375) +================================ + +Infineon's AURIX TC375 Lite Kit (KIT_A2G_TC375_LITE) is a low-cost +single-board evaluation platform for the TriCore TC3X (TC1.6.2P) +family. + +Features +======== + +- Infineon AURIX TC37x (TC375) - 3 TriCore CPUs, 4 MiB PFLASH, + 96 KiB LMU. +- ASCLIN0 routed to the on-board USB-serial bridge (115200-8-N-1) for + the NSH console. +- iSYSTEM DAP-Miniwiggler header for flash and debug. +- Single USB-C port for power, console and debug. + +Default configuration +===================== + +:: + + ./tools/configure.sh -E a2g-tc375-lite:nsh + make -j$(nproc) + +The default toolchain is ``tricore-elf-gcc``; the HighTec LLVM +toolchain can be selected via ``CONFIG_TRICORE_TOOLCHAIN_LLVM=y`` and +requires a valid HighTec licence reachable through ``RLM_LICENSE``. + +Console +======= + +The NSH prompt is exposed on UART0 (ASCLIN0) at 115200-8-N-1 over the +USB virtual COM port. + +Flashing +======== + +The board's ``scripts/Make.defs`` provides a ``flash`` target that +drives OpenOCD with the Infineon TAS server. The prerequisites are +documented in :doc:`../../index` (Flashing and debugging). + +.. code-block:: console + + # Once-per-session: start the TAS server (listens on 24817) + cd /bin && LD_LIBRARY_PATH=. ./tas_server & + + # Flash the kit + make flash + +Override knobs (all set with ``?=`` in ``Make.defs``): + +============================== ======================================= +``OPENOCD`` Path to the patched openocd binary. +``OPENOCD_SCRIPTS`` Directory holding the openocd scripts. +``OPENOCD_BOARD`` Per-board cfg used by openocd. +``OPENOCD_SERIAL`` Adapter serial reported by the Lite Kit. +``FLASH_IMAGE`` The .hex image to program. +============================== ======================================= + +Known limitations +================= + +- Only the ``:nsh`` configuration is validated. No kernel-mode build, + no networking, no file system. +- Single CPU (CPU0) only. AMP / multi-core bring-up is intentionally + not part of this port. +- After running a synchronous-trap test from NSH, the TC37x OCDS5 + debug unit can refuse a clean ``reset run``. Recover by + power-cycling the kit (USB unplug for 10+ seconds). See + :doc:`../../index` for details. +- ``ostest`` has not been run against this board. The port has been + validated through the NSH UART + STM clock-tick + synchronous-trap + test battery only. diff --git a/boards/Kconfig b/boards/Kconfig index 262e992ecc7d3..234b1200e3db6 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -2454,6 +2454,13 @@ config ARCH_BOARD_SABRE_6QUAD This options selects support for NuttX on the NXP/Freescale Sabre board featuring the iMX 6Quad CPU. +config ARCH_BOARD_A2G_TC375_LITE + bool "Infineon AURIX Lite Kit (TC375)" + depends on TC3X_CHIP_TC375 + ---help--- + Infineon AURIX Lite Kit evaluation board (KIT_A2G_TC375_LITE) + with the TC375 SoC. + config ARCH_BOARD_QEMU_ARMV7A bool "Qemu ARMv7a CPUs board" depends on ARCH_CHIP_QEMU_ARM @@ -3884,6 +3891,7 @@ config ARCH_BOARD default "milkv_duos" if ARCH_BOARD_SG2000_MILKV_DUOS default "starpro64" if ARCH_BOARD_EIC7700X_STARPRO64 default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD + default "a2g-tc375-lite" if ARCH_BOARD_A2G_TC375_LITE default "qemu-armv7a" if ARCH_BOARD_QEMU_ARMV7A default "qemu-armv7r" if ARCH_BOARD_QEMU_ARMV7R default "qemu-armv8a" if ARCH_BOARD_QEMU_ARMV8A @@ -4106,6 +4114,9 @@ endif if ARCH_BOARD_SABRE_6QUAD source "boards/arm/imx6/sabre-6quad/Kconfig" endif +if ARCH_BOARD_A2G_TC375_LITE +source "boards/tricore/tc3x/a2g-tc375-lite/Kconfig" +endif if ARCH_BOARD_MPS2_AN500 source "boards/arm/mps/mps2-an500/Kconfig" endif diff --git a/boards/tricore/tc3x/a2g-tc375-lite/CMakeLists.txt b/boards/tricore/tc3x/a2g-tc375-lite/CMakeLists.txt new file mode 100644 index 0000000000000..dfad4de0a2045 --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/tricore/tc3x/a2g-tc375-lite/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/tricore/tc3x/a2g-tc375-lite/Kconfig b/boards/tricore/tc3x/a2g-tc375-lite/Kconfig new file mode 100644 index 0000000000000..097d568f5e5e8 --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_A2G_TC375_LITE + +endif diff --git a/boards/tricore/tc3x/a2g-tc375-lite/configs/nsh-llvm/defconfig b/boards/tricore/tc3x/a2g-tc375-lite/configs/nsh-llvm/defconfig new file mode 100644 index 0000000000000..fe2d069144a2c --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/configs/nsh-llvm/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_BOARD_LATE_INITIALIZE is not set +CONFIG_ARCH="tricore" +CONFIG_ARCH_BOARD="a2g-tc375-lite" +CONFIG_ARCH_BOARD_A2G_TC375_LITE=y +CONFIG_ARCH_CHIP="tc3x" +CONFIG_ARCH_CHIP_FAMILY_TC3X=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_TRICORE=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=10000 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FLASH_SIZE=4194304 +CONFIG_FLASH_START=0x80000000 +CONFIG_INIT_ENTRYNAME="main" +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x90000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=1 +CONFIG_SYSLOG_NONE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TRICORE_ASCLINF_FREQUENCY=400000000 +CONFIG_TRICORE_TOOLCHAIN_LLVM=y +CONFIG_TRICORE_UART0=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=100 diff --git a/boards/tricore/tc3x/a2g-tc375-lite/configs/nsh/defconfig b/boards/tricore/tc3x/a2g-tc375-lite/configs/nsh/defconfig new file mode 100644 index 0000000000000..e2b89938d756b --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/configs/nsh/defconfig @@ -0,0 +1,41 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_BOARD_LATE_INITIALIZE is not set +CONFIG_ARCH="tricore" +CONFIG_ARCH_BOARD="a2g-tc375-lite" +CONFIG_ARCH_BOARD_A2G_TC375_LITE=y +CONFIG_ARCH_CHIP="tc3x" +CONFIG_ARCH_CHIP_FAMILY_TC3X=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_TRICORE=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=10000 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FLASH_SIZE=4194304 +CONFIG_FLASH_START=0x80000000 +CONFIG_INIT_ENTRYNAME="main" +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x90000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=1 +CONFIG_SYSLOG_NONE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TRICORE_ASCLINF_FREQUENCY=400000000 +CONFIG_TRICORE_UART0=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=100 diff --git a/boards/tricore/tc3x/a2g-tc375-lite/include/board.h b/boards/tricore/tc3x/a2g-tc375-lite/include/board.h new file mode 100644 index 0000000000000..4d12460774996 --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/include/board.h @@ -0,0 +1,31 @@ +/**************************************************************************** + * boards/tricore/tc3x/a2g-tc375-lite/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_TRICORE_TC3X_A2G_TC375_LITE_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define __BOARDS_TRICORE_TC3X_A2G_TC375_LITE_INCLUDE_BOARD_H + +#endif /* __BOARDS_TRICORE_TC3X_A2G_TC375_LITE_INCLUDE_BOARD_H */ diff --git a/boards/tricore/tc3x/a2g-tc375-lite/scripts/Make.defs b/boards/tricore/tc3x/a2g-tc375-lite/scripts/Make.defs new file mode 100644 index 0000000000000..2de9180c3013b --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/scripts/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# boards/tricore/tc3x/a2g-tc375-lite/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/tricore/src/tc3x/Toolchain.defs + +ifeq ($(CONFIG_TRICORE_TOOLCHAIN_LLVM),y) +ARCHSCRIPT += $(TOPDIR)$(DELIM)arch$(DELIM)tricore$(DELIM)src$(DELIM)common$(DELIM)tricore-llvm.ld +else +ARCHSCRIPT += $(TOPDIR)$(DELIM)arch$(DELIM)tricore$(DELIM)src$(DELIM)common$(DELIM)tricore.ld +endif + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +LDFLAGS += --gc-sections + +OPENOCD ?= /opt/tooling/tricore-openocd/bin/openocd +OPENOCD_SCRIPTS ?= /opt/tooling/tricore-openocd/share/openocd/scripts/ +OPENOCD_BOARD ?= board/infineon/kit_a2g_tc375_lite.cfg +OPENOCD_SERIAL ?= AURIX LITE KIT V2.0 (TC375) LKAS28QS +FLASH_IMAGE ?= $(TOPDIR)/nuttx.hex + +ifneq ($(OPENOCD_SERIAL),) +OPENOCD_SERIAL_ARG := -c "adapter serial \"$(OPENOCD_SERIAL)\"" +endif + +define FLASH + @echo "Flashing $(FLASH_IMAGE) via $(OPENOCD_BOARD)" + @if ! ss -ltn 2>/dev/null | grep -q ":24817"; then \ + echo "ERROR: tas_server not running on port 24817"; exit 1; \ + fi + $(OPENOCD) \ + -f $(OPENOCD_BOARD) \ + -s $(OPENOCD_SCRIPTS) \ + $(OPENOCD_SERIAL_ARG) \ + -c "init" \ + -c "reset halt" \ + -c "program $(FLASH_IMAGE) verify reset exit" +endef diff --git a/boards/tricore/tc3x/a2g-tc375-lite/scripts/tricore-llvm.ld b/boards/tricore/tc3x/a2g-tc375-lite/scripts/tricore-llvm.ld new file mode 100644 index 0000000000000..2af9948df0ee1 --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/scripts/tricore-llvm.ld @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/tricore/tc3x/a2g-tc375-lite/scripts/tricore-llvm.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH("tricore") +ENTRY(__start) +EXTERN(__start) + +__HEAP_SIZE = (48 * 1024); +CONFIG_TRICORE_CSA_COUNT = 512; +CONFIG_TRICORE_INITIAL_STACK_SIZE = 512; +CONFIG_TRICORE_INITIAL_STACK_OFFSET = 0xEB00; + +MEMORY +{ +#if CPU == 0 + dsram (rw): ORIGIN = 0x70000000, LENGTH = 240K + psram (rw): ORIGIN = 0x70100000, LENGTH = 64K + dlmu (rw): ORIGIN = 0x90000000, LENGTH = 64K + pflash (rx): ORIGIN = 0x80000000, LENGTH = 1M +#endif + pflash0 (rx): ORIGIN = 0xA0000000, LENGTH = 1M + +#if CPU == 1 + dsram (rw): ORIGIN = 0x60000000, LENGTH = 240K + psram (rw): ORIGIN = 0x60100000, LENGTH = 64K + dlmu (rw): ORIGIN = 0x90010000, LENGTH = 64K + pflash (rx): ORIGIN = 0x80100000, LENGTH = 1M +#endif + pflash1 (rx): ORIGIN = 0x80100000, LENGTH = 1M + +#if CPU == 2 + dsram (rw): ORIGIN = 0x50000000, LENGTH = 96K + psram (rw): ORIGIN = 0x50100000, LENGTH = 64K + dlmu (rw): ORIGIN = 0x90020000, LENGTH = 64K + pflash (rx): ORIGIN = 0x80200000, LENGTH = 1M +#endif + pflash2 (rx): ORIGIN = 0x80200000, LENGTH = 1M + +} + +REGION_ALIAS("CODE_MEM", pflash) +REGION_ALIAS("DATA_MEM", dsram) +REGION_ALIAS("BSS_MEM", dsram) +REGION_ALIAS("CSA_MEM", dsram) +REGION_ALIAS("HEAP_MEM", dsram) +REGION_ALIAS("PSRAM_MEM", psram) + +pflash0_base = ORIGIN(pflash0); +pflash1_base = ORIGIN(pflash1); +pflash2_base = ORIGIN(pflash2); + +SECTIONS +{ + .start : + { + KEEP(*(.start)) + . = ALIGN(4); + } > CODE_MEM + + .traptab : + { + KEEP(*(.traptab)) + . = ALIGN(256); + } > CODE_MEM + + .ivtab : + { + KEEP(*(.ivtab)) + . = ALIGN(4); + } > CODE_MEM + + .text : + { + KEEP(*(.text)) + . = ALIGN(2); + } > CODE_MEM + + .data : ALIGN(4) + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > DATA_MEM AT> CODE_MEM + _data_flash = LOADADDR(.data); + + .flash_banks : + { + _flash_banks = . ; + LONG(pflash0_base); + LONG(pflash1_base); + LONG(pflash2_base); + } > CODE_MEM + + .psram_base : + { + . += CONFIG_TRICORE_INITIAL_STACK_OFFSET; + __PSRAM_USTACK = . ; + . += CONFIG_TRICORE_INITIAL_STACK_SIZE; + __PSRAM_BOOT_CSA = . ; + } > PSRAM_MEM + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > BSS_MEM + + .ustack ALIGN(8) (NOLOAD) : + { + . += CONFIG_IDLETHREAD_STACKSIZE ; + __USTACK = . ; + } > BSS_MEM + +#if defined(CONFIG_ARCH_INTERRUPTSTACK) + .istack ALIGN(8) (NOLOAD) : + { + . += CONFIG_ARCH_INTERRUPTSTACK; + __istack = . ; + } > BSS_MEM +#endif + + .csa (NOLOAD) : ALIGN(64) + { + __CSA_BEGIN = . ; + . += CONFIG_TRICORE_CSA_COUNT * 64 ; + __CSA_END = .; + } > CSA_MEM + __CSA_SIZE = __CSA_END - __CSA_BEGIN; + + .heap (NOLOAD) : ALIGN(8) + { + _sheap = . ; + . += __HEAP_SIZE; + _eheap = . ; + } > HEAP_MEM + _heap_size = _sheap - _eheap; +} diff --git a/boards/tricore/tc3x/a2g-tc375-lite/src/CMakeLists.txt b/boards/tricore/tc3x/a2g-tc375-lite/src/CMakeLists.txt new file mode 100644 index 0000000000000..ddaa2af748d43 --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/src/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# boards/tricore/tc3x/a2g-tc375-lite/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_TRICORE_TOOLCHAIN_LLVM) + set_property( + GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_DIR}/arch/tricore/src/common/tricore-llvm.ld") +else() + set_property( + GLOBAL PROPERTY LD_SCRIPT "${NUTTX_DIR}/arch/tricore/src/common/tricore.ld") +endif() + +target_sources(board PRIVATE tc375_appinit.c) diff --git a/boards/tricore/tc3x/a2g-tc375-lite/src/Makefile b/boards/tricore/tc3x/a2g-tc375-lite/src/Makefile new file mode 100644 index 0000000000000..ad16cc0ff1a2b --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/src/Makefile @@ -0,0 +1,26 @@ +############################################################################ +# boards/tricore/tc3x/a2g-tc375-lite/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ +include $(TOPDIR)/Make.defs + +CSRCS = tc375_appinit.c + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/tricore/tc3x/a2g-tc375-lite/src/tc375_appinit.c b/boards/tricore/tc3x/a2g-tc375-lite/src/tc375_appinit.c new file mode 100644 index 0000000000000..56fb95f8b1456 --- /dev/null +++ b/boards/tricore/tc3x/a2g-tc375-lite/src/tc375_appinit.c @@ -0,0 +1,49 @@ +/**************************************************************************** + * boards/tricore/tc3x/a2g-tc375-lite/src/tc375_appinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "tricore_gpio.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void board_aurix_setup_serial_pin(int idx) +{ + if (idx != 0) + { + return; + } + + aurix_config_gpio(AURIX_GPIO(14, 0, GPIO_PERIPH, GPIO_ALT2)); + aurix_config_gpio(AURIX_GPIO(14, 1, GPIO_INPUT, GPIO_PULL_UP)); +} + +int board_app_initialize(uintptr_t arg) +{ + return OK; +} From 24ab6f216ce2f85e14241b39c24855e70e2782da Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Sat, 30 May 2026 22:13:53 +0530 Subject: [PATCH 11/12] boards/tc4x: AURIX Lite Kit (TC4D7) TC4D7 Lite Kit board support for the AURIX TC4X family. Only UART is supported; NSH defconfigs provided for both GCC and HighTec clang toolchains. Signed-off-by: Saravanan Sekar --- .../tricore/tc4x/a3g-tc4d7-lite/index.rst | 69 +++++++++++++++++++ boards/Kconfig | 11 +++ .../tc4x/a3g-tc4d7-lite/CMakeLists.txt | 23 +++++++ boards/tricore/tc4x/a3g-tc4d7-lite/Kconfig | 8 +++ .../a3g-tc4d7-lite/configs/nsh-llvm/defconfig | 41 +++++++++++ .../tc4x/a3g-tc4d7-lite/configs/nsh/defconfig | 40 +++++++++++ .../tc4x/a3g-tc4d7-lite/include/board.h | 26 +++++++ .../tc4x/a3g-tc4d7-lite/scripts/Make.defs | 62 +++++++++++++++++ .../tc4x/a3g-tc4d7-lite/src/CMakeLists.txt | 32 +++++++++ .../tricore/tc4x/a3g-tc4d7-lite/src/Makefile | 26 +++++++ .../tc4x/a3g-tc4d7-lite/src/tc4d7_appinit.c | 58 ++++++++++++++++ tools/ci/testlist/tricore-01.dat | 1 + 12 files changed, 397 insertions(+) create mode 100644 Documentation/platforms/tricore/tc4x/a3g-tc4d7-lite/index.rst create mode 100644 boards/tricore/tc4x/a3g-tc4d7-lite/CMakeLists.txt create mode 100644 boards/tricore/tc4x/a3g-tc4d7-lite/Kconfig create mode 100644 boards/tricore/tc4x/a3g-tc4d7-lite/configs/nsh-llvm/defconfig create mode 100644 boards/tricore/tc4x/a3g-tc4d7-lite/configs/nsh/defconfig create mode 100644 boards/tricore/tc4x/a3g-tc4d7-lite/include/board.h create mode 100644 boards/tricore/tc4x/a3g-tc4d7-lite/scripts/Make.defs create mode 100644 boards/tricore/tc4x/a3g-tc4d7-lite/src/CMakeLists.txt create mode 100644 boards/tricore/tc4x/a3g-tc4d7-lite/src/Makefile create mode 100644 boards/tricore/tc4x/a3g-tc4d7-lite/src/tc4d7_appinit.c create mode 100644 tools/ci/testlist/tricore-01.dat diff --git a/Documentation/platforms/tricore/tc4x/a3g-tc4d7-lite/index.rst b/Documentation/platforms/tricore/tc4x/a3g-tc4d7-lite/index.rst new file mode 100644 index 0000000000000..dfee0f2ca3c08 --- /dev/null +++ b/Documentation/platforms/tricore/tc4x/a3g-tc4d7-lite/index.rst @@ -0,0 +1,69 @@ +================================ +KIT_A3G_TC4D7_LITE (AURIX TC4D7) +================================ + +Infineon's AURIX TC4D7 Lite Kit (KIT_A3G_TC4D7_LITE) is the +introductory evaluation platform for the TriCore TC4X (TC1.8P) family. + +Features +======== + +- Infineon AURIX TC4D7 - 4 TriCore CPUs, 10 MiB PFLASH, 5 MiB LMU. +- ASCLIN0 routed to the on-board USB-serial bridge (115200-8-N-1) for + the NSH console. +- iSYSTEM DAP-Miniwiggler header for flash and debug. +- Single USB-C port for power, console and debug. + +Default configuration +===================== + +:: + + ./tools/configure.sh -E a3g-tc4d7-lite:nsh + make -j$(nproc) + +The default toolchain is ``tricore-elf-gcc``; the HighTec LLVM +toolchain can be selected via ``CONFIG_TRICORE_TOOLCHAIN_LLVM=y`` and +requires a valid HighTec licence reachable through ``RLM_LICENSE``. + +Console +======= + +The NSH prompt is exposed on UART0 (ASCLIN0) at 115200-8-N-1 over the +USB virtual COM port. + +Flashing +======== + +The board's ``scripts/Make.defs`` provides a ``flash`` target that +drives OpenOCD with the Infineon TAS server. The prerequisites are +documented in :doc:`../../index` (Flashing and debugging). + +.. code-block:: console + + # Once-per-session: start the TAS server (listens on 24817) + cd /bin && LD_LIBRARY_PATH=. ./tas_server & + + # Flash the kit + make flash + +Override knobs (all set with ``?=`` in ``Make.defs``): + +============================== ======================================= +``OPENOCD`` Path to the patched openocd binary. +``OPENOCD_SCRIPTS`` Directory holding the openocd scripts. +``OPENOCD_BOARD`` Per-board cfg used by openocd. +``OPENOCD_SERIAL`` Adapter serial reported by the Lite Kit. +``FLASH_IMAGE`` The .hex image to program. +============================== ======================================= + +Known limitations +================= + +- Only the ``:nsh`` configuration is validated. No kernel-mode build, + no networking, no file system. +- Single CPU (CPU0) only. AMP / multi-core bring-up is intentionally + not part of this port. +- ``ostest`` has not been run against this board. The port has been + validated through the NSH UART + STM clock-tick + synchronous-trap + test battery only. diff --git a/boards/Kconfig b/boards/Kconfig index 234b1200e3db6..2e9632a269bc7 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -2461,6 +2461,13 @@ config ARCH_BOARD_A2G_TC375_LITE Infineon AURIX Lite Kit evaluation board (KIT_A2G_TC375_LITE) with the TC375 SoC. +config ARCH_BOARD_A3G_TC4D7_LITE + bool "Infineon AURIX Lite Kit (TC4D7)" + depends on TC4X_CHIP_TC4D7 + ---help--- + Infineon AURIX Lite Kit evaluation board (KIT_A3G_TC4D7_LITE) + with the TC4D7 SoC. + config ARCH_BOARD_QEMU_ARMV7A bool "Qemu ARMv7a CPUs board" depends on ARCH_CHIP_QEMU_ARM @@ -3892,6 +3899,7 @@ config ARCH_BOARD default "starpro64" if ARCH_BOARD_EIC7700X_STARPRO64 default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD default "a2g-tc375-lite" if ARCH_BOARD_A2G_TC375_LITE + default "a3g-tc4d7-lite" if ARCH_BOARD_A3G_TC4D7_LITE default "qemu-armv7a" if ARCH_BOARD_QEMU_ARMV7A default "qemu-armv7r" if ARCH_BOARD_QEMU_ARMV7R default "qemu-armv8a" if ARCH_BOARD_QEMU_ARMV8A @@ -4117,6 +4125,9 @@ endif if ARCH_BOARD_A2G_TC375_LITE source "boards/tricore/tc3x/a2g-tc375-lite/Kconfig" endif +if ARCH_BOARD_A3G_TC4D7_LITE +source "boards/tricore/tc4x/a3g-tc4d7-lite/Kconfig" +endif if ARCH_BOARD_MPS2_AN500 source "boards/arm/mps/mps2-an500/Kconfig" endif diff --git a/boards/tricore/tc4x/a3g-tc4d7-lite/CMakeLists.txt b/boards/tricore/tc4x/a3g-tc4d7-lite/CMakeLists.txt new file mode 100644 index 0000000000000..311aabdba79c6 --- /dev/null +++ b/boards/tricore/tc4x/a3g-tc4d7-lite/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/tricore/tc4x/a3g-tc4d7-lite/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/tricore/tc4x/a3g-tc4d7-lite/Kconfig b/boards/tricore/tc4x/a3g-tc4d7-lite/Kconfig new file mode 100644 index 0000000000000..925099ab19563 --- /dev/null +++ b/boards/tricore/tc4x/a3g-tc4d7-lite/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_A3G_TC4D7_LITE + +endif diff --git a/boards/tricore/tc4x/a3g-tc4d7-lite/configs/nsh-llvm/defconfig b/boards/tricore/tc4x/a3g-tc4d7-lite/configs/nsh-llvm/defconfig new file mode 100644 index 0000000000000..22fbe822d701d --- /dev/null +++ b/boards/tricore/tc4x/a3g-tc4d7-lite/configs/nsh-llvm/defconfig @@ -0,0 +1,41 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_BOARD_LATE_INITIALIZE is not set +CONFIG_ARCH="tricore" +CONFIG_ARCH_BOARD="a3g-tc4d7-lite" +CONFIG_ARCH_BOARD_A3G_TC4D7_LITE=y +CONFIG_ARCH_CHIP="tc4x" +CONFIG_ARCH_CHIP_FAMILY_TC4X=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_TRICORE=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=10000 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FLASH_SIZE=4194304 +CONFIG_FLASH_START=0x80000000 +CONFIG_INIT_ENTRYNAME="main" +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=5242880 +CONFIG_RAM_START=0x90400000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=1 +CONFIG_SYSLOG_NONE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TRICORE_TOOLCHAIN_LLVM=y +CONFIG_TRICORE_UART0=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=100 diff --git a/boards/tricore/tc4x/a3g-tc4d7-lite/configs/nsh/defconfig b/boards/tricore/tc4x/a3g-tc4d7-lite/configs/nsh/defconfig new file mode 100644 index 0000000000000..ae727e9808a6e --- /dev/null +++ b/boards/tricore/tc4x/a3g-tc4d7-lite/configs/nsh/defconfig @@ -0,0 +1,40 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_BOARD_LATE_INITIALIZE is not set +CONFIG_ARCH="tricore" +CONFIG_ARCH_BOARD="a3g-tc4d7-lite" +CONFIG_ARCH_BOARD_A3G_TC4D7_LITE=y +CONFIG_ARCH_CHIP="tc4x" +CONFIG_ARCH_CHIP_FAMILY_TC4X=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_TRICORE=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=10000 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FLASH_SIZE=4194304 +CONFIG_FLASH_START=0x80000000 +CONFIG_INIT_ENTRYNAME="main" +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=5242880 +CONFIG_RAM_START=0x90400000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=1 +CONFIG_SYSLOG_NONE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TRICORE_UART0=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=100 diff --git a/boards/tricore/tc4x/a3g-tc4d7-lite/include/board.h b/boards/tricore/tc4x/a3g-tc4d7-lite/include/board.h new file mode 100644 index 0000000000000..094588a36d982 --- /dev/null +++ b/boards/tricore/tc4x/a3g-tc4d7-lite/include/board.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * boards/tricore/tc4x/a3g-tc4d7-lite/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_TRICORE_TC4X_A3G_TC4D7_LITE_INCLUDE_BOARD_H +#define __BOARDS_TRICORE_TC4X_A3G_TC4D7_LITE_INCLUDE_BOARD_H + +#endif /* __BOARDS_TRICORE_TC4X_A3G_TC4D7_LITE_INCLUDE_BOARD_H */ diff --git a/boards/tricore/tc4x/a3g-tc4d7-lite/scripts/Make.defs b/boards/tricore/tc4x/a3g-tc4d7-lite/scripts/Make.defs new file mode 100644 index 0000000000000..75fa09785b204 --- /dev/null +++ b/boards/tricore/tc4x/a3g-tc4d7-lite/scripts/Make.defs @@ -0,0 +1,62 @@ +############################################################################ +# boards/tricore/tc4x/a3g-tc4d7-lite/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/tricore/src/tc4x/Toolchain.defs + +ifeq ($(CONFIG_TRICORE_TOOLCHAIN_LLVM),y) +ARCHSCRIPT += $(TOPDIR)$(DELIM)arch$(DELIM)tricore$(DELIM)src$(DELIM)common$(DELIM)tricore-llvm.ld +else +ARCHSCRIPT += $(TOPDIR)$(DELIM)arch$(DELIM)tricore$(DELIM)src$(DELIM)common$(DELIM)tricore.ld +endif + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +OPENOCD ?= /opt/tooling/tricore-openocd/bin/openocd +OPENOCD_SCRIPTS ?= /opt/tooling/tricore-openocd/share/openocd/scripts/ +OPENOCD_BOARD ?= board/infineon/kit_a3g_tc4d7_lite.cfg +OPENOCD_SERIAL ?= AURIX LITE KIT V1.0 (TC4D7) LKAA9ZRG +FLASH_IMAGE ?= $(TOPDIR)/nuttx.hex + +ifneq ($(OPENOCD_SERIAL),) +OPENOCD_SERIAL_ARG := -c "adapter serial \"$(OPENOCD_SERIAL)\"" +endif + +define FLASH + @echo "Flashing $(FLASH_IMAGE) via $(OPENOCD_BOARD)" + @if ! ss -ltn 2>/dev/null | grep -q ":24817"; then \ + echo "ERROR: tas_server not running on port 24817"; exit 1; \ + fi + $(OPENOCD) \ + -f $(OPENOCD_BOARD) \ + -s $(OPENOCD_SCRIPTS) \ + $(OPENOCD_SERIAL_ARG) \ + -c "init" \ + -c "reset halt" \ + -c "program $(FLASH_IMAGE) verify reset exit" +endef diff --git a/boards/tricore/tc4x/a3g-tc4d7-lite/src/CMakeLists.txt b/boards/tricore/tc4x/a3g-tc4d7-lite/src/CMakeLists.txt new file mode 100644 index 0000000000000..f96072e92dbc9 --- /dev/null +++ b/boards/tricore/tc4x/a3g-tc4d7-lite/src/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# boards/tricore/tc4x/a3g-tc4d7-lite/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_TRICORE_TOOLCHAIN_LLVM) + set_property( + GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_DIR}/arch/tricore/src/common/tricore-llvm.ld") +else() + set_property( + GLOBAL PROPERTY LD_SCRIPT "${NUTTX_DIR}/arch/tricore/src/common/tricore.ld") +endif() + +target_sources(board PRIVATE tc4d7_appinit.c) diff --git a/boards/tricore/tc4x/a3g-tc4d7-lite/src/Makefile b/boards/tricore/tc4x/a3g-tc4d7-lite/src/Makefile new file mode 100644 index 0000000000000..d0c1f7f64e8fb --- /dev/null +++ b/boards/tricore/tc4x/a3g-tc4d7-lite/src/Makefile @@ -0,0 +1,26 @@ +############################################################################ +# boards/tricore/tc4x/a3g-tc4d7-lite/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ +include $(TOPDIR)/Make.defs + +CSRCS = tc4d7_appinit.c + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/tricore/tc4x/a3g-tc4d7-lite/src/tc4d7_appinit.c b/boards/tricore/tc4x/a3g-tc4d7-lite/src/tc4d7_appinit.c new file mode 100644 index 0000000000000..79059a7d02183 --- /dev/null +++ b/boards/tricore/tc4x/a3g-tc4d7-lite/src/tc4d7_appinit.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * boards/tricore/tc4x/a3g-tc4d7-lite/src/tc4d7_appinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "tricore_gpio.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void board_aurix_setup_serial_pin(int idx) +{ + switch (idx) + { + case 0: + aurix_config_gpio(AURIX_GPIO(14, 0, GPIO_PERIPH, GPIO_ALT2)); + aurix_config_gpio(AURIX_GPIO(14, 1, GPIO_INPUT, GPIO_PULL_UP)); + break; + + case 1: + aurix_config_gpio(AURIX_GPIO(15, 0, GPIO_PERIPH, GPIO_ALT2)); + aurix_config_gpio(AURIX_GPIO(15, 1, GPIO_INPUT, GPIO_PULL_UP)); + break; + + default: + break; + } +} + +int board_app_initialize(uintptr_t arg) +{ + return OK; +} diff --git a/tools/ci/testlist/tricore-01.dat b/tools/ci/testlist/tricore-01.dat new file mode 100644 index 0000000000000..3ba29be025169 --- /dev/null +++ b/tools/ci/testlist/tricore-01.dat @@ -0,0 +1 @@ +/tricore/* From 233dbd0e46ed0554b0fec3db34172857d6320365 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Sat, 30 May 2026 22:14:11 +0530 Subject: [PATCH 12/12] Documentation/platforms/tricore: Add TriCore AURIX overview Cover the feature matrix per AURIX family, architecture notes (CSA context switching, interrupt and trap dispatch), toolchain options (GCC and HighTec LLVM), source layout under arch/tricore/src, and the supported drivers (ASCLIN UART, GPIO, STM). Signed-off-by: Parthiban Nallathambi --- Documentation/platforms/tricore/index.rst | 310 ++++++++++++++++++++-- 1 file changed, 283 insertions(+), 27 deletions(-) diff --git a/Documentation/platforms/tricore/index.rst b/Documentation/platforms/tricore/index.rst index 3f677acaf4bcb..40f929946c817 100644 --- a/Documentation/platforms/tricore/index.rst +++ b/Documentation/platforms/tricore/index.rst @@ -2,29 +2,168 @@ TriCore ======= -NuttX runs on Infineon AURIX TriCore microcontrollers in flat 32-bit address -mode. The port is implemented entirely with direct SFR access; there is no -dependency on Infineon's iLLD SDK, low-level startup is provided by NuttX. +NuttX runs on Infineon AURIX TriCore microcontrollers in flat 32-bit +supervisor mode on CPU0. The port is implemented entirely with direct +SFR access; there is no dependency on Infineon's iLLD SDK, and the +low-level startup, trap handling and interrupt routing are provided by +NuttX itself. The port covers two AURIX SoC families: -================ ================ ===================== - Family TriCore ISA ARCH_FAMILY -================ ================ ===================== - TC3X (TC1.6.2) TC162 ``tc1v6`` - TC4X (TC1.8) TC18 ``tc1v8`` -================ ================ ===================== +- `AURIX TC3X `_ + using the TC1.6.2P ISA +- `AURIX TC4X `_ + using the TC1.8P ISA -Common features: +Key supported features +====================== -- Runs in Supervisor Mode on CPU0. -- IRQs routed by the Interrupt Router (IR), per-Service-Request-Node SRC - registers; SRPN equals the IRQ number. -- System Timer (STM) drives the NuttX systick (oneshot lower-half). -- ASCLIN-based UART for the NSH console. -- GPIO pinmuxing for both families through a shared aurix layer. -- HighTec LLVM 10.2.0 (clang -target tricore) and tricore-elf-gcc 11.3.1 - toolchains are both supported. +The table below summarises the state of the kernel-relevant features +across both AURIX SoC families. + +================================ ======== ======== +Feature TC3X TC4X +================================ ======== ======== +ISA version TC1.6.2P TC1.8P +Single-CPU NSH kernel Yes Yes +SMP / AMP No No +Hardware MPU (DPR/CPR) No No +MPU stack guard No No +System Timer (STM) tick Yes Yes +Single-precision FPU Yes Yes +Double-precision FPU No Yes +ASCLIN UART (NSH console) Yes Yes +GPIO pinmuxing Yes Yes +Instruction/data cache control Yes No +================================ ======== ======== + +Architecture +============ + +Registers +--------- + +The TriCore architecture exposes 32 General Purpose Registers (GPRs) +split into sixteen 32-bit data registers (D[0] through D[15]) and +sixteen 32-bit address registers (A[0] through A[15]). The Program +Counter (PC), Program Status Word (PSW) and Previous Context Information +register (PCXI) form the core system state. + +Several address and data registers have dedicated roles: + +- A[10]: Stack Pointer (SP) +- A[11]: Return Address (RA) +- A[0], A[1], A[8], A[9]: Global address registers +- D[15]: Implicit data register +- A[15]: Implicit base address register + +TC1.8P additionally exposes the PPRS (Previous Protection Register Set) +and FCX (Free CSA List Head Pointer) as architecturally visible system +registers. + +Context Save Areas (CSA) +------------------------ + +A defining feature of the TriCore architecture is its hardware-managed +context save/restore mechanism using Context Save Areas (CSAs). Each +CSA is a 64-byte memory block aligned on a 16-word boundary. CSAs are +linked together to form two lists: + +- **Free Context List (FCX)**: pool of available CSAs. +- **Previous Context List (PCX)**: chain of saved contexts for the + currently executing thread. + +The register set is split into an upper and a lower context: + +- **Upper context** (automatically saved on interrupts, traps and + calls): A[10]-A[15], D[8]-D[15], PSW, PCXI and the return address + A[11]. +- **Lower context** (saved explicitly via SVLCX or BISR): A[2]-A[7], + D[0]-D[7], and A[11]. + +This hardware mechanism eliminates the need for software to manually +push and pop registers on context switches, interrupt entry or function +calls. + +The NuttX port allocates the CSA pool as a fixed array sized by +``CONFIG_TRICORE_CSA_COUNT``. The boot stub in ``tricore_head.S`` +links every CSA into the free list and programs FCX and LCX before +calling ``nx_start()``. + +Interrupt handling +------------------ + +Each interrupt source is assigned a Service Request Priority Number +(SRPN) by writing the per-source SRC register inside the Interrupt +Router (IR). The Interrupt Control Register (ICR) holds the Current +CPU Priority Number (CCPN) and the Pending Interrupt Priority Number +(PIPN). + +An interrupt is taken when ``ICR.IE == 1`` AND ``PIPN > CCPN``. On +entry the hardware: + +- saves the upper context to a CSA; +- sets ``PCXI.PIE = ICR.IE`` and ``PCXI.PCPN = ICR.CCPN``; +- raises ``ICR.CCPN = ICR.PIPN`` and clears ``ICR.IE``; +- loads A[10] from the Interrupt Stack Pointer (ISP) if not already on + the interrupt stack; +- jumps to the vector entry computed from BIV and PIPN. + +NuttX configures BIV for a single-entry dispatch where every interrupt +priority arrives at the common ``tricore_doirq`` stub, which then +dispatches through the NuttX IRQ table. ``RFE`` (Return From +Exception) restores the upper context and ICR from PCXI. + +SRPN equals the NuttX IRQ number on TC4X. On TC3X the SRPN to IRQ +mapping is dense and identical except for the Time-Out-of-Service +field shift (TOS), which is rebuilt by NuttX at IRQ-attach time. + +Trap handling +------------- + +The TriCore architecture defines 8 trap classes addressed via the BTV +(Base Trap Vector) register with 32-byte vector spacing: + +- Class 0: MMU traps (virtual address fill / protection) +- Class 1: Internal protection (MPR/MPW/MPX/MPP) +- Class 2: Instruction errors (illegal opcode, privilege violation, + alignment) +- Class 3: Context management (CSA depletion, call depth overflow) +- Class 4: System bus and peripheral errors +- Class 5: Assertion (arithmetic overflow) +- Class 6: System call (``SYSCALL`` instruction) +- Class 7: Non-Maskable Interrupt + +NuttX routes every trap class through ``tricore_trap_handler`` in +``arch/tricore/src/common/tricore_trapcall.c``. The handler decodes +the class/TIN pair from the BTV stub, looks up the cause string and +emits a full register dump via ``up_dump_register``. Class 6 traps +are forwarded to ``tricore_svcall`` for syscall dispatch; all other +classes log + return so the system can keep running where the trap is +recoverable. Class 7 (NMI) panics the system. + +Toolchain +========= + +Two toolchains are supported and both must build the tree warning-free: + +- **AURIX GCC** (default). Available from + `Infineon Software Tools `_. + The current supported version is GCC 11.3.1 + (``tricore-elf-gcc 11.3.1``). +- **HighTec LLVM** (commercial; enables ``CONFIG_TRICORE_TOOLCHAIN_LLVM``). + Requires a HighTec Development Platform licence reachable through the + ``RLM_LICENSE`` environment variable at build time. + +Configure the chosen toolchain by placing its ``bin`` directory on the +build environment's ``PATH``: + +.. code-block:: console + + export PATH=/opt/tooling/tricore-gcc/bin:$PATH + +NuttX picks up the AURIX target tuple (``tricore-elf-``) and the right +``-mcpu=`` flag automatically based on the selected SoC family. Source layout ============= @@ -32,19 +171,136 @@ Source layout :: arch/tricore/ - include/{tc3x,tc4x}/ chip-public headers + include/ chip-public headers (arch.h, irq.h, ...) src/ - common/ core arch (boot, traps, IRQs, scheduling) - aurix/ shared peripherals (ASCLIN UART, GPIO) - tc3x/ TC3X-specific (clock tree, ENDINIT, GPIO) - tc4x/ TC4X-specific (clock tree, GPIO) + common/ core arch (boot, traps, IRQs, scheduling) + aurix/ shared peripherals (ASCLIN UART, GPIO) + tc3x/ TC3X-specific (clock tree, ENDINIT) + tc4x/ TC4X-specific (clock tree) + + boards/tricore/ + tc3x// TC3X boards + tc4x// TC4X boards + +Drivers +======= + +================================== ======== ======== +Driver TC3X TC4X +================================== ======== ======== +ASCLIN UART Yes Yes +GPIO pinmuxing Yes Yes +System Timer (STM) Yes Yes +Clock control Yes Yes +Interrupt Router (IR) Yes Yes +================================== ======== ======== + +Flashing and debugging +====================== + +The recommended flash path on Linux is OpenOCD with the TriCore/AURIX +extensions and Infineon's Device Access Server (DAS) talking to the +on-board DAP-Miniwiggler. + +Patched OpenOCD with AURIX support is maintained at +`linumiz/openocd-aurix `_. + +Two Infineon vendor packages are required at runtime: + +- `DAS (Device Access Server) `_, + which provides the ``tas_server`` daemon used by OpenOCD to talk to + the on-board debugger. +- `libftd2xx `_ from FTDI, + which must be placed alongside ``tas_server``. + +Build OpenOCD: + +.. code-block:: console + + sudo apt install build-essential git autoconf libtool \ + pkg-config libusb-1.0-0-dev + + git clone https://gitlab.com/linumiz/infineon/release/openocd-aurix.git + cd openocd-aurix + ./bootstrap + mkdir build && cd build + ../configure --prefix=/opt/tooling/tricore-openocd \ + --enable-tas-client --enable-ftdi \ + --enable-jlink --enable-stlink + make -j$(nproc) && sudo make install + +Install DAS following the package instructions, then copy ``libftd2xx`` +into the ``tas_server`` directory. + +Add a udev rule so the debugger is accessible without root: + +.. code-block:: console + + sudo tee /etc/udev/rules.d/99-infineon-aurix.rules >/dev/null <<'EOF' + SUBSYSTEM=="usb", ATTRS{idVendor}=="058b", MODE="0666", GROUP="plugdev" + SUBSYSTEM=="usb", ATTRS{idVendor}=="0403", MODE="0666", GROUP="plugdev" + EOF + sudo udevadm control --reload-rules + sudo udevadm trigger + sudo usermod -aG plugdev $USER + +Log out and back in to pick up the group membership. + +Start the TAS server once per boot. It listens on TCP port 24817: + +.. code-block:: console + + cd + LD_LIBRARY_PATH=. ./tas_server & + +With OpenOCD installed and ``tas_server`` running, flash from the NuttX +tree with: + +.. code-block:: console + + make flash + +Each AURIX board's ``Make.defs`` invokes OpenOCD with the correct board +configuration and adapter serial automatically. + +Known limitation: TC37x debug (OCDS5) +------------------------------------- + +After a synchronous trap on TC37x, the on-chip OCDS5 debug unit can +refuse a clean ``reset run`` until the next power cycle, producing +``[tc37x.cpu0] Failed to enable debug`` from OpenOCD. Recover by +power-cycling the kit (USB unplug for 10+ seconds). TC4Dx does not +exhibit this behaviour. + +Alternative tools +----------------- + +`iSYSTEM winIDEA `_ +together with the +`AURIX Development Studio `_ +is a commercial alternative supported on Windows. A full list of +supported flash programming tools is available at +`Infineon AURIX Flash Tools `_. + +Architecture references +======================= + +- `TC1.8 Architecture Manual Volume 1 `_ +- `TC1.8 Architecture Manual Volume 2 `_ +- `TC1.6 Architecture Manual Volume 1 `_ +- `TC1.6 Architecture Manual Volume 2 `_ + +Maintainers +=========== + +- Parthiban Nallathambi (`Linumiz `_) +- Saravanan Sekar (`Linumiz `_) -Supported boards -================ +Supported SoC families +====================== .. toctree:: :maxdepth: 1 :glob: - tc3x/* - tc4x/* + */*