From 4dda730e259b5aeae95edd888bdc0ea189401fca Mon Sep 17 00:00:00 2001 From: lccosy <1191294205@qq.com> Date: Thu, 4 Jun 2026 23:01:09 +0800 Subject: [PATCH 1/2] arch/arm/gd32f4: fix NULL pointer dereference in arm_earlyserialinit. Add NULL check for g_uart_devs[i] before accessing ->priv in arm_earlyserialinit() loop. When a USART is not enabled in defconfig, g_uart_devs[i] is NULL, causing a HardFault crash during early boot. The bug occurs because the original code only checked g_uart_devs[i]->priv without first verifying g_uart_devs[i] is not NULL. On Cortex-M4, NULL pointer dereference reads from Flash vector table (0x00000000 maps to 0x08000000), returning a function pointer that causes BusFault when written to. This fix matches the existing NULL check pattern used in arm_serialinit() at line 2835 of the same file. Tested on mplant-gd32f450 board with only USART5 enabled in defconfig. Before fix: HardFault at boot (IPSR=3, PC=0x080003e0) After fix: System boots normally to NSH Shell Signed-off-by: lccosy <1191294205@qq.com> --- arch/arm/src/gd32f4/gd32f4xx_serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/gd32f4/gd32f4xx_serial.c b/arch/arm/src/gd32f4/gd32f4xx_serial.c index f4a3659721db3..7291a9dceec0d 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_serial.c +++ b/arch/arm/src/gd32f4/gd32f4xx_serial.c @@ -2763,7 +2763,7 @@ void arm_earlyserialinit(void) for (i = 0; i < GD32_NUSART; i++) { - if (g_uart_devs[i]->priv) + if (g_uart_devs[i] && g_uart_devs[i]->priv) { up_disableusartint(g_uart_devs[i]->priv, 0); } From 6cd56e505e6020b1d2c6ea6989abbaa668e413b4 Mon Sep 17 00:00:00 2001 From: lccosy <1191294205@qq.com> Date: Thu, 11 Jun 2026 00:02:55 +0800 Subject: [PATCH 2/2] arch/arm/gd32f4: fix missing CTL selector bits in up_disableusartint. up_disableusartint() saves USART interrupt state from hardware CTL0-CTL3 registers but omits the CTL selector bits (bits 24-27) in the encoded ie value. When up_restoreusartint() later restores interrupts, it uses ie >> 24 to determine which CTL register to write. Without selector bits this evaluates to 0, so no CTL register is updated and all interrupt enables (including RBNEIE) are permanently lost. This causes RX interrupts to never fire after any call to up_putc() (e.g. via syslog), making the serial console unable to receive input. Fix by adding the corresponding CTL selector bit (USART_CFG_CTLx_INT << USART_CFG_SHIFT) whenever a CTL register has active interrupt bits. Signed-off-by: lccosy <1191294205@qq.com> --- arch/arm/src/gd32f4/gd32f4xx_serial.c | 30 +++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/gd32f4/gd32f4xx_serial.c b/arch/arm/src/gd32f4/gd32f4xx_serial.c index 7291a9dceec0d..5ced798a320d8 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_serial.c +++ b/arch/arm/src/gd32f4/gd32f4xx_serial.c @@ -1142,25 +1142,47 @@ static void up_disableusartint(struct up_dev_s *priv, uint32_t *ie) { uint32_t ctl; + ctl_ie = 0; + /* Save interrupt in CTL0 register */ ctl = up_serialin(priv, GD32_USART_CTL0_OFFSET); - ctl_ie = ((ctl & USART_CTL0_USED_INTS) >> USART_CFG_CTL0_INT_SHIFT); + if (ctl & USART_CTL0_USED_INTS) + { + ctl_ie |= ((ctl & USART_CTL0_USED_INTS) >> + USART_CFG_CTL0_INT_SHIFT); + ctl_ie |= (USART_CFG_CTL0_INT << USART_CFG_SHIFT); + } /* Save interrupt in CTL1 register */ ctl = up_serialin(priv, GD32_USART_CTL1_OFFSET); - ctl_ie |= ((ctl & USART_CTL1_USED_INTS) >> USART_CFG_CTL1_INT_SHIFT); + if (ctl & USART_CTL1_USED_INTS) + { + ctl_ie |= ((ctl & USART_CTL1_USED_INTS) >> + USART_CFG_CTL1_INT_SHIFT); + ctl_ie |= (USART_CFG_CTL1_INT << USART_CFG_SHIFT); + } /* Save interrupt in CTL2 register */ ctl = up_serialin(priv, GD32_USART_CTL2_OFFSET); - ctl_ie |= ((ctl & USART_CTL2_USED_INTS) << USART_CFG_CTL2_INT_SHIFT); + if (ctl & USART_CTL2_USED_INTS) + { + ctl_ie |= ((ctl & USART_CTL2_USED_INTS) << + USART_CFG_CTL2_INT_SHIFT); + ctl_ie |= (USART_CFG_CTL2_INT << USART_CFG_SHIFT); + } /* Save interrupt in CTL3 register */ ctl = up_serialin(priv, GD32_USART_CTL3_OFFSET); - ctl_ie |= ((ctl & USART_CTL3_USED_INTS) << USART_CFG_CTL3_INT_SHIFT); + if (ctl & USART_CTL3_USED_INTS) + { + ctl_ie |= ((ctl & USART_CTL3_USED_INTS) << + USART_CFG_CTL3_INT_SHIFT); + ctl_ie |= (USART_CFG_CTL3_INT << USART_CFG_SHIFT); + } *ie = ctl_ie; }