diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 5b2eb34fc1fc6..99047dd9757d4 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -265,43 +265,43 @@ /* Size SRAM */ #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #else # error STM32 F7 chip Family not identified @@ -310,33 +310,33 @@ /* Common to all Advanced (vs Foundation) Family members */ #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_NSPDIFRX 0 /* Not supported */ -# define STM32F7_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ -# define STM32F7_NI2C 3 /* I2C1-3 */ +# define STM32_NSPDIFRX 0 /* Not supported */ +# define STM32_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NI2C 3 /* I2C1-3 */ #else -# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ -# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ -# define STM32F7_NI2C 4 /* I2C1-4 */ +# define STM32_NSPDIFRX 4 /* 4 SPDIFRX inputs */ +# define STM32_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ +# define STM32_NI2C 4 /* I2C1-4 */ #endif /* Common to all Family members */ -# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */ -# define STM32F7_NUSART 4 /* USART1-3 and 6 */ -# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ -# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */ -# define STM32F7_NSAI 2 /* SAI1-2 */ -# define STM32F7_NDMA 2 /* DMA1-2 */ -# define STM32F7_NADC 3 /* 12-bit ADC1-3, number of channels vary */ -# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32F7_NCRC 1 /* CRC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NUART 4 /* UART 4-5 and 7-8 */ +# define STM32_NUSART 4 /* USART1-3 and 6 */ +# define STM32_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBOTGHS 1 /* USB OTG HS */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NADC 3 /* 12-bit ADC1-3, number of channels vary */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ /* TBD FPU Configuration */ @@ -351,82 +351,82 @@ /* Diversification based on Family and package */ #if defined(CONFIG_STM32F7_HAVE_FMC) -# define STM32F7_NFMC 1 /* Have FMC memory controller */ +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32F7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif #if defined(CONFIG_STM32F7_HAVE_ETHRNET) -# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif #if defined(CONFIG_STM32F7_HAVE_RNG) -# define STM32F7_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ #else -# define STM32F7_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ #endif #if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) -# define STM32F7_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ +# define STM32_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ #elif defined(CONFIG_STM32F7_HAVE_SPI5) -# define STM32F7_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ +# define STM32_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ #elif defined(CONFIG_STM32F7_HAVE_SPI4) -# define STM32F7_NSPI 4 /* SPI1-4 V series */ +# define STM32_NSPI 4 /* SPI1-4 V series */ #else -# define STM32F7_NSPI 3 /* SPI1-3 R series */ +# define STM32_NSPI 3 /* SPI1-3 R series */ #endif #if defined(CONFIG_STM32F7_HAVE_SDMMC2) -# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */ +# define STM32_NSDMMC 2 /* 2 SDMMC interfaces */ #else -# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */ +# define STM32_NSDMMC 1 /* 1 SDMMC interface */ #endif #if defined(CONFIG_STM32F7_HAVE_CAN3) -# define STM32F7_NCAN 3 /* CAN1-3 */ +# define STM32_NCAN 3 /* CAN1-3 */ #elif defined(CONFIG_STM32F7_HAVE_CAN2) -# define STM32F7_NCAN 2 /* CAN1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ #else -# define STM32F7_NCAN 1 /* CAN1 only */ +# define STM32_NCAN 1 /* CAN1 only */ #endif #if defined(CONFIG_STM32F7_HAVE_DCMI) -# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ #else -# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */ +# define STM32_NDCMI 0 /* No Digital camera interface (DCMI) */ #endif #if defined(CONFIG_STM32F7_HAVE_DSIHOST) -# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */ +# define STM32_NDSIHOST 1 /* Have MIPI DSI Host */ #else -# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */ +# define STM32_NDSIHOST 0 /* No MIPI DSI Host */ #endif #if defined (CONFIG_STM32F7_HAVE_LTDC) -# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ +# define STM32_NLCDTFT 1 /* One LCD-TFT */ #else -# define STM32F7_NLCDTFT 0 /* No LCD-TFT */ +# define STM32_NLCDTFT 0 /* No LCD-TFT */ #endif #if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ -# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ +# define STM32_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ #else -# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ +# define STM32_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ #endif #if defined(CONFIG_STM32F7_HAVE_JPEG) -#define STM32F7_NJPEG 1 /* One JPEG Converter */ +#define STM32_NJPEG 1 /* One JPEG Converter */ #else -#define STM32F7_NJPEG 0 /* No JPEG Converter */ +#define STM32_NJPEG 0 /* No JPEG Converter */ #endif #if defined(CONFIG_STM32F7_HAVE_CRYP) -#define STM32F7_NCRYP 1 /* One CRYP engine */ +#define STM32_NCRYP 1 /* One CRYP engine */ #else -#define STM32F7_NCRYP 0 /* No CRYP engine */ +#define STM32_NCRYP 0 /* No CRYP engine */ #endif #if defined(CONFIG_STM32F7_HAVE_HASH) -#define STM32F7_NHASH 1 /* One HASH engine */ +#define STM32_NHASH 1 /* One HASH engine */ #else -#define STM32F7_NHASH 0 /* No HASH engine */ +#define STM32_NHASH 0 /* No HASH engine */ #endif #if defined(CONFIG_STM32F7_HAVE_DFSDM) -#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */ +#define STM32_NDFSDM 4 /* One set of 4 Digital filters */ #else -#define STM32F7_NDFSDM 0 /* No Digital filters */ +#define STM32_NDFSDM 0 /* No Digital filters */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32h5/chip.h b/arch/arm/include/stm32h5/chip.h index 3db5fd6905a80..88906a435a09d 100644 --- a/arch/arm/include/stm32h5/chip.h +++ b/arch/arm/include/stm32h5/chip.h @@ -34,65 +34,65 @@ ****************************************************************************/ #if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32H5_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ -# define STM32H5_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ #elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32H5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -# define STM32H5_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ #else # error "Unsupported STM32H5 chip" #endif -#define STM32H5_NFSMC (1) /* Have FSMC memory controller */ -#define STM32H5_NATIM (2) /* Two advanced timers TIM1 and TIM8 */ -#define STM32H5_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */ -#define STM32H5_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */ -#define STM32H5_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */ -#define STM32H5_NBTIM (2) /* Two basic timers, TIM6-7 */ -#define STM32H5_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ -#define STM32H5_NRNG (1) /* Random number generator (RNG) */ +#define STM32_NFSMC (1) /* Have FSMC memory controller */ +#define STM32_NATIM (2) /* Two advanced timers TIM1 and TIM8 */ +#define STM32_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */ +#define STM32_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */ +#define STM32_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */ +#define STM32_NBTIM (2) /* Two basic timers, TIM6-7 */ +#define STM32_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ +#define STM32_NRNG (1) /* Random number generator (RNG) */ #if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NUART (6) /* UART 4-5, 7-8, 9, 12 */ -# define STM32H5_NUSART (5) /* USART 1-3, 6, 10-11 */ +# define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */ +# define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */ #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NUART (2) /* UART 4-5 */ -# define STM32H5_NUSART (4) /* USART 1-3, 6*/ +# define STM32_NUART (2) /* UART 4-5 */ +# define STM32_NUSART (4) /* USART 1-3, 6*/ #endif -#define STM32H5_NLPUART (1) /* LPUART 1 */ -#define STM32H5_QSPI (0) /* No QuadSPI1 */ -#define STM32H5_OCTOSPI (1) /* OCTOSPI1*/ +#define STM32_NLPUART (1) /* LPUART 1 */ +#define STM32_QSPI (0) /* No QuadSPI1 */ +#define STM32_OCTOSPI (1) /* OCTOSPI1*/ #if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NSPI (6) /* SPI1-SPI6 */ -# define STM32H5_NI2C (4) /* I2C1-4 */ +# define STM32_NSPI (6) /* SPI1-SPI6 */ +# define STM32_NI2C (4) /* I2C1-4 */ #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NSPI (3) /* SPI1-SPI3 */ -# define STM32H5_NI2C (3) /* I2C1-3 */ +# define STM32_NSPI (3) /* SPI1-SPI3 */ +# define STM32_NI2C (3) /* I2C1-3 */ #endif -#define STM32H5_NSWPMI (0) /* No SWPMI1 */ -#define STM32H5_NUSBOTGFS (0) /* USB OTG FS */ -#define STM32H5_NUSBFS (1) /* No USB FS */ -#define STM32H5_NCAN (2) /* CAN1 */ -#define STM32H5_NSAI (2) /* SAI1-2 */ +#define STM32_NSWPMI (0) /* No SWPMI1 */ +#define STM32_NUSBOTGFS (0) /* USB OTG FS */ +#define STM32_NUSBFS (1) /* No USB FS */ +#define STM32_NCAN (2) /* CAN1 */ +#define STM32_NSAI (2) /* SAI1-2 */ #if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NSDMMC (2) /* SDMMC interface */ +# define STM32_NSDMMC (2) /* SDMMC interface */ #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NSDMMC (1) /* SDMMC interface */ +# define STM32_NSDMMC (1) /* SDMMC interface */ #endif -#define STM32H5_NDMA (2) /* DMA1-2 */ -#define STM32H5_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */ -#define STM32H5_NADC (2) /* 12-bit ADC1, up to 20 channels */ -#define STM32H5_NDAC (1) /* 12-bit DAC1 */ -#define STM32H5_NCRC (1) /* CRC */ -#define STM32H5_NCOMP (0) /* Comparators */ -#define STM32H5_NOPAMP (0) /* Operational Amplifiers */ +#define STM32_NDMA (2) /* DMA1-2 */ +#define STM32_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */ +#define STM32_NADC (2) /* 12-bit ADC1, up to 20 channels */ +#define STM32_NDAC (1) /* 12-bit DAC1 */ +#define STM32_NCRC (1) /* CRC */ +#define STM32_NCOMP (0) /* Comparators */ +#define STM32_NOPAMP (0) /* Operational Amplifiers */ /* NVIC priority levels *****************************************************/ @@ -104,9 +104,9 @@ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ #if defined(CONFIG_STM32H5_HAVE_ETHERNET) -# define STM32H5_NETHERNET 1 /* Ethernet MAC */ +# define STM32_NETHERNET 1 /* Ethernet MAC */ #else -# define STM32H5_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ #endif #endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */ diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index b97a8659e6c32..2aa62e17e93c5 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -95,154 +95,154 @@ /* Memory */ # ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX -# define STM32H7_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ # else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # endif /* STM32H72XXX or STM32H73XXX / STM32H74XXX or STM32H75XXX */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ # if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ # elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ # elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ # elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else # error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #elif defined(CONFIG_STM32H7_STM32H7B3XX) /* Memory */ -# define STM32H7_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ # if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ # elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ # elif defined(CONFIG_STM32H7_IO_CONFIG_L) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ # elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else # error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #elif defined(CONFIG_STM32H7_STM32H7X7XX) /* Memory */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #else # error STM32 H7 chip Family not identified #endif @@ -260,15 +260,15 @@ /* Diversification based on Family and package */ #if defined(CONFIG_STM32H7_HAVE_ETHERNET) -# define STM32H7_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif #if defined(CONFIG_STM32H7_HAVE_FMC) -# define STM32H7_NFMC 1 /* Have FMC memory controller */ +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32H7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index febd84d6fac0e..79b07b9e1c97f 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -66,260 +66,260 @@ */ #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -# define STM32L4_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \ defined(CONFIG_STM32L4_STM32L486XX) -# define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ defined(CONFIG_STM32L4_STM32L462XX) -# define STM32L4_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L432XX) || defined(CONFIG_STM32L4_STM32L433XX) -# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) -# define STM32L4_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L4 chip" #endif #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 0 /* No QuadSPI1 */ -# define STM32L4_OCTOSPI 2 /* OCTOSPI1-2 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 4 /* I2C1-4 */ -# define STM32L4_NSWPMI 0 /* No SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ -# define STM32L4_NADC 1 /* 12-bit ADC1, up to 20 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 0 /* No QuadSPI1 */ +# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 0 /* No SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L4XR */ #if defined(CONFIG_STM32L4_STM32L4X5) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 3 /* I2C1-3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L4X5 */ #if defined(CONFIG_STM32L4_STM32L4X6) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ #if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NI2C 4 /* I2C1-4 */ +# define STM32_NI2C 4 /* I2C1-4 */ #else -# define STM32L4_NI2C 3 /* I2C1-3 */ +# define STM32_NI2C 3 /* I2C1-3 */ #endif -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ #if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NCAN 2 /* CAN1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ #else -# define STM32L4_NCAN 1 /* CAN1 */ +# define STM32_NCAN 1 /* CAN1 */ #endif -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ #if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ #else -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ #endif -# define STM32L4_NADC 3 /* 12-bit ADC1-3, up to 24 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ +# define STM32_NADC 3 /* 12-bit ADC1-3, up to 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L4X6 */ #if defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ defined(CONFIG_STM32L4_STM32L462XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 1 /* UART 4 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 4 /* I2C1-4 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 1 /* One basic timer, TIM6 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 1 /* UART 4 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ #if defined(CONFIG_STM32L4_STM32L451XX) -# define STM32L4_NUSBFS 0 /* No USB FS */ +# define STM32_NUSBFS 0 /* No USB FS */ #else -# define STM32L4_NUSBFS 1 /* USB FS */ +# define STM32_NUSBFS 1 /* USB FS */ #endif -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ #if defined(CONFIG_STM32L4_HAVE_SDMMC1) -# define STM32L4_NSDMMC 1 /* SDMMC interface */ +# define STM32_NSDMMC 1 /* SDMMC interface */ #else -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ #endif -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */ -# define STM32L4_NDAC 1 /* 12-bit DAC1 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */ +# define STM32_NDAC 1 /* 12-bit DAC1 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L451XX */ #if defined(CONFIG_STM32L4_STM32L432XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 2 /* USART 1-2 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 2 /* SPI1, SPI3 */ -# define STM32L4_NI2C 2 /* I2C1, I2C3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 2 /* USART 1-2 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 2 /* SPI1, SPI3 */ +# define STM32_NI2C 2 /* I2C1, I2C3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L432XX */ #if defined(CONFIG_STM32L4_STM32L433XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-SPI3 */ -# define STM32L4_NI2C 3 /* I2C1-I2C3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-SPI3 */ +# define STM32_NI2C 3 /* I2C1-I2C3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L433XX */ #if defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-SPI3 */ -# define STM32L4_NI2C 3 /* I2C1-I2C3 */ -# define STM32L4_NSWPMI 0 /* No SWPMI */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 0 /* No CAN */ -# define STM32L4_NSAI 0 /* No SAI */ -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 2 /* 12-bit ADC1-2, 10 channels */ -# define STM32L4_NDAC 0 /* No DAC */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 1 /* One basic timer, TIM6 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-SPI3 */ +# define STM32_NI2C 3 /* I2C1-I2C3 */ +# define STM32_NSWPMI 0 /* No SWPMI */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSAI 0 /* No SAI */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 2 /* 12-bit ADC1-2, 10 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L412XX || CONFIG_STM32L4_STM32L422XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l4/irq.h b/arch/arm/include/stm32l4/irq.h index a17c156715713..528204f89690a 100644 --- a/arch/arm/include/stm32l4/irq.h +++ b/arch/arm/include/stm32l4/irq.h @@ -44,26 +44,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32L4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32L4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32L4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32L4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32L4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32L4_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32L4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32L4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32L4_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32L4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files diff --git a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h index 1b3b5b27945ff..2d6e4d570f29d 100644 --- a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h @@ -52,99 +52,99 @@ * */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ - /* Reserved 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ - /* Reserved 42-48 */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ - /* Reserved 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ - /* Reserved 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ - /* Reserved 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_USB_FS (STM32L4_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ - /* Reserved 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32L4_IRQ_CRS (STM32L4_IRQ_FIRST + 82) /* 82: CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ + /* Reserved 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ + /* Reserved 42-48 */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ + /* Reserved 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ + /* Reserved 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ + /* Reserved 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ + /* Reserved 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 82) /* 82: CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ #if defined(CONFIG_STM32L4_STM32L4X3) -# define STM32L4_IRQ_NEXTINTS 85 +# define STM32_IRQ_NEXTINTS 85 #else # error "Unsupported STM32L4 chip" #endif /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4x5xx_irq.h b/arch/arm/include/stm32l4/stm32l4x5xx_irq.h index 3c0c8f49842a4..e21faaae23000 100644 --- a/arch/arm/include/stm32l4/stm32l4x5xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x5xx_irq.h @@ -48,99 +48,99 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_RESERVED78 (STM32L4_IRQ_FIRST + 78) /* 78: Reserved */ -#define STM32L4_IRQ_RESERVED79 (STM32L4_IRQ_FIRST + 79) /* 79: Reserved */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ - -#define STM32L4_IRQ_NEXTINTS 82 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST + 78) /* 78: Reserved */ +#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST + 79) /* 79: Reserved */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ + +#define STM32_IRQ_NEXTINTS 82 /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h index 039cc81d92a90..7e937ff34c7cd 100644 --- a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h @@ -48,117 +48,117 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ /* STM32L496xx/4A6xx only: */ -#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ -#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ -#define STM32L4_IRQ_CAN2TX (STM32L4_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */ -#define STM32L4_IRQ_CAN2RX0 (STM32L4_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */ -#define STM32L4_IRQ_CAN2RX1 (STM32L4_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */ -#define STM32L4_IRQ_CAN2SCE (STM32L4_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */ -#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ +#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ +#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */ +#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */ +#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */ +#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ #if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) -# define STM32L4_IRQ_NEXTINTS 82 +# define STM32_IRQ_NEXTINTS 82 #elif defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_IRQ_NEXTINTS 91 +# define STM32_IRQ_NEXTINTS 91 #else # error "Unsupported STM32L4 chip" #endif /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4xrxx_irq.h b/arch/arm/include/stm32l4/stm32l4xrxx_irq.h index 803bf8dc01240..ec9f7db1f952b 100644 --- a/arch/arm/include/stm32l4/stm32l4xrxx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4xrxx_irq.h @@ -48,109 +48,109 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ - /* Reserved 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_OCTOSPI1 (STM32L4_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_OCTOSPI2 (STM32L4_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_DSIHSOT (STM32L4_IRQ_FIRST + 78) /* 78: DSI global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ -#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ - /* Reserved 86-89: CAN2 */ -#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ -#define STM32L4_IRQ_LCD_TFT (STM32L4_IRQ_FIRST + 91) /* 91: LTDC global interrupt */ -#define STM32L4_IRQ_LCD_TFT_ER (STM32L4_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */ -#define STM32L4_IRQ_GFXMMU (STM32L4_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */ -#define STM32L4_IRQ_DMAMUX1_OVR (STM32L4_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ - -#define STM32L4_IRQ_NEXTINTS 95 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ + /* Reserved 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_OCTOSPI2 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_DSIHSOT (STM32_IRQ_FIRST + 78) /* 78: DSI global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ + /* Reserved 86-89: CAN2 */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ +#define STM32_IRQ_LCD_TFT (STM32_IRQ_FIRST + 91) /* 91: LTDC global interrupt */ +#define STM32_IRQ_LCD_TFT_ER (STM32_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */ +#define STM32_IRQ_GFXMMU (STM32_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ + +#define STM32_IRQ_NEXTINTS 95 /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l5/chip.h b/arch/arm/include/stm32l5/chip.h index 25fae6e32e0c9..e6948539e5f43 100644 --- a/arch/arm/include/stm32l5/chip.h +++ b/arch/arm/include/stm32l5/chip.h @@ -34,41 +34,41 @@ ****************************************************************************/ #if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32L5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif #if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L5_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L5_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L5_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L5_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L5_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L5_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L5_NRNG 1 /* Random number generator (RNG) */ -# define STM32L5_NUART 2 /* UART 4-5 */ -# define STM32L5_NUSART 3 /* USART 1-3 */ -# define STM32L5_NLPUART 1 /* LPUART 1 */ -# define STM32L5_QSPI 0 /* No QuadSPI1 */ -# define STM32L5_OCTOSPI 2 /* OCTOSPI1-2 */ -# define STM32L5_NSPI 3 /* SPI1-3 */ -# define STM32L5_NI2C 4 /* I2C1-4 */ -# define STM32L5_NSWPMI 0 /* No SWPMI1 */ -# define STM32L5_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L5_NUSBFS 0 /* No USB FS */ -# define STM32L5_NCAN 1 /* CAN1 */ -# define STM32L5_NSAI 2 /* SAI1-2 */ -# define STM32L5_NSDMMC 1 /* SDMMC interface */ -# define STM32L5_NDMA 2 /* DMA1-2 */ -# define STM32L5_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L5_NADC 1 /* 12-bit ADC1, up to 20 channels */ -# define STM32L5_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L5_NCRC 1 /* CRC */ -# define STM32L5_NCOMP 2 /* Comparators */ -# define STM32L5_NOPAMP 2 /* Operational Amplifiers */ +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 0 /* No QuadSPI1 */ +# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 0 /* No SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ #endif /* CONFIG_STM32L5_STM32L562XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l5/stm32l562xx_irq.h b/arch/arm/include/stm32l5/stm32l562xx_irq.h index a8e283dcc9543..731567e7ffa0e 100644 --- a/arch/arm/include/stm32l5/stm32l562xx_irq.h +++ b/arch/arm/include/stm32l5/stm32l562xx_irq.h @@ -50,124 +50,124 @@ * */ -#define STM32L5_IRQ_WWDG (STM32L5_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L5_IRQ_PVD_PVM (STM32L5_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ -#define STM32L5_IRQ_RTC (STM32L5_IRQ_FIRST + 2) /* 2: RTC global interrupts */ -#define STM32L5_IRQ_RTC_S (STM32L5_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ -#define STM32L5_IRQ_TAMP (STM32L5_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ -#define STM32L5_IRQ_TAMP_S (STM32L5_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ -#define STM32L5_IRQ_FLASH (STM32L5_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ -#define STM32L5_IRQ_FLASH_S (STM32L5_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ -#define STM32L5_IRQ_GTZC (STM32L5_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ -#define STM32L5_IRQ_RCC (STM32L5_IRQ_FIRST + 9) /* 9: RCC global interrupt */ -#define STM32L5_IRQ_RCC_S (STM32L5_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ -#define STM32L5_IRQ_EXTI0 (STM32L5_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ -#define STM32L5_IRQ_EXTI1 (STM32L5_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ -#define STM32L5_IRQ_EXTI2 (STM32L5_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ -#define STM32L5_IRQ_EXTI3 (STM32L5_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ -#define STM32L5_IRQ_EXTI4 (STM32L5_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ -#define STM32L5_IRQ_EXTI5 (STM32L5_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ -#define STM32L5_IRQ_EXTI6 (STM32L5_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ -#define STM32L5_IRQ_EXTI7 (STM32L5_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ -#define STM32L5_IRQ_EXTI8 (STM32L5_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ -#define STM32L5_IRQ_EXTI9 (STM32L5_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ -#define STM32L5_IRQ_EXTI10 (STM32L5_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ -#define STM32L5_IRQ_EXTI11 (STM32L5_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ -#define STM32L5_IRQ_EXTI12 (STM32L5_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ -#define STM32L5_IRQ_EXTI13 (STM32L5_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ -#define STM32L5_IRQ_EXTI14 (STM32L5_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ -#define STM32L5_IRQ_EXTI15 (STM32L5_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ -#define STM32L5_IRQ_DMAMUX1_OVR (STM32L5_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */ -#define STM32L5_IRQ_DMAMUX1_OVR_S (STM32L5_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */ -#define STM32L5_IRQ_DMA1CH1 (STM32L5_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */ -#define STM32L5_IRQ_DMA1CH2 (STM32L5_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */ -#define STM32L5_IRQ_DMA1CH3 (STM32L5_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */ -#define STM32L5_IRQ_DMA1CH4 (STM32L5_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */ -#define STM32L5_IRQ_DMA1CH5 (STM32L5_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */ -#define STM32L5_IRQ_DMA1CH6 (STM32L5_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */ -#define STM32L5_IRQ_DMA1CH7 (STM32L5_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */ -#define STM32L5_IRQ_DMA1CH8 (STM32L5_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */ -#define STM32L5_IRQ_ADC1_2 (STM32L5_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ -#define STM32L5_IRQ_DAC (STM32L5_IRQ_FIRST + 38) /* 38: DAC global interrupt */ -#define STM32L5_IRQ_FDCAN1_IT0 (STM32L5_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ -#define STM32L5_IRQ_FDCAN1_IT1 (STM32L5_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -#define STM32L5_IRQ_TIM1_BRK (STM32L5_IRQ_FIRST + 41) /* 41: TIM1 break */ -#define STM32L5_IRQ_TIM1_UP (STM32L5_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32L5_IRQ_TIM1_TRG_COM (STM32L5_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -#define STM32L5_IRQ_TIM1_CC (STM32L5_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ -#define STM32L5_IRQ_TIM2 (STM32L5_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ -#define STM32L5_IRQ_TIM3 (STM32L5_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ -#define STM32L5_IRQ_TIM4 (STM32L5_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ -#define STM32L5_IRQ_TIM5 (STM32L5_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ -#define STM32L5_IRQ_TIM6 (STM32L5_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ -#define STM32L5_IRQ_TIM7 (STM32L5_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32L5_IRQ_TIM8_BRK (STM32L5_IRQ_FIRST + 51) /* 51: TIM8 break */ -#define STM32L5_IRQ_TIM8_UP (STM32L5_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32L5_IRQ_TIM8_TRG_COM (STM32L5_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ -#define STM32L5_IRQ_TIM8_CC (STM32L5_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ -#define STM32L5_IRQ_I2C1_EV (STM32L5_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ -#define STM32L5_IRQ_I2C1_ER (STM32L5_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ -#define STM32L5_IRQ_I2C2_EV (STM32L5_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ -#define STM32L5_IRQ_I2C2_ER (STM32L5_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */ -#define STM32L5_IRQ_SPI1 (STM32L5_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */ -#define STM32L5_IRQ_SPI2 (STM32L5_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */ -#define STM32L5_IRQ_USART1 (STM32L5_IRQ_FIRST + 61) /* 61: USART1 global interrupt */ -#define STM32L5_IRQ_USART2 (STM32L5_IRQ_FIRST + 62) /* 62: USART2 global interrupt */ -#define STM32L5_IRQ_USART3 (STM32L5_IRQ_FIRST + 63) /* 63: USART3 global interrupt */ -#define STM32L5_IRQ_UART4 (STM32L5_IRQ_FIRST + 64) /* 64: UART4 global interrupt */ -#define STM32L5_IRQ_UART5 (STM32L5_IRQ_FIRST + 65) /* 65: UART5 global interrupt */ -#define STM32L5_IRQ_LPUART1 (STM32L5_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */ -#define STM32L5_IRQ_LPTIM1 (STM32L5_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */ -#define STM32L5_IRQ_LPTIM2 (STM32L5_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */ -#define STM32L5_IRQ_TIM15 (STM32L5_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */ -#define STM32L5_IRQ_TIM16 (STM32L5_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ -#define STM32L5_IRQ_TIM17 (STM32L5_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ -#define STM32L5_IRQ_COMP (STM32L5_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ -#define STM32L5_IRQ_USB_FS (STM32L5_IRQ_FIRST + 73) /* 73: USB global interrupt */ -#define STM32L5_IRQ_CRS (STM32L5_IRQ_FIRST + 74) /* 74: CRS global interrupt */ -#define STM32L5_IRQ_FMC (STM32L5_IRQ_FIRST + 75) /* 75: FMC global interrupt */ -#define STM32L5_IRQ_OCTOSPI1 (STM32L5_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */ - /* 77: Reserved */ -#define STM32L5_IRQ_SDMMC1 (STM32L5_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */ - /* 79: Reserved */ -#define STM32L5_IRQ_DMA2CH1 (STM32L5_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */ -#define STM32L5_IRQ_DMA2CH2 (STM32L5_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */ -#define STM32L5_IRQ_DMA2CH3 (STM32L5_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */ -#define STM32L5_IRQ_DMA2CH4 (STM32L5_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */ -#define STM32L5_IRQ_DMA2CH5 (STM32L5_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */ -#define STM32L5_IRQ_DMA2CH6 (STM32L5_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */ -#define STM32L5_IRQ_DMA2CH7 (STM32L5_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */ -#define STM32L5_IRQ_DMA2CH8 (STM32L5_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */ -#define STM32L5_IRQ_I2C3_EV (STM32L5_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */ -#define STM32L5_IRQ_I2C3_ER (STM32L5_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */ -#define STM32L5_IRQ_SAI1 (STM32L5_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */ -#define STM32L5_IRQ_SAI2 (STM32L5_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ -#define STM32L5_IRQ_TSC (STM32L5_IRQ_FIRST + 92) /* 92: TSC global interrupt */ -#define STM32L5_IRQ_AES (STM32L5_IRQ_FIRST + 93) /* 93: AES global interrupt */ -#define STM32L5_IRQ_RNG (STM32L5_IRQ_FIRST + 94) /* 94: RNG global interrupt */ -#define STM32L5_IRQ_FPU (STM32L5_IRQ_FIRST + 95) /* 95: FPU global interrupt */ -#define STM32L5_IRQ_HASH (STM32L5_IRQ_FIRST + 96) /* 96: HASH global interrupt */ -#define STM32L5_IRQ_PKA (STM32L5_IRQ_FIRST + 97) /* 97: PKA global interrupt */ -#define STM32L5_IRQ_LPTIM3 (STM32L5_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */ -#define STM32L5_IRQ_SPI3 (STM32L5_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */ -#define STM32L5_IRQ_I2C4_EV (STM32L5_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */ -#define STM32L5_IRQ_I2C4_ER (STM32L5_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT0 (STM32L5_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT1 (STM32L5_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT2 (STM32L5_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT3 (STM32L5_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */ -#define STM32L5_IRQ_UCPD1 (STM32L5_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */ -#define STM32L5_IRQ_ICACHE (STM32L5_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ -#define STM32L5_IRQ_OTFDEC1 (STM32L5_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD_PVM (STM32_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ +#define STM32_IRQ_RTC (STM32_IRQ_FIRST + 2) /* 2: RTC global interrupts */ +#define STM32_IRQ_RTC_S (STM32_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ +#define STM32_IRQ_TAMP (STM32_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ +#define STM32_IRQ_TAMP_S (STM32_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ +#define STM32_IRQ_FLASH_S (STM32_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ +#define STM32_IRQ_GTZC (STM32_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 9) /* 9: RCC global interrupt */ +#define STM32_IRQ_RCC_S (STM32_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ +#define STM32_IRQ_EXTI5 (STM32_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ +#define STM32_IRQ_EXTI6 (STM32_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ +#define STM32_IRQ_EXTI7 (STM32_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ +#define STM32_IRQ_EXTI8 (STM32_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ +#define STM32_IRQ_EXTI9 (STM32_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ +#define STM32_IRQ_EXTI10 (STM32_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ +#define STM32_IRQ_EXTI11 (STM32_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ +#define STM32_IRQ_EXTI12 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ +#define STM32_IRQ_EXTI13 (STM32_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ +#define STM32_IRQ_EXTI14 (STM32_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ +#define STM32_IRQ_EXTI15 (STM32_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */ +#define STM32_IRQ_DMAMUX1_OVR_S (STM32_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */ +#define STM32_IRQ_ADC1_2 (STM32_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ +#define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ +#define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ +#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ +#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ +#define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ +#define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ +#define STM32_IRQ_I2C2_ER (STM32_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 61) /* 61: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 62) /* 62: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 63) /* 63: USART3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 64) /* 64: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 65) /* 65: UART5 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ +#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 73) /* 73: USB global interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 74) /* 74: CRS global interrupt */ +#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 75) /* 75: FMC global interrupt */ +#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */ + /* 77: Reserved */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */ + /* 79: Reserved */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */ +#define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */ +#define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 92) /* 92: TSC global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 93) /* 93: AES global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 94) /* 94: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 95) /* 95: FPU global interrupt */ +#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 96) /* 96: HASH global interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 97) /* 97: PKA global interrupt */ +#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */ +#define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */ +#define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */ +#define STM32_IRQ_DFSDM1_FLT0 (STM32_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT1 (STM32_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT2 (STM32_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT3 (STM32_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */ +#define STM32_IRQ_UCPD1 (STM32_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */ +#define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ +#define STM32_IRQ_OTFDEC1 (STM32_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */ #if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_IRQ_NEXTINTS 109 +# define STM32_IRQ_NEXTINTS 109 #else # error "Unsupported STM32L5 chip" #endif /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32L5_IRQ_FIRST + STM32L5_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) #endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H */ diff --git a/arch/arm/include/stm32l5/stm32l5_irq.h b/arch/arm/include/stm32l5/stm32l5_irq.h index 8ffbc2ac9a97e..3e7709a902b23 100644 --- a/arch/arm/include/stm32l5/stm32l5_irq.h +++ b/arch/arm/include/stm32l5/stm32l5_irq.h @@ -46,26 +46,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32L5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32L5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32L5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32L5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32L5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32L5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32L5_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32L5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32L5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32L5_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). * These definitions are chip-specific */ -#define STM32L5_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32n6/chip.h b/arch/arm/include/stm32n6/chip.h index 72f643ba3b687..9c50b19c7c74b 100644 --- a/arch/arm/include/stm32n6/chip.h +++ b/arch/arm/include/stm32n6/chip.h @@ -52,10 +52,10 @@ * Each bank requires its RCC MEMENR clock enable bit to be set. */ -#define STM32N6_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */ +#define STM32_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */ -#define STM32N6_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */ -#define STM32N6_NUSART (1) /* USART1 */ +#define STM32_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */ +#define STM32_NUSART (1) /* USART1 */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32wb/chip.h b/arch/arm/include/stm32wb/chip.h index 56d7912fe51fd..61ffe8eb774fd 100644 --- a/arch/arm/include/stm32wb/chip.h +++ b/arch/arm/include/stm32wb/chip.h @@ -33,83 +33,83 @@ * Pre-processor Prototypes ****************************************************************************/ -#define STM32WB_NFSMC 0 /* No FSMC */ -#define STM32WB_NBTIM 0 /* No basic timers */ -#define STM32WB_NATIM 1 /* One advanced timers TIM1 */ -#define STM32WB_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */ -#define STM32WB_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -#define STM32WB_NGTIMNDMA 0 /* No general timers without DMA */ +#define STM32_NFSMC 0 /* No FSMC */ +#define STM32_NBTIM 0 /* No basic timers */ +#define STM32_NATIM 1 /* One advanced timers TIM1 */ +#define STM32_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */ +#define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +#define STM32_NGTIMNDMA 0 /* No general timers without DMA */ #if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ #else -# define STM32WB_NGTIM16 0 /* No 16-bit general timers */ +# define STM32_NGTIM16 0 /* No 16-bit general timers */ #endif #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NDMA 2 /* DMA1-2 with 7 channels each */ -# define STM32WB_NI2S 1 /* SAI1 (dual channel high quality audio) */ -# define STM32WB_NI2C 2 /* I2C1, I2C3 */ -# define STM32WB_NUSBOTG 1 /* USB 2.0 FS */ -# define STM32WB_NCMP 2 /* Two Comparators */ +# define STM32_NDMA 2 /* DMA1-2 with 7 channels each */ +# define STM32_NI2S 1 /* SAI1 (dual channel high quality audio) */ +# define STM32_NI2C 2 /* I2C1, I2C3 */ +# define STM32_NUSBOTG 1 /* USB 2.0 FS */ +# define STM32_NCMP 2 /* Two Comparators */ # if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NSPI 3 /* SPI1-2, QSPI */ +# define STM32_NSPI 3 /* SPI1-2, QSPI */ # else -# define STM32WB_NSPI 2 /* SPI1, QSPI */ +# define STM32_NSPI 2 /* SPI1, QSPI */ # endif #else -# define STM32WB_NDMA 1 /* DMA1 with 7 channels */ -# define STM32WB_NI2S 0 /* No SAI */ -# define STM32WB_NI2C 1 /* I2C1 */ -# define STM32WB_NUSBOTG 0 /* No USB */ -# define STM32WB_NCMP 0 /* No Comparators */ -# define STM32WB_NSPI 1 /* SPI1 */ +# define STM32_NDMA 1 /* DMA1 with 7 channels */ +# define STM32_NI2S 0 /* No SAI */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NUSBOTG 0 /* No USB */ +# define STM32_NCMP 0 /* No Comparators */ +# define STM32_NSPI 1 /* SPI1 */ #endif #if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) \ || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NLPUART 1 /* LPUART1 */ +# define STM32_NLPUART 1 /* LPUART1 */ #else -# define STM32WB_NLPUART 0 /* No LPUART */ +# define STM32_NLPUART 0 /* No LPUART */ #endif #if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NCAPSENSE 18 /* Capacitive sensing channels */ +# define STM32_NCAPSENSE 18 /* Capacitive sensing channels */ #else -# define STM32WB_NCAPSENSE 0 /* No Capacitive sensing */ +# define STM32_NCAPSENSE 0 /* No Capacitive sensing */ #endif #if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NLCD 1 /* One LCD controller with up to 8x40 +# define STM32_NLCD 1 /* One LCD controller with up to 8x40 * terminals, depending on subfamily. * 55Cx: 4x13 * 55Rx: 4x28 * 55Vx: 4x44, 8x40 */ #else -# define STM32WB_NLCD 0 /* No LCD */ +# define STM32_NLCD 0 /* No LCD */ #endif -#define STM32WB_NUSART 1 /* USART1 */ -#define STM32WB_NCAN 0 /* No CAN */ -#define STM32WB_NSDIO 0 /* No SDIO interface */ -#define STM32WB_NADC 1 /* ADC1, up to 19-channels */ -#define STM32WB_NDAC 0 /* No DAC */ -#define STM32WB_NCRC 1 /* CRC */ -#define STM32WB_NETHERNET 0 /* No ethernet */ -#define STM32WB_NRNG 1 /* Random number generator (RNG) */ -#define STM32WB_NDCMI 0 /* No digital camera interface (DCMI) */ +#define STM32_NUSART 1 /* USART1 */ +#define STM32_NCAN 0 /* No CAN */ +#define STM32_NSDIO 0 /* No SDIO interface */ +#define STM32_NADC 1 /* ADC1, up to 19-channels */ +#define STM32_NDAC 0 /* No DAC */ +#define STM32_NCRC 1 /* CRC */ +#define STM32_NETHERNET 0 /* No ethernet */ +#define STM32_NRNG 1 /* Random number generator (RNG) */ +#define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ #if defined(CONFIG_STM32WB_IO_CONFIG_C) -# define STM32WB_NGPIO 30 /* GPIO[A,B,C,E,H] */ +# define STM32_NGPIO 30 /* GPIO[A,B,C,E,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_C_48E) -# define STM32WB_NGPIO 37 /* GPIO[A,B,C,E,H] */ +# define STM32_NGPIO 37 /* GPIO[A,B,C,E,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_C_49) -# define STM32WB_NGPIO 25 /* GPIO[A,B,C,H] */ +# define STM32_NGPIO 25 /* GPIO[A,B,C,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_R) -# define STM32WB_NGPIO 49 /* GPIO[A,B,C,D,E,H] */ +# define STM32_NGPIO 49 /* GPIO[A,B,C,D,E,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NGPIO 72 /* GPIO[A,B,C,D,E,H] */ +# define STM32_NGPIO 72 /* GPIO[A,B,C,D,E,H] */ #else # error "Unsupported STM32WB chip" #endif @@ -139,23 +139,23 @@ */ #if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_SRAM1_SIZE (12*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (4*1024) +# define STM32_SRAM1_SIZE (12*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (4*1024) #elif defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) -# define STM32WB_SRAM1_SIZE (32*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) +# define STM32_SRAM1_SIZE (32*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) #elif (defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55)) \ && defined(CONFIG_STM32WB_IO_CONFIG_C) -# define STM32WB_SRAM1_SIZE (64*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) +# define STM32_SRAM1_SIZE (64*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) #elif defined(CONFIG_STM32WB_STM32WB55) && \ (defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)) -# define STM32WB_SRAM1_SIZE (192*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) +# define STM32_SRAM1_SIZE (192*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) #else # error "Unsupported STM32WB chip" #endif diff --git a/arch/arm/include/stm32wb/irq.h b/arch/arm/include/stm32wb/irq.h index 6bd24af39e9d4..381c7e9778db8 100644 --- a/arch/arm/include/stm32wb/irq.h +++ b/arch/arm/include/stm32wb/irq.h @@ -44,26 +44,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32WB_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32WB_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32WB_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32WB_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32WB_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32WB_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32WB_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32WB_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32WB_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32WB_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32WB_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files diff --git a/arch/arm/include/stm32wb/stm32wb_irq.h b/arch/arm/include/stm32wb/stm32wb_irq.h index 4efaba3559fbb..f61881f6a7ce4 100644 --- a/arch/arm/include/stm32wb/stm32wb_irq.h +++ b/arch/arm/include/stm32wb/stm32wb_irq.h @@ -51,146 +51,146 @@ * */ -#define STM32WB_IRQ_WWDG (STM32WB_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32WB_IRQ_PVD (STM32WB_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_PVM1 (STM32WB_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ +# define STM32_IRQ_PVM1 (STM32_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ #endif #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_PVM3 (STM32WB_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ -#endif - -#define STM32WB_IRQ_TAMPER (STM32WB_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */ -#define STM32WB_IRQ_TIMESTAMP (STM32WB_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */ -#define STM32WB_IRQ_LSECSS (STM32WB_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */ -#define STM32WB_IRQ_RTC_WKUP (STM32WB_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32WB_IRQ_FLASH (STM32WB_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32WB_IRQ_RCC (STM32WB_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32WB_IRQ_EXTI0 (STM32WB_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32WB_IRQ_EXTI1 (STM32WB_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32WB_IRQ_EXTI2 (STM32WB_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32WB_IRQ_EXTI3 (STM32WB_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32WB_IRQ_EXTI4 (STM32WB_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32WB_IRQ_DMA1CH1 (STM32WB_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32WB_IRQ_DMA1CH2 (STM32WB_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32WB_IRQ_DMA1CH3 (STM32WB_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32WB_IRQ_DMA1CH4 (STM32WB_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32WB_IRQ_DMA1CH5 (STM32WB_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32WB_IRQ_DMA1CH6 (STM32WB_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32WB_IRQ_DMA1CH7 (STM32WB_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32WB_IRQ_ADC1 (STM32WB_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +# define STM32_IRQ_PVM3 (STM32_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ +#endif + +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */ +#define STM32_IRQ_LSECSS (STM32_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) - #define STM32WB_IRQ_USB_HP (STM32WB_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ - #define STM32WB_IRQ_USB_LP (STM32WB_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ + #define STM32_IRQ_USB_HP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ + #define STM32_IRQ_USB_LP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ #endif -#define STM32WB_IRQ_C2SEV (STM32WB_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ +#define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_COMP (STM32WB_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ #endif -#define STM32WB_IRQ_EXTI95 (STM32WB_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */ -#define STM32WB_IRQ_TIM1BRK (STM32WB_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32WB_IRQ_TIM1UP (STM32WB_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32WB_IRQ_TIM1TRGCOM (STM32WB_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ #if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_TIM16 (STM32WB_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -# define STM32WB_IRQ_TIM17 (STM32WB_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +# define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +# define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ #endif -#define STM32WB_IRQ_TIM1CC (STM32WB_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32WB_IRQ_TIM2 (STM32WB_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32WB_IRQ_PKA (STM32WB_IRQ_FIRST + 29) /* 29: PKA Interrupt */ -#define STM32WB_IRQ_I2C1EV (STM32WB_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ -#define STM32WB_IRQ_I2C1ER (STM32WB_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 29) /* 29: PKA Interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_I2C3EV (STM32WB_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ -# define STM32WB_IRQ_I2C3ER (STM32WB_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ +# define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ +# define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ #endif -#define STM32WB_IRQ_SPI1 (STM32WB_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ #if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_SPI2 (STM32WB_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ #endif -#define STM32WB_IRQ_USART1 (STM32WB_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_LPUART1 (STM32WB_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ +# define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ #endif #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_SAI1 (STM32WB_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ +# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ #endif #if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) \ || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_TSC (STM32WB_IRQ_FIRST + 39) /* 39: TSC global interrupt */ +# define STM32_IRQ_TSC (STM32_IRQ_FIRST + 39) /* 39: TSC global interrupt */ #endif -#define STM32WB_IRQ_EXTI1510 (STM32WB_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32WB_IRQ_RTCALRM (STM32WB_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_CRS (STM32WB_IRQ_FIRST + 42) /* 42: CRS interrupt */ +# define STM32_IRQ_CRS (STM32_IRQ_FIRST + 42) /* 42: CRS interrupt */ #endif -#define STM32WB_IRQ_PWRSOTF (STM32WB_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */ -#define STM32WB_IRQ_PWRBLEACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ -#define STM32WB_IRQ_PWRRFPHASE (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ +#define STM32_IRQ_PWRSOTF (STM32_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */ +#define STM32_IRQ_PWRBLEACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ +#define STM32_IRQ_PWRRFPHASE (STM32_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ #if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_PWR802ACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ +# define STM32_IRQ_PWR802ACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ #endif -#define STM32WB_IRQ_IPCCRX (STM32WB_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */ -#define STM32WB_IRQ_IPCCTX (STM32WB_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */ -#define STM32WB_IRQ_HSEM (STM32WB_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */ -#define STM32WB_IRQ_LPTIM1 (STM32WB_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ -#define STM32WB_IRQ_LPTIM2 (STM32WB_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ +#define STM32_IRQ_IPCCRX (STM32_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */ +#define STM32_IRQ_IPCCTX (STM32_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */ +#define STM32_IRQ_HSEM (STM32_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ #if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_LCD (STM32WB_IRQ_FIRST + 49) /* 49: LCD global interrupt */ +# define STM32_IRQ_LCD (STM32_IRQ_FIRST + 49) /* 49: LCD global interrupt */ #endif #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_QUADSPI (STM32WB_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ -# define STM32WB_IRQ_AES1 (STM32WB_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ +# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ +# define STM32_IRQ_AES1 (STM32_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ #endif -#define STM32WB_IRQ_AES2 (STM32WB_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */ -#define STM32WB_IRQ_RNG (STM32WB_IRQ_FIRST + 53) /* 53: RNG global interrupt */ -#define STM32WB_IRQ_FPU (STM32WB_IRQ_FIRST + 54) /* 54: FPU global interrupt */ +#define STM32_IRQ_AES2 (STM32_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 53) /* 53: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 54) /* 54: FPU global interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_DMA2CH1 (STM32WB_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ -# define STM32WB_IRQ_DMA2CH2 (STM32WB_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ -# define STM32WB_IRQ_DMA2CH3 (STM32WB_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ -# define STM32WB_IRQ_DMA2CH4 (STM32WB_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */ -# define STM32WB_IRQ_DMA2CH5 (STM32WB_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */ -# define STM32WB_IRQ_DMA2CH6 (STM32WB_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */ -# define STM32WB_IRQ_DMA2CH7 (STM32WB_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */ +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */ +# define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */ +# define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */ #endif -#define STM32WB_IRQ_DMAMUX1 (STM32WB_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */ +#define STM32_IRQ_DMAMUX1 (STM32_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */ -#define STM32WB_IRQ_NEXTINTS 63 +#define STM32_IRQ_NEXTINTS 63 /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32WB_IRQ_FIRST + STM32WB_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32wl5/chip.h b/arch/arm/include/stm32wl5/chip.h index d7da1c8c45ee6..48c3f837a6bd9 100644 --- a/arch/arm/include/stm32wl5/chip.h +++ b/arch/arm/include/stm32wl5/chip.h @@ -34,28 +34,28 @@ ****************************************************************************/ #if defined(CONFIG_STM32WL5_STM32WL5XXX) -# define STM32WL5_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */ -# define STM32WL5_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif #if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) -# define STM32WL5_NATIM 1 /* One advanced timer TIM1 */ -# define STM32WL5_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32WL5_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ -# define STM32WL5_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */ -# define STM32WL5_NRNG 1 /* Random number generator (RNG) */ -# define STM32WL5_NUSART 2 /* USART 1-2 */ -# define STM32WL5_NLPUART 1 /* LPUART 1 */ -# define STM32WL5_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */ -# define STM32WL5_NI2C 3 /* I2C1-3 */ -# define STM32WL5_NDMA 2 /* Two DMA channels DMA1-2 */ -# define STM32WL5_NPORTS 4 /* GPIO{A,B,C,H} */ -# define STM32WL5_NADC 1 /* ADC1 */ -# define STM32WL5_NDAC 1 /* DAC1 */ -# define STM32WL5_NCRC 1 /* CRC1 */ -# define STM32WL5_NCOMP 1 /* COMP1 */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ +# define STM32_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUSART 2 /* USART 1-2 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NDMA 2 /* Two DMA channels DMA1-2 */ +# define STM32_NPORTS 4 /* GPIO{A,B,C,H} */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 1 /* DAC1 */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NCOMP 1 /* COMP1 */ #endif /* CONFIG_STM32WL5_STM32WL5XXX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32wl5/irq.h b/arch/arm/include/stm32wl5/irq.h index a8941dbeed680..08bbc522c55e2 100644 --- a/arch/arm/include/stm32wl5/irq.h +++ b/arch/arm/include/stm32wl5/irq.h @@ -44,26 +44,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32WL5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32WL5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32WL5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32WL5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32WL5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32WL5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32WL5_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32WL5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32WL5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32WL5_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32WL5_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files diff --git a/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h b/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h index 88ce31efc5a24..a8c99354b2159 100644 --- a/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h +++ b/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h @@ -48,80 +48,80 @@ * External interrupts (vectors >= 16) */ -#define STM32WL5_IRQ_WWDG (STM32WL5_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */ -#define STM32WL5_IRQ_PVD (STM32WL5_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */ -#define STM32WL5_IRQ_PVM (STM32WL5_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */ -#define STM32WL5_IRQ_TAMPER (STM32WL5_IRQ_FIRST + 2) /* 2: Tamper */ -#define STM32WL5_IRQ_LSE_CSS (STM32WL5_IRQ_FIRST + 2) /* 2: LSECSS */ -#define STM32WL5_IRQ_RTC_STAMP (STM32WL5_IRQ_FIRST + 2) /* 2: timestamp */ -#define STM32WL5_IRQ_RTC_SSRU (STM32WL5_IRQ_FIRST + 2) /* 2: RTC SSR underflow */ -#define STM32WL5_IRQ_RTC_WKUP (STM32WL5_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */ -#define STM32WL5_IRQ_FLASH (STM32WL5_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */ -#define STM32WL5_IRQ_RCC (STM32WL5_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32WL5_IRQ_EXTI0 (STM32WL5_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */ -#define STM32WL5_IRQ_EXTI1 (STM32WL5_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */ -#define STM32WL5_IRQ_EXTI2 (STM32WL5_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */ -#define STM32WL5_IRQ_EXTI3 (STM32WL5_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */ -#define STM32WL5_IRQ_EXTI4 (STM32WL5_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */ -#define STM32WL5_IRQ_DMA1CH1 (STM32WL5_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH2 (STM32WL5_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH3 (STM32WL5_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH4 (STM32WL5_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH5 (STM32WL5_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH6 (STM32WL5_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH7 (STM32WL5_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */ -#define STM32WL5_IRQ_ADC (STM32WL5_IRQ_FIRST + 18) /* 18: ADC global interrupt */ -#define STM32WL5_IRQ_DAC (STM32WL5_IRQ_FIRST + 19) /* 19: DAC global interrupt */ -#define STM32WL5_IRQ_C2SEV (STM32WL5_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */ -#define STM32WL5_IRQ_PWRC2H (STM32WL5_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */ -#define STM32WL5_IRQ_COMP (STM32WL5_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */ -#define STM32WL5_IRQ_EXTI95 (STM32WL5_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */ -#define STM32WL5_IRQ_TIM1BRK (STM32WL5_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */ -#define STM32WL5_IRQ_TIM1UP (STM32WL5_IRQ_FIRST + 24) /* 24: Timer 1 Update */ -#define STM32WL5_IRQ_TIM1TRG_COM (STM32WL5_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */ -#define STM32WL5_IRQ_TIM1CC (STM32WL5_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */ -#define STM32WL5_IRQ_TIM2 (STM32WL5_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */ -#define STM32WL5_IRQ_TIM16 (STM32WL5_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */ -#define STM32WL5_IRQ_TIM17 (STM32WL5_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */ -#define STM32WL5_IRQ_I2C1EV (STM32WL5_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ -#define STM32WL5_IRQ_I2C1ER (STM32WL5_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ -#define STM32WL5_IRQ_I2C2EV (STM32WL5_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */ -#define STM32WL5_IRQ_I2C2ER (STM32WL5_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */ -#define STM32WL5_IRQ_SPI1 (STM32WL5_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ -#define STM32WL5_IRQ_SPI2S2 (STM32WL5_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */ -#define STM32WL5_IRQ_USART1 (STM32WL5_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ -#define STM32WL5_IRQ_USART2 (STM32WL5_IRQ_FIRST + 37) /* 37: USART2 global interrupt */ -#define STM32WL5_IRQ_LPUART1 (STM32WL5_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */ -#define STM32WL5_IRQ_LPTIM1 (STM32WL5_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */ -#define STM32WL5_IRQ_LPTIM2 (STM32WL5_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */ -#define STM32WL5_IRQ_EXTI1510 (STM32WL5_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */ -#define STM32WL5_IRQ_RTCALRM (STM32WL5_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */ -#define STM32WL5_IRQ_LPTIM3 (STM32WL5_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */ - /* 44: Reserved */ -#define STM32WL5_IRQ_IPCC_C1_RX_IT (STM32WL5_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */ -#define STM32WL5_IRQ_IPCC_C1_TX_IT (STM32WL5_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */ -#define STM32WL5_IRQ_HSEM (STM32WL5_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */ -#define STM32WL5_IRQ_I2C3EV (STM32WL5_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */ -#define STM32WL5_IRQ_I2C3ER (STM32WL5_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */ -#define STM32WL5_IRQ_RADIO (STM32WL5_IRQ_FIRST + 50) /* 50: Radio */ -#define STM32WL5_IRQ_RFBUSY (STM32WL5_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */ -#define STM32WL5_IRQ_AES (STM32WL5_IRQ_FIRST + 51) /* 51: AES global interrupt */ -#define STM32WL5_IRQ_RNG (STM32WL5_IRQ_FIRST + 52) /* 52: True random number generator interrupt */ -#define STM32WL5_IRQ_PKA (STM32WL5_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */ -#define STM32WL5_IRQ_DMA2CH1 (STM32WL5_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH2 (STM32WL5_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH3 (STM32WL5_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH4 (STM32WL5_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH5 (STM32WL5_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH6 (STM32WL5_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH7 (STM32WL5_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */ -#define STM32WL5_IRQ_DMAMUX1_OVR (STM32WL5_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */ - -#define STM32WL5_IRQ_NEXTINTS 62 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */ +#define STM32_IRQ_PVM (STM32_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper */ +#define STM32_IRQ_LSE_CSS (STM32_IRQ_FIRST + 2) /* 2: LSECSS */ +#define STM32_IRQ_RTC_STAMP (STM32_IRQ_FIRST + 2) /* 2: timestamp */ +#define STM32_IRQ_RTC_SSRU (STM32_IRQ_FIRST + 2) /* 2: RTC SSR underflow */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 19) /* 19: DAC global interrupt */ +#define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */ +#define STM32_IRQ_PWRC2H (STM32_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 24) /* 24: Timer 1 Update */ +#define STM32_IRQ_TIM1TRG_COM (STM32_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ +#define STM32_IRQ_SPI2S2 (STM32_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 37) /* 37: USART2 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */ +#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */ + /* 44: Reserved */ +#define STM32_IRQ_IPCC_C1_RX_IT (STM32_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */ +#define STM32_IRQ_IPCC_C1_TX_IT (STM32_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */ +#define STM32_IRQ_HSEM (STM32_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */ +#define STM32_IRQ_RADIO (STM32_IRQ_FIRST + 50) /* 50: Radio */ +#define STM32_IRQ_RFBUSY (STM32_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 51) /* 51: AES global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 52) /* 52: True random number generator interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */ + +#define STM32_IRQ_NEXTINTS 62 /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32WL5_IRQ_FIRST + STM32WL5_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32f7/hardware/stm32_qspi.h b/arch/arm/src/stm32f7/hardware/stm32_qspi.h index 31cf04e853476..b857ca463b5ec 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32F7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32F7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_sai.h b/arch/arm/src/stm32f7/hardware/stm32_sai.h index c71d7adc87ff0..b93784989026a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sai.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sai.h @@ -36,67 +36,67 @@ /* Register Offsets *********************************************************/ -#define STM32F7_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ +#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ -#define STM32F7_SAI_A_OFFSET 0x0004 -#define STM32F7_SAI_B_OFFSET 0x0024 +#define STM32_SAI_A_OFFSET 0x0004 +#define STM32_SAI_B_OFFSET 0x0024 -#define STM32F7_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ -#define STM32F7_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ -#define STM32F7_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ -#define STM32F7_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ -#define STM32F7_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ -#define STM32F7_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ -#define STM32F7_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ -#define STM32F7_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ +#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ +#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ +#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ +#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ +#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ +#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ +#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ +#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ /* Register Addresses *******************************************************/ -#define STM32F7_SAI1_GCR (STM32_SAI1_BASE+STM32F7_SAI_GCR_OFFSET) - -#define STM32F7_SAI1_A_BASE (STM32_SAI1_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI1_B_BASE (STM32_SAI1_BASE+STM32F7_SAI_B_OFFSET) - -#define STM32F7_SAI1_ACR1 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_ACR2 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_AFRCR (STM32F7_SAI1_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_ASLOTR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_AIM (STM32F7_SAI1_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_ASR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_ACLRFR (STM32F7_SAI1_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_ADR (STM32F7_SAI1_A_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI1_BCR1 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_BCR2 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_BFRCR (STM32F7_SAI1_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_BSLOTR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_BIM (STM32F7_SAI1_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_BSR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_BCLRFR (STM32F7_SAI1_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_BDR (STM32F7_SAI1_B_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI2_GCR (STM32_SAI2_BASE+STM32F7_SAI_GCR_OFFSET) - -#define STM32F7_SAI2_A_BASE (STM32_SAI2_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI2_B_BASE (STM32_SAI2_BASE+STM32F7_SAI_B_OFFSET) - -#define STM32F7_SAI2_ACR1 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_ACR2 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_AFRCR (STM32F7_SAI2_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_ASLOTR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_AIM (STM32F7_SAI2_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_ASR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_ACLRFR (STM32F7_SAI2_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_ADR (STM32F7_SAI2_A_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI2_BCR1 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_BCR2 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_BFRCR (STM32F7_SAI2_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_BSLOTR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_BIM (STM32F7_SAI2_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_BSR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_BCLRFR (STM32F7_SAI2_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_BDR (STM32F7_SAI2_B_BASE+STM32F7_SAI_DR_OFFSET) +#define STM32_SAI1_GCR (STM32_SAI1_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_DR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h index e02cfef5ecfca..0c529af4b75d0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h index 07752be9bf57c..bdb8128244c19 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h index cbcba08dbf47f..00fe52c6f7cda 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h @@ -54,7 +54,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -64,7 +64,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -76,7 +76,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -88,7 +88,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -100,7 +100,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -112,7 +112,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h index d9d897fe1e321..5a3e8dbb1d480 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h index 6473f22947bf1..5c73674d3d0a7 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -66,7 +66,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -81,7 +81,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -96,7 +96,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -111,7 +111,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -126,7 +126,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -141,7 +141,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -156,7 +156,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h index 7d40fb94d08a2..eee436dc44f3f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h index 44bea32690327..f3144d3568da8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h index 4d6e8e398786a..8f2ede7053f76 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h index 0194d61ee7479..a6417e0d4a817 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h index dd0d8963188a0..946408d191603 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -68,7 +68,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -80,7 +80,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -92,7 +92,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -104,7 +104,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -116,7 +116,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h index 6dfbba5177a97..c996cd30768c9 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h @@ -52,7 +52,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -67,7 +67,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -82,7 +82,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -97,7 +97,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -112,7 +112,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -127,7 +127,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -142,7 +142,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -157,7 +157,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h index dc76911406292..370b090abd1c8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h index fc2fa7bec8174..b2586544aa498 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h @@ -99,7 +99,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -127,7 +127,7 @@ # define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -159,7 +159,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -181,7 +181,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -202,7 +202,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -223,7 +223,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -250,7 +250,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -265,7 +265,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -278,7 +278,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -292,7 +292,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -307,7 +307,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -320,7 +320,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -335,7 +335,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -346,7 +346,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 0991bcece13cb..47ac51b14eddd 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -79,10 +79,10 @@ /* Set the start and end of SRAM1 and SRAM2 */ #define SRAM1_START STM32_SRAM1_BASE -#define SRAM1_END (SRAM1_START + STM32F7_SRAM1_SIZE) +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) #define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* The STM32 F7 has DTCM memory */ diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c index 36d92cc7de361..bdf2060127cd5 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.c +++ b/arch/arm/src/stm32f7/stm32_bbsram.c @@ -130,7 +130,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32F7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -544,7 +544,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32F7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -627,7 +627,7 @@ static int stm32_bbsram_unlink(struct inode *inode) static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) { int i; - int avail = STM32F7_BBSRAM_SIZE; + int avail = STM32_BBSRAM_SIZE; int alloc; int size; int ret = -EFBIG; diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index 4d080578c4eeb..0eff55b26e1f8 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -46,7 +46,7 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_BBSRAM_SIZE 4096 +# define STM32_BBSRAM_SIZE 4096 #else # error "No backup SRAM on this STM32 Device" #endif @@ -55,11 +55,11 @@ # define CONFIG_STM32F7_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -129,7 +129,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: - * fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL + * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * diff --git a/arch/arm/src/stm32f7/stm32_can.h b/arch/arm/src/stm32f7/stm32_can.h index 05dbe1e10c650..b9377f433890a 100644 --- a/arch/arm/src/stm32f7/stm32_can.h +++ b/arch/arm/src/stm32f7/stm32_can.h @@ -151,4 +151,4 @@ int stm32_cansockinitialize(int port); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32_STM32F7_CAN_H */ diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index c421e4c0e5e1f..e4e8f68da1d87 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -729,7 +729,7 @@ static void stm32can_errint(struct stm32_can_s *priv, bool enable) } else { - regval &= ~STM32F7_CAN_ERRINT; + regval &= ~STM32_CAN_ERRINT; } stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); diff --git a/arch/arm/src/stm32f7/stm32_config.h b/arch/arm/src/stm32f7/stm32_config.h index 9bec9e5870441..c5a0cee3b6d49 100644 --- a/arch/arm/src/stm32f7/stm32_config.h +++ b/arch/arm/src/stm32f7/stm32_config.h @@ -46,19 +46,19 @@ # undef CONFIG_STM32F7_GPIOE_IRQ #endif -#if STM32F7_NPORTS < 1 +#if STM32_NPORTS < 1 # undef CONFIG_STM32F7_GPIOA_IRQ #endif -#if STM32F7_NPORTS < 2 +#if STM32_NPORTS < 2 # undef CONFIG_STM32F7_GPIOB_IRQ #endif -#if STM32F7_NPORTS < 3 +#if STM32_NPORTS < 3 # undef CONFIG_STM32F7_GPIOC_IRQ #endif -#if STM32F7_NPORTS < 4 +#if STM32_NPORTS < 4 # undef CONFIG_STM32F7_GPIOD_IRQ #endif -#if STM32F7_NPORTS < 5 +#if STM32_NPORTS < 5 # undef CONFIG_STM32F7_GPIOE_IRQ #endif @@ -66,25 +66,25 @@ /* Don't enable UARTs not supported by the chip. */ -#if STM32F7_NUART < 1 +#if STM32_NUART < 1 # undef CONFIG_STM32F7_UART0 # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 2 +#elif STM32_NUART < 2 # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 3 +#elif STM32_NUART < 3 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 4 +#elif STM32_NUART < 4 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 5 +#elif STM32_NUART < 5 # undef CONFIG_STM32F7_UART4 #endif @@ -115,14 +115,14 @@ /* Don't enable USARTs not supported by the chip. */ -#if STM32F7_NUSART < 1 +#if STM32_NUSART < 1 # undef CONFIG_STM32F7_USART0 # undef CONFIG_STM32F7_USART1 # undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 2 +#elif STM32_NUSART < 2 # undef CONFIG_STM32F7_USART1 # undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 3 +#elif STM32_NUSART < 3 # undef CONFIG_STM32F7_USART2 #endif @@ -158,8 +158,8 @@ /* Is there a serial console? There should be no more than one defined. * It could be on any: - * UARTn, n=1..STM32F7_NUART, or - * USARTn, n=1..STM32F7_NUSART + * UARTn, n=1..STM32_NUART, or + * USARTn, n=1..STM32_NUSART */ #undef HAVE_SERIAL_CONSOLE diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 72e2d1f52d360..4b1df56c919b7 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -55,7 +55,7 @@ ****************************************************************************/ #define DMA1_NSTREAMS 8 -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 # define DMA2_NSTREAMS 8 # define DMA_NSTREAMS (DMA1_NSTREAMS+DMA2_NSTREAMS) #else @@ -148,7 +148,7 @@ static struct stm32_dma_s g_dma[DMA_NSTREAMS] = .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), }, -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 { .stream = 0, .irq = STM32_IRQ_DMA2S0, @@ -268,13 +268,13 @@ static inline struct stm32_dma_s *stm32_dmastream(unsigned int stream, { int index; - DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32F7_NDMA); + DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA); /* Convert the controller + stream based on the fact that there are * 8 streams per controller. */ -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 index = controller << 3 | stream; #else index = stream; @@ -376,7 +376,7 @@ static int stm32_dmainterrupt(int irq, void *context, void *arg) controller = DMA1; } else -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) { stream = irq - STM32_IRQ_DMA2S0; diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index bf70e68ec45f4..45820a0adca3f 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -54,31 +54,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32F7_NGPIO] = +static const char g_portchar[STM32_NGPIO] = { -#if STM32F7_NGPIO > 11 +#if STM32_NGPIO > 11 # error "Additional support required for this number of GPIOs" -#elif STM32F7_NGPIO > 10 +#elif STM32_NGPIO > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32F7_NGPIO > 9 +#elif STM32_NGPIO > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32F7_NGPIO > 8 +#elif STM32_NGPIO > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32F7_NGPIO > 7 +#elif STM32_NGPIO > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32F7_NGPIO > 6 +#elif STM32_NGPIO > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32F7_NGPIO > 5 +#elif STM32_NGPIO > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32F7_NGPIO > 4 +#elif STM32_NGPIO > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32F7_NGPIO > 3 +#elif STM32_NGPIO > 3 'A', 'B', 'C', 'D' -#elif STM32F7_NGPIO > 2 +#elif STM32_NGPIO > 2 'A', 'B', 'C' -#elif STM32F7_NGPIO > 1 +#elif STM32_NGPIO > 1 'A', 'B' -#elif STM32F7_NGPIO > 0 +#elif STM32_NGPIO > 0 'A' #else # error "Bad number of GPIOs" @@ -112,7 +112,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32F7_NGPIO); + DEBUGASSERT(port < STM32_NGPIO); gpioinfo("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 22c185ac8f825..668418a15ca72 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -65,12 +65,12 @@ #include -/* STM32F7_NETHERNET determines the number of physical interfaces that can +/* STM32_NETHERNET determines the number of physical interfaces that can * be supported by the hardware. CONFIG_STM32F7_ETHMAC will defined if * any STM32F7 Ethernet support is enabled in the configuration. */ -#if STM32F7_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -78,7 +78,7 @@ /* Configuration ************************************************************/ -#if STM32F7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -243,14 +243,14 @@ #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) #define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32F7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. @@ -659,7 +659,7 @@ static uint8_t g_txbuffer[TXBUFFER_ALLOC] /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -3899,7 +3899,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) static inline #endif int stm32_ethinitialize(int intf) @@ -3912,7 +3912,7 @@ int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32F7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -3973,7 +3973,7 @@ int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32F7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -3988,11 +3988,11 @@ int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32F7_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.h b/arch/arm/src/stm32f7/stm32_ethernet.h index 26d0e98ab891f..b33dd2a646d96 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32F7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32F7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32F7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index cddddee17d64d..aeaea51aa198a 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -376,9 +376,9 @@ /* ADC1 + ADC2 + ADC3 interrupt */ -#define STM32F7_IRQ_ADC1_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC2_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC3_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC /* ADC common ***************************************************************/ @@ -392,38 +392,38 @@ #ifdef CONFIG_STM32F7_FOC_FOC0 # ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC1_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC0_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC0_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC0_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC0_ADC4 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC0_ADC_CMN FOC_ADC4_CMN # endif #endif #ifdef CONFIG_STM32F7_FOC_FOC1 # ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC1_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC1_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC1_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC1_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC1_ADC4 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC1_ADC_CMN FOC_ADC4_CMN # endif #endif @@ -772,7 +772,7 @@ void stm32_foc_sync_all(void) /* Store EGR register address */ - egr_reg[i] = foc_dev->pwm_base + STM32F7_GTIM_EGR_OFFSET; + egr_reg[i] = foc_dev->pwm_base + STM32_GTIM_EGR_OFFSET; } /* Write all registers at once */ diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 0033faf47da72..27455106e851e 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -60,39 +60,39 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32F7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 STM32_GPIOF_BASE, #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 STM32_GPIOG_BASE, #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -134,7 +134,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32F7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -409,7 +409,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -449,7 +449,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ diff --git a/arch/arm/src/stm32f7/stm32_gpio.h b/arch/arm/src/stm32f7/stm32_gpio.h index 00fee28b71a14..97fcbc8dfafef 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.h +++ b/arch/arm/src/stm32f7/stm32_gpio.h @@ -240,7 +240,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32F7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index f6f6d0c027208..53b8e44da21cb 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -232,9 +232,9 @@ #endif #if CONFIG_STM32F7_I2S1_DATALEN == 8 -# define STM32F7_I2S1_DATAMASK 0 +# define STM32_I2S1_DATAMASK 0 #elif CONFIG_STM32F7_I2S1_DATALEN == 16 -# define STM32F7_I2S1_DATAMASK 1 +# define STM32_I2S1_DATAMASK 1 #elif CONFIG_STM32F7_I2S1_DATALEN < 8 || CONFIG_STM32F7_I2S1_DATALEN > 16 # error Invalid value for CONFIG_STM32F7_I2S1_DATALEN #else @@ -242,9 +242,9 @@ #endif #if CONFIG_STM32F7_I2S2_DATALEN == 8 -# define STM32F7_I2S2_DATAMASK 0 +# define STM32_I2S2_DATAMASK 0 #elif CONFIG_STM32F7_I2S2_DATALEN == 16 -# define STM32F7_I2S2_DATAMASK 1 +# define STM32_I2S2_DATAMASK 1 #elif CONFIG_STM32F7_I2S2_DATALEN < 8 || CONFIG_STM32F7_I2S2_DATALEN > 16 # error Invalid value for CONFIG_STM32F7_I2S2_DATALEN #else @@ -252,9 +252,9 @@ #endif #if CONFIG_STM32F7_I2S3_DATALEN == 8 -# define STM32F7_I2S3_DATAMASK 0 +# define STM32_I2S3_DATAMASK 0 #elif CONFIG_STM32F7_I2S3_DATALEN == 16 -# define STM32F7_I2S3_DATAMASK 1 +# define STM32_I2S3_DATAMASK 1 #elif CONFIG_STM32F7_I2S3_DATALEN < 8 || CONFIG_STM32F7_I2S3_DATALEN > 16 # error Invalid value for CONFIG_STM32F7_I2S3_DATALEN #else @@ -2486,7 +2486,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32F7_I2S1_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32F7_I2S1 */ @@ -2551,7 +2551,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32F7_I2S2_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32F7_I2S2 */ @@ -2616,7 +2616,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32F7_I2S3_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S3_DATAMASK; + priv->align = STM32_I2S3_DATAMASK; #endif } #endif /* CONFIG_STM32F7_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index 3883278b6f33a..c05e18fc7fef9 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -107,14 +107,14 @@ #endif #ifdef CONFIG_STM32F7_SAI1 -#ifndef STM32F7_SAI1_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifndef STM32_SAI1_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif #ifdef CONFIG_STM32F7_SAI2 -#ifndef STM32F7_SAI2_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifndef STM32_SAI2_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif @@ -278,9 +278,9 @@ static const struct i2s_ops_s g_i2sops = static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -299,9 +299,9 @@ static struct stm32f7_sai_s g_sai1a_priv = static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -322,9 +322,9 @@ static struct stm32f7_sai_s g_sai1b_priv = static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -343,9 +343,9 @@ static struct stm32f7_sai_s g_sai2a_priv = static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -479,30 +479,30 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) #if 0 i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_CR1_OFFSET), - sai_getreg(priv, STM32F7_SAI_CR2_OFFSET), - sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_IM_OFFSET), - sai_getreg(priv, STM32F7_SAI_SR_OFFSET), - sai_getreg(priv, STM32F7_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); #else /* GCR */ #ifdef CONFIG_STM32F7_SAI1 - uint32_t gcr = getreg32(STM32F7_SAI1_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI1_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI1_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI1_GCR, gcr); #else - uint32_t gcr = getreg32(STM32F7_SAI2_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI2_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI2_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI2_GCR, gcr); #endif /* CR1 */ - uint32_t cr1 = sai_getreg(priv, STM32F7_SAI_CR1_OFFSET); - i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32F7_SAI_CR1_OFFSET, cr1); + uint32_t cr1 = sai_getreg(priv, STM32_SAI_CR1_OFFSET); + i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32_SAI_CR1_OFFSET, cr1); uint32_t mode = (cr1 & SAI_CR1_MODE_MASK) >> SAI_CR1_MODE_SHIFT; const char *mode_string[] = @@ -584,8 +584,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* CR2 */ - uint32_t cr2 = sai_getreg(priv, STM32F7_SAI_CR2_OFFSET); - i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32F7_SAI_CR2_OFFSET, cr2); + uint32_t cr2 = sai_getreg(priv, STM32_SAI_CR2_OFFSET); + i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32_SAI_CR2_OFFSET, cr2); uint32_t fth = (cr2 & SAI_CR2_FTH_MASK) >> SAI_CR2_FTH_SHIFT; const char *fth_string[] = { "FIFO empty", @@ -638,8 +638,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* FRCR */ - uint32_t frcr = sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET); - i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_FRCR_OFFSET, frcr); + uint32_t frcr = sai_getreg(priv, STM32_SAI_FRCR_OFFSET); + i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32_SAI_FRCR_OFFSET, frcr); uint32_t frl = (frcr & SAI_FRCR_FRL_MASK) >> SAI_FRCR_FRL_SHIFT; i2sinfo("\t\tFRCR: FRL[7:0] = %d\n", frl); @@ -662,8 +662,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* SLOTR */ - uint32_t slotr = sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET); - i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_SLOTR_OFFSET, slotr); + uint32_t slotr = sai_getreg(priv, STM32_SAI_SLOTR_OFFSET); + i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32_SAI_SLOTR_OFFSET, slotr); uint32_t fboff = (slotr & SAI_SLOTR_FBOFF_MASK) >> SAI_SLOTR_FBOFF_SHIFT; i2sinfo("\t\tSLOTR: FBOFF[4:0] = %d\n", fboff); @@ -731,7 +731,7 @@ static void sai_mckdivider(struct stm32f7_sai_s *priv) mckdiv += 1; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -878,7 +878,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32_dmasetup(priv->dma, priv->base + STM32F7_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -891,7 +891,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -1169,9 +1169,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -1244,7 +1244,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1344,7 +1344,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1528,28 +1528,28 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); - sai_modifyreg(priv, STM32F7_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32F7_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); sai_dump_regs(priv, "After initialization"); } diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index dd5a10c0ee0b6..c04b5eca68021 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -64,7 +64,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32F7_NUSART + STM32F7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -1790,7 +1790,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3565,7 +3565,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h index 447a020e51f6d..d65dbe36b2fd5 100644 --- a/arch/arm/src/stm32f7/stm32_uart.h +++ b/arch/arm/src/stm32f7/stm32_uart.h @@ -40,29 +40,29 @@ * device. */ -#if STM32F7_NUART < 4 +#if STM32_NUART < 4 # undef CONFIG_STM32F7_UART8 #endif -#if STM32F7_NUART < 3 +#if STM32_NUART < 3 # undef CONFIG_STM32F7_UART7 #endif -#if STM32F7_NUART < 2 +#if STM32_NUART < 2 # undef CONFIG_STM32F7_UART5 #endif -#if STM32F7_NUART < 1 +#if STM32_NUART < 1 # undef CONFIG_STM32F7_UART4 #endif -#if STM32F7_NUSART < 4 +#if STM32_NUSART < 4 # undef CONFIG_STM32F7_USART6 #endif -#if STM32F7_NUSART < 3 +#if STM32_NUSART < 3 # undef CONFIG_STM32F7_USART3 #endif -#if STM32F7_NUSART < 2 +#if STM32_NUSART < 2 # undef CONFIG_STM32F7_USART2 #endif -#if STM32F7_NUSART < 1 +#if STM32_NUSART < 1 # undef CONFIG_STM32F7_USART1 #endif diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 625c5917073de..2633267d2554b 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -132,36 +132,36 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index a0f80c1a0314e..f2a51b9e306be 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -134,36 +134,36 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index a497d7ccb8504..d59a5729de626 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -142,36 +142,36 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32h5/hardware/stm32_qspi.h b/arch/arm/src/stm32h5/hardware/stm32_qspi.h index bda49dd568b11..e4ea385ead69e 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h5/hardware/stm32_qspi.h @@ -36,8 +36,8 @@ /* General Characteristics **************************************************/ -#define STM32H5_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32H5_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h index 915d6b4d4b0a8..9718063e46175 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h @@ -53,7 +53,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -69,7 +69,7 @@ # define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -85,7 +85,7 @@ # define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -101,7 +101,7 @@ # define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -117,7 +117,7 @@ # define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -149,7 +149,7 @@ # define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -165,7 +165,7 @@ # define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 8 +#if STM32_NPORTS > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h index eb36e1b58c56a..5b3adf5963e8e 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h index 1ef4fae584542..d81ead3491d88 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h @@ -60,7 +60,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) @@ -77,7 +77,7 @@ # define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) @@ -94,7 +94,7 @@ # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) @@ -111,7 +111,7 @@ # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) @@ -128,7 +128,7 @@ # define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) @@ -145,7 +145,7 @@ # define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h index 74d23099c033c..3e9cf17197605 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h @@ -52,7 +52,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NLPUART > 0 +#if STM32_NLPUART > 0 # define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET) @@ -67,7 +67,7 @@ # define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) @@ -82,7 +82,7 @@ # define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) @@ -97,7 +97,7 @@ # define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) @@ -112,7 +112,7 @@ # define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 4 +#if STM32_NUSART > 4 # define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET) @@ -127,7 +127,7 @@ # define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 5 +#if STM32_NUSART > 5 # define STM32_USART10_CR1 (STM32_USART10_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART10_CR2 (STM32_USART10_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART10_CR3 (STM32_USART10_BASE + STM32_USART_CR3_OFFSET) @@ -142,7 +142,7 @@ # define STM32_USART10_PRESC (STM32_USART10_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 6 +#if STM32_NUSART > 6 # define STM32_USART11_CR1 (STM32_USART11_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART11_CR2 (STM32_USART11_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART11_CR3 (STM32_USART11_BASE + STM32_USART_CR3_OFFSET) @@ -157,7 +157,7 @@ # define STM32_USART11_PRESC (STM32_USART11_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) @@ -172,7 +172,7 @@ # define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) @@ -187,7 +187,7 @@ # define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET) @@ -202,7 +202,7 @@ # define STM32_UART7_PRESC (STM32_UART7_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET) @@ -217,7 +217,7 @@ # define STM32_UART8_PRESC (STM32_UART8_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 4 +#if STM32_NUART > 4 # define STM32_UART9_CR1 (STM32_UART9_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART9_CR2 (STM32_UART9_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART9_CR3 (STM32_UART9_BASE + STM32_USART_CR3_OFFSET) @@ -232,7 +232,7 @@ # define STM32_UART9_PRESC (STM32_UART9_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 5 +#if STM32_NUART > 5 # define STM32_UART12_CR1 (STM32_UART12_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART12_CR2 (STM32_UART12_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART12_CR3 (STM32_UART12_BASE + STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32h5/stm32_ethernet.c b/arch/arm/src/stm32h5/stm32_ethernet.c index 4dbcee14fb69b..27a40cc3ec5ec 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.c +++ b/arch/arm/src/stm32h5/stm32_ethernet.c @@ -66,12 +66,12 @@ #include -/* STM32H5_NETHERNET determines the number of physical interfaces that can +/* STM32_NETHERNET determines the number of physical interfaces that can * be supported by the hardware. CONFIG_STM32H5_ETHMAC will defined if * any STM32H5 Ethernet support is enabled in the configuration. */ -#if STM32H5_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ /* Configuration ************************************************************/ -#if STM32H5_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -227,14 +227,14 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC) #define RXBUFFER_SIZE (CONFIG_STM32H5_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32H5_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32H5_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. @@ -653,7 +653,7 @@ aligned_data(ARMV8M_DCACHE_LINESIZE); /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32H5_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -4181,7 +4181,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf) #else static inline int stm32_ethinitialize(int intf) @@ -4196,7 +4196,7 @@ static inline int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32H5_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -4268,7 +4268,7 @@ static inline int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32H5_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -4283,11 +4283,11 @@ static inline int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32H5_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32H5_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */ diff --git a/arch/arm/src/stm32h5/stm32_ethernet.h b/arch/arm/src/stm32h5/stm32_ethernet.h index 66107aa0181a4..d337248893cd2 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.h +++ b/arch/arm/src/stm32h5/stm32_ethernet.h @@ -29,7 +29,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32H5_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -65,7 +65,7 @@ extern "C" * ****************************************************************************/ -#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -100,5 +100,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32H5_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_ETHERNET_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/stm32_fdcan.c b/arch/arm/src/stm32h5/stm32_fdcan.c index 622c809eafa38..889a3af814940 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.c +++ b/arch/arm/src/stm32h5/stm32_fdcan.c @@ -328,10 +328,10 @@ # undef CONFIG_STM32H5_FDCAN_REGDEBUG #endif -#undef STM32H5_FDCAN_LOOPBACK +#undef STM32_FDCAN_LOOPBACK #if defined(CONFIG_STM32H5_FDCAN1_LOOPBACK) || \ defined(CONFIG_STM32H5_FDCAN2_LOOPBACK) -# define STM32H5_FDCAN_LOOPBACK 1 +# define STM32_FDCAN_LOOPBACK 1 #endif /**************************************************************************** @@ -403,7 +403,7 @@ struct stm32_config_s uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ uint8_t txeventesize; /* TXevent element size (words) */ uint8_t txbufferesize; /* TX buffer element size (words) */ -#ifdef STM32H5_FDCAN_LOOPBACK +#ifdef STM32_FDCAN_LOOPBACK bool loopback; /* True: Loopback mode */ #endif @@ -3282,7 +3282,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) #endif fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); -#ifdef STM32H5_FDCAN_LOOPBACK +#ifdef STM32_FDCAN_LOOPBACK /* Is loopback mode selected for this peripheral? */ if (config->loopback) diff --git a/arch/arm/src/stm32h5/stm32_gpio.c b/arch/arm/src/stm32h5/stm32_gpio.c index 7664d245c9e4f..334a5faf38ae4 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.c +++ b/arch/arm/src/stm32h5/stm32_gpio.c @@ -52,30 +52,30 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32H5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 STM32_GPIOA_BASE, #endif -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 STM32_GPIOB_BASE, #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 STM32_GPIOC_BASE, #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 STM32_GPIOD_BASE, #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 STM32_GPIOE_BASE, #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 STM32_GPIOF_BASE, #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 STM32_GPIOG_BASE, #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 STM32_GPIOH_BASE, #endif }; @@ -139,7 +139,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32H5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -350,7 +350,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -390,7 +390,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ diff --git a/arch/arm/src/stm32h5/stm32_gpio.h b/arch/arm/src/stm32h5/stm32_gpio.h index 9b3552cedc838..ab323a048ab37 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.h +++ b/arch/arm/src/stm32h5/stm32_gpio.h @@ -242,7 +242,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32H5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32h5/stm32_icache.c b/arch/arm/src/stm32h5/stm32_icache.c index 8cd9c0483eec4..8566734a1aed3 100644 --- a/arch/arm/src/stm32h5/stm32_icache.c +++ b/arch/arm/src/stm32h5/stm32_icache.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32H5_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\ +#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\ defined(CONFIG_STM32H5_ICACHE_ERR_INT)) /**************************************************************************** @@ -266,7 +266,7 @@ void stm32_icache_initialize(void) stm32_icache_setup_region(region3); #endif -#if STM32H5_ICACHE_INTERRUPT +#if STM32_ICACHE_INTERRUPT /* Attach ISR */ int ret; diff --git a/arch/arm/src/stm32h5/stm32_lowputc.c b/arch/arm/src/stm32h5/stm32_lowputc.c index 7de76e7300c85..16a0a6131663a 100644 --- a/arch/arm/src/stm32h5/stm32_lowputc.c +++ b/arch/arm/src/stm32h5/stm32_lowputc.c @@ -46,260 +46,260 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_LPUART1_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB3ENR -# define STM32H5_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN -# define STM32H5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32H5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32H5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB3ENR +# define STM32_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART1_BASE -# define STM32H5_APBCLOCK STM32_PCLK2_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB2ENR -# define STM32H5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART1_TX -# define STM32H5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART2_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART2EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART2_TX -# define STM32H5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART3_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART3EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART3_TX -# define STM32H5_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART4_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART4EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART4_TX -# define STM32H5_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART5_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART5EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART5_TX -# define STM32H5_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART6_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART6_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART6EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART6_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART6_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART6_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART6_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART6_TX -# define STM32H5_CONSOLE_RX GPIO_USART6_RX +# define STM32_CONSOLE_BASE STM32_USART6_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART6EN +# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART6_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP +# define STM32_CONSOLE_TX GPIO_USART6_TX +# define STM32_CONSOLE_RX GPIO_USART6_RX # ifdef CONFIG_USART6_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR # if (CONFIG_USART6_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART7_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART7_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART7EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART7_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART7_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART7_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART7_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART7_TX -# define STM32H5_CONSOLE_RX GPIO_UART7_RX +# define STM32_CONSOLE_BASE STM32_UART7_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART7EN +# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART7_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP +# define STM32_CONSOLE_TX GPIO_UART7_TX +# define STM32_CONSOLE_RX GPIO_UART7_RX # ifdef CONFIG_UART7_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR # if (CONFIG_UART7_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART8_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART8_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART8EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART8_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART8_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART8_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART8_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART8_TX -# define STM32H5_CONSOLE_RX GPIO_UART8_RX +# define STM32_CONSOLE_BASE STM32_UART8_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART8EN +# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART8_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP +# define STM32_CONSOLE_TX GPIO_UART8_TX +# define STM32_CONSOLE_RX GPIO_UART8_RX # ifdef CONFIG_UART8_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR # if (CONFIG_UART8_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART9_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART9_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART9EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART9_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART9_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART9_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART9_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART9_TX -# define STM32H5_CONSOLE_RX GPIO_UART9_RX +# define STM32_CONSOLE_BASE STM32_UART9_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART9EN +# define STM32_CONSOLE_BAUD CONFIG_UART9_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART9_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART9_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART9_2STOP +# define STM32_CONSOLE_TX GPIO_UART9_TX +# define STM32_CONSOLE_RX GPIO_UART9_RX # ifdef CONFIG_UART9_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR # if (CONFIG_UART9_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART10_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART10_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART10EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART10_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART10_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART10_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART10_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART10_TX -# define STM32H5_CONSOLE_RX GPIO_USART10_RX +# define STM32_CONSOLE_BASE STM32_USART10_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART10EN +# define STM32_CONSOLE_BAUD CONFIG_USART10_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART10_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART10_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART10_2STOP +# define STM32_CONSOLE_TX GPIO_USART10_TX +# define STM32_CONSOLE_RX GPIO_USART10_RX # ifdef CONFIG_USART10_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR # if (CONFIG_USART10_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART11_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART11_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART11EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART11_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART11_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART11_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART11_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART11_TX -# define STM32H5_CONSOLE_RX GPIO_USART11_RX +# define STM32_CONSOLE_BASE STM32_USART11_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART11EN +# define STM32_CONSOLE_BAUD CONFIG_USART11_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART11_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART11_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART11_2STOP +# define STM32_CONSOLE_TX GPIO_USART11_TX +# define STM32_CONSOLE_RX GPIO_USART11_RX # ifdef CONFIG_USART11_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR # if (CONFIG_USART11_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART12_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART12_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART12EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART12_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART12_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART12_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART12_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART12_TX -# define STM32H5_CONSOLE_RX GPIO_UART12_RX +# define STM32_CONSOLE_BASE STM32_UART12_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART12EN +# define STM32_CONSOLE_BAUD CONFIG_UART12_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART12_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART12_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART12_2STOP +# define STM32_CONSOLE_TX GPIO_UART12_TX +# define STM32_CONSOLE_RX GPIO_UART12_RX # ifdef CONFIG_UART12_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR # if (CONFIG_UART12_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32H5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32H5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -307,15 +307,15 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32H5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32H5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 # endif -# if STM32H5_CONSOLE_BASE == STM32_LPUART1_BASE +# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE # define USART_CR1_CLRBITS \ (USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \ @@ -333,7 +333,7 @@ /* CR2 settings */ -# if STM32H5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -362,7 +362,7 @@ # undef USE_OVER8 /* Calculate USART BAUD rate divider */ -# if STM32H5_CONSOLE_BASE == STM32_LPUART1_BASE +# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE /* BRR = (256 * (APBCLOCK / Prescaler)) / (Baud rate) * With Prescaler == 16, BRR = (16 * APBCLOCK / (Baud rate) @@ -388,19 +388,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32H5_USARTDIV8 \ - (((STM32H5_APBCLOCK << 1) + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) -# define STM32H5_USARTDIV16 \ - ((STM32H5_APBCLOCK + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32H5_USARTDIV8 > 2000 -# define STM32H5_BRR_VALUE STM32H5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32H5_BRR_VALUE \ - ((STM32H5_USARTDIV8 & 0xfff0) | ((STM32H5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif #endif /* HAVE_CONSOLE */ @@ -442,22 +442,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32H5_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32H5_CONSOLE_RS485_DIR - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - STM32H5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32H5_CONSOLE_BASE + STM32_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32H5_CONSOLE_RS485_DIR - while ((getreg32(STM32H5_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - !STM32H5_CONSOLE_RS485_DIR_POLARITY); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -483,7 +483,7 @@ void stm32_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB clock */ - modifyreg32(STM32H5_CONSOLE_APBREG, 0, STM32H5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -492,17 +492,17 @@ void stm32_lowsetup(void) * stm32_rcc.c */ -#ifdef STM32H5_CONSOLE_TX - stm32_configgpio(STM32H5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32H5_CONSOLE_RX - stm32_configgpio(STM32H5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32H5_CONSOLE_RS485_DIR - stm32_configgpio(STM32H5_CONSOLE_RS485_DIR); - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - !STM32H5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -510,42 +510,42 @@ void stm32_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32H5_BRR_VALUE, - STM32H5_CONSOLE_BASE + STM32_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32h5/stm32_rcc.c b/arch/arm/src/stm32h5/stm32_rcc.c index e54cd1f2ce227..0b4dc0fad41c1 100644 --- a/arch/arm/src/stm32h5/stm32_rcc.c +++ b/arch/arm/src/stm32h5/stm32_rcc.c @@ -111,14 +111,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32h5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32H5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32H5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -136,14 +136,14 @@ static inline void rcc_resetbkp(void) /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32H5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32H5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32_pwr_enablebkp(false); diff --git a/arch/arm/src/stm32h5/stm32_serial.c b/arch/arm/src/stm32h5/stm32_serial.c index 4d2e94ad5774e..d0a3152b47895 100644 --- a/arch/arm/src/stm32h5/stm32_serial.c +++ b/arch/arm/src/stm32h5/stm32_serial.c @@ -1429,7 +1429,7 @@ static struct stm32_serial_s g_uart12priv = /* This table lets us iterate over the configured USARTs */ static struct stm32_serial_s * const - g_uart_devs[STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -2012,7 +2012,7 @@ static void stm32serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -3930,7 +3930,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -4000,7 +4000,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -4069,7 +4069,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32h5/stm32_start.c b/arch/arm/src/stm32h5/stm32_start.c index 812f82951edbb..ec63b6dac101a 100644 --- a/arch/arm/src/stm32h5/stm32_start.c +++ b/arch/arm/src/stm32h5/stm32_start.c @@ -83,10 +83,10 @@ */ #define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32H5_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define SRAM3_START STM32_SRAM3_BASE -#define SRAM3_END (SRAM3_START + STM32H5_SRAM3_SIZE) +#define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index 46fb168b718d3..11d20e68e67e0 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -84,28 +84,28 @@ /* Hardware definitions */ -#define STM32H5_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS -#define STM32H5_EP0_MAX_PACKET_SIZE 64 -#define STM32H5_RETRY_COUNT 3 /* Control transfer retries */ +#define STM32_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS +#define STM32_EP0_MAX_PACKET_SIZE 64 +#define STM32_RETRY_COUNT 3 /* Control transfer retries */ /* PMA Buffer allocation (fixed-size bitmap allocator) */ -#define STM32H5_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */ -#define STM32H5_PMA_NBUFFERS 30 /* Total allocatable buffers */ -#define STM32H5_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */ -#define STM32H5_PMA_BUFFER_BIT(bn) (1U << (bn)) -#define STM32H5_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32H5_PMA_BUFFER_SIZE)) -#define STM32H5_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */ +#define STM32_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */ +#define STM32_PMA_NBUFFERS 30 /* Total allocatable buffers */ +#define STM32_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */ +#define STM32_PMA_BUFFER_BIT(bn) (1U << (bn)) +#define STM32_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32_PMA_BUFFER_SIZE)) +#define STM32_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */ /* Delays */ -#define STM32H5_DATANAK_DELAY SEC2TICK(5) -#define STM32H5_RESET_DELAY 100 /* ms */ +#define STM32_DATANAK_DELAY SEC2TICK(5) +#define STM32_RESET_DELAY 100 /* ms */ /* USB DRD base addresses */ -#define STM32H5_USBDRD_BASE STM32_USB_FS_BASE -#define STM32H5_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE +#define STM32_USBDRD_BASE STM32_USB_FS_BASE +#define STM32_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE /* Register access helpers */ @@ -115,7 +115,7 @@ /* Channel register access */ -#define STM32H5_USB_CHEP(n) (STM32H5_USBDRD_BASE + ((n) << 2)) +#define STM32_USB_CHEP(n) (STM32_USBDRD_BASE + ((n) << 2)) /* Host channel data PID values */ @@ -227,7 +227,7 @@ struct stm32_usbhost_s /* Host channels */ - struct stm32_chan_s chan[STM32H5_NHOST_CHANNELS]; + struct stm32_chan_s chan[STM32_NHOST_CHANNELS]; /* PMA allocation */ @@ -416,7 +416,7 @@ static void stm32_pma_write(const uint8_t *buffer, uint16_t pmaaddr, uint32_t count; uint32_t remaining; - pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr); + pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr); count = nbytes >> 2; /* Number of 32-bit words */ remaining = nbytes & 0x03; /* Remaining bytes */ @@ -466,7 +466,7 @@ static void stm32_pma_read(uint8_t *buffer, uint16_t pmaaddr, UP_DSB(); - pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr); + pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr); count = nbytes >> 2; remaining = nbytes & 0x03; @@ -508,9 +508,9 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv) flags = enter_critical_section(); - for (bufndx = 0; bufndx < STM32H5_PMA_NBUFFERS; bufndx++) + for (bufndx = 0; bufndx < STM32_PMA_NBUFFERS; bufndx++) { - uint32_t bit = STM32H5_PMA_BUFFER_BIT(bufndx); + uint32_t bit = STM32_PMA_BUFFER_BIT(bufndx); if ((priv->pma_bufavail & bit) != 0) { priv->pma_bufavail &= ~bit; /* Mark allocated */ @@ -524,12 +524,12 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv) if (bufno >= 0) { uinfo("PMA buffer allocated: bufno=%d addr=0x%04x\n", - bufno, STM32H5_PMA_BUFNO2ADDR(bufno)); + bufno, STM32_PMA_BUFNO2ADDR(bufno)); } else { uerr("ERROR: PMA buffer allocation failed, all %d buffers in use\n", - STM32H5_PMA_NBUFFERS); + STM32_PMA_NBUFFERS); } return bufno; @@ -548,14 +548,14 @@ static void stm32_pma_free_buffer(struct stm32_usbhost_s *priv, { irqstate_t flags; - DEBUGASSERT(bufno < STM32H5_PMA_NBUFFERS); + DEBUGASSERT(bufno < STM32_PMA_NBUFFERS); flags = enter_critical_section(); - priv->pma_bufavail |= STM32H5_PMA_BUFFER_BIT(bufno); /* Mark available */ + priv->pma_bufavail |= STM32_PMA_BUFFER_BIT(bufno); /* Mark available */ leave_critical_section(flags); uinfo("PMA buffer freed: bufno=%d addr=0x%04x\n", - bufno, STM32H5_PMA_BUFNO2ADDR(bufno)); + bufno, STM32_PMA_BUFNO2ADDR(bufno)); } /**************************************************************************** @@ -570,7 +570,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv) { int chidx; - for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { if (!priv->chan[chidx].inuse) { @@ -582,7 +582,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv) priv->chan[chidx].inuse = true; priv->chan[chidx].pmabufno = (uint8_t)bufno; - priv->chan[chidx].pmaaddr = STM32H5_PMA_BUFNO2ADDR(bufno); + priv->chan[chidx].pmaaddr = STM32_PMA_BUFNO2ADDR(bufno); uinfo("Channel allocated: chidx=%d\n", chidx); return chidx; } @@ -604,18 +604,18 @@ static inline void stm32_chan_free(struct stm32_usbhost_s *priv, { struct stm32_chan_s *chan; - DEBUGASSERT((unsigned)chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); chan = &priv->chan[chidx]; /* Free PMA buffer if allocated */ - if (chan->pmabufno != STM32H5_PMA_BUFFER_NONE) + if (chan->pmabufno != STM32_PMA_BUFFER_NONE) { stm32_set_chep_rx_status(priv, chidx, USB_CHEP_RX_STRX_DIS); stm32_set_chep_tx_status(priv, chidx, USB_CHEP_TX_STTX_DIS); stm32_pma_free_buffer(priv, chan->pmabufno); - chan->pmabufno = STM32H5_PMA_BUFFER_NONE; + chan->pmabufno = STM32_PMA_BUFFER_NONE; chan->pmaaddr = 0; uinfo("Channel freed: chidx=%d\n", chidx); } @@ -639,7 +639,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv, /* Status changes work by toggling the DTOG bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx)) + regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx)) & USB_CHEP_TX_DTOGMASK; if (status & USB_CHEP_TX_DTOG1) { @@ -651,7 +651,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv, regval ^= USB_CHEP_TX_DTOG2; } - stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx), + stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -671,7 +671,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv, /* Status changes work by toggling the DTOG bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx)) + regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx)) & USB_CHEP_RX_DTOGMASK; if (status & USB_CHEP_RX_DTOG1) { @@ -683,7 +683,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv, regval ^= USB_CHEP_RX_DTOG2; } - stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx), + stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -701,7 +701,7 @@ static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) /* Free all host channels */ - for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { if (priv->chan[chidx].inuse) { @@ -748,7 +748,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv, /* Read current register value and mask toggleable bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CH_T_MASK; + regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CH_T_MASK; /* Set endpoint type */ @@ -772,7 +772,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv, /* Write the channel register with VT bits preserved */ - stm32_putreg(STM32H5_USB_CHEP(chidx), + stm32_putreg(STM32_USB_CHEP(chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -944,7 +944,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, chan->eptype = USB_EP_ATTR_XFER_CONTROL; chan->funcaddr = funcaddr; chan->speed = speed; - chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE; + chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -956,7 +956,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, chan->eptype = USB_EP_ATTR_XFER_CONTROL; chan->funcaddr = funcaddr; chan->speed = speed; - chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE; + chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1092,7 +1092,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, bdval |= (nblocks << USB_PMA_RXBD_NUM_BLOCK_SHIFT); } - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_RXBD_OFFSET(chidx)); *pbd = bdval; @@ -1104,7 +1104,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, /* Clear data toggle if starting new transfer */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + regval = stm32_getreg(STM32_USB_CHEP(chidx)); if ((regval & USB_CHEP_DTOG_RX) != 0) { if (!chan->indata1) @@ -1113,7 +1113,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } else @@ -1124,7 +1124,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } @@ -1146,7 +1146,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, bdval = chan->pmaaddr; /* chan->pmaaddr is already 4 byte aligned */ bdval |= ((uint32_t)len << USB_PMA_TXBD_COUNT_SHIFT); - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_TXBD_OFFSET(chidx)); *pbd = bdval; @@ -1154,8 +1154,8 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, if (chan->pid == HC_PID_SETUP) { - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CHEP_REG_MASK; - stm32_putreg(STM32H5_USB_CHEP(chidx), + regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CHEP_REG_MASK; + stm32_putreg(STM32_USB_CHEP(chidx), regval | USB_CHEP_SETUP | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -1164,7 +1164,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, * hardware auto-toggles after successful transmit) */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + regval = stm32_getreg(STM32_USB_CHEP(chidx)); if ((regval & USB_CHEP_DTOG_TX) != 0) { if (!chan->outdata1) @@ -1173,7 +1173,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } else @@ -1184,7 +1184,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } @@ -1460,13 +1460,13 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) { struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uint32_t rx_status = chepval & USB_CHEP_RX_STRX_MASK; bool wakeup = false; if ((chepval & USB_CHEP_ERRRX) != 0) { - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uerr("ERRRX chidx=%d chepval=0x%08x rx_status=%d nak=%d\n", chidx, (unsigned int)chepval, (int)((chepval & USB_CHEP_RX_STRX_MASK) >> @@ -1479,7 +1479,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK) & ~USB_CHEP_ERRRX) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); chan->result = EIO; chan->chreason = CHREASON_TXERR; @@ -1500,7 +1500,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) uint16_t count; bool transfer_complete; - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_RXBD_OFFSET(chidx)); count = (*pbd >> USB_PMA_RXBD_COUNT_SHIFT) & 0x3ff; @@ -1546,10 +1546,10 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) * (toggle bit, write 1 keeps, write 0 clears) */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); /* More data expected - reactivate channel for next packet */ @@ -1598,9 +1598,9 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) * (toggle bit, write 1 keeps, write 0 clears) */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); if (wakeup) { @@ -1620,7 +1620,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) { struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uint32_t tx_status = chepval & USB_CHEP_TX_STTX_MASK; bool wakeup = false; @@ -1630,10 +1630,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) * write 1 to VTRX/VTTX to preserve */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_ERRTX) | USB_CHEP_VTRX | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); chan->result = EIO; chan->chreason = CHREASON_TXERR; @@ -1699,10 +1699,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) if ((chepval & USB_CHEP_NAK) != 0) { - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_NAK) | USB_CHEP_VTRX | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); } if (!chan->waiter && !chan->callback) @@ -1728,9 +1728,9 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) /* Clear VTTX by writing 0 to it */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffffff7f & USB_CHEP_REG_MASK)) | USB_CHEP_VTRX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); if (wakeup) { @@ -2132,11 +2132,11 @@ static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /* A single channel is represent by an index in the range of 0 to - * STM32H5_NHOST_CHANNELS. Otherwise, the ep must be a pointer to + * STM32_NHOST_CHANNELS. Otherwise, the ep must be a pointer to * an allocated control endpoint structure. */ - if ((uintptr_t)ep < STM32H5_NHOST_CHANNELS) + if ((uintptr_t)ep < STM32_NHOST_CHANNELS) { /* Halt the channel and mark the channel available */ @@ -2275,7 +2275,7 @@ static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, return ret; } - for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send SETUP */ @@ -2351,7 +2351,7 @@ static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, return ret; } - for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send SETUP */ @@ -2409,7 +2409,7 @@ static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, ssize_t nbytes; int ret; - DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS); ret = nxmutex_lock(&priv->lock); if (ret < 0) @@ -2461,7 +2461,7 @@ static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, struct stm32_chan_s *chan; int ret; - DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS); ret = nxmutex_lock(&priv->lock); if (ret < 0) @@ -2499,7 +2499,7 @@ static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) struct stm32_chan_s *chan; irqstate_t flags; - DEBUGASSERT(priv && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && chidx < STM32_NHOST_CHANNELS); chan = &priv->chan[chidx]; @@ -2595,7 +2595,7 @@ static void stm32_portreset(struct stm32_usbhost_s *priv) /* Wait for reset */ - nxsched_usleep(STM32H5_RESET_DELAY * 1000); + nxsched_usleep(STM32_RESET_DELAY * 1000); /* Release reset */ @@ -2722,15 +2722,15 @@ static void stm32_sw_initialize(struct stm32_usbhost_s *priv) /* Initialize PMA allocation - all buffers available */ - priv->pma_bufavail = STM32H5_PMA_BUFFER_ALLSET; + priv->pma_bufavail = STM32_PMA_BUFFER_ALLSET; /* Initialize channels */ - for (i = 0; i < STM32H5_NHOST_CHANNELS; i++) + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { priv->chan[i].chidx = i; priv->chan[i].inuse = false; - priv->chan[i].pmabufno = STM32H5_PMA_BUFFER_NONE; + priv->chan[i].pmabufno = STM32_PMA_BUFFER_NONE; nxsem_init(&priv->chan[i].waitsem, 0, 0); } } diff --git a/arch/arm/src/stm32h5/stm32h563xx_flash.c b/arch/arm/src/stm32h5/stm32h563xx_flash.c index 3b2aebdcaff4d..199cc59b9d931 100644 --- a/arch/arm/src/stm32h5/stm32h563xx_flash.c +++ b/arch/arm/src/stm32h5/stm32h563xx_flash.c @@ -96,7 +96,7 @@ #elif defined(CONFIG_STM32H5_FLASH_CONFIG_B) # define H5_FLASH_BANK_NBLOCKS 8 #else -# warning "No valid STM32H5_FLASH_CONFIG_x defined." +# warning "No valid STM32_FLASH_CONFIG_x defined." #endif #define H5_FLASH_BANKSIZE (FLASH_BLOCK_SIZE * H5_FLASH_BANK_NBLOCKS) diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index 62f94162fbb88..87b12f55e920f 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -58,19 +58,19 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* HSE divisor to yield ~1MHz RTC clock */ -#define HSE_DIVISOR (STM32H5_HSE_FREQUENCY + 500000) / 1000000 +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32H5_USE_CLK48) -# if defined(STM32H5_CLKUSB_SEL) -# if (STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK) -# define STM32H5_USE_HSI48 1 +#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if defined(STM32_CLKUSB_SEL) +# if (STM32_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK) +# define STM32_USE_HSI48 1 # endif # endif -# if defined(STM32H5_CLKRNG_SEL) -# if (STM32H5_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK) -# define STM32H5_USE_HSI48 1 +# if defined(STM32_CLKRNG_SEL) +# if (STM32_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK) +# define STM32_USE_HSI48 1 # endif # endif #endif @@ -203,30 +203,30 @@ static inline void rcc_enableahb2(void) /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOIEN #endif @@ -419,8 +419,8 @@ static inline void rcc_enableapb1l(void) regval |= RCC_APB1LENR_I3C1EN; #endif -#ifdef STM32H5_USE_HSI48 - if (STM32H5_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Bit 24: CRS clock enable */ @@ -842,10 +842,10 @@ void stm32_rcc_enableperipherals(void) rcc_enableapb2(); rcc_enableapb3(); -#ifdef STM32H5_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32h5_enable_hsi48(STM32H5_HSI48_SYNCSRC); + stm32h5_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -1097,14 +1097,14 @@ void stm32_stdclockconfig(void) } #if defined(CONFIG_STM32H5_IWDG) || defined(CONFIG_STM32H5_RTC_LSICLOCK) || \ - defined(STM32H5_USE_LSCO_LSI) + defined(STM32_USE_LSCO_LSI) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(STM32_USE_LSE) || defined(STM32H5_USE_LSCO_LSE) +#if defined(STM32_USE_LSE) || defined(STM32_USE_LSCO_LSE) /* Low speed external clock source LSE */ stm32_rcc_enablelse(); @@ -1203,19 +1203,19 @@ void stm32_stdclockconfig(void) /* Configure USB source clock */ -#if defined(STM32H5_CLKUSB_SEL) +#if defined(STM32_CLKUSB_SEL) regval = getreg32(STM32_RCC_CCIPR4); regval &= ~RCC_CCIPR4_USBSEL_MASK; - regval |= STM32H5_CLKUSB_SEL; + regval |= STM32_CLKUSB_SEL; putreg32(regval, STM32_RCC_CCIPR4); #endif /* Configure RNG source clock */ -#if defined(STM32H5_CLKRNG_SEL) +#if defined(STM32_CLKRNG_SEL) regval = getreg32(STM32_RCC_CCIPR5); regval &= ~RCC_CCIPR5_RNGSEL_MASK; - regval |= STM32H5_CLKRNG_SEL; + regval |= STM32_CLKRNG_SEL; putreg32(regval, STM32_RCC_CCIPR5); #endif } diff --git a/arch/arm/src/stm32h7/hardware/stm32_qspi.h b/arch/arm/src/stm32h7/hardware/stm32_qspi.h index dcc4e882cdf55..a66957eac8941 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32H7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32H7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h index e052e88da4538..c38ff4666e26a 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h @@ -55,7 +55,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -68,7 +68,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -81,7 +81,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -94,7 +94,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -107,7 +107,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -120,7 +120,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -146,7 +146,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -159,7 +159,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -172,7 +172,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -185,7 +185,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h index bd2e35904070d..944b1f0ef2cd2 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h index 2e00669d7d456..fa7c71d92bfc4 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h @@ -62,7 +62,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) @@ -79,7 +79,7 @@ # define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) @@ -96,7 +96,7 @@ # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) @@ -113,7 +113,7 @@ # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) @@ -130,7 +130,7 @@ # define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) @@ -147,7 +147,7 @@ # define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h index e5785ef1c16eb..7bab6c142c4f5 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) @@ -74,7 +74,7 @@ # define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) @@ -90,7 +90,7 @@ # define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) @@ -106,7 +106,7 @@ # define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET) @@ -122,7 +122,7 @@ # define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) @@ -137,7 +137,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) @@ -152,7 +152,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET) @@ -167,7 +167,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index cec7d503b3ba2..3b64acba7943f 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -111,10 +111,10 @@ /* Set the start and end of the SRAMs */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) #elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32H7_CORTEXM4_ENABLED) @@ -122,7 +122,7 @@ /* Configuration for M7 core when M4 core support enabled */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) /* Exclude SRAM123 */ @@ -134,8 +134,8 @@ /* Configuration for M4 core support enabled */ # define SRAM_START STM32_SRAM123_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM123_SIZE - \ - STM32H7_SRAM3_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM123_SIZE - \ + STM32_SRAM3_SIZE) #endif #undef HAVE_SRAM4 @@ -143,7 +143,7 @@ # define HAVE_SRAM4 1 # define SRAM4_START ((uint32_t)(STM32_SRAM4_BASE)) -# define SRAM4_END ((uint32_t)(SRAM4_START + STM32H7_SRAM4_SIZE)) +# define SRAM4_END ((uint32_t)(SRAM4_START + STM32_SRAM4_SIZE)) # define SRAM4_HEAP_START ((uint32_t)_sram4_heap_start) #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c index a4666960d318f..8f27740c1aafb 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.c +++ b/arch/arm/src/stm32h7/stm32_bbsram.c @@ -151,7 +151,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32H7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -591,7 +591,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32H7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -688,7 +688,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) * after reset due to the ECC behavior. */ - avail = STM32H7_BBSRAM_SIZE; + avail = STM32_BBSRAM_SIZE; for (i = 0; (i < CONFIG_STM32H7_BBSRAM_FILES) && ent[i] && (avail > 0); i++) @@ -793,9 +793,9 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) */ # if defined(CONFIG_BUILD_PROTECTED) - mpu_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); # else - mpu_user_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_user_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); mpu_control(true, true, true); # endif #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.h b/arch/arm/src/stm32h7/stm32_bbsram.h index c9d41f73cc23f..08421e22571bf 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.h +++ b/arch/arm/src/stm32h7/stm32_bbsram.h @@ -46,17 +46,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32H7_BBSRAM_SIZE 4096 +#define STM32_BBSRAM_SIZE 4096 #if !defined(CONFIG_STM32H7_BBSRAM_FILES) # define CONFIG_STM32H7_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32H7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32H7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -126,7 +126,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: -* fileno - the value returned by the ioctl STM32H7_BBSRAM_GETDESC_IOCTL +* fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * diff --git a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c index 6bdf846cfb081..c1a1e71517d5f 100644 --- a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c @@ -47,35 +47,35 @@ /* 32-Bit Timers ************************************************************/ -#define STM32H7_TIM2_RES 32 -#define STM32H7_TIM5_RES 32 +#define STM32_TIM2_RES 32 +#define STM32_TIM5_RES 32 /* 16-Bit Timers ************************************************************/ /* Advanced-Control Timers */ -#define STM32H7_TIM1_RES 16 -#define STM32H7_TIM8_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM8_RES 16 /* General-Purpose Timers */ -#define STM32H7_TIM3_RES 16 -#define STM32H7_TIM4_RES 16 -#define STM32H7_TIM12_RES 16 -#define STM32H7_TIM13_RES 16 -#define STM32H7_TIM14_RES 16 -#define STM32H7_TIM15_RES 16 -#define STM32H7_TIM16_RES 16 -#define STM32H7_TIM17_RES 16 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM12_RES 16 +#define STM32_TIM13_RES 16 +#define STM32_TIM14_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /* Basic Timers */ -#define STM32H7_TIM6_RES 16 -#define STM32H7_TIM7_RES 16 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 /* Low-Power Timers */ -#define STM32H7_LPTIM1_RES 16 -#define STM32H7_LPTIM2_RES 16 -#define STM32H7_LPTIM3_RES 16 -#define STM32H7_LPTIM4_RES 16 -#define STM32H7_LPTIM5_RES 16 +#define STM32_LPTIM1_RES 16 +#define STM32_LPTIM2_RES 16 +#define STM32_LPTIM3_RES 16 +#define STM32_LPTIM4_RES 16 +#define STM32_LPTIM5_RES 16 /**************************************************************************** * Private Types @@ -129,7 +129,7 @@ static const struct cap_ops_s g_cap_ops = static struct stm32_lowerhalf_s g_cap1_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM1_RES, + .resolution = STM32_TIM1_RES, .channel = CONFIG_STM32H7_TIM1_CHANNEL, .clock = CONFIG_STM32H7_TIM1_CLOCK, }; @@ -139,7 +139,7 @@ static struct stm32_lowerhalf_s g_cap1_lowerhalf = static struct stm32_lowerhalf_s g_cap2_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM2_RES, + .resolution = STM32_TIM2_RES, .channel = CONFIG_STM32H7_TIM2_CHANNEL, .clock = CONFIG_STM32H7_TIM2_CLOCK, }; @@ -149,7 +149,7 @@ static struct stm32_lowerhalf_s g_cap2_lowerhalf = static struct stm32_lowerhalf_s g_cap3_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM3_RES, + .resolution = STM32_TIM3_RES, .channel = CONFIG_STM32H7_TIM3_CHANNEL, .clock = CONFIG_STM32H7_TIM3_CLOCK, }; @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_cap3_lowerhalf = static struct stm32_lowerhalf_s g_cap4_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM4_RES, + .resolution = STM32_TIM4_RES, .channel = CONFIG_STM32H7_TIM4_CHANNEL, .clock = CONFIG_STM32H7_TIM4_CLOCK, }; @@ -169,7 +169,7 @@ static struct stm32_lowerhalf_s g_cap4_lowerhalf = static struct stm32_lowerhalf_s g_cap5_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM5_RES, + .resolution = STM32_TIM5_RES, .channel = CONFIG_STM32H7_TIM5_CHANNEL, .clock = CONFIG_STM32H7_TIM5_CLOCK, }; @@ -179,7 +179,7 @@ static struct stm32_lowerhalf_s g_cap5_lowerhalf = static struct stm32_lowerhalf_s g_cap8_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM8_RES, + .resolution = STM32_TIM8_RES, .channel = CONFIG_STM32H7_TIM8_CHANNEL, .clock = CONFIG_STM32H7_TIM8_CLOCK, }; @@ -189,7 +189,7 @@ static struct stm32_lowerhalf_s g_cap8_lowerhalf = static struct stm32_lowerhalf_s g_cap12_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM12_RES, + .resolution = STM32_TIM12_RES, .channel = CONFIG_STM32H7_TIM12_CHANNEL, .clock = CONFIG_STM32H7_TIM12_CLOCK, }; @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_cap12_lowerhalf = static struct stm32_lowerhalf_s g_cap13_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM13_RES, + .resolution = STM32_TIM13_RES, .channel = CONFIG_STM32H7_TIM13_CHANNEL, .clock = CONFIG_STM32H7_TIM13_CLOCK, }; @@ -209,7 +209,7 @@ static struct stm32_lowerhalf_s g_cap13_lowerhalf = static struct stm32_lowerhalf_s g_cap14_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM14_RES, + .resolution = STM32_TIM14_RES, .channel = CONFIG_STM32H7_TIM14_CHANNEL, .clock = CONFIG_STM32H7_TIM14_CLOCK, }; @@ -219,7 +219,7 @@ static struct stm32_lowerhalf_s g_cap14_lowerhalf = static struct stm32_lowerhalf_s g_cap15_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM15_RES, + .resolution = STM32_TIM15_RES, .channel = CONFIG_STM32H7_TIM15_CHANNEL, .clock = CONFIG_STM32H7_TIM15_CLOCK, }; @@ -229,7 +229,7 @@ static struct stm32_lowerhalf_s g_cap15_lowerhalf = static struct stm32_lowerhalf_s g_cap16_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM16_RES, + .resolution = STM32_TIM16_RES, .channel = CONFIG_STM32H7_TIM16_CHANNEL, .clock = CONFIG_STM32H7_TIM16_CLOCK, }; @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_cap16_lowerhalf = static struct stm32_lowerhalf_s g_cap17_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM17_RES, + .resolution = STM32_TIM17_RES, .channel = CONFIG_STM32H7_TIM17_CHANNEL, .clock = CONFIG_STM32H7_TIM17_CLOCK, }; diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 2787c840596ba..9cd6b485b88b5 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -68,12 +68,12 @@ #include -/* STM32H7_NETHERNET determines the number of physical interfaces that can +/* STM32_NETHERNET determines the number of physical interfaces that can * be supported by the hardware. CONFIG_STM32H7_ETHMAC will defined if * any STM32H7 Ethernet support is enabled in the configuration. */ -#if STM32H7_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -81,7 +81,7 @@ /* Configuration ************************************************************/ -#if STM32H7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -105,59 +105,59 @@ #endif #if defined(CONFIG_ETH0_PHY_AM79C874) -# define STM32H7_PHYID1 MII_PHYID1_AM79C874 -# define STM32H7_PHYID2 MII_PHYID2_AM79C874 +# define STM32_PHYID1 MII_PHYID1_AM79C874 +# define STM32_PHYID2 MII_PHYID2_AM79C874 #elif defined(CONFIG_ETH0_PHY_AR8031) -# define STM32H7_PHYID1 MII_PHYID1_AR8031 -# define STM32H7_PHYID2 MII_PHYID2_AR8031 +# define STM32_PHYID1 MII_PHYID1_AR8031 +# define STM32_PHYID2 MII_PHYID2_AR8031 #elif defined(CONFIG_ETH0_PHY_KS8721) -# define STM32H7_PHYID1 MII_PHYID1_KS8721 -# define STM32H7_PHYID2 MII_PHYID2_KS8721 +# define STM32_PHYID1 MII_PHYID1_KS8721 +# define STM32_PHYID2 MII_PHYID2_KS8721 #elif defined(CONFIG_ETH0_PHY_KSZ8041) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8041 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8041 +# define STM32_PHYID1 MII_PHYID1_KSZ8041 +# define STM32_PHYID2 MII_PHYID2_KSZ8041 #elif defined(CONFIG_ETH0_PHY_KSZ8051) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8051 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8051 +# define STM32_PHYID1 MII_PHYID1_KSZ8051 +# define STM32_PHYID2 MII_PHYID2_KSZ8051 #elif defined(CONFIG_ETH0_PHY_KSZ8061) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8061 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8061 +# define STM32_PHYID1 MII_PHYID1_KSZ8061 +# define STM32_PHYID2 MII_PHYID2_KSZ8061 #elif defined(CONFIG_ETH0_PHY_KSZ8081) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8081 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8081 +# define STM32_PHYID1 MII_PHYID1_KSZ8081 +# define STM32_PHYID2 MII_PHYID2_KSZ8081 #elif defined(CONFIG_ETH0_PHY_DP83848C) -# define STM32H7_PHYID1 MII_PHYID1_DP83848C -# define STM32H7_PHYID2 MII_PHYID2_DP83848C +# define STM32_PHYID1 MII_PHYID1_DP83848C +# define STM32_PHYID2 MII_PHYID2_DP83848C #elif defined(CONFIG_ETH0_PHY_DP83825I) -# define STM32H7_PHYID1 MII_PHYID1_DP83825I -# define STM32H7_PHYID2 MII_PHYID2_DP83825I +# define STM32_PHYID1 MII_PHYID1_DP83825I +# define STM32_PHYID2 MII_PHYID2_DP83825I #elif defined(CONFIG_ETH0_PHY_TJA1100) -# define STM32H7_PHYID1 MII_PHYID1_TJA1100 -# define STM32H7_PHYID2 MII_PHYID2_TJA1100 +# define STM32_PHYID1 MII_PHYID1_TJA1100 +# define STM32_PHYID2 MII_PHYID2_TJA1100 #elif defined(CONFIG_ETH0_PHY_TJA1101) -# define STM32H7_PHYID1 MII_PHYID1_TJA1101 -# define STM32H7_PHYID2 MII_PHYID2_TJA1101 +# define STM32_PHYID1 MII_PHYID1_TJA1101 +# define STM32_PHYID2 MII_PHYID2_TJA1101 #elif defined(CONFIG_ETH0_PHY_TJA1103) -# define STM32H7_PHYID1 MII_PHYID1_TJA1103 -# define STM32H7_PHYID2 MII_PHYID2_TJA1103 +# define STM32_PHYID1 MII_PHYID1_TJA1103 +# define STM32_PHYID2 MII_PHYID2_TJA1103 #elif defined(CONFIG_ETH0_PHY_LAN8720) -# define STM32H7_PHYID1 MII_PHYID1_LAN8720 -# define STM32H7_PHYID2 MII_PHYID2_LAN8720 +# define STM32_PHYID1 MII_PHYID1_LAN8720 +# define STM32_PHYID2 MII_PHYID2_LAN8720 #elif defined(CONFIG_ETH0_PHY_LAN8740) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740 -# define STM32H7_PHYID2 MII_PHYID2_LAN8740 +# define STM32_PHYID1 MII_PHYID1_LAN8740 +# define STM32_PHYID2 MII_PHYID2_LAN8740 #elif defined(CONFIG_ETH0_PHY_LAN8740A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740A -# define STM32H7_PHYID2 MII_PHYID2_LAN8740A +# define STM32_PHYID1 MII_PHYID1_LAN8740A +# define STM32_PHYID2 MII_PHYID2_LAN8740A #elif defined(CONFIG_ETH0_PHY_LAN8742A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8742A -# define STM32H7_PHYID2 MII_PHYID2_LAN8742A +# define STM32_PHYID1 MII_PHYID1_LAN8742A +# define STM32_PHYID2 MII_PHYID2_LAN8742A #elif defined(CONFIG_ETH0_PHY_DM9161) -# define STM32H7_PHYID1 MII_PHYID1_DM9161 -# define STM32H7_PHYID2 MII_PHYID2_DM9161 +# define STM32_PHYID1 MII_PHYID1_DM9161 +# define STM32_PHYID2 MII_PHYID2_DM9161 #elif defined(CONFIG_ETH0_PHY_YT8512) -# define STM32H7_PHYID1 MII_PHYID1_YT8512 -# define STM32H7_PHYID2 MII_PHYID2_YT8512 +# define STM32_PHYID1 MII_PHYID1_YT8512 +# define STM32_PHYID2 MII_PHYID2_YT8512 #else # warning "No PHY specified!" #endif @@ -289,14 +289,14 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) #define RXBUFFER_SIZE (CONFIG_STM32H7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32H7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32H7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. @@ -723,7 +723,7 @@ aligned_data(ARMV7M_DCACHE_LINESIZE); /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32H7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -3279,10 +3279,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if (phyval != STM32H7_PHYID1) + if (phyval != STM32_PHYID1) { nerr("ERROR: Incorrect PHYID1: %u expected: %u\n", - phyval, STM32H7_PHYID1); + phyval, STM32_PHYID1); return -ENXIO; } @@ -3297,10 +3297,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if ((phyval & 0xfff0) != (STM32H7_PHYID2 & 0xfff0)) + if ((phyval & 0xfff0) != (STM32_PHYID2 & 0xfff0)) { nerr("ERROR: Incorrect PHYID2: %u expected: %u\n", - phyval, STM32H7_PHYID2); + phyval, STM32_PHYID2); return -ENXIO; } @@ -4120,7 +4120,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf) #else static inline int stm32_ethinitialize(int intf) @@ -4135,7 +4135,7 @@ static inline int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32H7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -4216,7 +4216,7 @@ static inline int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32H7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -4231,11 +4231,11 @@ static inline int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32H7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32H7_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ diff --git a/arch/arm/src/stm32h7/stm32_ethernet.h b/arch/arm/src/stm32h7/stm32_ethernet.h index 6f7026bacacad..8faf17694caca 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32H7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32H7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index 8f59ef8b8a8c9..8723b1d4b5f59 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -62,47 +62,47 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32H7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32H7_NGPIO > 5 +#if STM32_NGPIO > 5 # if defined(CONFIG_STM32H7_HAVE_GPIOF) STM32_GPIOF_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 6 +#if STM32_NGPIO > 6 # if defined(CONFIG_STM32H7_HAVE_GPIOG) STM32_GPIOG_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -163,7 +163,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32H7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -443,7 +443,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -485,7 +485,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.h b/arch/arm/src/stm32h7/stm32_gpio.h index 02a644c3290bf..ab46e15a4025b 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.h +++ b/arch/arm/src/stm32h7/stm32_gpio.h @@ -184,37 +184,37 @@ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ #define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) # define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) # define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */ #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define GPIO_PORTJ (9 << GPIO_PORT_SHIFT) /* GPIOJ */ #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define GPIO_PORTK (10 << GPIO_PORT_SHIFT) /* GPIOK */ #endif @@ -262,7 +262,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32H7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32h7/stm32_mpuinit.c b/arch/arm/src/stm32h7/stm32_mpuinit.c index 91d78295bb85c..625e7eb2a5f2b 100644 --- a/arch/arm/src/stm32h7/stm32_mpuinit.c +++ b/arch/arm/src/stm32h7/stm32_mpuinit.c @@ -46,7 +46,7 @@ #ifdef CONFIG_RPTUN # ifdef CONFIG_STM32H7_SHMEM_SRAM3 # define STM32_SHMEM_BASE STM32_SRAM3_BASE -# define STM32_SHMEM_SIZE STM32H7_SRAM3_SIZE +# define STM32_SHMEM_SIZE STM32_SRAM3_SIZE # else # error missing shmem MPU configuration # endif diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h index 131be78c428de..43208d091f94f 100644 --- a/arch/arm/src/stm32h7/stm32_otg.h +++ b/arch/arm/src/stm32h7/stm32_otg.h @@ -42,7 +42,7 @@ #if (STM32_RCC_D2CCIP2R_USBSRC == RCC_D2CCIP2R_USBSEL_HSI48) && \ !defined(CONFIG_STM32H7_HSI48) # error board.h selected HSI48 as USB clock source, but HSI48 is not \ - enabled. Enable STM32H7_HSI48 + enabled. Enable STM32_HSI48 #endif #if defined(CONFIG_STM32H7_OTGHS) && !defined(CONFIG_STM32H7_OTGHS_FS) && \ diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 414e6c5dbdda7..cfddcb3be49fa 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -135,9 +135,9 @@ # warning "Large Non-DMA transfer may result in RX overrun failures" #elif defined(CONFIG_STM32H7_SDMMC1) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) # define SRAM4_START STM32_SRAM4_BASE -# define SRAM4_END (SRAM4_START + STM32H7_SRAM4_SIZE) +# define SRAM4_END (SRAM4_START + STM32_SRAM4_SIZE) #endif #if !defined(CONFIG_SCHED_WORKQUEUE) || !defined(CONFIG_SCHED_HPWORK) diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index 7860667a24507..e7442fe452ce0 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -65,7 +65,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32H7_NUSART + STM32H7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -1952,7 +1952,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3761,7 +3761,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; diff --git a/arch/arm/src/stm32h7/stm32_uart.h b/arch/arm/src/stm32h7/stm32_uart.h index 92234cb4c4556..ea17110980506 100644 --- a/arch/arm/src/stm32h7/stm32_uart.h +++ b/arch/arm/src/stm32h7/stm32_uart.h @@ -40,29 +40,29 @@ * device. */ -#if STM32H7_NUART < 4 +#if STM32_NUART < 4 # undef CONFIG_STM32H7_UART8 #endif -#if STM32H7_NUART < 3 +#if STM32_NUART < 3 # undef CONFIG_STM32H7_UART7 #endif -#if STM32H7_NUART < 2 +#if STM32_NUART < 2 # undef CONFIG_STM32H7_UART5 #endif -#if STM32H7_NUART < 1 +#if STM32_NUART < 1 # undef CONFIG_STM32H7_UART4 #endif -#if STM32H7_NUSART < 4 +#if STM32_NUSART < 4 # undef CONFIG_STM32H7_USART6 #endif -#if STM32H7_NUSART < 3 +#if STM32_NUSART < 3 # undef CONFIG_STM32H7_USART3 #endif -#if STM32H7_NUSART < 2 +#if STM32_NUSART < 2 # undef CONFIG_STM32H7_USART2 #endif -#if STM32H7_NUSART < 1 +#if STM32_NUSART < 1 # undef CONFIG_STM32H7_USART1 #endif diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index a1ce272975bf0..5fb2cae9f9489 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -408,36 +408,36 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 2a03208623676..481183e8ea5f0 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -383,36 +383,36 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32l4/chip.h b/arch/arm/src/stm32l4/chip.h index fb3a0d2202743..b1b27fca0dc7c 100644 --- a/arch/arm/src/stm32l4/chip.h +++ b/arch/arm/src/stm32l4/chip.h @@ -49,7 +49,7 @@ * arch/stm32l4/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32L4_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32L4 */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h index c78b9f598df27..f030bc56d9832 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h @@ -41,136 +41,136 @@ * offset 0x0100 for slave. */ -#define STM32L4_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ -#define STM32L4_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ -#define STM32L4_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32L4_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ -#define STM32L4_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ -#define STM32L4_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ -#define STM32L4_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ -#define STM32L4_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ -#define STM32L4_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ -#define STM32L4_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ -#define STM32L4_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ -#define STM32L4_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ -#define STM32L4_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ -#define STM32L4_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ -#define STM32L4_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ -#define STM32L4_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ -#define STM32L4_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ -#define STM32L4_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ -#define STM32L4_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ -#define STM32L4_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */ -#define STM32L4_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ -#define STM32L4_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ -#define STM32L4_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ -#define STM32L4_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ -#define STM32L4_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ -#define STM32L4_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ -#define STM32L4_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ -#define STM32L4_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ +#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ +#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ +#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ +#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ +#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ +#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ +#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ +#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ +#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ +#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ +#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ +#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ +#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ +#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ +#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ +#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ +#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ +#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ +#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ +#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */ +#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ +#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ +#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ +#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ +#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ +#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ +#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ +#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ /* Master and Slave ADC Common Registers */ -#define STM32L4_ADC_CSR_OFFSET 0x0000 /* Common status register */ -#define STM32L4_ADC_CCR_OFFSET 0x0008 /* Common control register */ +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ +# define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ #endif /* Register Addresses *******************************************************/ -#define STM32L4_ADC1_ISR (STM32L4_ADC1_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC1_IER (STM32L4_ADC1_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC1_CR (STM32L4_ADC1_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC1_CFGR (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC1_CFGR2 (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC1_SMPR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC1_SMPR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC1_TR1 (STM32L4_ADC1_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC1_TR2 (STM32L4_ADC1_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC1_TR3 (STM32L4_ADC1_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC1_SQR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC1_SQR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC1_SQR3 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC1_SQR4 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC1_DR (STM32L4_ADC1_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC1_JSQR (STM32L4_ADC1_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC1_OFR1 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC1_OFR2 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC1_OFR3 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC1_OFR4 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC1_JDR1 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC1_JDR2 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC1_JDR3 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC1_JDR4 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC1_AWD2CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC1_AWD3CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC1_DIFSEL (STM32L4_ADC1_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC1_CALFACT (STM32L4_ADC1_BASE+STM32L4_ADC_CALFACT_OFFSET) - -#define STM32L4_ADC2_ISR (STM32L4_ADC2_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC2_IER (STM32L4_ADC2_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC2_CR (STM32L4_ADC2_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC2_CFGR (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC2_CFGR2 (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC2_SMPR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC2_SMPR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC2_TR1 (STM32L4_ADC2_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC2_TR2 (STM32L4_ADC2_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC2_TR3 (STM32L4_ADC2_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC2_SQR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC2_SQR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC2_SQR3 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC2_SQR4 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC2_DR (STM32L4_ADC2_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC2_JSQR (STM32L4_ADC2_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC2_OFR1 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC2_OFR2 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC2_OFR3 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC2_OFR4 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC2_JDR1 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC2_JDR2 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC2_JDR3 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC2_JDR4 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC2_AWD2CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC2_AWD3CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC2_DIFSEL (STM32L4_ADC2_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC2_CALFACT (STM32L4_ADC2_BASE+STM32L4_ADC_CALFACT_OFFSET) - -#define STM32L4_ADC3_ISR (STM32L4_ADC3_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC3_IER (STM32L4_ADC3_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC3_CR (STM32L4_ADC3_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC3_CFGR (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC3_CFGR2 (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC3_SMPR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC3_SMPR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC3_TR1 (STM32L4_ADC3_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC3_TR2 (STM32L4_ADC3_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC3_TR3 (STM32L4_ADC3_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC3_SQR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC3_SQR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC3_SQR3 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC3_SQR4 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC3_DR (STM32L4_ADC3_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC3_JSQR (STM32L4_ADC3_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC3_OFR1 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC3_OFR2 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC3_OFR3 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC3_OFR4 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC3_JDR1 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC3_JDR2 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC3_JDR3 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC3_JDR4 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC3_AWD2CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC3_AWD3CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC3_DIFSEL (STM32L4_ADC3_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC3_CALFACT (STM32L4_ADC3_BASE+STM32L4_ADC_CALFACT_OFFSET) - -#define STM32L4_ADC_CSR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CSR_OFFSET) -#define STM32L4_ADC_CCR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CCR_OFFSET) +#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET) + +#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC2_CFGR2 (STM32_ADC2_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET) + +#define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC3_CFGR (STM32_ADC3_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC3_CFGR2 (STM32_ADC3_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET) + +#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) +#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_ADC_CDR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CDR_OFFSET) +# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -286,10 +286,12 @@ # define ADC_CFGR2_OVSR_64X (5 << ADC_CFGR2_OVSR_SHIFT) /* 64X oversampling */ # define ADC_CFGR2_OVSR_128X (6 << ADC_CFGR2_OVSR_SHIFT) /* 128X oversampling */ # define ADC_CFGR2_OVSR_256X (7 << ADC_CFGR2_OVSR_SHIFT) /* 256X oversampling */ + #define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */ #define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT) # define ADC_CFGR2_OVSS(value) ((value) << ADC_CFGR2_OVSS_SHIFT) - /* Value = 0..8 */ + /* Value = 0..8 */ + #define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered Regular Oversampling */ #define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular Oversampling mode */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_can.h b/arch/arm/src/stm32l4/hardware/stm32l4_can.h index ac0338cd867f9..5804564e8e289 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_can.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_can.h @@ -54,61 +54,61 @@ /* CAN control and status registers */ -#define STM32L4_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ -#define STM32L4_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ -#define STM32L4_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ -#define STM32L4_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) -#define STM32L4_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ -#define STM32L4_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ -#define STM32L4_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ -#define STM32L4_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ -#define STM32L4_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ +#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ +#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ +#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ +#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) +#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ +#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ +#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ +#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ +#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ /* CAN mailbox registers (3 TX and 2 RX) */ -#define STM32L4_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) -#define STM32L4_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ -#define STM32L4_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ -#define STM32L4_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ +#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) +#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ +#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ +#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ -#define STM32L4_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) -#define STM32L4_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ -#define STM32L4_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ -#define STM32L4_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ +#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) +#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ +#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ +#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ -#define STM32L4_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) -#define STM32L4_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ -#define STM32L4_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ -#define STM32L4_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ +#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) +#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ +#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ +#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ -#define STM32L4_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) -#define STM32L4_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ -#define STM32L4_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ -#define STM32L4_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ +#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) +#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ +#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ +#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ -#define STM32L4_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) -#define STM32L4_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ -#define STM32L4_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ +#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) +#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ +#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ -#define STM32L4_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) -#define STM32L4_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ -#define STM32L4_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ +#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) +#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ +#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ -#define STM32L4_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) -#define STM32L4_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ -#define STM32L4_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ +#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) +#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ +#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ -#define STM32L4_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) -#define STM32L4_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ -#define STM32L4_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ +#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) +#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ +#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ /* CAN filter registers */ -#define STM32L4_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ -#define STM32L4_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ -#define STM32L4_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ -#define STM32L4_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ -#define STM32L4_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ +#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ +#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ +#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ +#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ +#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ /* There are 14 filter banks on the device. Each filter bank is * composed of two 32-bit registers, CAN_FiR: @@ -119,63 +119,63 @@ * ... */ -#define STM32L4_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) +#define STM32_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) /* Register Addresses *******************************************************/ -#if STM32L4_NCAN > 0 -# define STM32L4_CAN1_MCR (STM32L4_CAN1_BASE+STM32L4_CAN_MCR_OFFSET) -# define STM32L4_CAN1_MSR (STM32L4_CAN1_BASE+STM32L4_CAN_MSR_OFFSET) -# define STM32L4_CAN1_TSR (STM32L4_CAN1_BASE+STM32L4_CAN_TSR_OFFSET) -# define STM32L4_CAN1_RFR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RFR_OFFSET(m)) -# define STM32L4_CAN1_RF0R (STM32L4_CAN1_BASE+STM32L4_CAN_RF0R_OFFSET) -# define STM32L4_CAN1_RF1R (STM32L4_CAN1_BASE+STM32L4_CAN_RF1R_OFFSET) -# define STM32L4_CAN1_IER (STM32L4_CAN1_BASE+STM32L4_CAN_IER_OFFSET) -# define STM32L4_CAN1_ESR (STM32L4_CAN1_BASE+STM32L4_CAN_ESR_OFFSET) -# define STM32L4_CAN1_BTR (STM32L4_CAN1_BASE+STM32L4_CAN_BTR_OFFSET) - -# define STM32L4_CAN1_TIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TIR_OFFSET(m)) -# define STM32L4_CAN1_TI0R (STM32L4_CAN1_BASE+STM32L4_CAN_TI0R_OFFSET) -# define STM32L4_CAN1_TI1R (STM32L4_CAN1_BASE+STM32L4_CAN_TI1R_OFFSET) -# define STM32L4_CAN1_TI2R (STM32L4_CAN1_BASE+STM32L4_CAN_TI2R_OFFSET) - -# define STM32L4_CAN1_TDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDTR_OFFSET(m)) -# define STM32L4_CAN1_TDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT0R_OFFSET) -# define STM32L4_CAN1_TDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT1R_OFFSET) -# define STM32L4_CAN1_TDT2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT2R_OFFSET) - -# define STM32L4_CAN1_TDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDLR_OFFSET(m)) -# define STM32L4_CAN1_TDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL0R_OFFSET) -# define STM32L4_CAN1_TDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL1R_OFFSET) -# define STM32L4_CAN1_TDL2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL2R_OFFSET) - -# define STM32L4_CAN1_TDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDHR_OFFSET(m)) -# define STM32L4_CAN1_TDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH0R_OFFSET) -# define STM32L4_CAN1_TDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH1R_OFFSET) -# define STM32L4_CAN1_TDH2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH2R_OFFSET) - -# define STM32L4_CAN1_RIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RIR_OFFSET(m)) -# define STM32L4_CAN1_RI0R (STM32L4_CAN1_BASE+STM32L4_CAN_RI0R_OFFSET) -# define STM32L4_CAN1_RI1R (STM32L4_CAN1_BASE+STM32L4_CAN_RI1R_OFFSET) - -# define STM32L4_CAN1_RDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDTR_OFFSET(m)) -# define STM32L4_CAN1_RDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT0R_OFFSET) -# define STM32L4_CAN1_RDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT1R_OFFSET) - -# define STM32L4_CAN1_RDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDLR_OFFSET(m)) -# define STM32L4_CAN1_RDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL0R_OFFSET) -# define STM32L4_CAN1_RDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL1R_OFFSET) - -# define STM32L4_CAN1_RDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDHR_OFFSET(m)) -# define STM32L4_CAN1_RDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH0R_OFFSET) -# define STM32L4_CAN1_RDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH1R_OFFSET) - -# define STM32L4_CAN1_FMR (STM32L4_CAN1_BASE+STM32L4_CAN_FMR_OFFSET) -# define STM32L4_CAN1_FM1R (STM32L4_CAN1_BASE+STM32L4_CAN_FM1R_OFFSET) -# define STM32L4_CAN1_FS1R (STM32L4_CAN1_BASE+STM32L4_CAN_FS1R_OFFSET) -# define STM32L4_CAN1_FFA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FFA1R_OFFSET) -# define STM32L4_CAN1_FA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FA1R_OFFSET) -# define STM32L4_CAN1_FIR(b,i) (STM32L4_CAN1_BASE+STM32L4_CAN_FIR_OFFSET(b,i)) +#if STM32_NCAN > 0 +# define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) +# define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) +# define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) +# define STM32_CAN1_RFR(m) (STM32_CAN1_BASE+STM32_CAN_RFR_OFFSET(m)) +# define STM32_CAN1_RF0R (STM32_CAN1_BASE+STM32_CAN_RF0R_OFFSET) +# define STM32_CAN1_RF1R (STM32_CAN1_BASE+STM32_CAN_RF1R_OFFSET) +# define STM32_CAN1_IER (STM32_CAN1_BASE+STM32_CAN_IER_OFFSET) +# define STM32_CAN1_ESR (STM32_CAN1_BASE+STM32_CAN_ESR_OFFSET) +# define STM32_CAN1_BTR (STM32_CAN1_BASE+STM32_CAN_BTR_OFFSET) + +# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE+STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN1_TI0R (STM32_CAN1_BASE+STM32_CAN_TI0R_OFFSET) +# define STM32_CAN1_TI1R (STM32_CAN1_BASE+STM32_CAN_TI1R_OFFSET) +# define STM32_CAN1_TI2R (STM32_CAN1_BASE+STM32_CAN_TI2R_OFFSET) + +# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE+STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN1_TDT0R (STM32_CAN1_BASE+STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN1_TDT1R (STM32_CAN1_BASE+STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN1_TDT2R (STM32_CAN1_BASE+STM32_CAN_TDT2R_OFFSET) + +# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE+STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN1_TDL0R (STM32_CAN1_BASE+STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN1_TDL1R (STM32_CAN1_BASE+STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN1_TDL2R (STM32_CAN1_BASE+STM32_CAN_TDL2R_OFFSET) + +# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE+STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN1_TDH0R (STM32_CAN1_BASE+STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN1_TDH1R (STM32_CAN1_BASE+STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN1_TDH2R (STM32_CAN1_BASE+STM32_CAN_TDH2R_OFFSET) + +# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE+STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN1_RI0R (STM32_CAN1_BASE+STM32_CAN_RI0R_OFFSET) +# define STM32_CAN1_RI1R (STM32_CAN1_BASE+STM32_CAN_RI1R_OFFSET) + +# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE+STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN1_RDT0R (STM32_CAN1_BASE+STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN1_RDT1R (STM32_CAN1_BASE+STM32_CAN_RDT1R_OFFSET) + +# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE+STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN1_RDL0R (STM32_CAN1_BASE+STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN1_RDL1R (STM32_CAN1_BASE+STM32_CAN_RDL1R_OFFSET) + +# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE+STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN1_RDH0R (STM32_CAN1_BASE+STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN1_RDH1R (STM32_CAN1_BASE+STM32_CAN_RDH1R_OFFSET) + +# define STM32_CAN1_FMR (STM32_CAN1_BASE+STM32_CAN_FMR_OFFSET) +# define STM32_CAN1_FM1R (STM32_CAN1_BASE+STM32_CAN_FM1R_OFFSET) +# define STM32_CAN1_FS1R (STM32_CAN1_BASE+STM32_CAN_FS1R_OFFSET) +# define STM32_CAN1_FFA1R (STM32_CAN1_BASE+STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN1_FA1R (STM32_CAN1_BASE+STM32_CAN_FA1R_OFFSET) +# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h index 4c9694ab78d14..350f0ab77f7de 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h @@ -29,15 +29,15 @@ /* Register Offsets *********************************************************/ -#define STM32L4_COMP_CSR_OFFSET(n) (((n)-1) << 2) -#define STM32L4_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */ -#define STM32L4_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */ +#define STM32_COMP_CSR_OFFSET(n) (((n)-1) << 2) +#define STM32_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */ +#define STM32_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */ /* Register Addresses *******************************************************/ -#define STM32L4_COMP_CSR(n) (STM32L4_COMP_BASE+STM32L4_COMP_CSR_OFFSET(n)) -#define STM32L4_COMP1_CSR (STM32L4_COMP_BASE+STM32L4_COMP1_CSR_OFFSET) -#define STM32L4_COMP2_CSR (STM32L4_COMP_BASE+STM32L4_COMP2_CSR_OFFSET) +#define STM32_COMP_CSR(n) (STM32_COMP_BASE+STM32_COMP_CSR_OFFSET(n)) +#define STM32_COMP1_CSR (STM32_COMP_BASE+STM32_COMP1_CSR_OFFSET) +#define STM32_COMP2_CSR (STM32_COMP_BASE+STM32_COMP2_CSR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -109,7 +109,9 @@ # define COMP_CSR_INMESEL_PIN4 (2 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 4: COMP1=PA4; COMP2=PA4 */ # define COMP_CSR_INMESEL_PIN5 (3 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 5: COMP1=PA5; COMP2=PA5 */ #endif - /* Bits 27-29: Reserved */ + +/* Bits 27-29: Reserved */ + #define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status bit */ #define COMP_CSR_LOCK_MASK (1 << 31) /* Bit 31: CSR register lock bit */ # define COMP_CSR_LOCK_RW (0) diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h index 5ff70d77eaabc..c282c4d4ecfea 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h @@ -29,17 +29,17 @@ /* Register Offsets *********************************************************/ -#define STM32L4_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32L4_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32L4_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32L4_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ /* Register Addresses *******************************************************/ -#define STM32L4_CRS_CR (STM32L4_CRS_BASE + STM32L4_CRS_CR_OFFSET) -#define STM32L4_CRS_CFGR (STM32L4_CRS_BASE + STM32L4_CRS_CFGR_OFFSET) -#define STM32L4_CRS_ISR (STM32L4_CRS_BASE + STM32L4_CRS_ISR_OFFSET) -#define STM32L4_CRS_ICR (STM32L4_CRS_BASE + STM32L4_CRS_ICR_OFFSET) +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h index d8d613212dae1..5d72eeb08bd01 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h @@ -36,51 +36,51 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DAC_CR_OFFSET 0x0000 /* DAC control register */ -#define STM32L4_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32L4_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ -#define STM32L4_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ -#define STM32L4_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32L4_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ -#define STM32L4_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ -#define STM32L4_DAC_SR_OFFSET 0x0034 /* DAC status register */ +#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ +#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ +#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ /* New registers not in STM32L1: */ -#define STM32L4_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ -#define STM32L4_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ -#define STM32L4_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */ -#define STM32L4_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */ -#define STM32L4_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */ -#define STM32L4_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */ +#define STM32_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ +#define STM32_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ +#define STM32_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */ +#define STM32_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */ +#define STM32_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */ +#define STM32_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */ /* Register Addresses *******************************************************/ -#define STM32L4_DAC_CR (STM32L4_DAC_BASE+STM32L4_DAC_CR_OFFSET) -#define STM32L4_DAC_SWTRIGR (STM32L4_DAC_BASE+STM32L4_DAC_SWTRIGR_OFFSET) -#define STM32L4_DAC_DHR12R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R1_OFFSET) -#define STM32L4_DAC_DHR12L1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L1_OFFSET) -#define STM32L4_DAC_DHR8R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R1_OFFSET) -#define STM32L4_DAC_DHR12R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R2_OFFSET) -#define STM32L4_DAC_DHR12L2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L2_OFFSET) -#define STM32L4_DAC_DHR8R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R2_OFFSET) -#define STM32L4_DAC_DHR12RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12RD_OFFSET) -#define STM32L4_DAC_DHR12LD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12LD_OFFSET) -#define STM32L4_DAC_DHR8RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR8RD_OFFSET) -#define STM32L4_DAC_DOR1 (STM32L4_DAC_BASE+STM32L4_DAC_DOR1_OFFSET) -#define STM32L4_DAC_DOR2 (STM32L4_DAC_BASE+STM32L4_DAC_DOR2_OFFSET) -#define STM32L4_DAC_SR (STM32L4_DAC_BASE+STM32L4_DAC_SR_OFFSET) -#define STM32L4_DAC_CCR (STM32L4_DAC_BASE+STM32L4_DAC_CCR_OFFSET) -#define STM32L4_DAC_MCR (STM32L4_DAC_BASE+STM32L4_DAC_MCR_OFFSET) -#define STM32L4_DAC_SHSR1 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR1_OFFSET) -#define STM32L4_DAC_SHSR2 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR2_OFFSET) -#define STM32L4_DAC_SHHR (STM32L4_DAC_BASE+STM32L4_DAC_SHHR_OFFSET) -#define STM32L4_DAC_SHRR (STM32L4_DAC_BASE+STM32L4_DAC_SHRR_OFFSET) +#define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET) +#define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET) +#define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET) +#define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET) +#define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET) +#define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET) +#define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET) +#define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET) +#define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET) +#define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET) +#define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET) +#define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET) +#define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET) +#define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET) +#define STM32_DAC_CCR (STM32_DAC_BASE+STM32_DAC_CCR_OFFSET) +#define STM32_DAC_MCR (STM32_DAC_BASE+STM32_DAC_MCR_OFFSET) +#define STM32_DAC_SHSR1 (STM32_DAC_BASE+STM32_DAC_SHSR1_OFFSET) +#define STM32_DAC_SHSR2 (STM32_DAC_BASE+STM32_DAC_SHSR2_OFFSET) +#define STM32_DAC_SHHR (STM32_DAC_BASE+STM32_DAC_SHHR_OFFSET) +#define STM32_DAC_SHRR (STM32_DAC_BASE+STM32_DAC_SHRR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h index 85546d55bc89a..eaa9eae902413 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h @@ -41,134 +41,134 @@ /* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */ -#define STM32L4_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y)) +#define STM32_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y)) -#define STM32L4_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */ -#define STM32L4_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */ -#define STM32L4_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */ -#define STM32L4_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */ +#define STM32_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */ +#define STM32_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */ +#define STM32_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */ +#define STM32_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */ -# define STM32L4_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */ -# define STM32L4_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */ -# define STM32L4_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */ +# define STM32_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */ +# define STM32_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */ +# define STM32_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */ +# define STM32_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */ #endif -#define STM32L4_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y)) +#define STM32_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y)) -#define STM32L4_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */ -#define STM32L4_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */ -#define STM32L4_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */ -#define STM32L4_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */ +#define STM32_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */ +#define STM32_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */ +#define STM32_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */ +#define STM32_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */ -# define STM32L4_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */ -# define STM32L4_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */ -# define STM32L4_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */ +# define STM32_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */ +# define STM32_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */ +# define STM32_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */ +# define STM32_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */ #endif -#define STM32L4_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y)) +#define STM32_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y)) -#define STM32L4_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */ #endif -#define STM32L4_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y)) +#define STM32_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y)) -#define STM32L4_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */ -#define STM32L4_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */ -#define STM32L4_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */ -#define STM32L4_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */ +#define STM32_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */ +#define STM32_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */ +#define STM32_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */ +#define STM32_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */ -# define STM32L4_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */ -# define STM32L4_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */ -# define STM32L4_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */ +# define STM32_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */ +# define STM32_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */ +# define STM32_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */ +# define STM32_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */ #endif -#define STM32L4_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */ +#define STM32_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */ -#define STM32L4_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */ -#define STM32L4_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */ -#define STM32L4_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */ -#define STM32L4_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */ +#define STM32_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */ +#define STM32_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */ +#define STM32_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */ +#define STM32_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */ -# define STM32L4_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */ -# define STM32L4_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */ -# define STM32L4_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */ +# define STM32_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */ +# define STM32_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */ +# define STM32_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */ +# define STM32_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */ #endif #ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */ - -# define STM32L4_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */ -# define STM32L4_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */ -# define STM32L4_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */ -# define STM32L4_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */ -# define STM32L4_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */ -# define STM32L4_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */ -# define STM32L4_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */ -# define STM32L4_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */ +# define STM32_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */ + +# define STM32_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */ +# define STM32_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */ +# define STM32_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */ +# define STM32_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */ +# define STM32_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */ +# define STM32_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */ +# define STM32_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */ +# define STM32_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */ #endif /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ -#define STM32L4_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */ -#define STM32L4_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */ -#define STM32L4_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */ -#define STM32L4_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */ -#define STM32L4_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */ -#define STM32L4_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */ -#define STM32L4_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */ -#define STM32L4_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */ -#define STM32L4_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */ -#define STM32L4_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */ -#define STM32L4_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */ -#define STM32L4_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */ -#define STM32L4_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */ -#define STM32L4_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */ -#define STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */ +#define STM32_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */ +#define STM32_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */ +#define STM32_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */ +#define STM32_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */ +#define STM32_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */ +#define STM32_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */ +#define STM32_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */ +#define STM32_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */ +#define STM32_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */ +#define STM32_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */ +#define STM32_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */ +#define STM32_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */ +#define STM32_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */ +#define STM32_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */ +#define STM32_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */ /* Register Addresses *******************************************************/ /* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */ -#define STM32L4_DFSDM_CHCFGR1(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR1_OFFSET(y)) -#define STM32L4_DFSDM_CH0CFGR1 (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CH0CFGR1_OFFSET) +#define STM32_DFSDM_CHCFGR1(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR1_OFFSET(y)) +#define STM32_DFSDM_CH0CFGR1 (STM32_DFSDM_BASE + STM32_DFSDM_CH0CFGR1_OFFSET) -#define STM32L4_DFSDM_CHCFGR2(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR2_OFFSET(y)) -#define STM32L4_DFSDM_CHAWSCDR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHAWSCDR_OFFSET(y)) -#define STM32L4_DFSDM_CHWDATR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHWDATR_OFFSET(y) -#define STM32L4_DFSDM_CHDATINR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDATINR_OFFSET(y)) +#define STM32_DFSDM_CHCFGR2(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR2_OFFSET(y)) +#define STM32_DFSDM_CHAWSCDR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHAWSCDR_OFFSET(y)) +#define STM32_DFSDM_CHWDATR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHWDATR_OFFSET(y) +#define STM32_DFSDM_CHDATINR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDATINR_OFFSET(y)) #ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_DFSDM_CHDLYR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDLYR_OFFSET(y)) +# define STM32_DFSDM_CHDLYR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDLYR_OFFSET(y)) #endif /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ -#define STM32L4_DFSDM_FLTCR1(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR1_OFFSET(x)) -#define STM32L4_DFSDM_FLTCR2(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR2_OFFSET(x)) -#define STM32L4_DFSDM_FLTISR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTISR_OFFSET(x)) -#define STM32L4_DFSDM_FLTICR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTICR_OFFSET(x)) -#define STM32L4_DFSDM_FLTJCHGR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJCHGR_OFFSET(x)) -#define STM32L4_DFSDM_FLTFCR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTFCR_OFFSET(x)) -#define STM32L4_DFSDM_FLTJDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJDATAR_OFFSET(x)) -#define STM32L4_DFSDM_FLTRDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTRDATAR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWHTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWHTR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWLTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWLTR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWSR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWSR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWCFR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWCFR_OFFSET(x)) -#define STM32L4_DFSDM_FLTEXMAX(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMAX_OFFSET(x)) -#define STM32L4_DFSDM_FLTEXMIN(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMIN_OFFSET(x)) -#define STM32L4_DFSDM_FLTCNVTIMR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x)) +#define STM32_DFSDM_FLTCR1(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR1_OFFSET(x)) +#define STM32_DFSDM_FLTCR2(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR2_OFFSET(x)) +#define STM32_DFSDM_FLTISR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTISR_OFFSET(x)) +#define STM32_DFSDM_FLTICR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTICR_OFFSET(x)) +#define STM32_DFSDM_FLTJCHGR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJCHGR_OFFSET(x)) +#define STM32_DFSDM_FLTFCR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTFCR_OFFSET(x)) +#define STM32_DFSDM_FLTJDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJDATAR_OFFSET(x)) +#define STM32_DFSDM_FLTRDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTRDATAR_OFFSET(x)) +#define STM32_DFSDM_FLTAWHTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWHTR_OFFSET(x)) +#define STM32_DFSDM_FLTAWLTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWLTR_OFFSET(x)) +#define STM32_DFSDM_FLTAWSR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWSR_OFFSET(x)) +#define STM32_DFSDM_FLTAWCFR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWCFR_OFFSET(x)) +#define STM32_DFSDM_FLTEXMAX(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMAX_OFFSET(x)) +#define STM32_DFSDM_FLTEXMIN(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMIN_OFFSET(x)) +#define STM32_DFSDM_FLTCNVTIMR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCNVTIMR_OFFSET(x)) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_exti.h b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h index f6295dc9c42fd..d10f7364f16d5 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h @@ -34,44 +34,44 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_NEXTI1 31 -#define STM32L4_EXTI1_MASK 0xffffffff -#define STM32L4_NEXTI2 9 -#define STM32L4_EXTI2_MASK 0x000001ff +#define STM32_NEXTI1 31 +#define STM32_EXTI1_MASK 0xffffffff +#define STM32_NEXTI2 9 +#define STM32_EXTI2_MASK 0x000001ff -#define STM32L4_EXTI1_BIT(n) (1 << (n)) -#define STM32L4_EXTI2_BIT(n) (1 << (n)) +#define STM32_EXTI1_BIT(n) (1 << (n)) +#define STM32_EXTI2_BIT(n) (1 << (n)) /* Register Offsets *********************************************************/ -#define STM32L4_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ -#define STM32L4_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ +#define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ +#define STM32_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ -#define STM32L4_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ -#define STM32L4_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ -#define STM32L4_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ -#define STM32L4_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ -#define STM32L4_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ -#define STM32L4_EXTI_PR_OFFSET 0x0014 /* Pending register */ +#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ +#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ +#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ +#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ +#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ +#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */ /* Register Addresses *******************************************************/ -#define STM32L4_EXTI1_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI1_OFFSET) -#define STM32L4_EXTI2_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI2_OFFSET) +#define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET) +#define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET) -#define STM32L4_EXTI1_IMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_IMR_OFFSET) -#define STM32L4_EXTI1_EMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_EMR_OFFSET) -#define STM32L4_EXTI1_RTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_RTSR_OFFSET) -#define STM32L4_EXTI1_FTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_FTSR_OFFSET) -#define STM32L4_EXTI1_SWIER (STM32L4_EXTI1_BASE+STM32L4_EXTI_SWIER_OFFSET) -#define STM32L4_EXTI1_PR (STM32L4_EXTI1_BASE+STM32L4_EXTI_PR_OFFSET) +#define STM32_EXTI1_IMR (STM32_EXTI1_BASE+STM32_EXTI_IMR_OFFSET) +#define STM32_EXTI1_EMR (STM32_EXTI1_BASE+STM32_EXTI_EMR_OFFSET) +#define STM32_EXTI1_RTSR (STM32_EXTI1_BASE+STM32_EXTI_RTSR_OFFSET) +#define STM32_EXTI1_FTSR (STM32_EXTI1_BASE+STM32_EXTI_FTSR_OFFSET) +#define STM32_EXTI1_SWIER (STM32_EXTI1_BASE+STM32_EXTI_SWIER_OFFSET) +#define STM32_EXTI1_PR (STM32_EXTI1_BASE+STM32_EXTI_PR_OFFSET) -#define STM32L4_EXTI2_IMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_IMR_OFFSET) -#define STM32L4_EXTI2_EMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_EMR_OFFSET) -#define STM32L4_EXTI2_RTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_RTSR_OFFSET) -#define STM32L4_EXTI2_FTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_FTSR_OFFSET) -#define STM32L4_EXTI2_SWIER (STM32L4_EXTI2_BASE+STM32L4_EXTI_SWIER_OFFSET) -#define STM32L4_EXTI2_PR (STM32L4_EXTI2_BASE+STM32L4_EXTI_PR_OFFSET) +#define STM32_EXTI2_IMR (STM32_EXTI2_BASE+STM32_EXTI_IMR_OFFSET) +#define STM32_EXTI2_EMR (STM32_EXTI2_BASE+STM32_EXTI_EMR_OFFSET) +#define STM32_EXTI2_RTSR (STM32_EXTI2_BASE+STM32_EXTI_RTSR_OFFSET) +#define STM32_EXTI2_FTSR (STM32_EXTI2_BASE+STM32_EXTI_FTSR_OFFSET) +#define STM32_EXTI2_SWIER (STM32_EXTI2_BASE+STM32_EXTI_SWIER_OFFSET) +#define STM32_EXTI2_PR (STM32_EXTI2_BASE+STM32_EXTI_PR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -105,62 +105,62 @@ /* Interrupt mask register */ -#define EXTI_IMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */ #define EXTI_IMR1_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR1_MASK STM32L4_EXTI1_MASK +#define EXTI_IMR1_MASK STM32_EXTI1_MASK -#define EXTI_IMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */ #define EXTI_IMR2_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR2_MASK STM32L4_EXTI2_MASK +#define EXTI_IMR2_MASK STM32_EXTI2_MASK /* Event mask register */ -#define EXTI_EMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Event request from line x is not mask */ #define EXTI_EMR1_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR1_MASK STM32L4_EXTI1_MASK +#define EXTI_EMR1_MASK STM32_EXTI1_MASK -#define EXTI_EMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Event request from line x is not mask */ #define EXTI_EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR2_MASK STM32L4_EXTI2_MASK +#define EXTI_EMR2_MASK STM32_EXTI2_MASK /* Rising Trigger selection register */ -#define EXTI_RTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ #define EXTI_RTSR1_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR1_MASK STM32L4_EXTI1_MASK +#define EXTI_RTSR1_MASK STM32_EXTI1_MASK -#define EXTI_RTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ #define EXTI_RTSR2_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR2_MASK STM32L4_EXTI2_MASK +#define EXTI_RTSR2_MASK STM32_EXTI2_MASK /* Falling Trigger selection register */ -#define EXTI_FTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR1_MASK STM32L4_EXTI1_MASK +#define EXTI_FTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR1_MASK STM32_EXTI1_MASK -#define EXTI_FTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR2_MASK STM32L4_EXTI2_MASK +#define EXTI_FTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR2_MASK STM32_EXTI2_MASK /* Software interrupt event register */ -#define EXTI_SWIER1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER1_MASK STM32L4_EXTI1_MASK +#define EXTI_SWIER1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER1_MASK STM32_EXTI1_MASK -#define EXTI_SWIER2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER2_MASK STM32L4_EXTI2_MASK +#define EXTI_SWIER2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER2_MASK STM32_EXTI2_MASK /* Pending register */ -#define EXTI_PR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR1_MASK STM32L4_EXTI1_MASK +#define EXTI_PR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR1_MASK STM32_EXTI1_MASK -#define EXTI_PR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR2_MASK STM32L4_EXTI2_MASK +#define EXTI_PR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR2_MASK STM32_EXTI2_MASK #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h index 8af1c073dc256..738544c954eb7 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h @@ -113,79 +113,79 @@ /* Define the valid configuration */ #if defined(CONFIG_STM32L4_FLASH_CONFIG_8) /* 64 kB */ -# define STM32L4_FLASH_NPAGES 32 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */ -# define STM32L4_FLASH_NPAGES 64 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */ -# define STM32L4_FLASH_NPAGES 128 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */ -# define STM32L4_FLASH_NPAGES 256 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */ -# define STM32L4_FLASH_NPAGES 512 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */ -# define STM32L4_FLASH_NPAGES 512 -# define STM32L4_FLASH_PAGESIZE 4096 +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 4096 #else # error "unknown flash configuration!" #endif -#ifdef STM32L4_FLASH_PAGESIZE -# define STM32L4_FLASH_SIZE (STM32L4_FLASH_NPAGES * STM32L4_FLASH_PAGESIZE) +#ifdef STM32_FLASH_PAGESIZE +# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif /* Register Offsets *********************************************************/ -#define STM32L4_FLASH_ACR_OFFSET 0x0000 -#define STM32L4_FLASH_PDKEYR_OFFSET 0x0004 -#define STM32L4_FLASH_KEYR_OFFSET 0x0008 -#define STM32L4_FLASH_OPTKEYR_OFFSET 0x000c -#define STM32L4_FLASH_SR_OFFSET 0x0010 -#define STM32L4_FLASH_CR_OFFSET 0x0014 -#define STM32L4_FLASH_ECCR_OFFSET 0x0018 -#define STM32L4_FLASH_OPTR_OFFSET 0x0020 -#define STM32L4_FLASH_PCROP1SR_OFFSET 0x0024 -#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028 -#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c -#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_PDKEYR_OFFSET 0x0004 +#define STM32_FLASH_KEYR_OFFSET 0x0008 +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c +#define STM32_FLASH_SR_OFFSET 0x0010 +#define STM32_FLASH_CR_OFFSET 0x0014 +#define STM32_FLASH_ECCR_OFFSET 0x0018 +#define STM32_FLASH_OPTR_OFFSET 0x0020 +#define STM32_FLASH_PCROP1SR_OFFSET 0x0024 +#define STM32_FLASH_PCROP1ER_OFFSET 0x0028 +#define STM32_FLASH_WRP1AR_OFFSET 0x002c +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 #if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044 -# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048 -# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c -# define STM32L4_FLASH_WRP2BR_OFFSET 0x0050 +# define STM32_FLASH_PCROP2SR_OFFSET 0x0044 +# define STM32_FLASH_PCROP2ER_OFFSET 0x0048 +# define STM32_FLASH_WRP2AR_OFFSET 0x004c +# define STM32_FLASH_WRP2BR_OFFSET 0x0050 #endif #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_CFGR_OFFSET 0x0130 +# define STM32_FLASH_CFGR_OFFSET 0x0130 #endif /* Register Addresses *******************************************************/ -#define STM32L4_FLASH_ACR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ACR_OFFSET) -#define STM32L4_FLASH_PDKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PDKEYR_OFFSET) -#define STM32L4_FLASH_KEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_KEYR_OFFSET) -#define STM32L4_FLASH_OPTKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTKEYR_OFFSET) -#define STM32L4_FLASH_SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_SR_OFFSET) -#define STM32L4_FLASH_CR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CR_OFFSET) -#define STM32L4_FLASH_ECCR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ECCR_OFFSET) -#define STM32L4_FLASH_OPTR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTR_OFFSET) -#define STM32L4_FLASH_PCROP1SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1SR_OFFSET) -#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET) -#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET) -#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET) +#define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) #if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET) -# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET) -# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET) -# define STM32L4_FLASH_WRP2BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2BR_OFFSET) +# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET) +# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET) +# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET) +# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET) #endif #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_CFGR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CFGR_OFFSET) +# define STM32_FLASH_CFGR (STM32_FLASHIF_BASE+STM32_FLASH_CFGR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h index 8938d7d983c51..e5501893ecb7a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h @@ -36,154 +36,154 @@ /* Register Offsets *********************************************************/ -#define STM32L4_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32L4_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32L4_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32L4_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32L4_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32L4_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32L4_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32L4_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32L4_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32L4_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32L4_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32L4_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */ /* Register Addresses *******************************************************/ -#if STM32L4_NPORTS > 0 -# define STM32L4_GPIOA_MODER (STM32L4_GPIOA_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOA_OTYPER (STM32L4_GPIOA_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOA_OSPEED (STM32L4_GPIOA_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOA_PUPDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOA_IDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOA_ODR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOA_BSRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOA_LCKR (STM32L4_GPIOA_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOA_AFRL (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOA_AFRH (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOA_BRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOA_ASCR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 1 -# define STM32L4_GPIOB_MODER (STM32L4_GPIOB_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOB_OTYPER (STM32L4_GPIOB_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOB_OSPEED (STM32L4_GPIOB_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOB_PUPDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOB_IDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOB_ODR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOB_BSRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOB_LCKR (STM32L4_GPIOB_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOB_AFRL (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOB_AFRH (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOB_BRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOB_ASCR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 2 -# define STM32L4_GPIOC_MODER (STM32L4_GPIOC_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOC_OTYPER (STM32L4_GPIOC_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOC_OSPEED (STM32L4_GPIOC_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOC_PUPDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOC_IDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOC_ODR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOC_BSRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOC_LCKR (STM32L4_GPIOC_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOC_AFRL (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOC_AFRH (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOC_BRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOC_ASCR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 3 -# define STM32L4_GPIOD_MODER (STM32L4_GPIOD_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOD_OTYPER (STM32L4_GPIOD_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOD_OSPEED (STM32L4_GPIOD_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOD_PUPDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOD_IDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOD_ODR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOD_BSRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOD_LCKR (STM32L4_GPIOD_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOD_AFRL (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOD_AFRH (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOD_BRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOD_ASCR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOD_ASCR (STM32_GPIOD_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 4 -# define STM32L4_GPIOE_MODER (STM32L4_GPIOE_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOE_OTYPER (STM32L4_GPIOE_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOE_OSPEED (STM32L4_GPIOE_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOE_PUPDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOE_IDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOE_ODR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOE_BSRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOE_LCKR (STM32L4_GPIOE_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOE_AFRL (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOE_AFRH (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOE_BRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOE_ASCR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOE_ASCR (STM32_GPIOE_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 5 -# define STM32L4_GPIOF_MODER (STM32L4_GPIOF_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOF_OTYPER (STM32L4_GPIOF_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOF_OSPEED (STM32L4_GPIOF_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOF_PUPDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOF_IDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOF_ODR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOF_BSRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOF_LCKR (STM32L4_GPIOF_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOF_AFRL (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOF_AFRH (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOF_BRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOF_ASCR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOF_ASCR (STM32_GPIOF_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 6 -# define STM32L4_GPIOG_MODER (STM32L4_GPIOG_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOG_OTYPER (STM32L4_GPIOG_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOG_OSPEED (STM32L4_GPIOG_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOG_PUPDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOG_IDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOG_ODR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOG_BSRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOG_LCKR (STM32L4_GPIOG_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOG_AFRL (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOG_AFRH (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOG_BRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOG_ASCR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOG_ASCR (STM32_GPIOG_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 7 -# define STM32L4_GPIOH_MODER (STM32L4_GPIOH_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOH_OTYPER (STM32L4_GPIOH_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOH_OSPEED (STM32L4_GPIOH_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOH_PUPDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOH_IDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOH_ODR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOH_BSRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOH_LCKR (STM32L4_GPIOH_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOH_AFRL (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOH_AFRH (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOH_BRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOH_ASCR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 8 -# define STM32L4_GPIOI_MODER (STM32L4_GPIOI_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOI_OTYPER (STM32L4_GPIOI_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOI_OSPEED (STM32L4_GPIOI_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOI_PUPDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOI_IDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOI_ODR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOI_BSRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOI_LCKR (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOI_AFRL (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOI_AFRH (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOI_BRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOI_ASCR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOI_BRR (STM32_GPIOI_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOI_ASCR (STM32_GPIOI_BASE+STM32_GPIO_ASCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h index 9ec04ef430a84..7fecf9bbd62d8 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h @@ -29,74 +29,74 @@ /* Register Offsets *********************************************************/ -#define STM32L4_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32L4_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32L4_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32L4_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32L4_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32L4_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32L4_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32L4_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32L4_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32L4_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32L4_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#if STM32L4_NI2C > 0 -# define STM32L4_I2C1_CR1 (STM32L4_I2C1_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C1_CR2 (STM32L4_I2C1_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C1_OAR1 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C1_OAR2 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C1_TIMINGR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C1_TIMEOUTR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C1_ISR (STM32L4_I2C1_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C1_ICR (STM32L4_I2C1_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C1_PECR (STM32L4_I2C1_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C1_RXDR (STM32L4_I2C1_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C1_TXDR (STM32L4_I2C1_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 0 +# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 1 -# define STM32L4_I2C2_CR1 (STM32L4_I2C2_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C2_CR2 (STM32L4_I2C2_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C2_OAR1 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C2_OAR2 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C2_TIMINGR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C2_TIMEOUTR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C2_ISR (STM32L4_I2C2_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C2_ICR (STM32L4_I2C2_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C2_PECR (STM32L4_I2C2_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C2_RXDR (STM32L4_I2C2_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C2_TXDR (STM32L4_I2C2_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 1 +# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 2 -# define STM32L4_I2C3_CR1 (STM32L4_I2C3_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C3_CR2 (STM32L4_I2C3_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C3_OAR1 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C3_OAR2 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C3_TIMINGR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C3_TIMEOUTR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C3_ISR (STM32L4_I2C3_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C3_ICR (STM32L4_I2C3_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C3_PECR (STM32L4_I2C3_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C3_RXDR (STM32L4_I2C3_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C3_TXDR (STM32L4_I2C3_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 2 +# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 3 -# define STM32L4_I2C4_CR1 (STM32L4_I2C4_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C4_CR2 (STM32L4_I2C4_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C4_OAR1 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C4_OAR2 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C4_TIMINGR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C4_TIMEOUTR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C4_ISR (STM32L4_I2C4_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C4_ICR (STM32L4_I2C4_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C4_PECR (STM32L4_I2C4_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C4_RXDR (STM32L4_I2C4_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C4_TXDR (STM32L4_I2C4_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 3 +# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h index 1da51068e5564..0a9c98ab0ba52 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h @@ -47,36 +47,36 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ -#define STM32L4_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ -#define STM32L4_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ -#define STM32L4_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ -#define STM32L4_LPTIM_CR_OFFSET 0x0010 /* Control Register */ -#define STM32L4_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ -#define STM32L4_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ -#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ +#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ +#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ +#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ +#define STM32_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ +#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control Register */ +#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ +#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ +#define STM32_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ /* Register Addresses *******************************************************/ /* Low-Power Timers - LPTIM1 and LPTIM2 */ -#define STM32L4_LPTIM1_ISR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ISR_OFFSET) -#define STM32L4_LPTIM1_ICR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ICR_OFFSET) -#define STM32L4_LPTIM1_IER (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_IER_OFFSET) -#define STM32L4_LPTIM1_CFGR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CFGR_OFFSET) -#define STM32L4_LPTIM1_CR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CR_OFFSET) -#define STM32L4_LPTIM1_CMP (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CMP_OFFSET) -#define STM32L4_LPTIM1_ARR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ARR_OFFSET) -#define STM32L4_LPTIM1_CNT (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CNT_OFFSET) - -#define STM32L4_LPTIM2_ISR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ISR_OFFSET) -#define STM32L4_LPTIM2_ICR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ICR_OFFSET) -#define STM32L4_LPTIM2_IER (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_IER_OFFSET) -#define STM32L4_LPTIM2_CFGR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CFGR_OFFSET) -#define STM32L4_LPTIM2_CR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CR_OFFSET) -#define STM32L4_LPTIM2_CMP (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CMP_OFFSET) -#define STM32L4_LPTIM2_ARR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ARR_OFFSET) -#define STM32L4_LPTIM2_CNT (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CNT_OFFSET) +#define STM32_LPTIM1_ISR (STM32_LPTIM1_BASE+STM32_LPTIM_ISR_OFFSET) +#define STM32_LPTIM1_ICR (STM32_LPTIM1_BASE+STM32_LPTIM_ICR_OFFSET) +#define STM32_LPTIM1_IER (STM32_LPTIM1_BASE+STM32_LPTIM_IER_OFFSET) +#define STM32_LPTIM1_CFGR (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR_OFFSET) +#define STM32_LPTIM1_CR (STM32_LPTIM1_BASE+STM32_LPTIM_CR_OFFSET) +#define STM32_LPTIM1_CMP (STM32_LPTIM1_BASE+STM32_LPTIM_CMP_OFFSET) +#define STM32_LPTIM1_ARR (STM32_LPTIM1_BASE+STM32_LPTIM_ARR_OFFSET) +#define STM32_LPTIM1_CNT (STM32_LPTIM1_BASE+STM32_LPTIM_CNT_OFFSET) + +#define STM32_LPTIM2_ISR (STM32_LPTIM2_BASE+STM32_LPTIM_ISR_OFFSET) +#define STM32_LPTIM2_ICR (STM32_LPTIM2_BASE+STM32_LPTIM_ICR_OFFSET) +#define STM32_LPTIM2_IER (STM32_LPTIM2_BASE+STM32_LPTIM_IER_OFFSET) +#define STM32_LPTIM2_CFGR (STM32_LPTIM2_BASE+STM32_LPTIM_CFGR_OFFSET) +#define STM32_LPTIM2_CR (STM32_LPTIM2_BASE+STM32_LPTIM_CR_OFFSET) +#define STM32_LPTIM2_CMP (STM32_LPTIM2_BASE+STM32_LPTIM_CMP_OFFSET) +#define STM32_LPTIM2_ARR (STM32_LPTIM2_BASE+STM32_LPTIM_ARR_OFFSET) +#define STM32_LPTIM2_CNT (STM32_LPTIM2_BASE+STM32_LPTIM_CNT_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h index 0cb4e62cac313..c677abec168b1 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h @@ -29,60 +29,60 @@ /* STM32L4XXX Address Blocks ************************************************/ -#define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ -#define STM32L4_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ -#define STM32L4_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ -# define STM32L4_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ -# define STM32L4_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ -#define STM32L4_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ -# define STM32L4_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ -# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ -#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ -#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */ -#define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */ -#define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */ - /* 0xc0000000-0xdfffffff: 512Mb (not used) */ -#define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ - -#define STM32L4_REGION_MASK 0xf0000000 -#define STM32L4_IS_SRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_SRAM_BASE) -#define STM32L4_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_FSMC_BANK1) +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ +# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ +#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ +#define STM32_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */ +#define STM32_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */ +#define STM32_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */ + /* 0xc0000000-0xdfffffff: 512Mb (not used) */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1) /* Code Base Addresses ******************************************************/ -#define STM32L4_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ - /* 0x00100000-0x07ffffff: Reserved */ -#define STM32L4_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ - /* 0x08100000-0x0fffffff: Reserved */ -#define STM32L4_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ -#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */ - /* 0x10010000-0x1ffeffff: Reserved */ -#define STM32L4_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */ -#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */ -#define STM32L4_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ - /* 0x1fff7400-0x1fff77ff: Reserved */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ + /* 0x00100000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ + /* 0x08100000-0x0fffffff: Reserved */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ +#define STM32_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */ + /* 0x10010000-0x1ffeffff: Reserved */ +#define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ + /* 0x1fff7400-0x1fff77ff: Reserved */ #ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */ - /* 0x1ff00010-0x1ff00fff: Reserved */ -# define STM32L4_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */ - /* 0x1ff01010-0x1ff01fff: Reserved */ +# define STM32_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */ + /* 0x1ff00010-0x1ff00fff: Reserved */ +# define STM32_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */ + /* 0x1ff01010-0x1ff01fff: Reserved */ #else -# define STM32L4_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */ - /* 0x1fff7810-0x1ffff7ff: Reserved */ -# define STM32L4_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */ - /* 0x1ffff810-0x1fffffff: Reserved */ +# define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */ + /* 0x1fff7810-0x1ffff7ff: Reserved */ +# define STM32_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */ + /* 0x1ffff810-0x1fffffff: Reserved */ #endif /* System Memory Addresses **************************************************/ -#define STM32L4_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32L4_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. */ -#define STM32L4_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. * 0: LQFP64 * 1: WLCSP64 @@ -105,123 +105,123 @@ /* 0x2001c000-0x2001ffff: * 16Kb aliased by bit-banding */ -#define STM32L4_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32L4_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ - /* 0x40009800-0x4000ffff: Reserved */ -#define STM32L4_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */ - /* 0x40016400-0x4001ffff: Reserved */ -#define STM32L4_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ - /* 0x40024400-0x47ffffff: Reserved */ -#define STM32L4_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */ - /* 0x50060c00-0x5fffffff: Reserved */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ + /* 0x40009800-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */ + /* 0x40016400-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x47ffffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */ + /* 0x50060c00-0x5fffffff: Reserved */ /* FSMC/QSPI Base Addresses *************************************************/ -#define STM32L4_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */ +#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */ /* in datasheet order */ /* APB1 Base Addresses ******************************************************/ -#define STM32L4_LPTIM2_BASE 0x40009400 -#define STM32L4_SWPMI1_BASE 0x40008800 -#define STM32L4_I2C4_BASE 0x40008400 -#define STM32L4_LPUART1_BASE 0x40008000 -#define STM32L4_LPTIM1_BASE 0x40007c00 -#define STM32L4_OPAMP_BASE 0x40007800 -#define STM32L4_DAC_BASE 0x40007400 -#define STM32L4_PWR_BASE 0x40007000 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_SWPMI1_BASE 0x40008800 +#define STM32_I2C4_BASE 0x40008400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007c00 +#define STM32_OPAMP_BASE 0x40007800 +#define STM32_DAC_BASE 0x40007400 +#define STM32_PWR_BASE 0x40007000 #if defined(CONFIG_STM32L4_STM32L4X3) -# define STM32L4_USB_SRAM_BASE 0x40006c00 -# define STM32L4_USB_FS_BASE 0x40006800 +# define STM32_USB_SRAM_BASE 0x40006c00 +# define STM32_USB_FS_BASE 0x40006800 #else -# define STM32L4_CAN2_BASE 0x40006800 +# define STM32_CAN2_BASE 0x40006800 #endif -#define STM32L4_CAN1_BASE 0x40006400 -#define STM32L4_CRS_BASE 0x40006000 -#define STM32L4_I2C3_BASE 0x40005c00 -#define STM32L4_I2C2_BASE 0x40005800 -#define STM32L4_I2C1_BASE 0x40005400 -#define STM32L4_UART5_BASE 0x40005000 -#define STM32L4_UART4_BASE 0x40004c00 -#define STM32L4_USART3_BASE 0x40004800 -#define STM32L4_USART2_BASE 0x40004400 -#define STM32L4_SPI3_BASE 0x40003c00 -#define STM32L4_SPI2_BASE 0x40003800 -#define STM32L4_IWDG_BASE 0x40003000 -#define STM32L4_WWDG_BASE 0x40002c00 -#define STM32L4_RTC_BASE 0x40002800 -#define STM32L4_LCD_BASE 0x40002400 -#define STM32L4_TIM7_BASE 0x40001400 -#define STM32L4_TIM6_BASE 0x40001000 -#define STM32L4_TIM5_BASE 0x40000c00 -#define STM32L4_TIM4_BASE 0x40000800 -#define STM32L4_TIM3_BASE 0x40000400 -#define STM32L4_TIM2_BASE 0x40000000 +#define STM32_CAN1_BASE 0x40006400 +#define STM32_CRS_BASE 0x40006000 +#define STM32_I2C3_BASE 0x40005c00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_UART5_BASE 0x40005000 +#define STM32_UART4_BASE 0x40004c00 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI3_BASE 0x40003c00 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002c00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_LCD_BASE 0x40002400 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM5_BASE 0x40000c00 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32L4_DSI_BASE 0x40016c00 -#define STM32L4_LTDC_BASE 0x40016800 -#define STM32L4_DFSDM_BASE 0x40016000 -#define STM32L4_SAI2_BASE 0x40015800 -#define STM32L4_SAI1_BASE 0x40015400 -#define STM32L4_TIM17_BASE 0x40014800 -#define STM32L4_TIM16_BASE 0x40014400 -#define STM32L4_TIM15_BASE 0x40014000 -#define STM32L4_USART1_BASE 0x40013800 -#define STM32L4_TIM8_BASE 0x40013400 -#define STM32L4_SPI1_BASE 0x40013000 -#define STM32L4_TIM1_BASE 0x40012c00 +#define STM32_DSI_BASE 0x40016c00 +#define STM32_LTDC_BASE 0x40016800 +#define STM32_DFSDM_BASE 0x40016000 +#define STM32_SAI2_BASE 0x40015800 +#define STM32_SAI1_BASE 0x40015400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM8_BASE 0x40013400 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012c00 #ifndef CONFIG_STM32L4_STM32L4XR -# define STM32L4_SDMMC1_BASE 0x40012800 +# define STM32_SDMMC1_BASE 0x40012800 #endif -#define STM32L4_FIREWALL_BASE 0x40011c00 -#define STM32L4_EXTI_BASE 0x40010400 -#define STM32L4_COMP_BASE 0x40010200 -#define STM32L4_VREFBUF_BASE 0x40010030 -#define STM32L4_SYSCFG_BASE 0x40010000 +#define STM32_FIREWALL_BASE 0x40011c00 +#define STM32_EXTI_BASE 0x40010400 +#define STM32_COMP_BASE 0x40010200 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32L4_GFXMMU_BASE 0x4002c000 -#define STM32L4_DMA2D_BASE 0x4002b000 -#define STM32L4_TSC_BASE 0x40024000 -#define STM32L4_CRC_BASE 0x40023000 -#define STM32L4_FLASHIF_BASE 0x40022000 -#define STM32L4_RCC_BASE 0x40021000 -#define STM32L4_DMAMUX1_BASE 0x40020800 -#define STM32L4_DMA2_BASE 0x40020400 -#define STM32L4_DMA1_BASE 0x40020000 +#define STM32_GFXMMU_BASE 0x4002c000 +#define STM32_DMA2D_BASE 0x4002b000 +#define STM32_TSC_BASE 0x40024000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_FLASHIF_BASE 0x40022000 +#define STM32_RCC_BASE 0x40021000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ #ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_SDMMC1_BASE 0x50062400 +# define STM32_SDMMC1_BASE 0x50062400 #endif -#define STM32L4_OCTOSPIIOM_BASE 0x50061c00 -#define STM32L4_RNG_BASE 0x50060800 -#define STM32L4_HASH_BASE 0x50060400 -#define STM32L4_AES_BASE 0x50060000 -#define STM32L4_DCMI_BASE 0x50050000 -#define STM32L4_ADC_BASE 0x50040000 -# define STM32L4_ADC1_BASE 0x50040000 /* ADC1 */ -# define STM32L4_ADC2_BASE 0x50040100 /* ADC2 */ -# define STM32L4_ADC3_BASE 0x50040200 /* ADC3 */ -# define STM32L4_ADCCMN_BASE 0x50040300 /* Common */ -#define STM32L4_OTGFS_BASE 0x50000000 -#define STM32L4_GPIOI_BASE 0x48002000 -#define STM32L4_GPIOH_BASE 0x48001c00 -#define STM32L4_GPIOG_BASE 0x48001800 -#define STM32L4_GPIOF_BASE 0x48001400 -#define STM32L4_GPIOE_BASE 0x48001000 -#define STM32L4_GPIOD_BASE 0x48000c00 -#define STM32L4_GPIOC_BASE 0x48000800 -#define STM32L4_GPIOB_BASE 0x48000400 -#define STM32L4_GPIOA_BASE 0x48000000 +#define STM32_OCTOSPIIOM_BASE 0x50061c00 +#define STM32_RNG_BASE 0x50060800 +#define STM32_HASH_BASE 0x50060400 +#define STM32_AES_BASE 0x50060000 +#define STM32_DCMI_BASE 0x50050000 +#define STM32_ADC_BASE 0x50040000 +# define STM32_ADC1_BASE 0x50040000 /* ADC1 */ +# define STM32_ADC2_BASE 0x50040100 /* ADC2 */ +# define STM32_ADC3_BASE 0x50040200 /* ADC3 */ +# define STM32_ADCCMN_BASE 0x50040300 /* Common */ +#define STM32_OTGFS_BASE 0x50000000 +#define STM32_GPIOI_BASE 0x48002000 +#define STM32_GPIOH_BASE 0x48001c00 +#define STM32_GPIOG_BASE 0x48001800 +#define STM32_GPIOF_BASE 0x48001400 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOD_BASE 0x48000c00 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOA_BASE 0x48000000 /* Cortex-M4 Base Addresses *************************************************/ @@ -229,7 +229,7 @@ * this address range */ -#define STM32L4_SCS_BASE 0xe000e000 -#define STM32L4_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h index ab598f0c70ac6..a6aaf5eba1e9a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h @@ -36,64 +36,64 @@ /* Register Offsets *********************************************************/ -#define STM32L4_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32L4_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32L4_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32L4_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32L4_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32L4_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32L4_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32L4_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32L4_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32L4_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32L4_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32L4_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32L4_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32L4_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32L4_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32L4_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32L4_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ -#define STM32L4_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ -#define STM32L4_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ -#define STM32L4_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ -#define STM32L4_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ -#define STM32L4_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32L4_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32L4_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ -#define STM32L4_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ +#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ +#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ +#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ +#define STM32_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ +# define STM32_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ #endif /* Register Addresses *******************************************************/ -#define STM32L4_PWR_CR1 (STM32L4_PWR_BASE+STM32L4_PWR_CR1_OFFSET) -#define STM32L4_PWR_CR2 (STM32L4_PWR_BASE+STM32L4_PWR_CR2_OFFSET) -#define STM32L4_PWR_CR3 (STM32L4_PWR_BASE+STM32L4_PWR_CR3_OFFSET) -#define STM32L4_PWR_CR4 (STM32L4_PWR_BASE+STM32L4_PWR_CR4_OFFSET) -#define STM32L4_PWR_SR1 (STM32L4_PWR_BASE+STM32L4_PWR_SR1_OFFSET) -#define STM32L4_PWR_SR2 (STM32L4_PWR_BASE+STM32L4_PWR_SR2_OFFSET) -#define STM32L4_PWR_SCR (STM32L4_PWR_BASE+STM32L4_PWR_SCR_OFFSET) -#define STM32L4_PWR_PUCRA (STM32L4_PWR_BASE+STM32L4_PWR_PUCRA_OFFSET) -#define STM32L4_PWR_PDCRA (STM32L4_PWR_BASE+STM32L4_PWR_PDCRA_OFFSET) -#define STM32L4_PWR_PUCRB (STM32L4_PWR_BASE+STM32L4_PWR_PUCRB_OFFSET) -#define STM32L4_PWR_PDCRB (STM32L4_PWR_BASE+STM32L4_PWR_PDCRB_OFFSET) -#define STM32L4_PWR_PUCRC (STM32L4_PWR_BASE+STM32L4_PWR_PUCRC_OFFSET) -#define STM32L4_PWR_PDCRC (STM32L4_PWR_BASE+STM32L4_PWR_PDCRC_OFFSET) -#define STM32L4_PWR_PUCRD (STM32L4_PWR_BASE+STM32L4_PWR_PUCRD_OFFSET) -#define STM32L4_PWR_PDCRD (STM32L4_PWR_BASE+STM32L4_PWR_PDCRD_OFFSET) -#define STM32L4_PWR_PUCRE (STM32L4_PWR_BASE+STM32L4_PWR_PUCRE_OFFSET) -#define STM32L4_PWR_PDCRE (STM32L4_PWR_BASE+STM32L4_PWR_PDCRE_OFFSET) -#define STM32L4_PWR_PUCRF (STM32L4_PWR_BASE+STM32L4_PWR_PUCRF_OFFSET) -#define STM32L4_PWR_PDCRF (STM32L4_PWR_BASE+STM32L4_PWR_PDCRF_OFFSET) -#define STM32L4_PWR_PUCRG (STM32L4_PWR_BASE+STM32L4_PWR_PUCRG_OFFSET) -#define STM32L4_PWR_PDCRG (STM32L4_PWR_BASE+STM32L4_PWR_PDCRG_OFFSET) -#define STM32L4_PWR_PUCRH (STM32L4_PWR_BASE+STM32L4_PWR_PUCRH_OFFSET) -#define STM32L4_PWR_PDCRH (STM32L4_PWR_BASE+STM32L4_PWR_PDCRH_OFFSET) -#define STM32L4_PWR_PUCRI (STM32L4_PWR_BASE+STM32L4_PWR_PUCRI_OFFSET) -#define STM32L4_PWR_PDCRI (STM32L4_PWR_BASE+STM32L4_PWR_PDCRI_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET) +#define STM32_PWR_PUCRG (STM32_PWR_BASE+STM32_PWR_PUCRG_OFFSET) +#define STM32_PWR_PDCRG (STM32_PWR_BASE+STM32_PWR_PDCRG_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_PUCRI (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET) +#define STM32_PWR_PDCRI (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET) #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_PWR_CR5 (STM32L4_PWR_BASE+STM32L4_PWR_CR5_OFFSET) +# define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h index 3a1b8214d2c86..c4b0817397879 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h @@ -38,40 +38,40 @@ /* General Characteristics **************************************************/ -#define STM32L4_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32L4_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ -#define STM32L4_QUADSPI_CR_OFFSET 0x0000 /* Control Register */ -#define STM32L4_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */ -#define STM32L4_QUADSPI_SR_OFFSET 0x0008 /* Status Register */ -#define STM32L4_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */ -#define STM32L4_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */ -#define STM32L4_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */ -#define STM32L4_QUADSPI_AR_OFFSET 0x0018 /* Address Register */ -#define STM32L4_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */ -#define STM32L4_QUADSPI_DR_OFFSET 0x0020 /* Data Register */ -#define STM32L4_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */ -#define STM32L4_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */ -#define STM32L4_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */ -#define STM32L4_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */ +#define STM32_QUADSPI_CR_OFFSET 0x0000 /* Control Register */ +#define STM32_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */ +#define STM32_QUADSPI_SR_OFFSET 0x0008 /* Status Register */ +#define STM32_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */ +#define STM32_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */ +#define STM32_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */ +#define STM32_QUADSPI_AR_OFFSET 0x0018 /* Address Register */ +#define STM32_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */ +#define STM32_QUADSPI_DR_OFFSET 0x0020 /* Data Register */ +#define STM32_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */ +#define STM32_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */ +#define STM32_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */ +#define STM32_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */ /* QSPI register addresses **************************************************/ -#define STM32L4_QUADSPI_CR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CR_OFFSET) /* Control Register */ -#define STM32L4_QUADSPI_DCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DCR_OFFSET) /* Device Configuration Register */ -#define STM32L4_QUADSPI_SR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_SR_OFFSET) /* Status Register */ -#define STM32L4_QUADSPI_FCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_FCR_OFFSET) /* Flag Clear Register */ -#define STM32L4_QUADSPI_DLR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DLR_OFFSET) /* Data Length Register */ -#define STM32L4_QUADSPI_CCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */ -#define STM32L4_QUADSPI_AR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_AR_OFFSET) /* Address Register */ -#define STM32L4_QUADSPI_ABR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */ -#define STM32L4_QUADSPI_DR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DR_OFFSET) /* Data Register */ -#define STM32L4_QUADSPI_PSMKR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */ -#define STM32L4_QUADSPI_PSMAR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */ -#define STM32L4_QUADSPI_PIR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PIR_OFFSET) /* Polling Interval Register */ -#define STM32L4_QUADSPI_LPTR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */ +#define STM32_QUADSPI_CR (STM32_QSPI_BASE+STM32_QUADSPI_CR_OFFSET) /* Control Register */ +#define STM32_QUADSPI_DCR (STM32_QSPI_BASE+STM32_QUADSPI_DCR_OFFSET) /* Device Configuration Register */ +#define STM32_QUADSPI_SR (STM32_QSPI_BASE+STM32_QUADSPI_SR_OFFSET) /* Status Register */ +#define STM32_QUADSPI_FCR (STM32_QSPI_BASE+STM32_QUADSPI_FCR_OFFSET) /* Flag Clear Register */ +#define STM32_QUADSPI_DLR (STM32_QSPI_BASE+STM32_QUADSPI_DLR_OFFSET) /* Data Length Register */ +#define STM32_QUADSPI_CCR (STM32_QSPI_BASE+STM32_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */ +#define STM32_QUADSPI_AR (STM32_QSPI_BASE+STM32_QUADSPI_AR_OFFSET) /* Address Register */ +#define STM32_QUADSPI_ABR (STM32_QSPI_BASE+STM32_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */ +#define STM32_QUADSPI_DR (STM32_QSPI_BASE+STM32_QUADSPI_DR_OFFSET) /* Data Register */ +#define STM32_QUADSPI_PSMKR (STM32_QSPI_BASE+STM32_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */ +#define STM32_QUADSPI_PSMAR (STM32_QSPI_BASE+STM32_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */ +#define STM32_QUADSPI_PIR (STM32_QSPI_BASE+STM32_QUADSPI_PIR_OFFSET) /* Polling Interval Register */ +#define STM32_QUADSPI_LPTR (STM32_QSPI_BASE+STM32_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */ /* QSPI register bit definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_rng.h b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h index 387776eb2ab50..b038e5cef497a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_rng.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h @@ -36,15 +36,15 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ -#define STM32L4_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ -#define STM32L4_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ +#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ +#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ +#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ /* Register Addresses *******************************************************/ -#define STM32L4_RNG_CR (STM32L4_RNG_BASE+STM32L4_RNG_CR_OFFSET) -#define STM32L4_RNG_SR (STM32L4_RNG_BASE+STM32L4_RNG_SR_OFFSET) -#define STM32L4_RNG_DR (STM32L4_RNG_BASE+STM32L4_RNG_DR_OFFSET) +#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET) +#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET) +#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h index d2f1ad30b0863..89ae64ee1ba1a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h @@ -29,117 +29,117 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32L4_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32L4_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32L4_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32L4_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32L4_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32L4_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32L4_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32L4_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32L4_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32L4_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32L4_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32L4_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32L4_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32L4_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32L4_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ -#define STM32L4_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32L4_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ -#define STM32L4_RTC_OR_OFFSET 0x004c /* RTC option register */ - -#define STM32L4_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) -#define STM32L4_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32L4_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32L4_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32L4_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32L4_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32L4_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32L4_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32L4_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32L4_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32L4_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32L4_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32L4_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32L4_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32L4_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32L4_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32L4_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32L4_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32L4_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32L4_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32L4_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ -#define STM32L4_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ -#define STM32L4_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ -#define STM32L4_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ -#define STM32L4_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ -#define STM32L4_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ -#define STM32L4_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ -#define STM32L4_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ -#define STM32L4_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ -#define STM32L4_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ -#define STM32L4_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ -#define STM32L4_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ -#define STM32L4_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ +#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */ + +#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) +#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ +#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ +#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ +#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ +#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ +#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ +#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ +#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ +#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ +#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ +#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ +#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ +#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ +#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ +#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ +#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ +#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ /* Register Addresses *******************************************************/ -#define STM32L4_RTC_TR (STM32L4_RTC_BASE+STM32L4_RTC_TR_OFFSET) -#define STM32L4_RTC_DR (STM32L4_RTC_BASE+STM32L4_RTC_DR_OFFSET) -#define STM32L4_RTC_CR (STM32L4_RTC_BASE+STM32L4_RTC_CR_OFFSET) -#define STM32L4_RTC_ISR (STM32L4_RTC_BASE+STM32L4_RTC_ISR_OFFSET) -#define STM32L4_RTC_PRER (STM32L4_RTC_BASE+STM32L4_RTC_PRER_OFFSET) -#define STM32L4_RTC_WUTR (STM32L4_RTC_BASE+STM32L4_RTC_WUTR_OFFSET) -#define STM32L4_RTC_ALRMAR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMAR_OFFSET) -#define STM32L4_RTC_ALRMBR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBR_OFFSET) -#define STM32L4_RTC_WPR (STM32L4_RTC_BASE+STM32L4_RTC_WPR_OFFSET) -#define STM32L4_RTC_SSR (STM32L4_RTC_BASE+STM32L4_RTC_SSR_OFFSET) -#define STM32L4_RTC_SHIFTR (STM32L4_RTC_BASE+STM32L4_RTC_SHIFTR_OFFSET) -#define STM32L4_RTC_TSTR (STM32L4_RTC_BASE+STM32L4_RTC_TSTR_OFFSET) -#define STM32L4_RTC_TSDR (STM32L4_RTC_BASE+STM32L4_RTC_TSDR_OFFSET) -#define STM32L4_RTC_TSSSR (STM32L4_RTC_BASE+STM32L4_RTC_TSSSR_OFFSET) -#define STM32L4_RTC_CALR (STM32L4_RTC_BASE+STM32L4_RTC_CALR_OFFSET) -#define STM32L4_RTC_TAMPCR (STM32L4_RTC_BASE+STM32L4_RTC_TAMPCR_OFFSET) -#define STM32L4_RTC_ALRMASSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMASSR_OFFSET) -#define STM32L4_RTC_ALRMBSSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBSSR_OFFSET) -#define STM32L4_RTC_OR (STM32L4_RTC_BASE+STM32L4_RTC_OR_OFFSET) - -#define STM32L4_RTC_BKR(n) (STM32L4_RTC_BASE+STM32L4_RTC_BKR_OFFSET(n)) -#define STM32L4_RTC_BK0R (STM32L4_RTC_BASE+STM32L4_RTC_BK0R_OFFSET) -#define STM32L4_RTC_BK1R (STM32L4_RTC_BASE+STM32L4_RTC_BK1R_OFFSET) -#define STM32L4_RTC_BK2R (STM32L4_RTC_BASE+STM32L4_RTC_BK2R_OFFSET) -#define STM32L4_RTC_BK3R (STM32L4_RTC_BASE+STM32L4_RTC_BK3R_OFFSET) -#define STM32L4_RTC_BK4R (STM32L4_RTC_BASE+STM32L4_RTC_BK4R_OFFSET) -#define STM32L4_RTC_BK5R (STM32L4_RTC_BASE+STM32L4_RTC_BK5R_OFFSET) -#define STM32L4_RTC_BK6R (STM32L4_RTC_BASE+STM32L4_RTC_BK6R_OFFSET) -#define STM32L4_RTC_BK7R (STM32L4_RTC_BASE+STM32L4_RTC_BK7R_OFFSET) -#define STM32L4_RTC_BK8R (STM32L4_RTC_BASE+STM32L4_RTC_BK8R_OFFSET) -#define STM32L4_RTC_BK9R (STM32L4_RTC_BASE+STM32L4_RTC_BK9R_OFFSET) -#define STM32L4_RTC_BK10R (STM32L4_RTC_BASE+STM32L4_RTC_BK10R_OFFSET) -#define STM32L4_RTC_BK11R (STM32L4_RTC_BASE+STM32L4_RTC_BK11R_OFFSET) -#define STM32L4_RTC_BK12R (STM32L4_RTC_BASE+STM32L4_RTC_BK12R_OFFSET) -#define STM32L4_RTC_BK13R (STM32L4_RTC_BASE+STM32L4_RTC_BK13R_OFFSET) -#define STM32L4_RTC_BK14R (STM32L4_RTC_BASE+STM32L4_RTC_BK14R_OFFSET) -#define STM32L4_RTC_BK15R (STM32L4_RTC_BASE+STM32L4_RTC_BK15R_OFFSET) -#define STM32L4_RTC_BK16R (STM32L4_RTC_BASE+STM32L4_RTC_BK16R_OFFSET) -#define STM32L4_RTC_BK17R (STM32L4_RTC_BASE+STM32L4_RTC_BK17R_OFFSET) -#define STM32L4_RTC_BK18R (STM32L4_RTC_BASE+STM32L4_RTC_BK18R_OFFSET) -#define STM32L4_RTC_BK19R (STM32L4_RTC_BASE+STM32L4_RTC_BK19R_OFFSET) -#define STM32L4_RTC_BK20R (STM32L4_RTC_BASE+STM32L4_RTC_BK20R_OFFSET) -#define STM32L4_RTC_BK21R (STM32L4_RTC_BASE+STM32L4_RTC_BK21R_OFFSET) -#define STM32L4_RTC_BK22R (STM32L4_RTC_BASE+STM32L4_RTC_BK22R_OFFSET) -#define STM32L4_RTC_BK23R (STM32L4_RTC_BASE+STM32L4_RTC_BK23R_OFFSET) -#define STM32L4_RTC_BK24R (STM32L4_RTC_BASE+STM32L4_RTC_BK24R_OFFSET) -#define STM32L4_RTC_BK25R (STM32L4_RTC_BASE+STM32L4_RTC_BK25R_OFFSET) -#define STM32L4_RTC_BK26R (STM32L4_RTC_BASE+STM32L4_RTC_BK26R_OFFSET) -#define STM32L4_RTC_BK27R (STM32L4_RTC_BASE+STM32L4_RTC_BK27R_OFFSET) -#define STM32L4_RTC_BK28R (STM32L4_RTC_BASE+STM32L4_RTC_BK28R_OFFSET) -#define STM32L4_RTC_BK29R (STM32L4_RTC_BASE+STM32L4_RTC_BK29R_OFFSET) -#define STM32L4_RTC_BK30R (STM32L4_RTC_BASE+STM32L4_RTC_BK30R_OFFSET) -#define STM32L4_RTC_BK31R (STM32L4_RTC_BASE+STM32L4_RTC_BK31R_OFFSET) - -# define STM32L4_RTC_BKCOUNT 32 +#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET) +#define STM32_RTC_OR (STM32_RTC_BASE+STM32_RTC_OR_OFFSET) + +#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n)) +#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET) +#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET) +#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET) +#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET) +#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET) +#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET) +#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET) +#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET) +#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET) +#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET) +#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET) +#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET) +#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET) +#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET) +#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET) +#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET) +#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) +#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) +#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) +#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) +#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET) +#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET) +#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET) +#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET) +#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET) +#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET) +#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET) +#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET) +#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET) +#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET) +#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET) +#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET) + +# define STM32_RTC_BKCOUNT 32 /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h index ea33be29c5270..d474d0a66c793 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h @@ -36,67 +36,67 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ +#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ -#define STM32L4_SAI_A_OFFSET 0x0004 -#define STM32L4_SAI_B_OFFSET 0x0024 +#define STM32_SAI_A_OFFSET 0x0004 +#define STM32_SAI_B_OFFSET 0x0024 -#define STM32L4_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ -#define STM32L4_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ -#define STM32L4_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ -#define STM32L4_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ -#define STM32L4_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ -#define STM32L4_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ -#define STM32L4_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ -#define STM32L4_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ +#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ +#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ +#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ +#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ +#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ +#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ +#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ +#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ /* Register Addresses *******************************************************/ -#define STM32L4_SAI1_GCR (STM32L4_SAI_GCR_OFFSET) - -#define STM32L4_SAI1_A_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_A_OFFSET) -#define STM32L4_SAI1_B_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_B_OFFSET) - -#define STM32L4_SAI1_ACR1 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR1_OFFSET) -#define STM32L4_SAI1_ACR2 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR2_OFFSET) -#define STM32L4_SAI1_AFRCR (STM32L4_SAI1_A_BASE+STM32L4_SAI_AFRCR_OFFSET) -#define STM32L4_SAI1_ASLOTR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASLOTR_OFFSET) -#define STM32L4_SAI1_AIM (STM32L4_SAI1_A_BASE+STM32L4_SAI_AIM_OFFSET) -#define STM32L4_SAI1_ASR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASR_OFFSET) -#define STM32L4_SAI1_ACLRFR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACLRFR_OFFSET) -#define STM32L4_SAI1_ADR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ADR_OFFSET) - -#define STM32L4_SAI1_BCR1 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR1_OFFSET) -#define STM32L4_SAI1_BCR2 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR2_OFFSET) -#define STM32L4_SAI1_BFRCR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BFRCR_OFFSET) -#define STM32L4_SAI1_BSLOTR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSLOTR_OFFSET) -#define STM32L4_SAI1_BIM (STM32L4_SAI1_B_BASE+STM32L4_SAI_BIM_OFFSET) -#define STM32L4_SAI1_BSR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSR_OFFSET) -#define STM32L4_SAI1_BCLRFR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCLRFR_OFFSET) -#define STM32L4_SAI1_BDR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BDR_OFFSET) - -#define STM32L4_SAI2_GCR (STM32L4_SAI2_BASE+STM32L4_SAI_GCR_OFFSET) - -#define STM32L4_SAI2_A_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_A_OFFSET) -#define STM32L4_SAI2_B_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_B_OFFSET) - -#define STM32L4_SAI2_ACR1 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR1_OFFSET) -#define STM32L4_SAI2_ACR2 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR2_OFFSET) -#define STM32L4_SAI2_AFRCR (STM32L4_SAI2_A_BASE+STM32L4_SAI_AFRCR_OFFSET) -#define STM32L4_SAI2_ASLOTR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASLOTR_OFFSET) -#define STM32L4_SAI2_AIM (STM32L4_SAI2_A_BASE+STM32L4_SAI_AIM_OFFSET) -#define STM32L4_SAI2_ASR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASR_OFFSET) -#define STM32L4_SAI2_ACLRFR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACLRFR_OFFSET) -#define STM32L4_SAI2_ADR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ADR_OFFSET) - -#define STM32L4_SAI2_BCR1 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR1_OFFSET) -#define STM32L4_SAI2_BCR2 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR2_OFFSET) -#define STM32L4_SAI2_BFRCR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BFRCR_OFFSET) -#define STM32L4_SAI2_BSLOTR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSLOTR_OFFSET) -#define STM32L4_SAI2_BIM (STM32L4_SAI2_B_BASE+STM32L4_SAI_BIM_OFFSET) -#define STM32L4_SAI2_BSR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSR_OFFSET) -#define STM32L4_SAI2_BCLRFR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCLRFR_OFFSET) -#define STM32L4_SAI2_BDR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BDR_OFFSET) +#define STM32_SAI1_GCR (STM32_SAI_GCR_OFFSET) + +#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_ACR1_OFFSET) +#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_ACR2_OFFSET) +#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_AFRCR_OFFSET) +#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_ASLOTR_OFFSET) +#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_AIM_OFFSET) +#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_ASR_OFFSET) +#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_ACLRFR_OFFSET) +#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_ADR_OFFSET) + +#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_BCR1_OFFSET) +#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_BCR2_OFFSET) +#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_BFRCR_OFFSET) +#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_BSLOTR_OFFSET) +#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_BIM_OFFSET) +#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_BSR_OFFSET) +#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_BCLRFR_OFFSET) +#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_BDR_OFFSET) + +#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_ACR1_OFFSET) +#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_ACR2_OFFSET) +#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_AFRCR_OFFSET) +#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_ASLOTR_OFFSET) +#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_AIM_OFFSET) +#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_ASR_OFFSET) +#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_ACLRFR_OFFSET) +#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_ADR_OFFSET) + +#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_BCR1_OFFSET) +#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_BCR2_OFFSET) +#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_BFRCR_OFFSET) +#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_BSLOTR_OFFSET) +#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_BIM_OFFSET) +#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_BSR_OFFSET) +#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_BCLRFR_OFFSET) +#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_BDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h index 6098c3949d376..cada1d6e980f3 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h @@ -36,48 +36,48 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32L4_SPI_CLK_MAX 40000000UL +#define STM32_SPI_CLK_MAX 40000000UL /* Register Offsets *********************************************************/ -#define STM32L4_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32L4_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32L4_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32L4_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32L4_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32L4_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32L4_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#if STM32L4_NSPI > 0 -# define STM32L4_SPI1_CR1 (STM32L4_SPI1_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI1_CR2 (STM32L4_SPI1_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI1_SR (STM32L4_SPI1_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI1_DR (STM32L4_SPI1_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI1_CRCPR (STM32L4_SPI1_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI1_RXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI1_TXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L4_NSPI > 1 -# define STM32L4_SPI2_CR1 (STM32L4_SPI2_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI2_CR2 (STM32L4_SPI2_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI2_SR (STM32L4_SPI2_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI2_DR (STM32L4_SPI2_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI2_CRCPR (STM32L4_SPI2_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI2_RXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI2_TXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L4_NSPI > 2 -# define STM32L4_SPI3_CR1 (STM32L4_SPI3_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI3_CR2 (STM32L4_SPI3_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI3_SR (STM32L4_SPI3_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI3_DR (STM32L4_SPI3_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI3_CRCPR (STM32L4_SPI3_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI3_RXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI3_TXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h index b643e79014eef..0c632105d7fbf 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L4_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L4_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L4_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L4_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L4_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32L4_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L4_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32L4_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32L4_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32L4_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L4_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L4_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32L4_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32L4_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32L4_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L4_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32L4_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32L4_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32L4_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32L4_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32L4_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32L4_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L4_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32L4_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32L4_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32L4_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32L4_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32L4_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32L4_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32L4_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L4_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L4_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32L4_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32L4_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32L4_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32L4_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32L4_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L4_TIM1_CR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR1_OFFSET) -#define STM32L4_TIM1_CR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR2_OFFSET) -#define STM32L4_TIM1_SMCR (STM32L4_TIM1_BASE+STM32L4_ATIM_SMCR_OFFSET) -#define STM32L4_TIM1_DIER (STM32L4_TIM1_BASE+STM32L4_ATIM_DIER_OFFSET) -#define STM32L4_TIM1_SR (STM32L4_TIM1_BASE+STM32L4_ATIM_SR_OFFSET) -#define STM32L4_TIM1_EGR (STM32L4_TIM1_BASE+STM32L4_ATIM_EGR_OFFSET) -#define STM32L4_TIM1_CCMR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR1_OFFSET) -#define STM32L4_TIM1_CCMR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR2_OFFSET) -#define STM32L4_TIM1_CCER (STM32L4_TIM1_BASE+STM32L4_ATIM_CCER_OFFSET) -#define STM32L4_TIM1_CNT (STM32L4_TIM1_BASE+STM32L4_ATIM_CNT_OFFSET) -#define STM32L4_TIM1_PSC (STM32L4_TIM1_BASE+STM32L4_ATIM_PSC_OFFSET) -#define STM32L4_TIM1_ARR (STM32L4_TIM1_BASE+STM32L4_ATIM_ARR_OFFSET) -#define STM32L4_TIM1_RCR (STM32L4_TIM1_BASE+STM32L4_ATIM_RCR_OFFSET) -#define STM32L4_TIM1_CCR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR1_OFFSET) -#define STM32L4_TIM1_CCR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR2_OFFSET) -#define STM32L4_TIM1_CCR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR3_OFFSET) -#define STM32L4_TIM1_CCR4 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR4_OFFSET) -#define STM32L4_TIM1_BDTR (STM32L4_TIM1_BASE+STM32L4_ATIM_BDTR_OFFSET) -#define STM32L4_TIM1_DCR (STM32L4_TIM1_BASE+STM32L4_ATIM_DCR_OFFSET) -#define STM32L4_TIM1_DMAR (STM32L4_TIM1_BASE+STM32L4_ATIM_DMAR_OFFSET) -#define STM32L4_TIM1_OR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR1_OFFSET) -#define STM32L4_TIM1_CCMR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR3_OFFSET) -#define STM32L4_TIM1_CCR5 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR5_OFFSET) -#define STM32L4_TIM1_CCR6 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR6_OFFSET) -#define STM32L4_TIM1_OR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR2_OFFSET) -#define STM32L4_TIM1_OR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR3_OFFSET) - -#define STM32L4_TIM8_CR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR1_OFFSET) -#define STM32L4_TIM8_CR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR2_OFFSET) -#define STM32L4_TIM8_SMCR (STM32L4_TIM8_BASE+STM32L4_ATIM_SMCR_OFFSET) -#define STM32L4_TIM8_DIER (STM32L4_TIM8_BASE+STM32L4_ATIM_DIER_OFFSET) -#define STM32L4_TIM8_SR (STM32L4_TIM8_BASE+STM32L4_ATIM_SR_OFFSET) -#define STM32L4_TIM8_EGR (STM32L4_TIM8_BASE+STM32L4_ATIM_EGR_OFFSET) -#define STM32L4_TIM8_CCMR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR1_OFFSET) -#define STM32L4_TIM8_CCMR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR2_OFFSET) -#define STM32L4_TIM8_CCER (STM32L4_TIM8_BASE+STM32L4_ATIM_CCER_OFFSET) -#define STM32L4_TIM8_CNT (STM32L4_TIM8_BASE+STM32L4_ATIM_CNT_OFFSET) -#define STM32L4_TIM8_PSC (STM32L4_TIM8_BASE+STM32L4_ATIM_PSC_OFFSET) -#define STM32L4_TIM8_ARR (STM32L4_TIM8_BASE+STM32L4_ATIM_ARR_OFFSET) -#define STM32L4_TIM8_RCR (STM32L4_TIM8_BASE+STM32L4_ATIM_RCR_OFFSET) -#define STM32L4_TIM8_CCR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR1_OFFSET) -#define STM32L4_TIM8_CCR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR2_OFFSET) -#define STM32L4_TIM8_CCR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR3_OFFSET) -#define STM32L4_TIM8_CCR4 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR4_OFFSET) -#define STM32L4_TIM8_BDTR (STM32L4_TIM8_BASE+STM32L4_ATIM_BDTR_OFFSET) -#define STM32L4_TIM8_DCR (STM32L4_TIM8_BASE+STM32L4_ATIM_DCR_OFFSET) -#define STM32L4_TIM8_DMAR (STM32L4_TIM8_BASE+STM32L4_ATIM_DMAR_OFFSET) -#define STM32L4_TIM8_OR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR1_OFFSET) -#define STM32L4_TIM8_CCMR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR3_OFFSET) -#define STM32L4_TIM8_CCR5 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR5_OFFSET) -#define STM32L4_TIM8_CCR6 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR6_OFFSET) -#define STM32L4_TIM8_OR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR2_OFFSET) -#define STM32L4_TIM8_OR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE+STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L4_TIM2_CR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM2_CR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM2_SMCR (STM32L4_TIM2_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM2_DIER (STM32L4_TIM2_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM2_SR (STM32L4_TIM2_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM2_EGR (STM32L4_TIM2_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM2_CCMR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM2_CCMR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM2_CCER (STM32L4_TIM2_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM2_CNT (STM32L4_TIM2_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM2_PSC (STM32L4_TIM2_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM2_ARR (STM32L4_TIM2_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM2_CCR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM2_CCR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM2_CCR3 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM2_CCR4 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM2_DCR (STM32L4_TIM2_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM2_DMAR (STM32L4_TIM2_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM2_OR (STM32L4_TIM2_BASE+STM32L4_GTIM_OR_OFFSET) - -#define STM32L4_TIM3_CR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM3_CR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM3_SMCR (STM32L4_TIM3_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM3_DIER (STM32L4_TIM3_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM3_SR (STM32L4_TIM3_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM3_EGR (STM32L4_TIM3_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM3_CCMR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM3_CCMR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM3_CCER (STM32L4_TIM3_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM3_CNT (STM32L4_TIM3_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM3_PSC (STM32L4_TIM3_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM3_ARR (STM32L4_TIM3_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM3_CCR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM3_CCR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM3_CCR3 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM3_CCR4 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM3_DCR (STM32L4_TIM3_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM3_DMAR (STM32L4_TIM3_BASE+STM32L4_GTIM_DMAR_OFFSET) - -#define STM32L4_TIM4_CR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM4_CR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM4_SMCR (STM32L4_TIM4_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM4_DIER (STM32L4_TIM4_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM4_SR (STM32L4_TIM4_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM4_EGR (STM32L4_TIM4_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM4_CCMR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM4_CCMR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM4_CCER (STM32L4_TIM4_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM4_CNT (STM32L4_TIM4_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM4_PSC (STM32L4_TIM4_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM4_ARR (STM32L4_TIM4_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM4_CCR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM4_CCR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM4_CCR3 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM4_CCR4 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM4_DCR (STM32L4_TIM4_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM4_DMAR (STM32L4_TIM4_BASE+STM32L4_GTIM_DMAR_OFFSET) - -#define STM32L4_TIM5_CR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM5_CR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM5_SMCR (STM32L4_TIM5_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM5_DIER (STM32L4_TIM5_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM5_SR (STM32L4_TIM5_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM5_EGR (STM32L4_TIM5_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM5_CCMR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM5_CCMR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM5_CCER (STM32L4_TIM5_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM5_CNT (STM32L4_TIM5_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM5_PSC (STM32L4_TIM5_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM5_ARR (STM32L4_TIM5_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM5_CCR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM5_CCR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM5_CCR3 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM5_CCR4 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM5_DCR (STM32L4_TIM5_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM5_DMAR (STM32L4_TIM5_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM5_OR (STM32L4_TIM5_BASE+STM32L4_GTIM_OR_OFFSET) - -#define STM32L4_TIM15_CR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM15_CR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM15_SMCR (STM32L4_TIM15_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM15_DIER (STM32L4_TIM15_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM15_SR (STM32L4_TIM15_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM15_EGR (STM32L4_TIM15_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM15_CCMR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM15_CCER (STM32L4_TIM15_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM15_CNT (STM32L4_TIM15_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM15_PSC (STM32L4_TIM15_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM15_ARR (STM32L4_TIM15_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM15_RCR (STM32L4_TIM15_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM15_CCR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM15_CCR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM15_BDTR (STM32L4_TIM15_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM15_DCR (STM32L4_TIM15_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM15_DMAR (STM32L4_TIM15_BASE+STM32L4_GTIM_DMAR_OFFSET) - -#define STM32L4_TIM16_CR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM16_CR2 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM16_DIER (STM32L4_TIM16_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM16_SR (STM32L4_TIM16_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM16_EGR (STM32L4_TIM16_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM16_CCMR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM16_CCER (STM32L4_TIM16_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM16_CNT (STM32L4_TIM16_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM16_PSC (STM32L4_TIM16_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM16_ARR (STM32L4_TIM16_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM16_RCR (STM32L4_TIM16_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM16_CCR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM16_BDTR (STM32L4_TIM16_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM16_DCR (STM32L4_TIM16_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM16_DMAR (STM32L4_TIM16_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM16_OR (STM32L4_TIM16_BASE+STM32L4_GTIM_OR_OFFSET) - -#define STM32L4_TIM17_CR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM17_CR2 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM17_DIER (STM32L4_TIM17_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM17_SR (STM32L4_TIM17_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM17_EGR (STM32L4_TIM17_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM17_CCMR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM17_CCER (STM32L4_TIM17_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM17_CNT (STM32L4_TIM17_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM17_PSC (STM32L4_TIM17_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM17_ARR (STM32L4_TIM17_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM17_RCR (STM32L4_TIM17_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM17_CCR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM17_BDTR (STM32L4_TIM17_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM17_DCR (STM32L4_TIM17_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM17_DMAR (STM32L4_TIM17_BASE+STM32L4_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_TIM6_CR1 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR1_OFFSET) -#define STM32L4_TIM6_CR2 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR2_OFFSET) -#define STM32L4_TIM6_DIER (STM32L4_TIM6_BASE+STM32L4_BTIM_DIER_OFFSET) -#define STM32L4_TIM6_SR (STM32L4_TIM6_BASE+STM32L4_BTIM_SR_OFFSET) -#define STM32L4_TIM6_EGR (STM32L4_TIM6_BASE+STM32L4_BTIM_EGR_OFFSET) -#define STM32L4_TIM6_CNT (STM32L4_TIM6_BASE+STM32L4_BTIM_CNT_OFFSET) -#define STM32L4_TIM6_PSC (STM32L4_TIM6_BASE+STM32L4_BTIM_PSC_OFFSET) -#define STM32L4_TIM6_ARR (STM32L4_TIM6_BASE+STM32L4_BTIM_ARR_OFFSET) - -#define STM32L4_TIM7_CR1 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR1_OFFSET) -#define STM32L4_TIM7_CR2 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR2_OFFSET) -#define STM32L4_TIM7_DIER (STM32L4_TIM7_BASE+STM32L4_BTIM_DIER_OFFSET) -#define STM32L4_TIM7_SR (STM32L4_TIM7_BASE+STM32L4_BTIM_SR_OFFSET) -#define STM32L4_TIM7_EGR (STM32L4_TIM7_BASE+STM32L4_BTIM_EGR_OFFSET) -#define STM32L4_TIM7_CNT (STM32L4_TIM7_BASE+STM32L4_BTIM_CNT_OFFSET) -#define STM32L4_TIM7_PSC (STM32L4_TIM7_BASE+STM32L4_BTIM_PSC_OFFSET) -#define STM32L4_TIM7_ARR (STM32L4_TIM7_BASE+STM32L4_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h index c904dba002a48..d2d43e82eb0c6 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h @@ -37,88 +37,88 @@ /* Register Offsets *********************************************************/ -#define STM32L4_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32L4_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32L4_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32L4_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32L4_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32L4_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32L4_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32L4_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32L4_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32L4_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32L4_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ /* Register Addresses *******************************************************/ -#if STM32L4_NUSART > 0 -# define STM32L4_USART1_CR1 (STM32L4_USART1_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART1_CR2 (STM32L4_USART1_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART1_CR3 (STM32L4_USART1_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART1_BRR (STM32L4_USART1_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART1_GTPR (STM32L4_USART1_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART1_RTOR (STM32L4_USART1_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART1_RQR (STM32L4_USART1_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART1_ISR (STM32L4_USART1_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART1_ICR (STM32L4_USART1_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART1_RDR (STM32L4_USART1_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART1_TDR (STM32L4_USART1_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 1 -# define STM32L4_USART2_CR1 (STM32L4_USART2_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART2_CR2 (STM32L4_USART2_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART2_CR3 (STM32L4_USART2_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART2_BRR (STM32L4_USART2_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART2_GTPR (STM32L4_USART2_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART2_RTOR (STM32L4_USART2_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART2_RQR (STM32L4_USART2_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART2_ISR (STM32L4_USART2_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART2_ICR (STM32L4_USART2_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART2_RDR (STM32L4_USART2_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART2_TDR (STM32L4_USART2_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 2 -# define STM32L4_USART3_CR1 (STM32L4_USART3_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART3_CR2 (STM32L4_USART3_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART3_CR3 (STM32L4_USART3_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART3_BRR (STM32L4_USART3_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART3_GTPR (STM32L4_USART3_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART3_RTOR (STM32L4_USART3_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART3_RQR (STM32L4_USART3_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART3_ISR (STM32L4_USART3_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART3_ICR (STM32L4_USART3_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART3_RDR (STM32L4_USART3_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART3_TDR (STM32L4_USART3_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 3 -# define STM32L4_UART4_CR1 (STM32L4_UART4_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_UART4_CR2 (STM32L4_UART4_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_UART4_CR3 (STM32L4_UART4_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_UART4_BRR (STM32L4_UART4_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_UART4_GTPR (STM32L4_UART4_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_UART4_RTOR (STM32L4_UART4_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_UART4_RQR (STM32L4_UART4_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_UART4_ISR (STM32L4_UART4_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_UART4_ICR (STM32L4_UART4_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_UART4_RDR (STM32L4_UART4_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_UART4_TDR (STM32L4_UART4_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 3 +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 4 -# define STM32L4_UART5_CR1 (STM32L4_UART5_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_UART5_CR2 (STM32L4_UART5_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_UART5_CR3 (STM32L4_UART5_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_UART5_BRR (STM32L4_UART5_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_UART5_GTPR (STM32L4_UART5_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_UART5_RTOR (STM32L4_UART5_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_UART5_RQR (STM32L4_UART5_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_UART5_ISR (STM32L4_UART5_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_UART5_ICR (STM32L4_UART5_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_UART5_RDR (STM32L4_UART5_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_UART5_TDR (STM32L4_UART5_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 4 +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h index acea9cc7e31e9..1fdac887f955e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h @@ -40,71 +40,71 @@ /* Endpoint Registers */ -#define STM32L4_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ +#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ -#define STM32L4_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ -#define STM32L4_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ -#define STM32L4_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ -#define STM32L4_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ -#define STM32L4_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ -#define STM32L4_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ -#define STM32L4_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ -#define STM32L4_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ +#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ +#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ +#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ +#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ +#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ +#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ +#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ +#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ /* Common Registers */ -#define STM32L4_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ -#define STM32L4_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ -#define STM32L4_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ -#define STM32L4_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ -#define STM32L4_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ -#define STM32L4_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ -#define STM32L4_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ +#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ +#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ +#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ +#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ +#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ +#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ +#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ /* Buffer Descriptor Table (Relatative to BTABLE address) */ -#define STM32L4_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ -#define STM32L4_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ -#define STM32L4_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ -#define STM32L4_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ +#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ +#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ +#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ +#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ -#define STM32L4_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32L4_USB_BTABLE) + ((ep) << 3)) + (o)) -#define STM32L4_USB_ADDR_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET) -#define STM32L4_USB_COUNT_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET) -#define STM32L4_USB_ADDR_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET) -#define STM32L4_USB_COUNT_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) +#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Addresses *******************************************************/ /* Endpoint Registers */ -#define STM32L4_USB_EPR(n) (STM32L4_USB_FS_BASE + STM32L4_USB_EPR_OFFSET(n)) -#define STM32L4_USB_EP0R (STM32L4_USB_FS_BASE + STM32L4_USB_EP0R_OFFSET) -#define STM32L4_USB_EP1R (STM32L4_USB_FS_BASE + STM32L4_USB_EP1R_OFFSET) -#define STM32L4_USB_EP2R (STM32L4_USB_FS_BASE + STM32L4_USB_EP2R_OFFSET) -#define STM32L4_USB_EP3R (STM32L4_USB_FS_BASE + STM32L4_USB_EP3R_OFFSET) -#define STM32L4_USB_EP4R (STM32L4_USB_FS_BASE + STM32L4_USB_EP4R_OFFSET) -#define STM32L4_USB_EP5R (STM32L4_USB_FS_BASE + STM32L4_USB_EP5R_OFFSET) -#define STM32L4_USB_EP6R (STM32L4_USB_FS_BASE + STM32L4_USB_EP6R_OFFSET) -#define STM32L4_USB_EP7R (STM32L4_USB_FS_BASE + STM32L4_USB_EP7R_OFFSET) +#define STM32_USB_EPR(n) (STM32_USB_FS_BASE + STM32_USB_EPR_OFFSET(n)) +#define STM32_USB_EP0R (STM32_USB_FS_BASE + STM32_USB_EP0R_OFFSET) +#define STM32_USB_EP1R (STM32_USB_FS_BASE + STM32_USB_EP1R_OFFSET) +#define STM32_USB_EP2R (STM32_USB_FS_BASE + STM32_USB_EP2R_OFFSET) +#define STM32_USB_EP3R (STM32_USB_FS_BASE + STM32_USB_EP3R_OFFSET) +#define STM32_USB_EP4R (STM32_USB_FS_BASE + STM32_USB_EP4R_OFFSET) +#define STM32_USB_EP5R (STM32_USB_FS_BASE + STM32_USB_EP5R_OFFSET) +#define STM32_USB_EP6R (STM32_USB_FS_BASE + STM32_USB_EP6R_OFFSET) +#define STM32_USB_EP7R (STM32_USB_FS_BASE + STM32_USB_EP7R_OFFSET) /* Common Registers */ -#define STM32L4_USB_CNTR (STM32L4_USB_FS_BASE + STM32L4_USB_CNTR_OFFSET) -#define STM32L4_USB_ISTR (STM32L4_USB_FS_BASE + STM32L4_USB_ISTR_OFFSET) -#define STM32L4_USB_FNR (STM32L4_USB_FS_BASE + STM32L4_USB_FNR_OFFSET) -#define STM32L4_USB_DADDR (STM32L4_USB_FS_BASE + STM32L4_USB_DADDR_OFFSET) -#define STM32L4_USB_BTABLE (STM32L4_USB_FS_BASE + STM32L4_USB_BTABLE_OFFSET) -#define STM32L4_USB_LPMCSR (STM32L4_USB_FS_BASE + STM32L4_USB_LPMCSR_OFFSET) -#define STM32L4_USB_BCDR (STM32L4_USB_FS_BASE + STM32L4_USB_BCDR_OFFSET) +#define STM32_USB_CNTR (STM32_USB_FS_BASE + STM32_USB_CNTR_OFFSET) +#define STM32_USB_ISTR (STM32_USB_FS_BASE + STM32_USB_ISTR_OFFSET) +#define STM32_USB_FNR (STM32_USB_FS_BASE + STM32_USB_FNR_OFFSET) +#define STM32_USB_DADDR (STM32_USB_FS_BASE + STM32_USB_DADDR_OFFSET) +#define STM32_USB_BTABLE (STM32_USB_FS_BASE + STM32_USB_BTABLE_OFFSET) +#define STM32_USB_LPMCSR (STM32_USB_FS_BASE + STM32_USB_LPMCSR_OFFSET) +#define STM32_USB_BCDR (STM32_USB_FS_BASE + STM32_USB_BCDR_OFFSET) /* Buffer Descriptor Table (Relatative to BTABLE address) */ -#define STM32L4_USB_BTABLE_ADDR(ep,o) (STM32L4_USB_SRAM_BASE + STM32L4_USB_BTABLE_RADDR(ep,o)) -#define STM32L4_USB_ADDR_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET) -#define STM32L4_USB_COUNT_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET) -#define STM32L4_USB_ADDR_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET) -#define STM32L4_USB_COUNT_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USB_SRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o)) +#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h index 335086592073e..1ceca936c5588 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h @@ -37,27 +37,27 @@ /* Register Offsets *********************************************************/ -#define STM32L4_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ -#define STM32L4_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ -#define STM32L4_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ -#define STM32L4_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ -#define STM32L4_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ +#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ +#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ +#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ +#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ +#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ -#define STM32L4_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ -#define STM32L4_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ -#define STM32L4_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ +#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ +#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ +#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ /* Register Addresses *******************************************************/ -#define STM32L4_IWDG_KR (STM32L4_IWDG_BASE+STM32L4_IWDG_KR_OFFSET) -#define STM32L4_IWDG_PR (STM32L4_IWDG_BASE+STM32L4_IWDG_PR_OFFSET) -#define STM32L4_IWDG_RLR (STM32L4_IWDG_BASE+STM32L4_IWDG_RLR_OFFSET) -#define STM32L4_IWDG_SR (STM32L4_IWDG_BASE+STM32L4_IWDG_SR_OFFSET) -#define STM32L4_IWDG_WINR (STM32L4_IWDG_BASE+STM32L4_IWDG_WINR_OFFSET) +#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET) +#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) +#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) +#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) +#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) -#define STM32L4_WWDG_CR (STM32L4_WWDG_BASE+STM32L4_WWDG_CR_OFFSET) -#define STM32L4_WWDG_CFR (STM32L4_WWDG_BASE+STM32L4_WWDG_CFR_OFFSET) -#define STM32L4_WWDG_SR (STM32L4_WWDG_BASE+STM32L4_WWDG_SR_OFFSET) +#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) +#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) +#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h index bc4070f7dfcb0..587031ae9344a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -277,21 +277,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) - -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -306,145 +306,145 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) /* AES */ -#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6) -#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6) -#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6) -#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6) +#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DCMI */ -#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4) -#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0) +#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4) +#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) -#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0) -#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0) +#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0) +#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h index 153953e705af3..7aa56323221ea 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h index 73fcb283519c8..f7951f4ed794c 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h index 968eddee74915..94a366dbf5148 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h @@ -38,33 +38,33 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h index b56cb00fc7035..0ff70f0abf297 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -277,21 +277,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) - -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -306,167 +306,167 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) -#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0) +#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) -#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0) +#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) -#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 3) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 3) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) - -#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6) -#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6) -#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6) -#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6) - -#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5) -#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5) -#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) -#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) - -#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7) -#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7) -#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) -#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) - -#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) -#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) + +#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) + +#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2) -#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2) +#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h index 6ca4fea84720a..df83782f5a863 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h index 9ca5ed2dbecc6..7e78f15e1711e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h @@ -48,182 +48,182 @@ /* Core global control and status registers */ -#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ -#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ -#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ -#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ +#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ +#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ +#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ +#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ -#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ +#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ +#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ -#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ -#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ +#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ +#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ -#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ +#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) /* Register Addresses *******************************************************/ -#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET) -#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET) -#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET) -#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET) -#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET) -#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET) -#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET) -#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET) -#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET) -#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET) -#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET) -#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET) -#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET) -#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET) -#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET) -#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET) -#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET) -#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET) - -#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n)) +#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) +#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) +#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) +#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) +#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) +#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) +#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) +#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) +#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) +#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) +#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) +#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) +#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) +#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) +#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) +#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET) +#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET) +#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET) +#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) + +#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET) -#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET) -#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET) -#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET) -#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET) -#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET) -#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET) +#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) +#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) +#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) +#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) +#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) +#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) +#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) -#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n)) +#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) -#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n)) +#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n)) +#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n)) +#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n)) +#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET) -#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET) -#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET) -#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET) -#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET) -#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET) -#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET) -#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET) -#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET) -#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET) +#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) +#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) +#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) +#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) +#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) +#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) +#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) +#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) +#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) +#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) -#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n)) +#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) -#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n)) +#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n)) +#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n)) +#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n)) +#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) -#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n)) +#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n)) +#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET) +#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n)) +#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) /* Register Bitfield Definitions ********************************************/ @@ -741,7 +741,7 @@ #define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0 #define OTGFS_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: XXX */ #define OTGFS_DSTS_DEVLNSTS_MASK (0x3 << OTGFS_DSTS_DEVLNSTS_SHIFT) - /* Bits 24-31: Reserved, must be kept at reset value */ + /* Bits 24-31: Reserved, must be kept at reset value */ /* Device IN endpoint common interrupt mask register */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h index 218ac07c4bb84..c3c76f22cb69e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h @@ -37,69 +37,69 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h index c092d69675ac4..20d9addcad042 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h @@ -38,33 +38,33 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h index 48c9a9d1d99d5..f0dbeddab006f 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -276,21 +276,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) - -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -305,186 +305,186 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) -#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0) +#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) -#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0) +#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) /* AES */ -#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6) -#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6) -#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6) -#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6) +#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DCMI */ -#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4) -#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0) +#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4) +#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) -#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0) /* HASH */ -#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 6) +#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32_DMA2_CHAN7, 6) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) -#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0) -#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0) +#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0) +#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) - -#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6) -#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6) -#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6) -#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6) - -#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5) -#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5) -#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) -#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) - -#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7) -#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7) -#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) -#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) - -#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) -#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) + +#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) + +#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2) -#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2) +#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h index 4272f345b7604..19df3fe795c58 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h index 12288d4b39f99..c92296e69f669 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h @@ -48,182 +48,182 @@ /* Core global control and status registers */ -#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ -#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ -#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ -#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ +#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ +#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ +#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ +#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ -#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ +#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ +#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ -#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ -#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ +#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ +#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ -#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ +#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) /* Register Addresses *******************************************************/ -#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET) -#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET) -#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET) -#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET) -#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET) -#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET) -#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET) -#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET) -#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET) -#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET) -#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET) -#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET) -#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET) -#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET) -#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET) -#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET) -#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET) -#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET) - -#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n)) +#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) +#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) +#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) +#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) +#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) +#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) +#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) +#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) +#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) +#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) +#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) +#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) +#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) +#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) +#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) +#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET) +#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET) +#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET) +#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) + +#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET) -#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET) -#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET) -#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET) -#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET) -#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET) -#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET) +#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) +#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) +#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) +#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) +#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) +#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) +#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) -#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n)) +#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) -#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n)) +#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n)) +#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n)) +#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n)) +#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET) -#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET) -#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET) -#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET) -#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET) -#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET) -#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET) -#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET) -#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET) -#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET) +#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) +#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) +#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) +#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) +#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) +#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) +#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) +#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) +#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) +#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) -#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n)) +#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) -#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n)) +#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n)) +#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n)) +#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n)) +#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) -#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n)) +#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n)) +#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET) +#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n)) +#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h index 991c15297562a..73d2f0b9785c6 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h index 1bf04c71f6e05..9819f2a7eb13a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h @@ -38,35 +38,35 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) -#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h index 8229ac0413c8d..5f32ee5ef75d1 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h @@ -41,139 +41,139 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h index c0572faa6bccd..19a79a36e07e7 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h @@ -39,64 +39,65 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32L4_DMAMUX_C0CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(0) -#define STM32L4_DMAMUX_C1CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(1) -#define STM32L4_DMAMUX_C2CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(2) -#define STM32L4_DMAMUX_C3CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(3) -#define STM32L4_DMAMUX_C4CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(4) -#define STM32L4_DMAMUX_C5CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(5) -#define STM32L4_DMAMUX_C6CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(6) -#define STM32L4_DMAMUX_C7CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(7) -#define STM32L4_DMAMUX_C8CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(8) -#define STM32L4_DMAMUX_C9CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(9) -#define STM32L4_DMAMUX_C10CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(10) -#define STM32L4_DMAMUX_C11CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(11) -#define STM32L4_DMAMUX_C12CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(12) -#define STM32L4_DMAMUX_C13CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(13) - /* 0x034-0x07C: Reserved */ -#define STM32L4_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32L4_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ - -#define STM32L4_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ -#define STM32L4_DMAMUX_RG0CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(0) -#define STM32L4_DMAMUX_RG1CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(1) -#define STM32L4_DMAMUX_RG2CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(2) -#define STM32L4_DMAMUX_RG3CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(3) -#define STM32L4_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32L4_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3FC: Reserved */ +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) +/* 0x034-0x07C: Reserved */ + +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ + +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3FC: Reserved */ /* Register Addresses *******************************************************/ -#define STM32L4_DMAMUX1_CXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CXCR_OFFSET(x)) -#define STM32L4_DMAMUX1_C0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C0CR_OFFSET) -#define STM32L4_DMAMUX1_C1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C1CR_OFFSET) -#define STM32L4_DMAMUX1_C2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C2CR_OFFSET) -#define STM32L4_DMAMUX1_C3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C3CR_OFFSET) -#define STM32L4_DMAMUX1_C4CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C4CR_OFFSET) -#define STM32L4_DMAMUX1_C5CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C5CR_OFFSET) -#define STM32L4_DMAMUX1_C6CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C6CR_OFFSET) -#define STM32L4_DMAMUX1_C7CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C7CR_OFFSET) -#define STM32L4_DMAMUX1_C8CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C8CR_OFFSET) -#define STM32L4_DMAMUX1_C9CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C9CR_OFFSET) -#define STM32L4_DMAMUX1_C10CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C10CR_OFFSET) -#define STM32L4_DMAMUX1_C11CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C11CR_OFFSET) -#define STM32L4_DMAMUX1_C12CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C12CR_OFFSET) -#define STM32L4_DMAMUX1_C13CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C13CR_OFFSET) - -#define STM32L4_DMAMUX1_CSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CSR_OFFSET) -#define STM32L4_DMAMUX1_CFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CFR_OFFSET) - -#define STM32L4_DMAMUX1_RGXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGXCR_OFFSET(x)) -#define STM32L4_DMAMUX1_RG0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG0CR_OFFSET) -#define STM32L4_DMAMUX1_RG1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG1CR_OFFSET) -#define STM32L4_DMAMUX1_RG2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG2CR_OFFSET) -#define STM32L4_DMAMUX1_RG3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG3CR_OFFSET) - -#define STM32L4_DMAMUX1_RGSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGSR_OFFSET) -#define STM32L4_DMAMUX1_RGCFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGCFR_OFFSET) +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C13CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h index 9c2f082d507b5..d6b0830307809 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h index c2bc0db32bc09..ecc515f114133 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h index d95a8e753639d..4d3b2cad34147 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h @@ -38,35 +38,35 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) -#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c index 21f9264bc5289..2a4ff88f8f5e7 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ b/arch/arm/src/stm32l4/stm32l4_1wire.c @@ -176,10 +176,10 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, static const struct stm32_1wire_config_s stm32_1wire1_config = { - .usartbase = STM32L4_USART1_BASE, - .apbclock = STM32L4_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), - .irq = STM32L4_IRQ_USART1, + .irq = STM32_IRQ_USART1, }; static struct stm32_1wire_priv_s stm32_1wire1_priv = @@ -200,10 +200,10 @@ static struct stm32_1wire_priv_s stm32_1wire1_priv = static const struct stm32_1wire_config_s stm32_1wire2_config = { - .usartbase = STM32L4_USART2_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), - .irq = STM32L4_IRQ_USART2, + .irq = STM32_IRQ_USART2, }; static struct stm32_1wire_priv_s stm32_1wire2_priv = @@ -224,10 +224,10 @@ static struct stm32_1wire_priv_s stm32_1wire2_priv = static const struct stm32_1wire_config_s stm32_1wire3_config = { - .usartbase = STM32L4_USART3_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), - .irq = STM32L4_IRQ_USART3, + .irq = STM32_IRQ_USART3, }; static struct stm32_1wire_priv_s stm32_1wire3_priv = @@ -248,10 +248,10 @@ static struct stm32_1wire_priv_s stm32_1wire3_priv = static const struct stm32_1wire_config_s stm32_1wire4_config = { - .usartbase = STM32L4_UART4_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), - .irq = STM32L4_IRQ_UART4, + .irq = STM32_IRQ_UART4, }; static struct stm32_1wire_priv_s stm32_1wire4_priv = @@ -272,10 +272,10 @@ static struct stm32_1wire_priv_s stm32_1wire4_priv = static const struct stm32_1wire_config_s stm32_1wire5_config = { - .usartbase = STM32L4_UART5_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), - .irq = STM32L4_IRQ_UART5, + .irq = STM32_IRQ_UART5, }; static struct stm32_1wire_priv_s stm32_1wire5_priv = @@ -338,7 +338,7 @@ static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) { - return stm32_1wire_in(priv, STM32L4_USART_RDR_OFFSET) & 0xff; + return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; } /**************************************************************************** @@ -351,7 +351,7 @@ static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) { - stm32_1wire_out(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); + stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); } /**************************************************************************** @@ -377,13 +377,13 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) * for baud changing. */ - cr1 = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); enabled = cr1 & USART_CR1_UE; if (enabled) { cr1 &= ~USART_CR1_UE; - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); } /* In case of oversampling by 8, the equation is: @@ -428,12 +428,12 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) cr1 |= USART_CR1_OVER8; } - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1); - stm32_1wire_out(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); if (enabled) { - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1 | USART_CR1_UE); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_UE); } } @@ -464,37 +464,37 @@ static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, return; #ifdef CONFIG_STM32L4_USART1_1WIREDRIVER - case STM32L4_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif #ifdef CONFIG_STM32L4_USART2_1WIREDRIVER - case STM32L4_USART2_BASE: + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_USART3_1WIREDRIVER - case STM32L4_USART3_BASE: + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_UART4_1WIREDRIVER - case STM32L4_UART4_BASE: + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_UART5_1WIREDRIVER - case STM32L4_UART5_BASE: + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -534,33 +534,33 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) * Set LBDIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); regval |= USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 * Clear TE, REm, all interrupt enable bits, PCE, PS and M * Set RXNEIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); regval |= USART_CR1_RXNEIE; - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 * Clear CTSE, RTSE, and all interrupt enable bits * Set ONEBIT, HDSEL and EIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); /* Set baud rate */ @@ -569,9 +569,9 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) /* Enable Rx, Tx, and the USART */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Configure pins for USART use */ @@ -608,21 +608,21 @@ static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) /* Disable RXNEIE, Rx, Tx, and the USART */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Clear LBDIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); regval &= ~USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); /* Clear ONEBIT, HDSEL and EIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); /* Disable USART APB1/2 clock */ @@ -765,7 +765,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) /* Get the masked USART status word. */ - sr = stm32_1wire_in(priv, STM32L4_USART_ISR_OFFSET); + sr = stm32_1wire_in(priv, STM32_USART_ISR_OFFSET); /* Receive loop */ @@ -858,7 +858,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); if (priv->msgs != NULL) @@ -873,7 +873,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) if ((sr & USART_ISR_LBDF) != 0) { - stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, USART_ICR_LBDCF); + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF); if (priv->msgs != NULL) { diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index d6f484eed911f..52d7977f353c6 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -81,7 +81,7 @@ /* RCC reset ****************************************************************/ -#define STM32L4_RCC_RSTR STM32L4_RCC_AHB2RSTR +#define STM32_RCC_RSTR STM32_RCC_AHB2RSTR #define RCC_RSTR_ADC1RST RCC_AHB2RSTR_ADCRST #define RCC_RSTR_ADC2RST RCC_AHB2RSTR_ADCRST #define RCC_RSTR_ADC3RST RCC_AHB2RSTR_ADCRST @@ -89,7 +89,7 @@ /* ADC interrupts ***********************************************************/ #if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_IRQ_ADC12 STM32L4_IRQ_ADC1 +# define STM32_IRQ_ADC12 STM32_IRQ_ADC1 #endif /* ADC Channels/DMA *********************************************************/ @@ -425,14 +425,14 @@ static struct stm32_dev_s g_adcpriv1 = .llops = &g_adc_llops, #endif #ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC12, + .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #endif /* CONFIG_STM32L4_ADC_NOIRQ */ .intf = 1, #ifdef HAVE_ADC_RESOLUTION .resolution = CONFIG_STM32L4_ADC1_RESOLUTION, #endif - .base = STM32L4_ADC1_BASE, + .base = STM32_ADC1_BASE, #if defined(ADC1_HAVE_TIMER) || defined(ADC1_HAVE_EXTCFG) .extcfg = ADC1_EXTCFG_VALUE, #endif @@ -485,14 +485,14 @@ static struct stm32_dev_s g_adcpriv2 = .llops = &g_adc_llops, #endif #ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC12, + .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #endif /* CONFIG_STM32L4_ADC_NOIRQ */ .intf = 2, #ifdef HAVE_ADC_RESOLUTION .resolution = CONFIG_STM32L4_ADC2_RESOLUTION, #endif - .base = STM32L4_ADC2_BASE, + .base = STM32_ADC2_BASE, #if defined(ADC2_HAVE_TIMER) || defined(ADC2_HAVE_EXTCFG) .extcfg = ADC2_EXTCFG_VALUE, #endif @@ -545,14 +545,14 @@ static struct stm32_dev_s g_adcpriv3 = .llops = &g_adc_llops, #endif #ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC3, + .irq = STM32_IRQ_ADC3, .isr = adc3_interrupt, #endif /* CONFIG_STM32L4_ADC_NOIRQ */ .intf = 3, #ifdef HAVE_ADC_RESOLUTION .resolution = CONFIG_STM32L4_ADC3_RESOLUTION, #endif - .base = STM32L4_ADC3_BASE, + .base = STM32_ADC3_BASE, #if defined(ADC3_HAVE_TIMER) || defined(ADC3_HAVE_EXTCFG) .extcfg = ADC3_EXTCFG_VALUE, #endif @@ -771,38 +771,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) { ainfo("%s:\n", msg); ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32L4_GTIM_SR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -830,14 +830,14 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable) { /* Start the counter */ - tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } } #endif @@ -870,7 +870,7 @@ static int adc_timinit(struct stm32_dev_s *priv) uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; uint32_t channel = priv->channel - 1; /* If the timer base address is zero, then this ADC was not configured to @@ -955,30 +955,30 @@ static int adc_timinit(struct stm32_dev_s *priv) clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the ARR Preload Bit */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Set the reload and prescaler values */ - tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); /* Clear the advanced timers repetition counter in TIM1 */ - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { - tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ } /* Handle channel specific setup */ /* Assume that channel is disabled and polarity is active high */ - ccer_val = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer_val = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -995,41 +995,41 @@ static int adc_timinit(struct stm32_dev_s *priv) if (channel > 1) { - ccmr_offset = STM32L4_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = tim_getreg(priv, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; tim_putreg(priv, ccmr_offset, ccmr_orig); - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer_val); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer_val); switch (channel) { case 0: /* TIMx CC1 */ { - tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } break; case 1: /* TIMx CC2 */ { - tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } break; case 2: /* TIMx CC3 */ { - tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } break; case 3: /* TIMx CC4 */ { - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -1063,7 +1063,7 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, container_of(cb, struct stm32_dev_s, pm_callback); uint32_t regval; - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); if ((state >= PM_IDLE) && (regval & ADC_CR_ADSTART)) { return -EBUSY; @@ -1087,16 +1087,16 @@ static void adc_wdog_enable(struct stm32_dev_s *priv) /* Initialize the Analog watchdog enable */ - regval = adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CFGR_OFFSET); regval |= ADC_CFGR_AWD1EN | ADC_CFGR_CONT | ADC_CFGR_OVRMOD; - adc_putreg(priv, STM32L4_ADC_CFGR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CFGR_OFFSET, regval); /* Switch to analog watchdog interrupt */ - regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET); + regval = adc_getreg(priv, STM32_ADC_IER_OFFSET); regval |= ADC_INT_AWD1; regval &= ~ADC_INT_EOC; - adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval); + adc_putreg(priv, STM32_ADC_IER_OFFSET, regval); } /**************************************************************************** @@ -1119,7 +1119,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) ainfo("enable: %d\n", enable ? 1 : 0); - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); if (enable) { /* Start conversion of regular channels */ @@ -1133,7 +1133,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) regval |= ADC_CR_ADSTP; } - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); } #ifdef ADC_HAVE_INJECTED @@ -1162,11 +1162,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) { /* Start the conversion of regular channels */ - adc_modifyreg(priv, STM32L4_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); } else { - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); /* Is a conversion ongoing? */ @@ -1174,11 +1174,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) { /* Stop the conversion */ - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); /* Wait for the conversion to stop */ - while ((adc_getreg(priv, STM32L4_ADC_CR_OFFSET) & + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_JADSTP) != 0); } } @@ -1216,7 +1216,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) /* Set or clear the selected bit in the AHB2 reset register */ - regval = getreg32(STM32L4_RCC_AHB2RSTR); + regval = getreg32(STM32_RCC_AHB2RSTR); if (reset) { regval |= RCC_AHB2RSTR_ADCRST; @@ -1226,7 +1226,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) regval &= ~RCC_AHB2RSTR_ADCRST; } - putreg32(regval, STM32L4_RCC_AHB2RSTR); + putreg32(regval, STM32_RCC_AHB2RSTR); leave_critical_section(flags); } @@ -1247,13 +1247,13 @@ static void adc_enable(struct stm32_dev_s *priv) { uint32_t regval; - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); /* Exit deep power down mode and enable voltage regulator */ regval &= ~ADC_CR_DEEPPWD; regval |= ADC_CR_ADVREGEN; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for voltage regulator to power up */ @@ -1264,11 +1264,11 @@ static void adc_enable(struct stm32_dev_s *priv) */ regval |= ADC_CR_ADCAL; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for calibration to complete */ - while (adc_getreg(priv, STM32L4_ADC_CR_OFFSET) & ADC_CR_ADCAL); + while (adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL); /* Enable ADC * Note: ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle @@ -1277,13 +1277,13 @@ static void adc_enable(struct stm32_dev_s *priv) * ARM instructions. */ - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); regval |= ADC_CR_ADEN; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for hardware to be ready for conversions */ - while (!(adc_getreg(priv, STM32L4_ADC_ISR_OFFSET) & ADC_INT_ADRDY)); + while (!(adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ADRDY)); } /**************************************************************************** @@ -1400,7 +1400,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Set CFGR configuration */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); /* Configuration of the channel conversions */ @@ -1432,7 +1432,7 @@ static int adc_setup(struct adc_dev_s *dev) adc_internal(priv, &setbits); - stm32_modifyreg32(STM32L4_ADC_CCR, clrbits, setbits); + stm32_modifyreg32(STM32_ADC_CCR, clrbits, setbits); #ifdef ADC_HAVE_DMA if (priv->hasdma) @@ -1569,7 +1569,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable) ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); - regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET); + regval = adc_getreg(priv, STM32_ADC_IER_OFFSET); if (enable) { /* Enable end of conversion interrupt */ @@ -1592,7 +1592,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable) regval &= ~ADC_INT_MASK; } - adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval); + adc_putreg(priv, STM32_ADC_IER_OFFSET, regval); } /**************************************************************************** @@ -1615,7 +1615,7 @@ static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res) /* Modify appropriate register */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK, + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK, res << ADC_CFGR_RES_SHIFT); errout: @@ -1635,8 +1635,8 @@ static void adc_sample_time_set(struct adc_dev_s *dev) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - adc_putreg(priv, STM32L4_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); - adc_putreg(priv, STM32L4_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); } /**************************************************************************** @@ -1673,7 +1673,7 @@ static int adc_extsel_set(struct stm32_dev_s *priv, uint32_t extcfg) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); } return OK; @@ -1714,7 +1714,7 @@ static int adc_jextsel_set(struct stm32_dev_s *priv, uint32_t jextcfg) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); } return OK; @@ -1731,25 +1731,25 @@ static void adc_dumpregs(struct stm32_dev_s *priv) ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32 " CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_ISR_OFFSET), - adc_getreg(priv, STM32L4_ADC_IER_OFFSET), - adc_getreg(priv, STM32L4_ADC_CR_OFFSET), - adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET)); + adc_getreg(priv, STM32_ADC_ISR_OFFSET), + adc_getreg(priv, STM32_ADC_IER_OFFSET), + adc_getreg(priv, STM32_ADC_CR_OFFSET), + adc_getreg(priv, STM32_ADC_CFGR_OFFSET)); ainfo("SQR1: 0x%08" PRIx32 " SQR2: 0x%08" PRIx32 " SQR3: 0x%08" PRIx32 " SQR4: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_SQR1_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR2_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR3_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR4_OFFSET)); + adc_getreg(priv, STM32_ADC_SQR1_OFFSET), + adc_getreg(priv, STM32_ADC_SQR2_OFFSET), + adc_getreg(priv, STM32_ADC_SQR3_OFFSET), + adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); ainfo("SMPR1: 0x%08" PRIx32 " SMPR2: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_SMPR1_OFFSET), - adc_getreg(priv, STM32L4_ADC_SMPR2_OFFSET)); + adc_getreg(priv, STM32_ADC_SMPR1_OFFSET), + adc_getreg(priv, STM32_ADC_SMPR2_OFFSET)); #ifdef ADC_HAVE_INJECTED ainfo("JSQR: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_JSQR_OFFSET)); + adc_getreg(priv, STM32_ADC_JSQR_OFFSET)); #endif } @@ -1841,7 +1841,7 @@ static int adc_offset_set(struct stm32_dev_s *priv, goto errout; } - reg = STM32L4_ADC_OFR1_OFFSET + i * 4; + reg = STM32_ADC_OFR1_OFFSET + i * 4; regval = ADC_OFR_OFFSETY_EN; adc_putreg(priv, reg, regval); @@ -1898,23 +1898,23 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); + STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); + STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); + STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); bits = ((uint32_t)priv->rnchannels - 1) << ADC_SQR1_L_SHIFT | adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); + STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); #ifdef ADC_HAVE_DFSDM if (priv->hasdfsdm) @@ -1966,7 +1966,7 @@ static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); return OK; } @@ -2026,7 +2026,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) case ANIOC_WDOG_UPPER: /* Set watchdog upper threshold */ { - regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET); /* Verify new upper threshold greater than lower threshold */ @@ -2041,7 +2041,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) regval &= ~ADC_TR1_HT_MASK; regval |= ((arg << ADC_TR1_HT_SHIFT) & ADC_TR1_HT_MASK); - adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval); /* Ensure analog watchdog is enabled */ @@ -2051,7 +2051,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) case ANIOC_WDOG_LOWER: /* Set watchdog lower threshold */ { - regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET); /* Verify new lower threshold less than upper threshold */ @@ -2066,7 +2066,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) regval &= ~ADC_TR1_LT_MASK; regval |= ((arg << ADC_TR1_LT_SHIFT) & ADC_TR1_LT_MASK); - adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval); /* Ensure analog watchdog is enabled */ @@ -2133,7 +2133,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) if ((adcisr & ADC_INT_AWD1) != 0) { - value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET); + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); value &= ADC_DR_MASK; awarn("WARNING: Analog Watchdog, " @@ -2158,7 +2158,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * (It is cleared by reading the ADC_DR) */ - value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET); + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); value &= ADC_DR_MASK; /* Verify that the upper-half driver has bound its callback functions */ @@ -2198,7 +2198,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) { for (i = 0; i < priv->cjchannels; i++) { - value = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * i)) & + value = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * i)) & ADC_JDR_MASK; if (priv->cb != NULL) @@ -2232,7 +2232,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) uint32_t pending; #ifdef CONFIG_STM32L4_ADC1 - regval = getreg32(STM32L4_ADC1_ISR); + regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2240,12 +2240,12 @@ static int adc12_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC1_ISR); + putreg32(regval, STM32_ADC1_ISR); } #endif #ifdef CONFIG_STM32L4_ADC2 - regval = getreg32(STM32L4_ADC2_ISR); + regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2253,7 +2253,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC2_ISR); + putreg32(regval, STM32_ADC2_ISR); } #endif @@ -2279,7 +2279,7 @@ static int adc3_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_ADC3_ISR); + regval = getreg32(STM32_ADC3_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2287,7 +2287,7 @@ static int adc3_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC3_ISR); + putreg32(regval, STM32_ADC3_ISR); } return OK; @@ -2339,7 +2339,7 @@ static void adc_dma_cfg(struct stm32_dev_s *priv) /* Modify CFGR configuration */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); } /**************************************************************************** @@ -2362,7 +2362,7 @@ static void adc_dma_start(struct adc_dev_s *dev) #ifndef CONFIG_STM32L4_ADC_NOIRQ stm32l4_dmasetup(priv->dma, - priv->base + STM32L4_ADC_DR_OFFSET, + priv->base + STM32_ADC_DR_OFFSET, (uint32_t)priv->r_dmabuffer, priv->rnchannels * priv->dmabatch, ADC_DMA_CONTROL_WORD); @@ -2418,8 +2418,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, /* Restart DMA for the next conversion series */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0); - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN); } #endif #endif /* ADC_HAVE_DMA */ @@ -2437,7 +2437,7 @@ static void adc_llops_intack(struct stm32_adc_dev_s *dev, /* Clear pending interrupts */ - adc_putreg(priv, STM32L4_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); + adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); } /**************************************************************************** @@ -2451,7 +2451,7 @@ static void adc_llops_inten(struct stm32_adc_dev_s *dev, /* Enable interrupts */ - adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); } /**************************************************************************** @@ -2465,7 +2465,7 @@ static void adc_llops_intdis(struct stm32_adc_dev_s *dev, /* Disable interrupts */ - adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); } /**************************************************************************** @@ -2478,7 +2478,7 @@ static uint32_t adc_llops_intget(struct stm32_adc_dev_s *dev) uint32_t regval; uint32_t pending; - regval = adc_getreg(priv, STM32L4_ADC_ISR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); pending = regval & ADC_ISR_ALLINTS; return pending; @@ -2492,7 +2492,7 @@ static uint32_t adc_llops_regget(struct stm32_adc_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - return adc_getreg(priv, STM32L4_ADC_DR_OFFSET) & ADC_DR_MASK; + return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_MASK; } /**************************************************************************** @@ -2545,7 +2545,7 @@ static int adc_regbufregister(struct stm32_adc_dev_s *dev, struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; stm32l4_dmasetup(priv->dma, - priv->base + STM32L4_ADC_DR_OFFSET, + priv->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); @@ -2578,7 +2578,7 @@ static void adc_llops_dma_start(struct stm32_adc_dev_s *adc, dev->dma = stm32l4_dmachannel(dev->dmachan); stm32l4_dmasetup(dev->dma, - dev->base + STM32L4_ADC_DR_OFFSET, + dev->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); @@ -2639,7 +2639,7 @@ static uint32_t adc_llops_injget(struct stm32_adc_dev_s *dev, goto errout; } - regval = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * chan)) & + regval = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * chan)) & ADC_JDR_MASK; errout: diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index b2f2c16b7f997..34980e8ccb8bc 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -91,15 +91,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32L4_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32L4_ADC3 #endif -#if STM32L4_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32L4_ADC2 #endif -#if STM32L4_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32L4_ADC1 #endif @@ -178,38 +178,38 @@ #if defined(CONFIG_STM32L4_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN +# define ADC1_TIMER_BASE STM32_TIM1_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN +# define ADC1_TIMER_BASE STM32_TIM2_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN +# define ADC1_TIMER_BASE STM32_TIM3_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN +# define ADC1_TIMER_BASE STM32_TIM4_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN +# define ADC1_TIMER_BASE STM32_TIM6_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN +# define ADC1_TIMER_BASE STM32_TIM8_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN +# define ADC1_TIMER_BASE STM32_TIM15_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN #else # undef ADC1_HAVE_TIMER @@ -227,38 +227,38 @@ #if defined(CONFIG_STM32L4_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN +# define ADC2_TIMER_BASE STM32_TIM1_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN +# define ADC2_TIMER_BASE STM32_TIM2_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN +# define ADC2_TIMER_BASE STM32_TIM3_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN +# define ADC2_TIMER_BASE STM32_TIM4_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN +# define ADC2_TIMER_BASE STM32_TIM6_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN +# define ADC2_TIMER_BASE STM32_TIM8_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM15_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN +# define ADC2_TIMER_BASE STM32_TIM15_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN #else # undef ADC2_HAVE_TIMER @@ -276,38 +276,38 @@ #if defined(CONFIG_STM32L4_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM1_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN +# define ADC3_TIMER_BASE STM32_TIM1_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM2_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN +# define ADC3_TIMER_BASE STM32_TIM2_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM3_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN +# define ADC3_TIMER_BASE STM32_TIM3_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM4_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN +# define ADC3_TIMER_BASE STM32_TIM4_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM6_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN +# define ADC3_TIMER_BASE STM32_TIM6_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM8_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN +# define ADC3_TIMER_BASE STM32_TIM8_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM15_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN +# define ADC3_TIMER_BASE STM32_TIM15_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN #else # undef ADC3_HAVE_TIMER diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c index 1edbe3d122a38..3669cf0233af1 100644 --- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c +++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c @@ -96,19 +96,19 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32L4_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32L4_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ -#define SRAM2_START STM32L4_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Set the range of SRAM3, requiring a third memory region */ -#ifdef STM32L4_SRAM3_SIZE -# define SRAM3_START STM32L4_SRAM3_BASE -# define SRAM3_END (SRAM3_START + STM32L4_SRAM3_SIZE) +#ifdef STM32_SRAM3_SIZE +# define SRAM3_START STM32_SRAM3_BASE +# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 71e397a63254b..2d53c1edba865 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -181,13 +181,13 @@ static struct stm32l4_can_s g_can1priv = .port = 1, .canrx = { - STM32L4_IRQ_CAN1RX0, - STM32L4_IRQ_CAN1RX1, + STM32_IRQ_CAN1RX0, + STM32_IRQ_CAN1RX1, }, - .cantx = STM32L4_IRQ_CAN1TX, + .cantx = STM32_IRQ_CAN1TX, .filter = 0, - .base = STM32L4_CAN1_BASE, - .fbase = STM32L4_CAN1_BASE, + .base = STM32_CAN1_BASE, + .fbase = STM32_CAN1_BASE, .baud = CONFIG_STM32L4_CAN1_BAUD, }; @@ -381,18 +381,18 @@ static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, /* CAN control and status registers */ caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_MCR_OFFSET), - getreg32(priv->base + STM32L4_CAN_MSR_OFFSET), - getreg32(priv->base + STM32L4_CAN_TSR_OFFSET)); + getreg32(priv->base + STM32_CAN_MCR_OFFSET), + getreg32(priv->base + STM32_CAN_MSR_OFFSET), + getreg32(priv->base + STM32_CAN_TSR_OFFSET)); caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RF0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RF1R_OFFSET)); + getreg32(priv->base + STM32_CAN_RF0R_OFFSET), + getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_IER_OFFSET), - getreg32(priv->base + STM32L4_CAN_ESR_OFFSET), - getreg32(priv->base + STM32L4_CAN_BTR_OFFSET)); + getreg32(priv->base + STM32_CAN_IER_OFFSET), + getreg32(priv->base + STM32_CAN_ESR_OFFSET), + getreg32(priv->base + STM32_CAN_BTR_OFFSET)); } #endif @@ -427,38 +427,38 @@ static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" PRIx32 " TDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH0R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" PRIx32 " TDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH1R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" PRIx32 " TDH2R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH2R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" PRIx32 " RDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RI0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDT0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDL0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDH0R_OFFSET)); + getreg32(priv->base + STM32_CAN_RI0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" PRIx32 " RDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RI1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDT1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDL1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDH1R_OFFSET)); + getreg32(priv->base + STM32_CAN_RI1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH1R_OFFSET)); } #endif @@ -494,17 +494,17 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_FMR_OFFSET), - getreg32(priv->base + STM32L4_CAN_FM1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FS1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FFA1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FA1R_OFFSET)); + getreg32(priv->base + STM32_CAN_FMR_OFFSET), + getreg32(priv->base + STM32_CAN_FM1R_OFFSET), + getreg32(priv->base + STM32_CAN_FS1R_OFFSET), + getreg32(priv->base + STM32_CAN_FFA1R_OFFSET), + getreg32(priv->base + STM32_CAN_FA1R_OFFSET)); for (i = 0; i < CAN_NFILTERS; i++) { caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", - i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 1)), - i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 2))); + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); } } #endif @@ -555,12 +555,12 @@ static void stm32l4can_reset(struct can_dev_s *dev) /* Reset the CAN */ - regval = getreg32(STM32L4_RCC_APB1RSTR1); + regval = getreg32(STM32_RCC_APB1RSTR1); regval |= regbit; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); regval &= ~regbit; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); leave_critical_section(flags); } @@ -714,7 +714,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) /* Enable/disable the FIFO 0/1 message pending interrupt */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); if (enable) { regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1; @@ -724,7 +724,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1); } - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); } /**************************************************************************** @@ -752,9 +752,9 @@ static void stm32l4can_txint(struct can_dev_s *dev, bool enable) if (!enable) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); regval &= ~CAN_IER_TMEIE; - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); } } @@ -806,7 +806,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, uint32_t brp; DEBUGASSERT(bt != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> CAN_BTR_SJW_SHIFT) + 1; bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> @@ -815,7 +815,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, CAN_BTR_TS2_SHIFT) + 1; brp = ((regval & CAN_BTR_BRP_MASK) >> CAN_BTR_BRP_SHIFT) + 1; - bt->bt_baud = STM32L4_PCLK1_FREQUENCY / + bt->bt_baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); ret = OK; } @@ -848,18 +848,18 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, uint32_t regval; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32L4_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); /* Extract bit timing data. * tmp is in clocks per bit time. */ - tmp = STM32L4_PCLK1_FREQUENCY / bt->bt_baud; + tmp = STM32_PCLK1_FREQUENCY / bt->bt_baud; /* This value is dynamic as requested by user */ @@ -904,12 +904,12 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, break; } - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); ret = stm32l4can_exitinitmode(priv); if (ret >= 0) { - priv->baud = STM32L4_PCLK1_FREQUENCY / + priv->baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); } } @@ -934,7 +934,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, DEBUGASSERT(bm != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); bm->bm_loopback = ((regval & CAN_BTR_LBKM) == CAN_BTR_LBKM); bm->bm_silent = ((regval & CAN_BTR_SILM) == CAN_BTR_SILM); @@ -961,7 +961,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, DEBUGASSERT(bm != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); if (bm->bm_loopback) { @@ -989,7 +989,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, break; } - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); ret = stm32l4can_exitinitmode(priv); } @@ -1078,7 +1078,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_NART; @@ -1088,7 +1088,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_NART; } - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; @@ -1102,7 +1102,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_ABOM; @@ -1112,7 +1112,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_ABOM; } - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; @@ -1185,7 +1185,7 @@ static int stm32l4can_send(struct can_dev_s *dev, /* Select one empty transmit mailbox */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); if ((regval & CAN_TSR_TME0) != 0 && (regval & CAN_TSR_RQCP0) == 0) { txmb = 0; @@ -1206,10 +1206,10 @@ static int stm32l4can_send(struct can_dev_s *dev, /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); /* Set up the ID, standard 11-bit or extended 29-bit. */ @@ -1233,15 +1233,15 @@ static int stm32l4can_send(struct can_dev_s *dev, regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0); #endif #endif - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); /* Set up the DLC */ dlc = msg->cm_hdr.ch_dlc; - regval = stm32l4can_getreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb)); regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT); regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT; - stm32l4can_putreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval); /* Set up the data fields */ @@ -1272,7 +1272,7 @@ static int stm32l4can_send(struct can_dev_s *dev, } } - stm32l4can_putreg(priv, STM32L4_CAN_TDLR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval); regval = 0; if (dlc > 4) @@ -1299,19 +1299,19 @@ static int stm32l4can_send(struct can_dev_s *dev, } } - stm32l4can_putreg(priv, STM32L4_CAN_TDHR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval); /* Enable the transmit mailbox empty interrupt (may already be enabled) */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); regval |= CAN_IER_TMEIE; - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); /* Request transmission */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */ - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); stm32l4can_dumpmbregs(priv, "After send"); return OK; @@ -1338,7 +1338,7 @@ static bool stm32l4can_txready(struct can_dev_s *dev) /* Return true if any mailbox is available */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); return (regval & CAN_ALL_MAILBOXES) != 0; @@ -1369,7 +1369,7 @@ static bool stm32l4can_txempty(struct can_dev_s *dev) /* Return true if all mailboxes are available */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES; @@ -1406,7 +1406,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Verify that a message is pending in the FIFO */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; if (npending < 1) { @@ -1425,7 +1425,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Get the CAN identifier. */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RIR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb)); #ifdef CONFIG_CAN_EXTID if ((regval & CAN_RIR_IDE) != 0) @@ -1462,18 +1462,18 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Get the DLC */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDTR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb)); hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; /* Save the message data */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDLR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb)); data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDHR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb)); data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; @@ -1488,9 +1488,9 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) #ifndef CONFIG_CAN_EXTID errout: #endif - regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); regval |= CAN_RFR_RFOM; - stm32l4can_putreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb), regval); + stm32l4can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval); return ret; } @@ -1560,7 +1560,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) /* Get the transmit status */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); /* Check for RQCP0: Request completed mailbox 0 */ @@ -1570,7 +1570,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST0 and TERR0) for Mailbox 0. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP0); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0); /* Check for errors */ @@ -1590,7 +1590,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST1 and TERR1) for Mailbox 1. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP1); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1); /* Check for errors */ @@ -1610,7 +1610,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST2 and TERR2) for Mailbox 2. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP2); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2); /* Check for errors */ @@ -1690,7 +1690,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) uint32_t ts2; caninfo("CAN%d PCLK1: %d baud: %d\n", - priv->port, STM32L4_PCLK1_FREQUENCY, priv->baud); + priv->port, STM32_PCLK1_FREQUENCY, priv->baud); /* Try to get CAN_BIT_QUANTA quanta in one bit_time. * @@ -1708,7 +1708,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) * PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4 */ - tmp = STM32L4_PCLK1_FREQUENCY / priv->baud; + tmp = STM32_PCLK1_FREQUENCY / priv->baud; if (tmp < CAN_BIT_QUANTA) { /* At the smallest brp value (1), there are already too few bit times @@ -1762,7 +1762,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) tmp |= CAN_BTR_LBKM; #endif - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, tmp); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp); return OK; } @@ -1791,15 +1791,15 @@ static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) /* Enter initialization mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval |= CAN_MCR_INRQ; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Wait until initialization mode is acknowledged */ for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET); if ((regval & CAN_MSR_INAK) != 0) { /* We are in initialization mode */ @@ -1840,15 +1840,15 @@ static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv) /* Exit Initialization mode, enter Normal mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~CAN_MCR_INRQ; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Wait until the initialization mode exit is acknowledged */ for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET); if ((regval & CAN_MSR_INAK) == 0) { /* We are out of initialization mode */ @@ -1893,9 +1893,9 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) /* Exit from sleep mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~CAN_MCR_SLEEP; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); ret = stm32l4can_enterinitmode(priv); if (ret != 0) @@ -1913,10 +1913,10 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) * - Transmit FIFO priority */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM); - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Configure bit timing. */ @@ -1975,52 +1975,52 @@ static int stm32l4can_filterinit(struct stm32l4_can_s *priv) /* Enter filter initialization mode */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval |= CAN_FMR_FINIT; - stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); /* Disable the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); /* Select the 32-bit scale for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FS1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FS1R_OFFSET); regval |= bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FS1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval); /* There are 14 or 28 filter banks (depending) on the device. * Each filter bank is composed of two 32-bit registers, CAN_FiR: */ - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 1), 0); - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 2), 0); + stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0); + stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0); /* Set Id/Mask mode for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FM1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FM1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FM1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval); /* Assign FIFO 0 for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FFA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FFA1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FFA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval); /* Enable the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET); regval |= bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); /* Exit filter initialization mode */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval &= ~CAN_FMR_FINIT; - stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index 8328d9a13fb9c..2a33a504bf32a 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -42,7 +42,7 @@ /* Up to 1 CAN interfaces are supported */ -#if STM32L4_NCAN < 1 +#if STM32_NCAN < 1 # undef CONFIG_STM32L4_CAN1 #endif diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c index 6bc365394b3f1..a2af78f842101 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -104,12 +104,12 @@ static struct stm32l4_comp_config_s g_comp1priv = .rising = true, .falling = false }, - .inp = STM32L4_COMP_INP_PIN_2, - .inm = STM32L4_COMP_INM_VREF, - .hyst = STM32L4_COMP_HYST_LOW, - .speed = STM32L4_COMP_SPEED_MEDIUM, + .inp = STM32_COMP_INP_PIN_2, + .inm = STM32_COMP_INM_VREF, + .hyst = STM32_COMP_HYST_LOW, + .speed = STM32_COMP_SPEED_MEDIUM, .inverted = false, - .csr = STM32L4_COMP1_CSR, + .csr = STM32_COMP1_CSR, }; static struct comp_dev_s g_comp1dev = @@ -126,12 +126,12 @@ static struct stm32l4_comp_config_s g_comp2priv = .rising = true, .falling = false }, - .inp = STM32L4_COMP_INP_PIN_1, - .inm = STM32L4_COMP_INM_DAC_1, - .hyst = STM32L4_COMP_HYST_LOW, - .speed = STM32L4_COMP_SPEED_MEDIUM, + .inp = STM32_COMP_INP_PIN_1, + .inm = STM32_COMP_INM_DAC_1, + .hyst = STM32_COMP_HYST_LOW, + .speed = STM32_COMP_SPEED_MEDIUM, .inverted = false, - .csr = STM32L4_COMP2_CSR, + .csr = STM32_COMP2_CSR, }; static struct comp_dev_s g_comp2dev = @@ -324,7 +324,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) DEBUGASSERT(cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling)); - ainfo("isr: %d\n", (cfg->csr == STM32L4_COMP1_CSR ? 0 : 1)); + ainfo("isr: %d\n", (cfg->csr == STM32_COMP1_CSR ? 0 : 1)); cfg->interrupt.cb->au_notify(dev, comp_read(dev)); @@ -356,28 +356,28 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) int cmp; cfg = dev->ad_priv; - cmp = cfg->csr == STM32L4_COMP1_CSR ? STM32L4_COMP1 : STM32L4_COMP2; + cmp = cfg->csr == STM32_COMP1_CSR ? STM32_COMP1 : STM32_COMP2; /* Input plus */ mask |= COMP_CSR_INPSEL_MASK; switch (cfg->inp) { - case STM32L4_COMP_INP_PIN_1: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 : + case STM32_COMP_INP_PIN_1: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1); regval |= COMP_CSR_INPSEL_PIN1; break; - case STM32L4_COMP_INP_PIN_2: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 : + case STM32_COMP_INP_PIN_2: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2); regval |= COMP_CSR_INPSEL_PIN2; break; #if defined(CONFIG_STM32L4_STM32L4X3) - case STM32L4_COMP_INP_PIN_3: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 : + case STM32_COMP_INP_PIN_3: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3); regval |= COMP_CSR_INPSEL_PIN3; break; @@ -392,46 +392,46 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_INMSEL_MASK; switch (cfg->inm) { - case STM32L4_COMP_INM_1_4_VREF: + case STM32_COMP_INM_1_4_VREF: regval |= COMP_CSR_INMSEL_25PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_1_2_VREF: + case STM32_COMP_INM_1_2_VREF: regval |= COMP_CSR_INMSEL_50PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_3_4_VREF: + case STM32_COMP_INM_3_4_VREF: regval |= COMP_CSR_INMSEL_75PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_VREF: + case STM32_COMP_INM_VREF: regval |= COMP_CSR_INMSEL_VREF; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= COMP_CSR_SCALEN; break; - case STM32L4_COMP_INM_DAC_1: + case STM32_COMP_INM_DAC_1: regval |= COMP_CSR_INMSEL_DAC1; break; - case STM32L4_COMP_INM_DAC_2: + case STM32_COMP_INM_DAC_2: regval |= COMP_CSR_INMSEL_DAC2; break; - case STM32L4_COMP_INM_PIN_1: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_1 : + case STM32_COMP_INM_PIN_1: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_1 : GPIO_COMP2_INM_1); regval |= COMP_CSR_INMSEL_PIN1; break; - case STM32L4_COMP_INM_PIN_2: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 : + case STM32_COMP_INM_PIN_2: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2); #if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ defined(CONFIG_STM32L4_STM32L4XR) @@ -444,24 +444,24 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) break; #if defined(CONFIG_STM32L4_STM32L4X3) - case STM32L4_COMP_INM_PIN_3: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_3 : + case STM32_COMP_INM_PIN_3: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 : GPIO_COMP2_INM_3); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; regval |= COMP_CSR_INMESEL_PIN3; break; - case STM32L4_COMP_INM_PIN_4: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_4 : + case STM32_COMP_INM_PIN_4: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_4 : GPIO_COMP2_INM_4); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; regval |= COMP_CSR_INMESEL_PIN4; break; - case STM32L4_COMP_INM_PIN_5: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_5 : + case STM32_COMP_INM_PIN_5: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_5 : GPIO_COMP2_INM_5); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -478,19 +478,19 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_HYST_MASK; switch (cfg->hyst) { - case STM32L4_COMP_HYST_NONE: + case STM32_COMP_HYST_NONE: regval |= COMP_CSR_HYST_NONE; break; - case STM32L4_COMP_HYST_LOW: + case STM32_COMP_HYST_LOW: regval |= COMP_CSR_HYST_LOW; break; - case STM32L4_COMP_HYST_MEDIUM: + case STM32_COMP_HYST_MEDIUM: regval |= COMP_CSR_HYST_MEDIUM; break; - case STM32L4_COMP_HYST_HIGH: + case STM32_COMP_HYST_HIGH: regval |= COMP_CSR_HYST_HIGH; break; @@ -503,15 +503,15 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_PWRMODE_MASK; switch (cfg->speed) { - case STM32L4_COMP_SPEED_HIGH: + case STM32_COMP_SPEED_HIGH: regval |= COMP_CSR_PWRMODE_HIGH; break; - case STM32L4_COMP_SPEED_MEDIUM: + case STM32_COMP_SPEED_MEDIUM: regval |= COMP_CSR_PWRMODE_MEDIUM; break; - case STM32L4_COMP_SPEED_LOW: + case STM32_COMP_SPEED_LOW: regval |= COMP_CSR_PWRMODE_LOW; break; diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h index d862d14a9eef6..0414ed9f774da 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/stm32l4_comp.h @@ -56,35 +56,35 @@ enum stm32l4_comp_e { - STM32L4_COMP1, - STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32_COMP1, + STM32_COMP2, + STM32_COMP_NUM /* Number of comparators */ }; /* Plus input */ enum stm32l4_comp_inp_e { - STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ - STM32L4_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ - STM32L4_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */ + STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ + STM32_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */ }; /* Minus input */ enum stm32l4_comp_inm_e { - STM32L4_COMP_INM_1_4_VREF, - STM32L4_COMP_INM_1_2_VREF, - STM32L4_COMP_INM_3_4_VREF, - STM32L4_COMP_INM_VREF, - STM32L4_COMP_INM_DAC_1, - STM32L4_COMP_INM_DAC_2, - STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ - STM32L4_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */ - STM32L4_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */ - STM32L4_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */ - STM32L4_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ + STM32_COMP_INM_1_4_VREF, + STM32_COMP_INM_1_2_VREF, + STM32_COMP_INM_3_4_VREF, + STM32_COMP_INM_VREF, + STM32_COMP_INM_DAC_1, + STM32_COMP_INM_DAC_2, + STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */ + STM32_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */ + STM32_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */ + STM32_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ }; #else @@ -93,31 +93,31 @@ enum stm32l4_comp_inm_e enum stm32l4_comp_e { - STM32L4_COMP1, - STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32_COMP1, + STM32_COMP2, + STM32_COMP_NUM /* Number of comparators */ }; /* Plus input */ enum stm32l4_comp_inp_e { - STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ - STM32L4_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ + STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ }; /* Minus input */ enum stm32l4_comp_inm_e { - STM32L4_COMP_INM_1_4_VREF, - STM32L4_COMP_INM_1_2_VREF, - STM32L4_COMP_INM_3_4_VREF, - STM32L4_COMP_INM_VREF, - STM32L4_COMP_INM_DAC_1, - STM32L4_COMP_INM_DAC_2, - STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ - STM32L4_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */ + STM32_COMP_INM_1_4_VREF, + STM32_COMP_INM_1_2_VREF, + STM32_COMP_INM_3_4_VREF, + STM32_COMP_INM_VREF, + STM32_COMP_INM_DAC_1, + STM32_COMP_INM_DAC_2, + STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */ }; #endif @@ -125,19 +125,19 @@ enum stm32l4_comp_inm_e enum stm32l4_comp_hyst_e { - STM32L4_COMP_HYST_NONE, - STM32L4_COMP_HYST_LOW, - STM32L4_COMP_HYST_MEDIUM, - STM32L4_COMP_HYST_HIGH + STM32_COMP_HYST_NONE, + STM32_COMP_HYST_LOW, + STM32_COMP_HYST_MEDIUM, + STM32_COMP_HYST_HIGH }; /* Power/Speed Modes */ enum stm32l4_comp_speed_e { - STM32L4_COMP_SPEED_HIGH, - STM32L4_COMP_SPEED_MEDIUM, - STM32L4_COMP_SPEED_LOW + STM32_COMP_SPEED_HIGH, + STM32_COMP_SPEED_MEDIUM, + STM32_COMP_SPEED_LOW }; /* Comparator configuration *************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index a2c59beca1726..a529515e70e2a 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -55,18 +55,18 @@ /* Up to 1 DAC interface for up to 2 channels are supported */ -#if STM32L4_NDAC > 2 +#if STM32_NDAC > 2 # warning "Extra DAC channels. Only DAC1 and DAC2 are supported" #endif -#if STM32L4_NDAC < 2 +#if STM32_NDAC < 2 # undef CONFIG_STM32L4_DAC2 # undef CONFIG_STM32L4_DAC2_DMA # undef CONFIG_STM32L4_DAC2_TIMER # undef CONFIG_STM32L4_DAC2_TIMER_FREQUENCY #endif -#if STM32L4_NDAC < 1 +#if STM32_NDAC < 1 # undef CONFIG_STM32L4_DAC1 # undef CONFIG_STM32L4_DAC1_DMA # undef CONFIG_STM32L4_DAC1_TIMER @@ -178,47 +178,47 @@ # endif # define NEED_TIM6 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC1_TIMER_BASE STM32L4_TIM6_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM6_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC1_TIMER == 8 # ifndef CONFIG_STM32L4_TIM8_DAC # error "CONFIG_STM32L4_TIM8_DAC required for DAC1" # endif # define NEED_TIM8 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC1_TIMER_BASE STM32L4_TIM8_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM8_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY # elif CONFIG_STM32L4_DAC1_TIMER == 7 # ifndef CONFIG_STM32L4_TIM7_DAC # error "CONFIG_STM32L4_TIM7_DAC required for DAC1" # endif # define NEED_TIM7 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC1_TIMER_BASE STM32L4_TIM7_BASE +# define DAC1_TIMER_BASE STM32_TIM7_BASE # elif CONFIG_STM32L4_DAC1_TIMER == 5 # ifndef CONFIG_STM32L4_TIM5_DAC # error "CONFIG_STM32L4_TIM5_DAC required for DAC1" # endif # define NEED_TIM5 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC1_TIMER_BASE STM32L4_TIM5_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM5_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC1_TIMER == 2 # ifndef CONFIG_STM32L4_TIM2_DAC # error "CONFIG_STM32L4_TIM2_DAC required for DAC1" # endif # define NEED_TIM2 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC1_TIMER_BASE STM32L4_TIM2_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM2_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC1_TIMER == 4 # ifndef CONFIG_STM32L4_TIM4_DAC # error "CONFIG_STM32L4_TIM4_DAC required for DAC1" # endif # define NEED_TIM4 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC1_TIMER_BASE STM32L4_TIM4_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM4_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else # error "Unsupported CONFIG_STM32L4_DAC1_TIMER" # endif @@ -232,43 +232,43 @@ # error "CONFIG_STM32L4_TIM6_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC2_TIMER_BASE STM32L4_TIM6_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM6_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 8 # ifndef CONFIG_STM32L4_TIM8_DAC # error "CONFIG_STM32L4_TIM8_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC2_TIMER_BASE STM32L4_TIM8_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM8_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 7 # ifndef CONFIG_STM32L4_TIM7_DAC # error "CONFIG_STM32L4_TIM7_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC2_TIMER_BASE STM32L4_TIM7_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM7_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 5 # ifndef CONFIG_STM32L4_TIM5_DAC # error "CONFIG_STM32L4_TIM5_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC2_TIMER_BASE STM32L4_TIM5_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM5_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 2 # ifndef CONFIG_STM32L4_TIM2_DAC # error "CONFIG_STM32L4_TIM2_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC2_TIMER_BASE STM32L4_TIM2_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM2_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 4 # ifndef CONFIG_STM32L4_TIM4_DAC # error "CONFIG_STM32L4_TIM4_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC2_TIMER_BASE STM32L4_TIM4_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM4_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else # error "Unsupported CONFIG_STM32L4_DAC2_TIMER" # endif @@ -422,8 +422,8 @@ static struct stm32_chan_s g_dac1priv = #else .pin = GPIO_DAC1_OUT, #endif - .dro = STM32L4_DAC_DHR12R1, - .cr = STM32L4_DAC_CR, + .dro = STM32_DAC_DHR12R1, + .cr = STM32_DAC_CR, #ifdef CONFIG_STM32L4_DAC1_DMA .hasdma = 1, .dmachan = DAC1_DMA_CHAN, @@ -462,8 +462,8 @@ static struct stm32_chan_s g_dac2priv = #else .pin = GPIO_DAC2_OUT, #endif - .dro = STM32L4_DAC_DHR12R2, - .cr = STM32L4_DAC_CR, + .dro = STM32_DAC_DHR12R2, + .cr = STM32_DAC_CR, #ifdef CONFIG_STM32L4_DAC2_DMA .hasdma = 1, .dmachan = DAC2_DMA_CHAN, @@ -507,7 +507,7 @@ static struct stm32_dac_s g_dacblock; static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset) { - return getreg32(STM32L4_DAC_BASE + offset); + return getreg32(STM32_DAC_BASE + offset); } /**************************************************************************** @@ -532,7 +532,7 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, { unsigned int shift; - /* DAC channels 1 and 2 share the STM32L4_DAC[1]_CR control register. If + /* DAC channels 1 and 2 share the STM32_DAC[1]_CR control register. If * future chips have DAC channel 3 (and perhaps channel 4) they likely have * their own register like in STM32. In either case, bit 0 of the interface * number provides the correct shift. @@ -567,7 +567,7 @@ static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, { unsigned int shift; - /* DAC channels 1 and 2 share the STM32L4_DAC_MCR control register. + /* DAC channels 1 and 2 share the STM32_DAC_MCR control register. * Bit 0 of the interface number provides the correct shift. * * Bit 0 = 0: Shift = 0 @@ -575,7 +575,7 @@ static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, */ shift = (chan->intf & 1) << 4; - modifyreg32(STM32L4_DAC_MCR, clearbits << shift, setbits << shift); + modifyreg32(STM32_DAC_MCR, clearbits << shift, setbits << shift); } /**************************************************************************** @@ -588,10 +588,10 @@ static void dac_dumpregs(struct stm32_chan_s *priv) ainfo("CR: 0x%08" PRIx32 " SWTRGR: 0x%08" PRIx32 "SR: 0x%08" PRIx32 " MCR: 0x%08" PRIx32 "\n", - dac_getreg(priv, STM32L4_DAC_CR_OFFSET), - dac_getreg(priv, STM32L4_DAC_SWTRIGR_OFFSET), - dac_getreg(priv, STM32L4_DAC_SR_OFFSET), - dac_getreg(priv, STM32L4_DAC_MCR_OFFSET)); + dac_getreg(priv, STM32_DAC_CR_OFFSET), + dac_getreg(priv, STM32_DAC_SWTRIGR_OFFSET), + dac_getreg(priv, STM32_DAC_SR_OFFSET), + dac_getreg(priv, STM32_DAC_MCR_OFFSET)); } /**************************************************************************** @@ -867,7 +867,7 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) /* Reset counters (generate an update) */ #ifdef HAVE_DMA - tim_modifyreg(chan, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(chan, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); #endif return OK; } @@ -923,7 +923,7 @@ static int dac_timinit(struct stm32_chan_s *chan) * default) will be enabled */ - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; switch (chan->timer) { @@ -965,7 +965,7 @@ static int dac_timinit(struct stm32_chan_s *chan) #endif #ifdef NEED_TIM8 case 8: - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; setbits = RCC_APB2ENR_TIM8EN; pclk = BOARD_TIM8_FREQUENCY; break; @@ -1036,26 +1036,26 @@ static int dac_timinit(struct stm32_chan_s *chan) /* Set the reload and prescaler values */ - tim_putreg(chan, STM32L4_GTIM_ARR_OFFSET, (uint16_t)reload); - tim_putreg(chan, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + tim_putreg(chan, STM32_GTIM_ARR_OFFSET, (uint16_t)reload); + tim_putreg(chan, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); /* Count mode up, auto reload */ - tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Selection TRGO selection: update */ - tim_modifyreg(chan, STM32L4_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, + tim_modifyreg(chan, STM32_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, GTIM_CR2_MMS_UPDATE); /* Update DMA request enable ???? */ #if 0 - tim_modifyreg(chan, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); + tim_modifyreg(chan, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); #endif /* Enable the counter */ - tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); return OK; } #endif @@ -1200,14 +1200,14 @@ static void dac_blockinit(void) /* Put the entire DAC block in reset state */ flags = enter_critical_section(); - regval = getreg32(STM32L4_RCC_APB1RSTR1); + regval = getreg32(STM32_RCC_APB1RSTR1); regval |= RCC_APB1RSTR1_DAC1RST; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); /* Take the DAC out of reset state */ regval &= ~RCC_APB1RSTR1_DAC1RST; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); leave_critical_section(flags); /* Mark the DAC block as initialized */ @@ -1286,7 +1286,7 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev) /* Reset counters (generate an update) */ - tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); } /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c index 0c4d0c9534494..451f8050480e5 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c @@ -75,21 +75,21 @@ /* Abbreviated register access **********************************************/ -#define CHCFGR1_OFFSET(priv) STM32L4_DFSDM_CHCFGR1_OFFSET((priv)->current) -#define CHCFGR2_OFFSET(priv) STM32L4_DFSDM_CHCFGR2_OFFSET((priv)->current) - -#define FLTCR1_OFFSET(priv) STM32L4_DFSDM_FLTCR1_OFFSET((priv)->intf) -#define FLTCR2_OFFSET(priv) STM32L4_DFSDM_FLTCR2_OFFSET((priv)->intf) -#define FLTISR_OFFSET(priv) STM32L4_DFSDM_FLTISR_OFFSET((priv)->intf) -#define FLTICR_OFFSET(priv) STM32L4_DFSDM_FLTICR_OFFSET((priv)->intf) -#define FLTFCR_OFFSET(priv) STM32L4_DFSDM_FLTFCR_OFFSET((priv)->intf) -#define FLTRDATAR_OFFSET(priv) STM32L4_DFSDM_FLTRDATAR_OFFSET((priv)->intf) -#define FLTAWHTR_OFFSET(priv) STM32L4_DFSDM_FLTAWHTR_OFFSET((priv)->intf) -#define FLTAWLTR_OFFSET(priv) STM32L4_DFSDM_FLTAWLTR_OFFSET((priv)->intf) -#define FLTAWSR_OFFSET(priv) STM32L4_DFSDM_FLTAWSR_OFFSET((priv)->intf) -#define FLTAWCFR_OFFSET(priv) STM32L4_DFSDM_FLTAWCFR_OFFSET((priv)->intf) -#define FLTEXMAX_OFFSET(priv) STM32L4_DFSDM_FLTEXMAX_OFFSET((priv)->intf) -#define FLTEXMIN_OFFSET(priv) STM32L4_DFSDM_FLTEXMIN_OFFSET((priv)->intf) +#define CHCFGR1_OFFSET(priv) STM32_DFSDM_CHCFGR1_OFFSET((priv)->current) +#define CHCFGR2_OFFSET(priv) STM32_DFSDM_CHCFGR2_OFFSET((priv)->current) + +#define FLTCR1_OFFSET(priv) STM32_DFSDM_FLTCR1_OFFSET((priv)->intf) +#define FLTCR2_OFFSET(priv) STM32_DFSDM_FLTCR2_OFFSET((priv)->intf) +#define FLTISR_OFFSET(priv) STM32_DFSDM_FLTISR_OFFSET((priv)->intf) +#define FLTICR_OFFSET(priv) STM32_DFSDM_FLTICR_OFFSET((priv)->intf) +#define FLTFCR_OFFSET(priv) STM32_DFSDM_FLTFCR_OFFSET((priv)->intf) +#define FLTRDATAR_OFFSET(priv) STM32_DFSDM_FLTRDATAR_OFFSET((priv)->intf) +#define FLTAWHTR_OFFSET(priv) STM32_DFSDM_FLTAWHTR_OFFSET((priv)->intf) +#define FLTAWLTR_OFFSET(priv) STM32_DFSDM_FLTAWLTR_OFFSET((priv)->intf) +#define FLTAWSR_OFFSET(priv) STM32_DFSDM_FLTAWSR_OFFSET((priv)->intf) +#define FLTAWCFR_OFFSET(priv) STM32_DFSDM_FLTAWCFR_OFFSET((priv)->intf) +#define FLTEXMAX_OFFSET(priv) STM32_DFSDM_FLTEXMAX_OFFSET((priv)->intf) +#define FLTEXMIN_OFFSET(priv) STM32_DFSDM_FLTEXMIN_OFFSET((priv)->intf) /* DFSDM Filter interrupts **************************************************/ @@ -277,10 +277,10 @@ static const struct adc_ops_s g_adcops = #if defined(CONFIG_STM32L4_DFSDM1_FLT0) static struct stm32_dev_s g_dfsdmpriv0 = { - .irq = STM32L4_IRQ_DFSDM0, + .irq = STM32_IRQ_DFSDM0, .isr = dfsdm_flt0_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, @@ -306,10 +306,10 @@ static struct adc_dev_s g_dfsdmdev0 = #if defined(CONFIG_STM32L4_DFSDM1_FLT1) static struct stm32_dev_s g_dfsdmpriv1 = { - .irq = STM32L4_IRQ_DFSDM1, + .irq = STM32_IRQ_DFSDM1, .isr = dfsdm_flt1_interrupt, .intf = 1, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, @@ -335,10 +335,10 @@ static struct adc_dev_s g_dfsdmdev1 = #if defined(CONFIG_STM32L4_DFSDM1_FLT2) static struct stm32_dev_s g_dfsdmpriv2 = { - .irq = STM32L4_IRQ_DFSDM2, + .irq = STM32_IRQ_DFSDM2, .isr = dfsdm_flt2_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, @@ -364,10 +364,10 @@ static struct adc_dev_s g_dfsdmdev2 = #if defined(CONFIG_STM32L4_DFSDM1_FLT3) static struct stm32_dev_s g_dfsdmpriv3 = { - .irq = STM32L4_IRQ_DFSDM3, + .irq = STM32_IRQ_DFSDM3, .isr = dfsdm_flt3_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, @@ -548,38 +548,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) { ainfo("%s:\n", msg); ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32L4_GTIM_SR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -607,13 +607,13 @@ static void dfsdm_timstart(struct stm32_dev_s *priv, bool enable) { /* Start the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } } #endif @@ -747,24 +747,24 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the reload and prescaler values */ - tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); /* Clear the advanced timers repetition counter in TIM1 */ - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { - tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ } /* TIMx event generation: Bit 0 UG: Update generation */ - tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Handle channel specific setup */ @@ -788,7 +788,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -808,7 +808,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -828,7 +828,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -848,7 +848,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -866,7 +866,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -878,15 +878,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) /* Disable the Channel by resetting the CCxE Bit in the CCER register */ - ccer = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~ccenable; - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */ - cr2 = tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccmr1 = tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccmr2 = tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET); + cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); /* Reset the Output Compare Mode Bits and set the select output compare * mode @@ -912,7 +912,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) ATIM_CCER_CC3E | ATIM_CCER_CC4E); ccer |= ccenable; - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { /* Reset output N polarity level, output N state, output compare state, * output compare N idle state. @@ -937,15 +937,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) /* Save the modified register values */ - tim_putreg(priv, STM32L4_GTIM_CR2_OFFSET, cr2); - tim_putreg(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - tim_putreg(priv, STM32L4_GTIM_CCMR2_OFFSET, ccmr2); - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); - tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, egr); + tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); + tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr); /* Set the ARR Preload Bit */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Enable the timer counter */ @@ -1050,7 +1050,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset) /* Set or clear the selected bit in the APB2 reset register */ - regval = getreg32(STM32L4_RCC_APB2RSTR); + regval = getreg32(STM32_RCC_APB2RSTR); if (reset) { regval |= RCC_APB2RSTR_DFSDMRST; @@ -1060,7 +1060,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset) regval &= ~RCC_APB2RSTR_DFSDMRST; } - putreg32(regval, STM32L4_RCC_APB2RSTR); + putreg32(regval, STM32_RCC_APB2RSTR); leave_critical_section(flags); } @@ -1079,12 +1079,12 @@ static void dfsdm_enable(struct stm32_dev_s *priv) { uint32_t regval; - regval = dfsdm_getreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET); + regval = dfsdm_getreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET); /* Enable DFSMDM */ regval |= DFSDM_CH0CFGR1_DFSDMEN; - dfsdm_putreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET, regval); + dfsdm_putreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET, regval); } /**************************************************************************** @@ -1588,7 +1588,7 @@ static int dfsdm_flt0_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(0)); + regval = getreg32(STM32_DFSDM_FLTISR(0)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1613,7 +1613,7 @@ static int dfsdm_flt1_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(1)); + regval = getreg32(STM32_DFSDM_FLTISR(1)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1638,7 +1638,7 @@ static int dfsdm_flt2_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(2)); + regval = getreg32(STM32_DFSDM_FLTISR(2)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1663,7 +1663,7 @@ static int dfsdm_flt3_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(3)); + regval = getreg32(STM32_DFSDM_FLTISR(3)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index 6039443f5ab53..5e763736b202f 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -91,32 +91,32 @@ #if defined(CONFIG_STM32L4_TIM1_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM1_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM1_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN #elif defined(CONFIG_STM32L4_TIM3_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM3_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM3_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN #elif defined(CONFIG_STM32L4_TIM4_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM4_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM4_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN #elif defined(CONFIG_STM32L4_TIM6_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM6_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM6_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN #elif defined(CONFIG_STM32L4_TIM7_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM7_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM7_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM7_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN #elif defined(CONFIG_STM32L4_TIM8_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM8_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM8_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN #elif defined(CONFIG_STM32L4_TIM16_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM16_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM16_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM16_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN #else # undef DFSDM_HAVE_TIMER #endif diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.c b/arch/arm/src/stm32l4/stm32l4_dfumode.c index 026c03f7bcb10..19c87426f6c55 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.c +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.c @@ -51,67 +51,67 @@ static inline void rcc_reset(void) /* Enable the MSI clock */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); - while (!(getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY)); + while (!(getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY)); /* Set MSI to 4MHz */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_4M | RCC_CR_MSIRGSEL; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset enable bits for other clocks than MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_HSIASFS | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); - putreg32(0, STM32L4_RCC_PLLSAI1CFG); - putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG); + putreg32(0, STM32_RCC_PLLSAI1CFG); + putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32_RCC_PLLSAI1CFG); - putreg32(0, STM32L4_RCC_PLLSAI2CFG); - putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG); + putreg32(0, STM32_RCC_PLLSAI2CFG); + putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32_RCC_PLLSAI1CFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } static inline void apb_reset(void) { - putreg32(0xffffffff, STM32L4_RCC_APB1RSTR1); - putreg32(0xffffffff, STM32L4_RCC_APB1RSTR2); - putreg32(0xffffffff, STM32L4_RCC_APB2RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB1RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB2RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB3RSTR); - - putreg32(0, STM32L4_RCC_APB1RSTR1); - putreg32(0, STM32L4_RCC_APB1RSTR2); - putreg32(0, STM32L4_RCC_APB2RSTR); - putreg32(0, STM32L4_RCC_AHB1RSTR); - putreg32(0, STM32L4_RCC_AHB2RSTR); - putreg32(0, STM32L4_RCC_AHB3RSTR); + putreg32(0xffffffff, STM32_RCC_APB1RSTR1); + putreg32(0xffffffff, STM32_RCC_APB1RSTR2); + putreg32(0xffffffff, STM32_RCC_APB2RSTR); + putreg32(0xffffffff, STM32_RCC_AHB1RSTR); + putreg32(0xffffffff, STM32_RCC_AHB2RSTR); + putreg32(0xffffffff, STM32_RCC_AHB3RSTR); + + putreg32(0, STM32_RCC_APB1RSTR1); + putreg32(0, STM32_RCC_APB1RSTR2); + putreg32(0, STM32_RCC_APB2RSTR); + putreg32(0, STM32_RCC_AHB1RSTR); + putreg32(0, STM32_RCC_AHB2RSTR); + putreg32(0, STM32_RCC_AHB3RSTR); } #endif @@ -144,10 +144,10 @@ void stm32l4_dfumode(void) /* remap ROM at address zero */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); regval |= RCC_APB2ENR_SYSCFGEN; - putreg32(regval, STM32L4_RCC_APB2ENR); - putreg32(SYSCFG_MEMRMP_SYSTEM, STM32L4_SYSCFG_MEMRMP); + putreg32(regval, STM32_RCC_APB2ENR); + putreg32(SYSCFG_MEMRMP_SYSTEM, STM32_SYSCFG_MEMRMP); /* set stack pointer and program-counter to ROM values */ diff --git a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c index a9f32ad8a822f..48d4cace76373 100644 --- a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c +++ b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c @@ -50,31 +50,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32L4_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { -#if STM32L4_NPORTS > 11 +#if STM32_NPORTS > 11 # error "Additional support required for this number of GPIOs" -#elif STM32L4_NPORTS > 10 +#elif STM32_NPORTS > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32L4_NPORTS > 9 +#elif STM32_NPORTS > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32L4_NPORTS > 8 +#elif STM32_NPORTS > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32L4_NPORTS > 7 +#elif STM32_NPORTS > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32L4_NPORTS > 6 +#elif STM32_NPORTS > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32L4_NPORTS > 5 +#elif STM32_NPORTS > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32L4_NPORTS > 4 +#elif STM32_NPORTS > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32L4_NPORTS > 3 +#elif STM32_NPORTS > 3 'A', 'B', 'C', 'D' -#elif STM32L4_NPORTS > 2 +#elif STM32_NPORTS > 2 'A', 'B', 'C' -#elif STM32L4_NPORTS > 1 +#elif STM32_NPORTS > 1 'A', 'B' -#elif STM32L4_NPORTS > 0 +#elif STM32_NPORTS > 0 'A' #else # error "Bad number of GPIOs" @@ -108,33 +108,33 @@ int stm32l4_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32L4_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32L4_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32L4_GPIO_MODER_OFFSET), - getreg32(base + STM32L4_GPIO_OTYPER_OFFSET), - getreg32(base + STM32L4_GPIO_OSPEED_OFFSET), - getreg32(base + STM32L4_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 " BSRR: %08" PRIx32 " LCKR: %04x\n", - getreg32(base + STM32L4_GPIO_IDR_OFFSET), - getreg32(base + STM32L4_GPIO_ODR_OFFSET), - getreg32(base + STM32L4_GPIO_BSRR_OFFSET), - getreg32(base + STM32L4_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32L4_GPIO_AFRH_OFFSET), - getreg32(base + STM32L4_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32L4_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c index c67451e4437d3..2ad3d44cde555 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c @@ -73,7 +73,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR); return ret; } @@ -109,29 +109,29 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); - up_enable_irq(STM32L4_IRQ_RTCALRM); + irq_attach(STM32_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); + up_enable_irq(STM32_IRQ_RTCALRM); } else { - up_disable_irq(STM32L4_IRQ_RTCALRM); + up_disable_irq(STM32_IRQ_RTCALRM); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_RTC_ALARM, risingedge ? EXTI1_RTC_ALARM : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_RTC_ALARM, fallingedge ? EXTI1_RTC_ALARM : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_RTC_ALARM, event ? EXTI1_RTC_ALARM : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_RTC_ALARM, func ? EXTI1_RTC_ALARM : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c index b3b39ce340fa9..35fd4128668f3 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c @@ -64,11 +64,11 @@ struct comp_callback_s /* Interrupt handlers attached to the COMP EXTI lines */ -static struct comp_callback_s g_comp_handlers[STM32L4_COMP_NUM]; +static struct comp_callback_s g_comp_handlers[STM32_COMP_NUM]; /* Comparator EXTI lines */ -static const uint32_t g_comp_lines[STM32L4_COMP_NUM] = +static const uint32_t g_comp_lines[STM32_COMP_NUM] = { #if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) @@ -92,15 +92,15 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) /* Examine the state of each comparator line and dispatch interrupts */ - pr = getreg32(STM32L4_EXTI1_PR); - for (i = 0; i < STM32L4_COMP_NUM; i++) + pr = getreg32(STM32_EXTI1_PR); + for (i = 0; i < STM32_COMP_NUM; i++) { ln = g_comp_lines[i]; if ((pr & ln) != 0) { /* Clear the pending interrupt */ - putreg32(ln, STM32L4_EXTI1_PR); + putreg32(ln, STM32_EXTI1_PR); if (g_comp_handlers[i].callback != NULL) { xcpt_t callback = g_comp_handlers[i].callback; @@ -152,25 +152,25 @@ int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, if (func != NULL) { - irq_attach(STM32L4_IRQ_COMP, stm32l4_exti_comp_isr, NULL); - up_enable_irq(STM32L4_IRQ_COMP); + irq_attach(STM32_IRQ_COMP, stm32l4_exti_comp_isr, NULL); + up_enable_irq(STM32_IRQ_COMP); } else { - up_disable_irq(STM32L4_IRQ_COMP); + up_disable_irq(STM32_IRQ_COMP); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, risingedge ? + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : ln, risingedge ? ln : 0); - modifyreg32(STM32L4_EXTI1_FTSR, fallingedge ? + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : ln, fallingedge ? ln : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, event ? 0 : ln, event ? ln : 0); - modifyreg32(STM32L4_EXTI1_IMR, func ? 0 : ln, func ? ln : 0); + modifyreg32(STM32_EXTI1_EMR, event ? 0 : ln, event ? ln : 0); + modifyreg32(STM32_EXTI1_IMR, func ? 0 : ln, func ? ln : 0); /* Get the previous IRQ handler and save the new IRQ handler. */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c index 2b02e9d15aa0c..767bffb83caab 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c @@ -72,7 +72,7 @@ static int stm32l4_exti0_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0001, STM32L4_EXTI1_PR); + putreg32(0x0001, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -93,7 +93,7 @@ static int stm32l4_exti1_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0002, STM32L4_EXTI1_PR); + putreg32(0x0002, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -114,7 +114,7 @@ static int stm32l4_exti2_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0004, STM32L4_EXTI1_PR); + putreg32(0x0004, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -135,7 +135,7 @@ static int stm32l4_exti3_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0008, STM32L4_EXTI1_PR); + putreg32(0x0008, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -156,7 +156,7 @@ static int stm32l4_exti4_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0010, STM32L4_EXTI1_PR); + putreg32(0x0010, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -180,7 +180,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32L4_EXTI1_PR); + pr = getreg32(STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -193,7 +193,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32L4_EXTI1_PR); + putreg32(mask, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -257,7 +257,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { struct gpio_callback_s *shared_cbs; uint32_t pin = pinset & GPIO_PIN_MASK; - uint32_t exti = STM32L4_EXTI1_BIT(pin); + uint32_t exti = STM32_EXTI1_BIT(pin); int irq; xcpt_t handler; int nshared; @@ -267,7 +267,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32L4_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) @@ -295,14 +295,14 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, } else if (pin < 10) { - irq = STM32L4_IRQ_EXTI95; + irq = STM32_IRQ_EXTI95; handler = stm32l4_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32L4_IRQ_EXTI1510; + irq = STM32_IRQ_EXTI1510; handler = stm32l4_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; @@ -353,19 +353,19 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c index b18efc39ef771..854df35b91382 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c @@ -71,7 +71,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_PVD_LINE, STM32L4_EXTI1_PR); + putreg32(EXTI1_PVD_LINE, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -116,29 +116,29 @@ int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); - up_enable_irq(STM32L4_IRQ_PVD); + irq_attach(STM32_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); + up_enable_irq(STM32_IRQ_PVD); } else { - up_disable_irq(STM32L4_IRQ_PVD); + up_disable_irq(STM32_IRQ_PVD); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_PVD_LINE, risingedge ? EXTI1_PVD_LINE : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_PVD_LINE, fallingedge ? EXTI1_PVD_LINE : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_PVD_LINE, event ? EXTI1_PVD_LINE : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_PVD_LINE, func ? EXTI1_PVD_LINE : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c index 24f4e00b3055c..2bcf7b22ef38f 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c @@ -73,7 +73,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_RTC_WAKEUP, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_WAKEUP, STM32_EXTI1_PR); return ret; } @@ -109,29 +109,29 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL); - up_enable_irq(STM32L4_IRQ_RTC_WKUP); + irq_attach(STM32_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL); + up_enable_irq(STM32_IRQ_RTC_WKUP); } else { - up_disable_irq(STM32L4_IRQ_RTC_WKUP); + up_disable_irq(STM32_IRQ_RTC_WKUP); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_RTC_WAKEUP, risingedge ? EXTI1_RTC_WAKEUP : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_RTC_WAKEUP, fallingedge ? EXTI1_RTC_WAKEUP : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_RTC_WAKEUP, event ? EXTI1_RTC_WAKEUP : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_RTC_WAKEUP, func ? EXTI1_RTC_WAKEUP : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.c b/arch/arm/src/stm32l4/stm32l4_firewall.c index 56b92cf9b0821..c4597da0e98a5 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.c +++ b/arch/arm/src/stm32l4/stm32l4_firewall.c @@ -67,34 +67,34 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) * data must be in SRAM1 */ - if ((setup->codestart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE) + if ((setup->codestart & STM32_FLASH_MASK) != STM32_FLASH_BASE) { return -EINVAL; } - if ((setup->nvdatastart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE) + if ((setup->nvdatastart & STM32_FLASH_MASK) != STM32_FLASH_BASE) { return -EINVAL; } /* Define address and length registers */ - modifyreg32(STM32L4_FIREWALL_CSSA, FIREWALL_CSSADD_MASK, + modifyreg32(STM32_FIREWALL_CSSA, FIREWALL_CSSADD_MASK, setup->codestart); - modifyreg32(STM32L4_FIREWALL_CSL, FIREWALL_CSSLENG_MASK, + modifyreg32(STM32_FIREWALL_CSL, FIREWALL_CSSLENG_MASK, setup->codelen); - modifyreg32(STM32L4_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK, + modifyreg32(STM32_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK, setup->nvdatastart); - modifyreg32(STM32L4_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK, + modifyreg32(STM32_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK, setup->nvdatalen); - modifyreg32(STM32L4_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK, + modifyreg32(STM32_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK, setup->datastart); - modifyreg32(STM32L4_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK, + modifyreg32(STM32_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK, setup->datalen); /* Define access options */ - reg = getreg32(STM32L4_FIREWALL_CR); + reg = getreg32(STM32_FIREWALL_CR); if (setup->datashared) { reg |= FIREWALL_CR_VDS; @@ -105,13 +105,13 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) reg |= FIREWALL_CR_VDE; } - putreg32(reg, STM32L4_FIREWALL_CR); + putreg32(reg, STM32_FIREWALL_CR); /* Enable firewall */ - reg = getreg32(STM32L4_SYSCFG_CFGR1); + reg = getreg32(STM32_SYSCFG_CFGR1); reg &= ~SYSCFG_CFGR1_FWDIS; - putreg32(reg, STM32L4_SYSCFG_CFGR1); + putreg32(reg, STM32_SYSCFG_CFGR1); /* Now protected code can only be accessed by jumping to the FW gate */ diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index dc6983cd00f53..914e213005a5d 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -70,7 +70,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32L4_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #if FLASH_PAGE_SIZE == 2048 @@ -78,7 +78,7 @@ #elif FLASH_PAGE_SIZE == 4096 # define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */ #else -# error Unsupported STM32L4_FLASH_PAGESIZE +# error Unsupported STM32_FLASH_PAGESIZE #endif #define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT) @@ -104,35 +104,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } - if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32L4_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32L4_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32L4_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32L4_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -149,8 +149,8 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); #if defined(CONFIG_STM32L4_STM32L4X5) || \ @@ -160,41 +160,41 @@ static inline void flash_erase(size_t page) { /* Select bank 1 */ - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_BKER, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_BKER, 0); } else { /* Select bank 2 */ - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_BKER); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_BKER); } #endif - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } #if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) static void data_cache_disable(void) { - modifyreg32(STM32L4_FLASH_ACR, FLASH_ACR_DCEN, 0); + modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0); } static void data_cache_enable(void) { /* Reset data cache */ - modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCRST); + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST); /* Enable data cache */ - modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCEN); + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN); } #endif /* defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ @@ -274,20 +274,20 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32L4_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32L4_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } @@ -300,42 +300,42 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32L4_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32L4_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32L4_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32L4_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32L4_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32L4_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32L4_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32L4_FLASH_PAGESIZE + STM32L4_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32L4_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -347,7 +347,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32L4_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -385,7 +385,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32L4_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -419,12 +419,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32L4_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32L4_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32L4_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -498,7 +498,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) data_cache_disable(); #endif - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); set_pg_bit = true; for (i = 0; i < FLASH_PAGE_WORDS; i += 2) @@ -506,14 +506,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } /* Verify */ - if (getreg32(STM32L4_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { ret = -EROFS; goto out; @@ -527,7 +527,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) } } - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); set_pg_bit = false; #if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) @@ -547,7 +547,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) out: if (set_pg_bit) { - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); #if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_enable(); #endif @@ -560,9 +560,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32L4_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32L4_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c index 433a55288f29c..37f2a2b8c9fa2 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ b/arch/arm/src/stm32l4/stm32l4_freerun.c @@ -69,7 +69,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg) DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; - STM32L4_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ACKINT(freerun->tch, 0); return OK; } @@ -117,7 +117,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, return -EBUSY; } - STM32L4_TIM_SETCLOCK(freerun->tch, frequency); + STM32_TIM_SETCLOCK(freerun->tch, frequency); /* Initialize the remaining fields in the state structure and return * success. @@ -128,17 +128,17 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, /* Set up to receive the callback when the counter overflow occurs */ - STM32L4_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0); /* Set timer period */ - STM32L4_TIM_SETPERIOD(freerun->tch, UINT32_MAX); + STM32_TIM_SETPERIOD(freerun->tch, UINT32_MAX); /* Start the counter */ - STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_UP); - STM32L4_TIM_ACKINT(freerun->tch, 0); - STM32L4_TIM_ENABLEINT(freerun->tch, 0); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); + STM32_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ENABLEINT(freerun->tch, 0); return OK; } @@ -184,9 +184,9 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, flags = enter_critical_section(); overflow = freerun->overflow; - counter = STM32L4_TIM_GETCOUNTER(freerun->tch); - pending = STM32L4_TIM_CHECKINT(freerun->tch, 0); - verify = STM32L4_TIM_GETCOUNTER(freerun->tch); + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -194,7 +194,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, if (pending) { - STM32L4_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ACKINT(freerun->tch, 0); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -260,9 +260,9 @@ int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun) /* Now we can disable the timer interrupt and disable the timer. */ - STM32L4_TIM_DISABLEINT(freerun->tch, 0); - STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_SETISR(freerun->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(freerun->tch, 0); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); /* Free the timer */ diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index 1cf19f3dac6cb..228dec79877df 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -54,34 +54,34 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32L4_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32L4_NPORTS > 0 - STM32L4_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32L4_NPORTS > 1 - STM32L4_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32L4_NPORTS > 2 - STM32L4_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32L4_NPORTS > 3 - STM32L4_GPIOD_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, #endif -#if STM32L4_NPORTS > 4 - STM32L4_GPIOE_BASE, +#if STM32_NPORTS > 4 + STM32_GPIOE_BASE, #endif -#if STM32L4_NPORTS > 5 - STM32L4_GPIOF_BASE, +#if STM32_NPORTS > 5 + STM32_GPIOF_BASE, #endif -#if STM32L4_NPORTS > 6 - STM32L4_GPIOG_BASE, +#if STM32_NPORTS > 6 + STM32_GPIOG_BASE, #endif -#if STM32L4_NPORTS > 7 - STM32L4_GPIOH_BASE, +#if STM32_NPORTS > 7 + STM32_GPIOH_BASE, #endif -#if STM32L4_NPORTS > 8 - STM32L4_GPIOI_BASE, +#if STM32_NPORTS > 8 + STM32_GPIOI_BASE, #endif }; @@ -144,7 +144,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32L4_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -202,10 +202,10 @@ int stm32l4_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32L4_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -228,10 +228,10 @@ int stm32l4_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32L4_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -246,12 +246,12 @@ int stm32l4_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32L4_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32L4_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -289,14 +289,14 @@ int stm32l4_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32L4_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32L4_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -309,7 +309,7 @@ int stm32l4_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32L4_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -331,7 +331,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32L4_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -351,11 +351,11 @@ int stm32l4_configgpio(uint32_t cfgset) if (pinmode == GPIO_MODER_ANALOG) { - modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin)); + modifyreg32(base + STM32_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin)); } else { - modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0); + modifyreg32(base + STM32_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0); } #endif @@ -412,7 +412,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -433,7 +433,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32L4_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -452,7 +452,7 @@ bool stm32l4_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -461,7 +461,7 @@ bool stm32l4_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32L4_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index 2df58191ee1c9..4969756362b04 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -244,7 +244,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32L4_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.c b/arch/arm/src/stm32l4/stm32l4_hsi48.c index 75ab0311ff4b5..e34c588f6a156 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.c +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.c @@ -80,13 +80,13 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * enabled. */ - regval = getreg32(STM32L4_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval |= RCC_CRRCR_HSI48ON; - putreg32(regval, STM32L4_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Wait for the HSI48 clock to stabilize */ - while ((getreg32(STM32L4_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); + while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); /* Return if no synchronization */ @@ -100,7 +100,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * clock or the USB SOF signal. */ - regval = getreg32(STM32L4_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; switch (syncsrc) @@ -119,7 +119,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) break; } - putreg32(regval, STM32L4_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic * hardware adjustment of TRIM bits according to the measured frequency @@ -127,9 +127,9 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * frequency error counter and SYNC events. */ - regval = getreg32(STM32L4_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; - putreg32(regval, STM32L4_CRS_CR); + putreg32(regval, STM32_CRS_CR); } /**************************************************************************** @@ -152,17 +152,17 @@ void stm32l4_disable_hsi48(void) /* Disable the HSI48 clock */ - regval = getreg32(STM32L4_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~RCC_CRRCR_HSI48ON; - putreg32(regval, STM32L4_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Set other registers to the default settings. */ - regval = getreg32(STM32L4_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; - putreg32(regval, STM32L4_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); - regval = getreg32(STM32L4_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32L4_CRS_CR); + putreg32(regval, STM32_CRS_CR); } diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 15dfac9e14ee0..4e42d3beb516a 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -520,14 +520,14 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef CONFIG_STM32L4_I2C1 static const struct stm32l4_i2c_config_s stm32l4_i2c1_config = { - .base = STM32L4_I2C1_BASE, + .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, .reset_bit = RCC_APB1RSTR1_I2C1RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C1EV, - .er_irq = STM32L4_IRQ_I2C1ER + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER #endif }; @@ -556,14 +556,14 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = #ifdef CONFIG_STM32L4_I2C2 static const struct stm32l4_i2c_config_s stm32l4_i2c2_config = { - .base = STM32L4_I2C2_BASE, + .base = STM32_I2C2_BASE, .clk_bit = RCC_APB1ENR1_I2C2EN, .reset_bit = RCC_APB1RSTR1_I2C2RST, .scl_pin = GPIO_I2C2_SCL, .sda_pin = GPIO_I2C2_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C2EV, - .er_irq = STM32L4_IRQ_I2C2ER + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER #endif }; @@ -592,14 +592,14 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = #ifdef CONFIG_STM32L4_I2C3 static const struct stm32l4_i2c_config_s stm32l4_i2c3_config = { - .base = STM32L4_I2C3_BASE, + .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C3EV, - .er_irq = STM32L4_IRQ_I2C3ER + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER #endif }; @@ -628,14 +628,14 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv = #ifdef CONFIG_STM32L4_I2C4 static const struct stm32l4_i2c_config_s stm32l4_i2c4_config = { - .base = STM32L4_I2C4_BASE, + .base = STM32_I2C4_BASE, .clk_bit = RCC_APB1ENR2_I2C4EN, .reset_bit = RCC_APB1RSTR2_I2C4RST, .scl_pin = GPIO_I2C4_SCL, .sda_pin = GPIO_I2C4_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C4EV, - .er_irq = STM32L4_IRQ_I2C4ER + .ev_irq = STM32_IRQ_I2C4EV, + .er_irq = STM32_IRQ_I2C4ER #endif }; @@ -791,7 +791,7 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) static inline void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif @@ -823,7 +823,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) * error-related, are enabled here. */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -861,7 +861,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; @@ -930,7 +930,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_set_7bit_address(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); } @@ -945,7 +945,7 @@ static inline void stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv, uint8_t n_bytes) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } @@ -959,7 +959,7 @@ stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv, static inline void stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** @@ -972,7 +972,7 @@ stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } @@ -986,7 +986,7 @@ stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } @@ -1000,7 +1000,7 @@ stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } @@ -1040,7 +1040,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET); + cr = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -1048,7 +1048,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + sr = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { return; @@ -1253,20 +1253,20 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, /* I2C peripheral must be disabled to update clocking configuration */ pe = (stm32l4_i2c_getreg32(priv, - STM32L4_I2C_CR1_OFFSET) & I2C_CR1_PE); + STM32_I2C_CR1_OFFSET) & I2C_CR1_PE); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } -#if defined(STM32L4_I2C_USE_HSI16) || (STM32L4_PCLK1_FREQUENCY == 16000000) +#if defined(STM32_I2C_USE_HSI16) || (STM32_PCLK1_FREQUENCY == 16000000) i2cclk_mhz = 16; -#elif STM32L4_PCLK1_FREQUENCY == 48000000 +#elif STM32_PCLK1_FREQUENCY == 48000000 i2cclk_mhz = 48; -#elif STM32L4_PCLK1_FREQUENCY == 80000000 +#elif STM32_PCLK1_FREQUENCY == 80000000 i2cclk_mhz = 80; -#elif STM32L4_PCLK1_FREQUENCY == 120000000 +#elif STM32_PCLK1_FREQUENCY == 120000000 i2cclk_mhz = 120; #else # warning STM32_I2C_INIT: Peripheral clock is PCLK and the speed/timing calculations need to be redone. @@ -1454,11 +1454,11 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - stm32l4_i2c_putreg32(priv, STM32L4_I2C_TIMINGR_OFFSET, timingr); + stm32l4_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1605,7 +1605,7 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** @@ -1626,7 +1626,7 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) i2cinfo("Sending STOP\n"); stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } @@ -1641,7 +1641,7 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) static inline uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32L4_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** @@ -1655,7 +1655,7 @@ uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } @@ -1684,7 +1684,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Get state of the I2C controller */ - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1853,7 +1853,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Transmit current byte */ - stm32l4_i2c_putreg(priv, STM32L4_I2C_TXDR_OFFSET, *priv->ptr); + stm32l4_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1928,7 +1928,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32l4_i2c_getreg(priv, STM32L4_I2C_RXDR_OFFSET); + *priv->ptr = stm32l4_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1949,7 +1949,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Unsupported state */ stm32l4_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -2193,7 +2193,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); @@ -2216,7 +2216,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #else /* Read rest of the state */ - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -2254,7 +2254,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -2268,7 +2268,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Clear all interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -2281,7 +2281,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif } - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; @@ -2320,18 +2320,18 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Enable power and reset the peripheral */ #ifdef CONFIG_STM32L4_I2C4 - if (priv->config->base == STM32L4_I2C4_BASE) + if (priv->config->base == STM32_I2C4_BASE) { - modifyreg32(STM32L4_RCC_APB1ENR2, 0, priv->config->clk_bit); - modifyreg32(STM32L4_RCC_APB1RSTR2, 0, priv->config->reset_bit); - modifyreg32(STM32L4_RCC_APB1RSTR2, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR2, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR2, priv->config->reset_bit, 0); } else #endif { - modifyreg32(STM32L4_RCC_APB1ENR1, 0, priv->config->clk_bit); - modifyreg32(STM32L4_RCC_APB1RSTR1, 0, priv->config->reset_bit); - modifyreg32(STM32L4_RCC_APB1RSTR1, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR1, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR1, priv->config->reset_bit, 0); } /* Configure pins */ @@ -2368,7 +2368,7 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Enable I2C peripheral */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } @@ -2385,7 +2385,7 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) { /* Disable I2C */ - stm32l4_i2c_putreg32(priv, STM32L4_I2C_CR1_OFFSET, 0); + stm32l4_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ @@ -2405,14 +2405,14 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) /* Disable clocking */ #ifdef CONFIG_STM32L4_I2C4 - if (priv->config->base == STM32L4_I2C4_BASE) + if (priv->config->base == STM32_I2C4_BASE) { - modifyreg32(STM32L4_RCC_APB1ENR2, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0); } else #endif { - modifyreg32(STM32L4_RCC_APB1ENR1, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, priv->config->clk_bit, 0); } return OK; @@ -2493,8 +2493,8 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, waitrc = stm32l4_i2c_sem_waitdone(priv); - cr1 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR1_OFFSET); - cr2 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET); + cr1 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 3cbb653dd08db..77c20d24e4a8b 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -204,13 +204,13 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32L4_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32L4_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -220,19 +220,19 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32L4_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32L4_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32L4_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32L4_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -262,7 +262,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32L4_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -316,13 +316,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32L4_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32L4_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32L4_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif stm32l4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); @@ -332,23 +332,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32L4_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32L4_IRQ_NMI, stm32l4_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32l4_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32L4_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32L4_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32L4_IRQ_PENDSV, stm32l4_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32l4_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32L4_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32L4_IRQ_RESERVED, stm32l4_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32l4_reserved, NULL); #endif stm32l4_dumpnvic("initial", NR_IRQS); @@ -384,7 +384,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -419,7 +419,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -462,10 +462,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32L4_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32L4_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -478,7 +478,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32L4_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c index 2c0894c78bee7..05f19076f09ba 100644 --- a/arch/arm/src/stm32l4/stm32l4_iwdg.c +++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c @@ -65,7 +65,7 @@ * 1000 * 4095 / Fmin = 34,944 MSec */ -#define IWDG_FMIN (STM32L4_LSI_FREQUENCY / 256) +#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256) #define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN) /* Configuration ************************************************************/ @@ -254,26 +254,26 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) /* Enable write access to IWDG_PR and IWDG_RLR registers */ - stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. These bits * were set the last time that the PR register was written and may not * yet be cleared. */ - while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); /* Set the prescaler */ - stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32L4_IWDG_PR); + stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); /* Set the reload value */ - stm32l4_putreg((uint16_t)priv->reload, STM32L4_IWDG_RLR); + stm32l4_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); /* Reload the counter (and disable write access) */ - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. This is * to wait for the change to take effect before exiting critical section, @@ -289,7 +289,7 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) if (priv->started) { - while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); } leave_critical_section(flags); @@ -335,7 +335,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_START, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); priv->started = true; leave_critical_section(flags); @@ -395,7 +395,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) /* Reload the IWDG timer */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); leave_critical_section(flags); @@ -629,7 +629,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32l4_rcc_enablelsi(); - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32L4_RCC_CSR)); + wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.c b/arch/arm/src/stm32l4/stm32l4_lowputc.c index 56a8fc0391182..440c185a92cb9 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.c +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.c @@ -46,127 +46,127 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_LPUART1_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR2 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32L4_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32L4_CONSOLE_TX GPIO_LPUART1_TX -# define STM32L4_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART1_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK2_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB2ENR -# define STM32L4_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART1_TX -# define STM32L4_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART2_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART2_TX -# define STM32L4_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART3_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART3EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART3_TX -# define STM32L4_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_UART4_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART4EN -# define STM32L4_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32L4_CONSOLE_TX GPIO_UART4_TX -# define STM32L4_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_UART5_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART5EN -# define STM32L4_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32L4_CONSOLE_TX GPIO_UART5_TX -# define STM32L4_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32L4_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32L4_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -174,9 +174,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32L4_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32L4_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -192,7 +192,7 @@ /* CR2 settings */ -# if STM32L4_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -234,19 +234,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32L4_USARTDIV8 \ - (((STM32L4_APBCLOCK << 1) + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD) -# define STM32L4_USARTDIV16 \ - ((STM32L4_APBCLOCK + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32L4_USARTDIV8 > 100 -# define STM32L4_BRR_VALUE STM32L4_USARTDIV16 +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32L4_BRR_VALUE \ - ((STM32L4_USARTDIV8 & 0xfff0) | ((STM32L4_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif #endif /* HAVE_CONSOLE */ @@ -288,22 +288,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32L4_CONSOLE_RS485_DIR - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - STM32L4_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32L4_CONSOLE_BASE + STM32L4_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32L4_CONSOLE_RS485_DIR - while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - !STM32L4_CONSOLE_RS485_DIR_POLARITY); + stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -329,7 +329,7 @@ void stm32l4_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32L4_CONSOLE_APBREG, 0, STM32L4_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -338,17 +338,17 @@ void stm32l4_lowsetup(void) * stm32l4_rcc.c */ -#ifdef STM32L4_CONSOLE_TX - stm32l4_configgpio(STM32L4_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32l4_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32L4_CONSOLE_RX - stm32l4_configgpio(STM32L4_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32l4_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32L4_CONSOLE_RS485_DIR - stm32l4_configgpio(STM32L4_CONSOLE_RS485_DIR); - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - !STM32L4_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l4_configgpio(STM32_CONSOLE_RS485_DIR); + stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -356,42 +356,42 @@ void stm32l4_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32L4_BRR_VALUE, - STM32L4_CONSOLE_BASE + STM32L4_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c index 0426016bd4464..f376a1fd16955 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -154,9 +154,9 @@ static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops = static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = { .ops = &stm32l4_lptim_ops, - .mode = STM32L4_LPTIM_MODE_UNUSED, - .base = STM32L4_LPTIM1_BASE, - .freq = STM32L4_LPTIM1_FREQUENCY, /* Must be defined in board.h */ + .mode = STM32_LPTIM_MODE_UNUSED, + .base = STM32_LPTIM1_BASE, + .freq = STM32_LPTIM1_FREQUENCY, /* Must be defined in board.h */ }; #endif @@ -164,9 +164,9 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = { .ops = &stm32l4_lptim_ops, - .mode = STM32L4_LPTIM_MODE_UNUSED, - .base = STM32L4_LPTIM2_BASE, - .freq = STM32L4_LPTIM2_FREQUENCY, /* Must be defined in board.h */ + .mode = STM32_LPTIM_MODE_UNUSED, + .base = STM32_LPTIM2_BASE, + .freq = STM32_LPTIM2_FREQUENCY, /* Must be defined in board.h */ }; #endif @@ -218,13 +218,13 @@ static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev) switch (((struct stm32l4_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); break; #endif #if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); break; #endif @@ -246,13 +246,13 @@ static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev) switch (((struct stm32l4_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); break; #endif #if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); break; #endif @@ -274,15 +274,15 @@ static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev) switch (((struct stm32l4_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); - modifyreg32(STM32L4_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); + modifyreg32(STM32_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); break; #endif #if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); - modifyreg32(STM32L4_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); + modifyreg32(STM32_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); break; #endif } @@ -300,12 +300,12 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, { DEBUGASSERT(dev != NULL && cfg != NULL); - channel &= STM32L4_LPTIM_CH_MASK; + channel &= STM32_LPTIM_CH_MASK; switch (((struct stm32l4_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: switch (channel) { # if defined(GPIO_LPTIM1_OUT_1) @@ -330,7 +330,7 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, #endif /* CONFIG_STM32L4_LPTIM1 */ #if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: switch (channel) { # if defined(GPIO_LPTIM2_OUT_1) @@ -369,24 +369,24 @@ static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, stm32l4_lptim_mode_t mode) { const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base + - STM32L4_LPTIM_CR_OFFSET; + STM32_LPTIM_CR_OFFSET; DEBUGASSERT(dev != NULL); /* Mode */ - switch (mode & STM32L4_LPTIM_MODE_MASK) + switch (mode & STM32_LPTIM_MODE_MASK) { - case STM32L4_LPTIM_MODE_DISABLED: + case STM32_LPTIM_MODE_DISABLED: modifyreg32(addr, LPTIM_CR_ENABLE, 0); break; - case STM32L4_LPTIM_MODE_SINGLE: + case STM32_LPTIM_MODE_SINGLE: modifyreg32(addr, 0, LPTIM_CR_ENABLE); modifyreg32(addr, 0, LPTIM_CR_SNGSTRT); break; - case STM32L4_LPTIM_MODE_CONTINUOUS: + case STM32_LPTIM_MODE_CONTINUOUS: modifyreg32(addr, 0, LPTIM_CR_ENABLE); modifyreg32(addr, 0, LPTIM_CR_CNTSTRT); break; @@ -469,7 +469,7 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, actual = priv->freq >> 7; } - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, setbits); stm32l4_lptim_enable(dev); @@ -519,9 +519,9 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, DEBUGASSERT(dev != NULL); - if (clksrc == STM32L4_LPTIM_CLK_EXT) + if (clksrc == STM32_LPTIM_CLK_EXT) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_EXTCLK); } @@ -532,12 +532,12 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_mask = RCC_CCIPR_LPTIM1SEL_MASK; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_mask = RCC_CCIPR_LPTIM2SEL_MASK; break; #endif @@ -547,61 +547,61 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, switch (clksrc) { - case STM32L4_LPTIM_CLK_PCLK: + case STM32_LPTIM_CLK_PCLK: switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_PCLK; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_PCLK; break; #endif } break; - case STM32L4_LPTIM_CLK_HSI: + case STM32_LPTIM_CLK_HSI: switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_HSI; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_HSI; break; #endif } break; - case STM32L4_LPTIM_CLK_LSI: + case STM32_LPTIM_CLK_LSI: switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSI; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSI; break; #endif } break; - case STM32L4_LPTIM_CLK_LSE: + case STM32_LPTIM_CLK_LSE: switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSE; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSE; break; #endif @@ -611,9 +611,9 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, break; } - modifyreg32(STM32L4_RCC_CCIPR, ccr_mask, ccr_bits); + modifyreg32(STM32_RCC_CCIPR, ccr_mask, ccr_bits); - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_INTCLK); } @@ -632,7 +632,7 @@ static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev, (struct stm32l4_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); - putreg32(period, (uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET)); + putreg32(period, (uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** @@ -645,7 +645,7 @@ static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev) (struct stm32l4_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); - return getreg32((uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET)); + return getreg32((uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** @@ -657,14 +657,14 @@ static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, { DEBUGASSERT(dev != NULL); - if (cntmode == STM32L4_LPTIM_COUNT_CLOCK) + if (cntmode == STM32_LPTIM_COUNT_CLOCK) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_COUNTMODE, 0); } - else if (cntmode == STM32L4_LPTIM_COUNT_EXTTRIG) + else if (cntmode == STM32_LPTIM_COUNT_EXTTRIG) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, 0, LPTIM_CFGR_COUNTMODE); } else @@ -686,20 +686,20 @@ static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, switch (polarity) { - case STM32L4_LPTIM_CLKPOL_RISING: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_RISING: + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_RISING); break; - case STM32L4_LPTIM_CLKPOL_FALLING: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_FALLING: + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_FALLING); break; - case STM32L4_LPTIM_CLKPOL_BOTH: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_BOTH: + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_BOTH); break; @@ -725,9 +725,9 @@ static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) do { counter1 = getreg32((uintptr_t)(priv->base + - STM32L4_LPTIM_CNT_OFFSET)); + STM32_LPTIM_CNT_OFFSET)); counter2 = getreg32((uintptr_t)(priv->base + - STM32L4_LPTIM_CNT_OFFSET)); + STM32_LPTIM_CNT_OFFSET)); } while (counter1 != counter2); @@ -757,7 +757,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Is device already allocated */ if (((struct stm32l4_lptim_priv_s *)dev)->mode != - STM32L4_LPTIM_MODE_UNUSED) + STM32_LPTIM_MODE_UNUSED) { return NULL; } @@ -772,7 +772,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Mark it as used */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_DISABLED; + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED; return dev; } @@ -791,7 +791,7 @@ int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s * dev) /* Mark it as free */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_UNUSED; + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h index 1f57f6ac9eda1..db940b524c3d8 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/stm32l4_lptim.h @@ -86,14 +86,14 @@ /* Helpers ******************************************************************/ -#define STM32L4_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L4_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L4_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) -#define STM32L4_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s)) -#define STM32L4_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L4_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m)) -#define STM32L4_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L4_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) +#define STM32_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s)) +#define STM32_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m)) +#define STM32_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d)) /**************************************************************************** * Public Types @@ -121,14 +121,14 @@ struct stm32l4_lptim_dev_s typedef enum { - STM32L4_LPTIM_MODE_UNUSED = -1, + STM32_LPTIM_MODE_UNUSED = -1, /* MODES */ - STM32L4_LPTIM_MODE_DISABLED = 0x0000, - STM32L4_LPTIM_MODE_SINGLE = 0x0001, - STM32L4_LPTIM_MODE_CONTINUOUS = 0x0002, - STM32L4_LPTIM_MODE_MASK = 0x000f, + STM32_LPTIM_MODE_DISABLED = 0x0000, + STM32_LPTIM_MODE_SINGLE = 0x0001, + STM32_LPTIM_MODE_CONTINUOUS = 0x0002, + STM32_LPTIM_MODE_MASK = 0x000f, } stm32l4_lptim_mode_t; /* LPTIM Clock Source */ @@ -137,11 +137,11 @@ typedef enum { /* Clock Sources */ - STM32L4_LPTIM_CLK_PCLK = 0x0000, - STM32L4_LPTIM_CLK_LSI = 0x0001, - STM32L4_LPTIM_CLK_HSI = 0x0002, - STM32L4_LPTIM_CLK_LSE = 0x0003, - STM32L4_LPTIM_CLK_EXT = 0x0004, + STM32_LPTIM_CLK_PCLK = 0x0000, + STM32_LPTIM_CLK_LSI = 0x0001, + STM32_LPTIM_CLK_HSI = 0x0002, + STM32_LPTIM_CLK_LSE = 0x0003, + STM32_LPTIM_CLK_EXT = 0x0004, } stm32l4_lptim_clksrc_t; /* LPTIM Counter Modes */ @@ -150,8 +150,8 @@ typedef enum { /* Modes */ - STM32L4_LPTIM_COUNT_CLOCK = 0x0000, - STM32L4_LPTIM_COUNT_EXTTRIG = 0x0001, + STM32_LPTIM_COUNT_CLOCK = 0x0000, + STM32_LPTIM_COUNT_EXTTRIG = 0x0001, } stm32l4_lptim_cntmode_t; /* LPTIM Clock Polarity */ @@ -160,24 +160,24 @@ typedef enum { /* MODES */ - STM32L4_LPTIM_CLKPOL_RISING = 0x0000, - STM32L4_LPTIM_CLKPOL_FALLING = 0x0001, - STM32L4_LPTIM_CLKPOL_BOTH = 0x0002, + STM32_LPTIM_CLKPOL_RISING = 0x0000, + STM32_LPTIM_CLKPOL_FALLING = 0x0001, + STM32_LPTIM_CLKPOL_BOTH = 0x0002, } stm32l4_lptim_clkpol_t; /* LPTIM Channel Modes */ typedef enum { - STM32L4_LPTIM_CH_DISABLED = 0x0000, + STM32_LPTIM_CH_DISABLED = 0x0000, /* CHANNELS */ - STM32L4_LPTIM_CH_CHINVALID = 0x0000, - STM32L4_LPTIM_CH_CH1 = 0x0001, - STM32L4_LPTIM_CH_CH2 = 0x0002, - STM32L4_LPTIM_CH_CH3 = 0x0003, - STM32L4_LPTIM_CH_MASK = 0x000f, + STM32_LPTIM_CH_CHINVALID = 0x0000, + STM32_LPTIM_CH_CH1 = 0x0001, + STM32_LPTIM_CH_CH2 = 0x0002, + STM32_LPTIM_CH_CH3 = 0x0003, + STM32_LPTIM_CH_MASK = 0x000f, } stm32l4_lptim_channel_t; /* LPTIM Operations */ diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index 19914bc5b05ab..6859cfec064dc 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -68,7 +68,7 @@ void stm32l4_rcc_enablelse(void) /* Check if the External Low-Speed (LSE) oscillator is already running. */ - regval = getreg32(STM32L4_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) != (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) @@ -94,11 +94,11 @@ void stm32l4_rcc_enablelse(void) RCC_BDCR_LSEDRV_SHIFT; #endif - putreg32(regval, STM32L4_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready */ - while (((regval = getreg32(STM32L4_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) + while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { stm32l4_waste(); } @@ -116,7 +116,7 @@ void stm32l4_rcc_enablelse(void) regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L4_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32l4/stm32l4_lsi.c b/arch/arm/src/stm32l4/stm32l4_lsi.c index fb26a31ba160f..2897d3646bac1 100644 --- a/arch/arm/src/stm32l4/stm32l4_lsi.c +++ b/arch/arm/src/stm32l4/stm32l4_lsi.c @@ -46,11 +46,11 @@ void stm32l4_rcc_enablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L4_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32L4_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** @@ -67,7 +67,7 @@ void stm32l4_rcc_disablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L4_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c index 0b70b905db882..68ff5860cf27d 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c @@ -86,10 +86,10 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) * Disable the TC now and disable any further interrupts. */ - STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32L4_TIM_DISABLEINT(oneshot->tch, 0); - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(oneshot->tch, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, 0); /* The timer is no longer running */ @@ -200,7 +200,7 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, return -EBUSY; } - STM32L4_TIM_SETCLOCK(oneshot->tch, frequency); + STM32_TIM_SETCLOCK(oneshot->tch, frequency); /* Initialize the remaining fields in the state structure. */ @@ -302,19 +302,19 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32L4_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0); /* Set timer period */ oneshot->period = (uint32_t)period; - STM32L4_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); /* Start the counter */ - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_PULSE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - STM32L4_TIM_ACKINT(oneshot->tch, 0); - STM32L4_TIM_ENABLEINT(oneshot->tch, 0); + STM32_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_ENABLEINT(oneshot->tch, 0); /* Enable interrupts. We should get the callback when the interrupt * occurs. @@ -389,14 +389,14 @@ int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, tmrinfo("Cancelling...\n"); - count = STM32L4_TIM_GETCOUNTER(oneshot->tch); + count = STM32_TIM_GETCOUNTER(oneshot->tch); period = oneshot->period; /* Now we can disable the interrupt and stop the timer. */ - STM32L4_TIM_DISABLEINT(oneshot->tch, 0); - STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(oneshot->tch, 0); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); oneshot->running = false; oneshot->handler = NULL; diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index bce7dcc074286..00fb8ba0b3070 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -49,7 +49,7 @@ /* Number of endpoints */ -#define STM32L4_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ +#define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ /**************************************************************************** * Public Functions Prototypes diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index cfaf97f447309..ef8f20ba9dab0 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -115,8 +115,8 @@ */ #if CONFIG_USBDEV_EP1_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 1 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 1 # undef CONFIG_USBDEV_EP2_TXFIFO_SIZE # define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP3_TXFIFO_SIZE @@ -126,8 +126,8 @@ # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP2_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 2 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 2 # undef CONFIG_USBDEV_EP3_TXFIFO_SIZE # define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP4_TXFIFO_SIZE @@ -135,20 +135,20 @@ # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP3_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 3 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 3 # undef CONFIG_USBDEV_EP4_TXFIFO_SIZE # define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP4_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 4 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 4 # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP5_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 5 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 5 #endif /* Sanity check on allocations specified. */ @@ -168,48 +168,48 @@ * boundaries; FIFO sizes must be provided in units of 32-bit words. */ -#define STM32L4_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) -#define STM32L4_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) +#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) +#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) -#define STM32L4_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP0_TXFIFO_WORDS < 16 || STM32L4_EP0_TXFIFO_WORDS > 256 +#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 # error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP1_TXFIFO_BYTES != 0 && STM32L4_EP1_TXFIFO_WORDS < 16 +#if STM32_EP1_TXFIFO_BYTES != 0 && STM32_EP1_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP2_TXFIFO_BYTES != 0 && STM32L4_EP2_TXFIFO_WORDS < 16 +#if STM32_EP2_TXFIFO_BYTES != 0 && STM32_EP2_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP3_TXFIFO_BYTES != 0 && STM32L4_EP3_TXFIFO_WORDS < 16 +#if STM32_EP3_TXFIFO_BYTES != 0 && STM32_EP3_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP4_TXFIFO_BYTES != 0 && STM32L4_EP4_TXFIFO_WORDS < 16 +#if STM32_EP4_TXFIFO_BYTES != 0 && STM32_EP4_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP4_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP5_TXFIFO_BYTES != 0 && STM32L4_EP5_TXFIFO_WORDS < 16 +#if STM32_EP5_TXFIFO_BYTES != 0 && STM32_EP5_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP5_TXFIFO_SIZE is out of range" #endif @@ -238,95 +238,95 @@ /* Trace error codes */ -#define STM32L4_TRACEERR_ALLOCFAIL 0x01 -#define STM32L4_TRACEERR_BADCLEARFEATURE 0x02 -#define STM32L4_TRACEERR_BADDEVGETSTATUS 0x03 -#define STM32L4_TRACEERR_BADEPNO 0x04 -#define STM32L4_TRACEERR_BADEPGETSTATUS 0x05 -#define STM32L4_TRACEERR_BADGETCONFIG 0x06 -#define STM32L4_TRACEERR_BADGETSETDESC 0x07 -#define STM32L4_TRACEERR_BADGETSTATUS 0x08 -#define STM32L4_TRACEERR_BADSETADDRESS 0x09 -#define STM32L4_TRACEERR_BADSETCONFIG 0x0a -#define STM32L4_TRACEERR_BADSETFEATURE 0x0b -#define STM32L4_TRACEERR_BADTESTMODE 0x0c -#define STM32L4_TRACEERR_BINDFAILED 0x0d -#define STM32L4_TRACEERR_DISPATCHSTALL 0x0e -#define STM32L4_TRACEERR_DRIVER 0x0f -#define STM32L4_TRACEERR_DRIVERREGISTERED 0x10 -#define STM32L4_TRACEERR_EP0NOSETUP 0x11 -#define STM32L4_TRACEERR_EP0SETUPSTALLED 0x12 -#define STM32L4_TRACEERR_EPINNULLPACKET 0x13 -#define STM32L4_TRACEERR_EPINUNEXPECTED 0x14 -#define STM32L4_TRACEERR_EPOUTNULLPACKET 0x15 -#define STM32L4_TRACEERR_EPOUTUNEXPECTED 0x16 -#define STM32L4_TRACEERR_INVALIDCTRLREQ 0x17 -#define STM32L4_TRACEERR_INVALIDPARMS 0x18 -#define STM32L4_TRACEERR_IRQREGISTRATION 0x19 -#define STM32L4_TRACEERR_NOEP 0x1a -#define STM32L4_TRACEERR_NOTCONFIGURED 0x1b -#define STM32L4_TRACEERR_EPOUTQEMPTY 0x1c -#define STM32L4_TRACEERR_EPINREQEMPTY 0x1d -#define STM32L4_TRACEERR_NOOUTSETUP 0x1e -#define STM32L4_TRACEERR_POLLTIMEOUT 0x1f +#define STM32_TRACEERR_ALLOCFAIL 0x01 +#define STM32_TRACEERR_BADCLEARFEATURE 0x02 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 +#define STM32_TRACEERR_BADEPNO 0x04 +#define STM32_TRACEERR_BADEPGETSTATUS 0x05 +#define STM32_TRACEERR_BADGETCONFIG 0x06 +#define STM32_TRACEERR_BADGETSETDESC 0x07 +#define STM32_TRACEERR_BADGETSTATUS 0x08 +#define STM32_TRACEERR_BADSETADDRESS 0x09 +#define STM32_TRACEERR_BADSETCONFIG 0x0a +#define STM32_TRACEERR_BADSETFEATURE 0x0b +#define STM32_TRACEERR_BADTESTMODE 0x0c +#define STM32_TRACEERR_BINDFAILED 0x0d +#define STM32_TRACEERR_DISPATCHSTALL 0x0e +#define STM32_TRACEERR_DRIVER 0x0f +#define STM32_TRACEERR_DRIVERREGISTERED 0x10 +#define STM32_TRACEERR_EP0NOSETUP 0x11 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 +#define STM32_TRACEERR_EPINNULLPACKET 0x13 +#define STM32_TRACEERR_EPINUNEXPECTED 0x14 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 +#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 +#define STM32_TRACEERR_INVALIDPARMS 0x18 +#define STM32_TRACEERR_IRQREGISTRATION 0x19 +#define STM32_TRACEERR_NOEP 0x1a +#define STM32_TRACEERR_NOTCONFIGURED 0x1b +#define STM32_TRACEERR_EPOUTQEMPTY 0x1c +#define STM32_TRACEERR_EPINREQEMPTY 0x1d +#define STM32_TRACEERR_NOOUTSETUP 0x1e +#define STM32_TRACEERR_POLLTIMEOUT 0x1f /* Trace interrupt codes */ -#define STM32L4_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ -#define STM32L4_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ - -#define STM32L4_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ -#define STM32L4_TRACEINTID_EPIN (10 + 1) -#define STM32L4_TRACEINTID_MISMATCH (10 + 2) -#define STM32L4_TRACEINTID_WAKEUP (10 + 3) -#define STM32L4_TRACEINTID_SUSPEND (10 + 4) -#define STM32L4_TRACEINTID_SOF (10 + 5) -#define STM32L4_TRACEINTID_RXFIFO (10 + 6) -#define STM32L4_TRACEINTID_DEVRESET (10 + 7) -#define STM32L4_TRACEINTID_ENUMDNE (10 + 8) -#define STM32L4_TRACEINTID_IISOIXFR (10 + 9) -#define STM32L4_TRACEINTID_IISOOXFR (10 + 10) -#define STM32L4_TRACEINTID_SRQ (10 + 11) -#define STM32L4_TRACEINTID_OTG (10 + 12) - -#define STM32L4_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ -#define STM32L4_TRACEINTID_EPOUT_EPDISD (40 + 1) -#define STM32L4_TRACEINTID_EPOUT_SETUP (40 + 2) -#define STM32L4_TRACEINTID_DISPATCH (40 + 3) - -#define STM32L4_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ -#define STM32L4_TRACEINTID_EPGETSTATUS (50 + 1) -#define STM32L4_TRACEINTID_DEVGETSTATUS (50 + 2) -#define STM32L4_TRACEINTID_IFGETSTATUS (50 + 3) -#define STM32L4_TRACEINTID_CLEARFEATURE (50 + 4) -#define STM32L4_TRACEINTID_SETFEATURE (50 + 5) -#define STM32L4_TRACEINTID_SETADDRESS (50 + 6) -#define STM32L4_TRACEINTID_GETSETDESC (50 + 7) -#define STM32L4_TRACEINTID_GETCONFIG (50 + 8) -#define STM32L4_TRACEINTID_SETCONFIG (50 + 9) -#define STM32L4_TRACEINTID_GETSETIF (50 + 10) -#define STM32L4_TRACEINTID_SYNCHFRAME (50 + 11) - -#define STM32L4_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ -#define STM32L4_TRACEINTID_EPIN_TOC (70 + 1) -#define STM32L4_TRACEINTID_EPIN_ITTXFE (70 + 2) -#define STM32L4_TRACEINTID_EPIN_EPDISD (70 + 3) -#define STM32L4_TRACEINTID_EPIN_TXFE (70 + 4) - -#define STM32L4_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ - -#define STM32L4_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ -#define STM32L4_TRACEINTID_OUTRECVD (90 + 1) -#define STM32L4_TRACEINTID_OUTDONE (90 + 2) -#define STM32L4_TRACEINTID_SETUPDONE (90 + 3) -#define STM32L4_TRACEINTID_SETUPRECVD (90 + 4) +#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ +#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ + +#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ +#define STM32_TRACEINTID_EPIN (10 + 1) +#define STM32_TRACEINTID_MISMATCH (10 + 2) +#define STM32_TRACEINTID_WAKEUP (10 + 3) +#define STM32_TRACEINTID_SUSPEND (10 + 4) +#define STM32_TRACEINTID_SOF (10 + 5) +#define STM32_TRACEINTID_RXFIFO (10 + 6) +#define STM32_TRACEINTID_DEVRESET (10 + 7) +#define STM32_TRACEINTID_ENUMDNE (10 + 8) +#define STM32_TRACEINTID_IISOIXFR (10 + 9) +#define STM32_TRACEINTID_IISOOXFR (10 + 10) +#define STM32_TRACEINTID_SRQ (10 + 11) +#define STM32_TRACEINTID_OTG (10 + 12) + +#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ +#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) +#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) +#define STM32_TRACEINTID_DISPATCH (40 + 3) + +#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ +#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) +#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) +#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) +#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) +#define STM32_TRACEINTID_SETFEATURE (50 + 5) +#define STM32_TRACEINTID_SETADDRESS (50 + 6) +#define STM32_TRACEINTID_GETSETDESC (50 + 7) +#define STM32_TRACEINTID_GETCONFIG (50 + 8) +#define STM32_TRACEINTID_SETCONFIG (50 + 9) +#define STM32_TRACEINTID_GETSETIF (50 + 10) +#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) + +#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ +#define STM32_TRACEINTID_EPIN_TOC (70 + 1) +#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) +#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) +#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) + +#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ + +#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ +#define STM32_TRACEINTID_OUTRECVD (90 + 1) +#define STM32_TRACEINTID_OUTDONE (90 + 2) +#define STM32_TRACEINTID_SETUPDONE (90 + 3) +#define STM32_TRACEINTID_SETUPRECVD (90 + 4) /* Endpoints ****************************************************************/ /* Odd physical endpoint numbers are IN; even are OUT */ -#define STM32L4_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) -#define STM32L4_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) +#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) +#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) /* Endpoint 0 */ @@ -336,16 +336,16 @@ * This is a bitmap, and the first endpoint (0) is reserved. */ -#define STM32L4_EP_AVAILABLE (((1 << STM32L4_NENDPOINTS) - 1) & ~1) +#define STM32_EP_AVAILABLE (((1 << STM32_NENDPOINTS) - 1) & ~1) /* Maximum packet sizes for full speed endpoints */ -#define STM32L4_MAXPACKET (64) /* Max packet size (1-64) */ +#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ /* Delays *******************************************************************/ -#define STM32L4_READY_DELAY 200000 -#define STM32L4_FLUSH_DELAY 200000 +#define STM32_READY_DELAY 200000 +#define STM32_FLUSH_DELAY 200000 /* Request queue operations *************************************************/ @@ -538,8 +538,8 @@ struct stm32l4_usbdev_s /* The endpoint lists */ - struct stm32l4_ep_s epin[STM32L4_NENDPOINTS]; - struct stm32l4_ep_s epout[STM32L4_NENDPOINTS]; + struct stm32l4_ep_s epin[STM32_NENDPOINTS]; + struct stm32l4_ep_s epout[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -789,37 +789,37 @@ static const struct usbdev_ops_s g_devops = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(STM32L4_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32L4_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32L4_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADEPNO), - TRACE_STR(STM32L4_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32L4_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32L4_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32L4_TRACEERR_BADTESTMODE), - TRACE_STR(STM32L4_TRACEERR_BINDFAILED), - TRACE_STR(STM32L4_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32L4_TRACEERR_DRIVER), - TRACE_STR(STM32L4_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32L4_TRACEERR_EP0NOSETUP), - TRACE_STR(STM32L4_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32L4_TRACEERR_EPINNULLPACKET), - TRACE_STR(STM32L4_TRACEERR_EPINUNEXPECTED), - TRACE_STR(STM32L4_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32L4_TRACEERR_EPOUTUNEXPECTED), - TRACE_STR(STM32L4_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32L4_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32L4_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32L4_TRACEERR_NOEP), - TRACE_STR(STM32L4_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32L4_TRACEERR_EPOUTQEMPTY), - TRACE_STR(STM32L4_TRACEERR_EPINREQEMPTY), - TRACE_STR(STM32L4_TRACEERR_NOOUTSETUP), - TRACE_STR(STM32L4_TRACEERR_POLLTIMEOUT), + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BADTESTMODE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOEP), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), TRACE_STR_END }; #endif @@ -831,48 +831,48 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(STM32L4_TRACEINTID_USB), - TRACE_STR(STM32L4_TRACEINTID_INTPENDING), - TRACE_STR(STM32L4_TRACEINTID_EPOUT), - TRACE_STR(STM32L4_TRACEINTID_EPIN), - TRACE_STR(STM32L4_TRACEINTID_MISMATCH), - TRACE_STR(STM32L4_TRACEINTID_WAKEUP), - TRACE_STR(STM32L4_TRACEINTID_SUSPEND), - TRACE_STR(STM32L4_TRACEINTID_SOF), - TRACE_STR(STM32L4_TRACEINTID_RXFIFO), - TRACE_STR(STM32L4_TRACEINTID_DEVRESET), - TRACE_STR(STM32L4_TRACEINTID_ENUMDNE), - TRACE_STR(STM32L4_TRACEINTID_IISOIXFR), - TRACE_STR(STM32L4_TRACEINTID_IISOOXFR), - TRACE_STR(STM32L4_TRACEINTID_SRQ), - TRACE_STR(STM32L4_TRACEINTID_OTG), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_XFRC), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_EPDISD), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_SETUP), - TRACE_STR(STM32L4_TRACEINTID_DISPATCH), - TRACE_STR(STM32L4_TRACEINTID_GETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32L4_TRACEINTID_SETFEATURE), - TRACE_STR(STM32L4_TRACEINTID_SETADDRESS), - TRACE_STR(STM32L4_TRACEINTID_GETSETDESC), - TRACE_STR(STM32L4_TRACEINTID_GETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_SETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_GETSETIF), - TRACE_STR(STM32L4_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32L4_TRACEINTID_EPIN_XFRC), - TRACE_STR(STM32L4_TRACEINTID_EPIN_TOC), - TRACE_STR(STM32L4_TRACEINTID_EPIN_ITTXFE), - TRACE_STR(STM32L4_TRACEINTID_EPIN_EPDISD), - TRACE_STR(STM32L4_TRACEINTID_EPIN_TXFE), - TRACE_STR(STM32L4_TRACEINTID_EPIN_EMPWAIT), - TRACE_STR(STM32L4_TRACEINTID_OUTNAK), - TRACE_STR(STM32L4_TRACEINTID_OUTRECVD), - TRACE_STR(STM32L4_TRACEINTID_OUTDONE), - TRACE_STR(STM32L4_TRACEINTID_SETUPDONE), - TRACE_STR(STM32L4_TRACEINTID_SETUPRECVD), + TRACE_STR(STM32_TRACEINTID_USB), + TRACE_STR(STM32_TRACEINTID_INTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUT), + TRACE_STR(STM32_TRACEINTID_EPIN), + TRACE_STR(STM32_TRACEINTID_MISMATCH), + TRACE_STR(STM32_TRACEINTID_WAKEUP), + TRACE_STR(STM32_TRACEINTID_SUSPEND), + TRACE_STR(STM32_TRACEINTID_SOF), + TRACE_STR(STM32_TRACEINTID_RXFIFO), + TRACE_STR(STM32_TRACEINTID_DEVRESET), + TRACE_STR(STM32_TRACEINTID_ENUMDNE), + TRACE_STR(STM32_TRACEINTID_IISOIXFR), + TRACE_STR(STM32_TRACEINTID_IISOOXFR), + TRACE_STR(STM32_TRACEINTID_SRQ), + TRACE_STR(STM32_TRACEINTID_OTG), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), + TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SETADDRESS), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), + TRACE_STR(STM32_TRACEINTID_OUTNAK), + TRACE_STR(STM32_TRACEINTID_OUTRECVD), + TRACE_STR(STM32_TRACEINTID_OUTDONE), + TRACE_STR(STM32_TRACEINTID_SETUPDONE), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD), TRACE_STR_END }; #endif @@ -1068,7 +1068,7 @@ static void stm32l4_ep0in_activate(void) /* Set the max packet size of the IN EP. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(0)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(0)); regval &= ~OTGFS_DIEPCTL0_MPSIZ_MASK; #if CONFIG_USBDEV_EP0_MAXSIZE == 8 @@ -1083,13 +1083,13 @@ static void stm32l4_ep0in_activate(void) # error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" #endif - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(0)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(0)); /* Clear global IN NAK */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGINAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** @@ -1109,13 +1109,13 @@ static void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv) regval = (USB_SIZEOF_CTRLREQ * 3 << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) | (OTGFS_DOEPTSIZ0_PKTCNT) | (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPTSIZ(0)); + stm32l4_putreg(regval, STM32_OTGFS_DOEPTSIZ(0)); /* Then clear NAKing and enable the transfer */ - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(0)); + regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(0)); regval |= (OTGFS_DOEPCTL0_CNAK | OTGFS_DOEPCTL0_EPENA); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(0)); + stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(0)); } /**************************************************************************** @@ -1140,7 +1140,7 @@ static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, /* Get the TxFIFO for this endpoint (same as the endpoint number) */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(privep->epphy); + regaddr = STM32_OTGFS_DFIFO_DEP(privep->epphy); /* Then transfer each word to the TxFIFO */ @@ -1177,7 +1177,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Read the DIEPSIZx register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPTSIZ(privep->epphy)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ @@ -1223,11 +1223,11 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Save DIEPSIZx register value */ - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTSIZ(privep->epphy)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Read the DIEPCTLx register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(privep->epphy)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); /* If this is an isochronous endpoint, then set the even/odd frame bit * the DIEPCTLx register. @@ -1239,7 +1239,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, * even/odd frame to match. */ - uint32_t status = stm32l4_getreg(STM32L4_OTGFS_DSTS); + uint32_t status = stm32l4_getreg(STM32_OTGFS_DSTS); if ((status & OTGFS_DSTS_SOFFN0) == OTGFS_DSTS_SOFFN_EVEN) { regval |= OTGFS_DIEPCTL_SEVNFRM; @@ -1254,7 +1254,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, regval &= ~OTGFS_DIEPCTL_EPDIS; regval |= (OTGFS_DIEPCTL_CNAK | OTGFS_DIEPCTL_EPENA); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(privep->epphy)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); /* Transfer the data to the TxFIFO. At this point, the caller has already * assured that there is sufficient space in the TxFIFO to hold the @@ -1308,7 +1308,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, privreq = stm32l4_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPINREQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); /* There is no TX transfer in progress and no new pending TX * requests to send. To stop transmitting any data on a particular @@ -1316,7 +1316,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * bit, the following field must be programmed. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= OTGFS_DIEPCTL_SNAK; stm32l4_putreg(regval, regaddr); @@ -1419,7 +1419,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * n: n words available */ - regaddr = STM32L4_OTGFS_DTXFSTS(privep->epphy); + regaddr = STM32_OTGFS_DTXFSTS(privep->epphy); /* Check for space in the TxFIFO. If space in the TxFIFO is not * available, then set up an interrupt to resume the transfer when @@ -1429,23 +1429,23 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, regval = stm32l4_getreg(regaddr); if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EMPWAIT), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval); /* There is insufficient space in the TxFIFO. Wait for a TxFIFO * empty interrupt and try again. */ - uint32_t empmsk = stm32l4_getreg(STM32L4_OTGFS_DIEPEMPMSK); + uint32_t empmsk = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); empmsk |= OTGFS_DIEPEMPMSK(privep->epphy); - stm32l4_putreg(empmsk, STM32L4_OTGFS_DIEPEMPMSK); + stm32l4_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); #ifdef CONFIG_DEBUG_FEATURES /* Check if the configured TXFIFO size is sufficient for a given * request. If not, raise an assertion here. */ - regval = stm32l4_getreg(STM32L4_OTG_DIEPTXF(privep->epphy)); + regval = stm32l4_getreg(STM32_OTG_DIEPTXF(privep->epphy)); regval &= OTGFS_DIEPTXF_INEPTXFD_MASK; regval >>= OTGFS_DIEPTXF_INEPTXFD_SHIFT; uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", @@ -1519,7 +1519,7 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, * we might as well use the address associated with EP0. */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(EP0); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits and write 4 x 8-bits at time * (to avoid unaligned accesses) @@ -1565,7 +1565,7 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) * we might as well use the address associated with EP0. */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(EP0); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits at time */ @@ -1607,7 +1607,7 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, * should not happen. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); privep->active = false; return; } @@ -1681,7 +1681,7 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, * does not become constipated. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOOUTSETUP), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); stm32l4_rxfifo_discard(privep, bcnt); privep->active = false; } @@ -1732,7 +1732,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * NAKing is working as expected. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); /* Discard the data in the RxFIFO */ @@ -1814,7 +1814,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, privreq = stm32l4_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); /* There are no read requests to be setup. Configure the @@ -1823,7 +1823,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, * NAK after a transfer is completed until SNAK is cleared). */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= OTGFS_DOEPCTL_SNAK; stm32l4_putreg(regval, regaddr); @@ -1842,7 +1842,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, if (privreq->req.len <= 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTNULLPACKET), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); stm32l4_req_complete(privep, OK); } @@ -1870,7 +1870,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Then setup the hardware to perform this transfer */ - regaddr = STM32L4_OTGFS_DOEPTSIZ(privep->epphy); + regaddr = STM32_OTGFS_DOEPTSIZ(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~(OTGFS_DOEPTSIZ_XFRSIZ_MASK | OTGFS_DOEPTSIZ_PKTCNT_MASK); regval |= (xfrsize << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT); @@ -1879,7 +1879,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Then enable the transfer */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); /* When an isochronous transfer is enabled the Even/Odd frame bit must @@ -2021,7 +2021,7 @@ struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep; uint8_t epphy = USB_EPNO(eplog); - if (epphy >= STM32L4_NENDPOINTS) + if (epphy >= STM32_NENDPOINTS) { return NULL; } @@ -2057,7 +2057,7 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, { int ret = -EIO; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); if (priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -2070,7 +2070,7 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); priv->stalled = true; } @@ -2093,9 +2093,9 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Clear the Remote Wake-up Signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); /* Flush the EP0 Tx FIFO */ @@ -2112,17 +2112,17 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Mark all endpoints as available */ - priv->epavail[0] = STM32L4_EP_AVAILABLE; - priv->epavail[1] = STM32L4_EP_AVAILABLE; + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; /* Disable all end point interrupts */ - for (i = 0; i < STM32L4_NENDPOINTS ; i++) + for (i = 0; i < STM32_NENDPOINTS ; i++) { /* Disable endpoint interrupts */ - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); /* Return write requests to the class implementation */ @@ -2143,22 +2143,22 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) privep->stalled = false; } - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); + stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Mask all device endpoint interrupts except EP0 */ regval = (OTGFS_DAINT_IEP(EP0) | OTGFS_DAINT_OEP(EP0)); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); /* Unmask OUT interrupts */ regval = (OTGFS_DOEPMSK_XFRCM | OTGFS_DOEPMSK_STUPM | OTGFS_DOEPMSK_EPDM); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPMSK); + stm32l4_putreg(regval, STM32_OTGFS_DOEPMSK); /* Unmask IN interrupts */ regval = (OTGFS_DIEPMSK_XFRCM | OTGFS_DIEPMSK_EPDM | OTGFS_DIEPMSK_TOM); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPMSK); + stm32l4_putreg(regval, STM32_OTGFS_DIEPMSK); /* Reset device address to 0 */ @@ -2212,7 +2212,7 @@ static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, break; default: - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADTESTMODE), testmode); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); priv->dotest = false; priv->testmode = OTGFS_TESTMODE_DISABLED; priv->stalled = true; @@ -2249,7 +2249,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSTATUS), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); if (!priv->addressed || ctrlreq->len != 2 || USB_REQ_ISOUT(ctrlreq->type) || @@ -2264,12 +2264,12 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, case USB_REQ_RECIPIENT_ENDPOINT: { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_EPGETSTATUS), 0); + STM32_TRACEINTID_EPGETSTATUS), 0); privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index); if (!privep) { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADEPGETSTATUS), 0); + STM32_TRACEERR_BADEPGETSTATUS), 0); priv->stalled = true; } else @@ -2294,7 +2294,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, if (ctrlreq->index == 0) { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_DEVGETSTATUS), 0); + STM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup and self-powered */ @@ -2309,7 +2309,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, else { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADDEVGETSTATUS), 0); + STM32_TRACEERR_BADDEVGETSTATUS), 0); priv->stalled = true; } } @@ -2318,7 +2318,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, case USB_REQ_RECIPIENT_INTERFACE: { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_IFGETSTATUS), 0); + STM32_TRACEINTID_IFGETSTATUS), 0); priv->ep0data[0] = 0; priv->ep0data[1] = 0; @@ -2329,7 +2329,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, default: { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADGETSTATUS), 0); + STM32_TRACEERR_BADGETSTATUS), 0); priv->stalled = true; } break; @@ -2346,7 +2346,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_CLEARFEATURE), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); if (priv->addressed != 0 && ctrlreq->len == 0) { uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; @@ -2373,7 +2373,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADCLEARFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); priv->stalled = true; } } @@ -2387,7 +2387,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETFEATURE), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); if (priv->addressed != 0 && ctrlreq->len == 0) { uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; @@ -2419,13 +2419,13 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->stalled = true; } } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->stalled = true; } } @@ -2439,7 +2439,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETADDRESS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value); if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2457,7 +2457,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); priv->stalled = true; } } @@ -2478,7 +2478,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETDESC), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) { @@ -2486,7 +2486,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETSETDESC), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); priv->stalled = true; } } @@ -2500,7 +2500,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETCONFIG), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); if (priv->addressed && (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2512,7 +2512,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); priv->stalled = true; } } @@ -2526,7 +2526,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETCONFIG), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); if (priv->addressed && (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2559,7 +2559,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); priv->stalled = true; } } @@ -2580,7 +2580,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETIF), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); stm32l4_req_dispatch(priv, &priv->ctrlreq); } break; @@ -2593,13 +2593,13 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDCTRLREQ), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); priv->stalled = true; } break; @@ -2623,7 +2623,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) if (priv->ep0state != EP0STATE_SETUP_READY) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0NOSETUP), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); return; } @@ -2673,7 +2673,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) if (priv->stalled) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0SETUPSTALLED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); stm32l4_ep0_stall(priv); } @@ -2761,8 +2761,8 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINT); - regval &= stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINT); + regval &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; if (daint == 0) @@ -2777,10 +2777,10 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINT); + regval = stm32l4_getreg(STM32_OTGFS_DAINT); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTUNEXPECTED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), (uint16_t)regval); epno = 0; @@ -2788,9 +2788,9 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { if ((daint & 1) != 0) { - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPINT(epno)); + regval = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(epno)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); } epno++; @@ -2811,8 +2811,8 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { /* Yes.. get the OUT endpoint interrupt status */ - doepint = stm32l4_getreg(STM32L4_OTGFS_DOEPINT(epno)); - doepint &= stm32l4_getreg(STM32L4_OTGFS_DOEPMSK); + doepint = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); + doepint &= stm32l4_getreg(STM32_OTGFS_DOEPMSK); /* Transfer completed interrupt. * This interrupt is triggered when stm32l4_rxinterrupt() removes @@ -2823,13 +2823,13 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_XFRC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ stm32l4_putreg(OTGFS_DOEPINT_XFRC, - STM32L4_OTGFS_DOEPINT(epno)); + STM32_OTGFS_DOEPINT(epno)); /* Handle the RX transfer data ready event */ @@ -2844,13 +2844,13 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_EPDISD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ stm32l4_putreg(OTGFS_DOEPINT_EPDISD, - STM32L4_OTGFS_DOEPINT(epno)); + STM32_OTGFS_DOEPINT(epno)); } #endif @@ -2858,7 +2858,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_SETUP), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), priv->ep0state); /* Handle the receipt of the IN SETUP packets now (OUT setup @@ -2872,7 +2872,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) } stm32l4_putreg(OTGFS_DOEPINT_SETUP, - STM32L4_OTGFS_DOEPINT(epno)); + STM32_OTGFS_DOEPINT(epno)); } } @@ -2892,10 +2892,10 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) static inline void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv) { - uint32_t regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + uint32_t regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval &= OTGFS_DCTL_TCTL_MASK; regval |= (uint32_t)priv->testmode << OTGFS_DCTL_TCTL_SHIFT; - stm32l4_putreg(regval , STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval , STM32_OTGFS_DCTL); priv->dotest = 0; priv->testmode = OTGFS_TESTMODE_DISABLED; @@ -3006,8 +3006,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - daint = stm32l4_getreg(STM32L4_OTGFS_DAINT); - daint &= stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + daint = stm32l4_getreg(STM32_OTGFS_DAINT); + daint &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); daint &= OTGFS_DAINT_IEP_MASK; if (daint == 0) @@ -3022,8 +3022,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - daint = stm32l4_getreg(STM32L4_OTGFS_DAINT); - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPINUNEXPECTED), + daint = stm32l4_getreg(STM32_OTGFS_DAINT); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), (uint16_t)daint); daint &= OTGFS_DAINT_IEP_MASK; @@ -3034,8 +3034,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((daint & 1) != 0) { uerr("DIEPINT(%d) = %08" PRIx32 "\n", - epno, stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno))); - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(epno)); + epno, stm32l4_getreg(STM32_OTGFS_DIEPINT(epno))); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); } epno++; @@ -3059,7 +3059,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * register. */ - mask = stm32l4_getreg(STM32L4_OTGFS_DIEPMSK); + mask = stm32l4_getreg(STM32_OTGFS_DIEPMSK); /* Check if the TxFIFO not empty interrupt is enabled for this * endpoint in the DIEPMSK register. Bits n corresponds to @@ -3068,7 +3068,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * no TXFE bit in the mask register, so we fake one here. */ - empty = stm32l4_getreg(STM32L4_OTGFS_DIEPEMPMSK); + empty = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0) { mask |= OTGFS_DIEPINT_TXFE; @@ -3078,7 +3078,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * interrupts. */ - diepint = stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno)) & mask; + diepint = stm32l4_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; /* Decode and process the enabled, pending interrupts */ @@ -3086,7 +3086,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_XFRC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), (uint16_t)diepint); /* It is possible that logic may be waiting for a the @@ -3096,9 +3096,9 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32L4_OTGFS_DIEPEMPMSK); + stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); stm32l4_putreg(OTGFS_DIEPINT_XFRC, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); /* IN transfer complete */ @@ -3109,9 +3109,9 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_TOC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_TOC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_TOC, STM32L4_OTGFS_DIEPINT(epno)); + stm32l4_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); } /* IN token received when TxFIFO is empty. Applies to non-periodic @@ -3123,11 +3123,11 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_ITTXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_ITTXFE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); stm32l4_epin_request(priv, &priv->epin[epno]); stm32l4_putreg(OTGFS_DIEPINT_ITTXFE, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } /* IN endpoint NAK effective (ignored as this used only in polled @@ -3136,10 +3136,10 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) #if 0 if ((diepint & OTGFS_DIEPINT_INEPNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_INEPNE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); stm32l4_putreg(OTGFS_DIEPINT_INEPNE, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3149,10 +3149,10 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) #if 0 if ((diepint & OTGFS_DIEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EPDISD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); stm32l4_putreg(OTGFS_DIEPINT_EPDISD, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3160,7 +3160,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_TXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_TXFE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint); /* If we were waiting for TxFIFO to become empty, the we might @@ -3176,7 +3176,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32L4_OTGFS_DIEPEMPMSK); + stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); /* Handle TxFIFO empty */ @@ -3186,7 +3186,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) /* Clear the pending TxFIFO empty interrupt */ stm32l4_putreg(OTGFS_DIEPINT_TXFE, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } } @@ -3210,16 +3210,16 @@ static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) /* Restart the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Clear remote wake-up signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); /* Restore full power -- whatever that means for this particular board */ @@ -3261,7 +3261,7 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * connected to the host, and that we have been configured. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32l4_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) { @@ -3269,16 +3269,16 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * PHY clock. */ - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); regval |= OTGFS_PCGCCTL_STPPCLK; - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); /* Setting OTGFS_PCGCCTL_GATEHCLK gate HCLK to modules other than * the AHB Slave and Master and wakeup logic. */ regval |= OTGFS_PCGCCTL_GATEHCLK; - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); } #endif @@ -3305,23 +3305,23 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) int bcnt; int epphy; - while (0 != (stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) + while (0 != (stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) { /* Get the status from the top of the FIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP); + regval = stm32l4_getreg(STM32_OTGFS_GRXSTSP); /* Decode status fields */ epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT; - /* Workaround for bad values read from the STM32L4_OTGFS_GRXSTSP + /* Workaround for bad values read from the STM32_OTGFS_GRXSTSP * register happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c * All of which provide out of range indexes for epout[epphy] */ - if (epphy < STM32L4_NENDPOINTS) + if (epphy < STM32_NENDPOINTS) { privep = &priv->epout[epphy]; @@ -3338,7 +3338,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTNAK: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTNAK), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); } break; @@ -3351,7 +3351,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTRECVD: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTRECVD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT; @@ -3375,7 +3375,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTDONE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTDONE), epphy); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); } break; @@ -3392,7 +3392,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_SETUPDONE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); /* On the L4 This event does not occur on the next SETUP @@ -3412,7 +3412,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) { uint16_t datlen; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPRECVD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); /* Read EP0 setup data. NOTE: If multiple SETUP packets are @@ -3459,7 +3459,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT); } @@ -3489,10 +3489,10 @@ static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv) * PHY interface. */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_TRDT_MASK; regval |= OTGFS_GUSBCFG_TRDT(6); - stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG); + stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); } /**************************************************************************** @@ -3515,7 +3515,7 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) * transfers. */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Is this an isochronous IN endpoint? */ @@ -3538,9 +3538,9 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32L4_OTGFS_DSTS); + dsts = stm32l4_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3599,7 +3599,7 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) * DOEPCTLx:EPENA = 1 */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Is this an isochronous OUT endpoint? */ @@ -3622,9 +3622,9 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32L4_OTGFS_DSTS); + dsts = stm32l4_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3684,7 +3684,7 @@ static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) /* Check for session end detected */ - regval = stm32l4_getreg(STM32L4_OTGFS_GOTGINT); + regval = stm32l4_getreg(STM32_OTGFS_GOTGINT); if ((regval & OTGFS_GOTGINT_SEDET) != 0) { #warning "Missing logic" @@ -3692,7 +3692,7 @@ static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) /* Clear OTG interrupt */ - stm32l4_putreg(regval, STM32L4_OTGFS_GOTGINT); + stm32l4_putreg(regval, STM32_OTGFS_GOTGINT); } #endif @@ -3717,11 +3717,11 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t reserved; - usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), priv->ep0state); /* Assure that we are in device mode */ - DEBUGASSERT((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == + DEBUGASSERT((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == OTGFS_GINTSTS_DEVMODE); /* Get the state of all enabled interrupts. We will do this repeatedly @@ -3733,16 +3733,16 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Get the set of pending, un-masked interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); + regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); reserved = (regval & OTGFS_GINT_RESERVED); - regval &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + regval &= stm32l4_getreg(STM32_OTGFS_GINTMSK); /* With out modifying the reserved bits, acknowledge all * **Writable** pending irqs we will service below */ stm32l4_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), - STM32L4_OTGFS_GINTSTS); + STM32_OTGFS_GINTSTS); /* Break out of the loop when there are no further pending (and * unmasked) interrupts to be processes. @@ -3753,7 +3753,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) break; } - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_INTPENDING), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t)regval); /* OUT endpoint interrupt. The core sets this bit to indicate that an @@ -3762,7 +3762,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_OEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); stm32l4_epout_interrupt(priv); } @@ -3773,7 +3773,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_IEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); stm32l4_epin_interrupt(priv); } @@ -3783,7 +3783,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_DEBUG_FEATURES if ((regval & OTGFS_GINT_MMIS) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_MISMATCH), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval); } #endif @@ -3792,7 +3792,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_WKUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WAKEUP), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); stm32l4_resumeinterrupt(priv); } @@ -3801,7 +3801,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_USBSUSP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSPEND), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); stm32l4_suspendinterrupt(priv); } @@ -3811,7 +3811,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_SOFINTERRUPT if ((regval & OTGFS_GINT_SOF) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SOF), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); usbdev_sof_irq(&priv->usbdev, stm32l4_getframe(&priv->usbdev)); } @@ -3823,7 +3823,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_RXFLVL) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RXFIFO), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); stm32l4_rxinterrupt(priv); } @@ -3832,13 +3832,13 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & (OTGFS_GINT_USBRST | OTGFS_GINT_RSTDET)) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DEVRESET), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval); /* Perform the device reset */ stm32l4_usbreset(priv); - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3846,7 +3846,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_ENUMDNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ENUMDNE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); stm32l4_enuminterrupt(priv); } @@ -3860,7 +3860,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_ISOCHRONOUS if ((regval & OTGFS_GINT_IISOIXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOIXFR), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); stm32l4_isocininterrupt(priv); } @@ -3877,7 +3877,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_IISOOXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOOXFR), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); stm32l4_isocoutinterrupt(priv); } @@ -3888,7 +3888,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_VBUSSENSING if ((regval & OTGFS_GINT_SRQ) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SRQ), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); stm32l4_sessioninterrupt(priv); } @@ -3897,14 +3897,14 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_OTG) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OTG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); stm32l4_otginterrupt(priv); } #endif } - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3927,14 +3927,14 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) /* First, make sure that there is no GNOAKEFF interrupt pending. */ #if 0 - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32L4_OTGFS_GINTSTS); + stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #endif /* Enable Global OUT NAK mode in the core. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_SGONAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); #if 0 /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK @@ -3942,8 +3942,8 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * from the RxFIFO, the core sets the GONAKEFF interrupt. */ - while ((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32L4_OTGFS_GINTSTS); + while ((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); + stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #else /* Since we are in the interrupt handler, we cannot wait inline for the @@ -3954,7 +3954,7 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * reported in OTGFS DCTL register? */ - while ((stm32l4_getreg(STM32L4_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); + while ((stm32l4_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); #endif } @@ -3972,9 +3972,9 @@ static void stm32l4_disablegonak(struct stm32l4_ep_s *privep) /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGONAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** @@ -4042,7 +4042,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, * register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); if ((regval & OTGFS_DOEPCTL_USBAEP) == 0) { @@ -4066,9 +4066,9 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } @@ -4138,7 +4138,7 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, * register. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { @@ -4164,9 +4164,9 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } @@ -4264,7 +4264,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) * int DOECPTL register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~OTGFS_DOEPCTL_USBAEP; regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_SNAK); @@ -4275,7 +4275,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) */ #if 0 /* Doesn't happen */ - regaddr = STM32L4_OTGFS_DOEPINT(privep->epphy); + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4285,7 +4285,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) /* Clear the EPDISD interrupt indication */ - stm32l4_putreg(OTGFS_DOEPINT_EPDISD, STM32L4_OTGFS_DOEPINT(privep->epphy)); + stm32l4_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); /* Then disable the Global OUT NAK mode to continue receiving data * from other non-disabled OUT endpoints. @@ -4295,9 +4295,9 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued read requests */ @@ -4326,7 +4326,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * hardware. Trying to disable again will just hang in the wait. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { @@ -4342,11 +4342,11 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * to poll this bit below). */ - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, STM32L4_OTGFS_DIEPINT(privep->epphy)); + stm32l4_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); /* Set the endpoint in NAK mode */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); @@ -4356,7 +4356,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * NAK mode */ - regaddr = STM32L4_OTGFS_DIEPINT(privep->epphy); + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); /* Clear the INEPNE interrupt indication */ @@ -4369,7 +4369,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) */ flags = enter_critical_section(); - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); @@ -4379,7 +4379,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * endpoint is completely disabled. */ - regaddr = STM32L4_OTGFS_DIEPINT(privep->epphy); + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); /* Clear the EPDISD interrupt indication */ @@ -4392,9 +4392,9 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued write requests */ @@ -4417,7 +4417,7 @@ static int stm32l4_ep_disable(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -4457,7 +4457,7 @@ static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -4468,7 +4468,7 @@ static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) kmm_malloc(sizeof(struct stm32l4_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } @@ -4492,7 +4492,7 @@ static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -4566,7 +4566,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -4579,7 +4579,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); return -ESHUTDOWN; } @@ -4658,7 +4658,7 @@ static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -4704,7 +4704,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) * in the DOECPTL register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_STALL); stm32l4_putreg(regval, regaddr); @@ -4714,7 +4714,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) */ #if 0 /* Doesn't happen */ - regaddr = STM32L4_OTGFS_DOEPINT(privep->epphy); + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4742,7 +4742,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) * register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= OTGFS_DOEPCTL_STALL; stm32l4_putreg(regval, regaddr); @@ -4769,7 +4769,7 @@ static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) /* Get the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); /* Then stall the endpoint */ @@ -4830,7 +4830,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); stallbit = OTGFS_DIEPCTL_STALL; data0bit = OTGFS_DIEPCTL_SD0PID; } @@ -4838,7 +4838,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); stallbit = OTGFS_DOEPCTL_STALL; data0bit = OTGFS_DOEPCTL_SD0PID; } @@ -4966,9 +4966,9 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, * by the hardware. */ - if (epphy >= STM32L4_NENDPOINTS) + if (epphy >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPNO), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); return NULL; } @@ -4988,7 +4988,7 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, * endpoints. */ - for (epno = 1; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 1; epno < STM32_NENDPOINTS; epno++) { uint8_t bit = 1 << epno; if ((epavail & bit) != 0) @@ -5007,7 +5007,7 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, /* We should not get here */ } - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOEP), (uint16_t)eplog); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); leave_critical_section(flags); return NULL; } @@ -5055,7 +5055,7 @@ static int stm32l4_getframe(struct usbdev_s *dev) /* Return the last frame number of the last SOF detected by the hardware */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32l4_getreg(STM32_OTGFS_DSTS); return (int)((regval & OTGFS_DSTS_SOFFN_MASK) >> OTGFS_DSTS_SOFFN_SHIFT); } @@ -5082,24 +5082,24 @@ static int stm32l4_wakeup(struct usbdev_s *dev) { /* Yes... is the core suspended? */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32l4_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0) { /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Activate Remote wakeup signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); up_mdelay(5); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); } } @@ -5124,7 +5124,7 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) #ifdef CONFIG_DEBUG_FEATURES if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -5148,7 +5148,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); irqstate_t flags = enter_critical_section(); - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); if (enable) { /* Connect the device by clearing the soft disconnect bit in the DCTL @@ -5166,7 +5166,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval |= OTGFS_DCTL_SDIS; } - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); leave_critical_section(flags); return OK; } @@ -5186,10 +5186,10 @@ static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, /* Set the device address in the DCFG register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32l4_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DAD_MASK; regval |= ((uint32_t)address << OTGFS_DCFG_DAD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32l4_putreg(regval, STM32_OTGFS_DCFG); /* Are we now addressed? (i.e., do we have a non-NULL device * address?) @@ -5223,13 +5223,13 @@ static int stm32l4_txfifo_flush(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(regval, STM32L4_OTGFS_GRSTCTL); + stm32l4_putreg(regval, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5257,13 +5257,13 @@ static int stm32l4_rxfifo_flush(void) /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32L4_OTGFS_GRSTCTL); + stm32l4_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5296,12 +5296,12 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->epin[EP0].ep; - priv->epavail[0] = STM32L4_EP_AVAILABLE; - priv->epavail[1] = STM32L4_EP_AVAILABLE; + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; /* Initialize the IN endpoint list */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -5319,7 +5319,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) */ privep->epphy = i; - privep->ep.eplog = STM32L4_EPPHYIN2LOG(i); + privep->ep.eplog = STM32_EPPHYIN2LOG(i); /* Control until endpoint is activated */ @@ -5329,7 +5329,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) /* Initialize the OUT endpoint list */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -5346,7 +5346,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) */ privep->epphy = i; - privep->ep.eplog = STM32L4_EPPHYOUT2LOG(i); + privep->ep.eplog = STM32_EPPHYOUT2LOG(i); /* Control until endpoint is activated */ @@ -5382,7 +5382,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * (not just half full). */ - stm32l4_putreg(OTGFS_GAHBCFG_TXFELVL, STM32L4_OTGFS_GAHBCFG); + stm32l4_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); /* Common USB OTG core initialization */ @@ -5390,10 +5390,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * IDLE state. */ - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5402,10 +5402,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(OTGFS_GRSTCTL_CSRST, STM32L4_OTGFS_GRSTCTL); - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + stm32l4_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5426,101 +5426,101 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GCCFG_VBDEN; #endif - stm32l4_putreg(regval, STM32L4_OTGFS_GCCFG); + stm32l4_putreg(regval, STM32_OTGFS_GCCFG); up_mdelay(20); /* When VBUS sensing is not used we need to force the B session valid */ #ifndef CONFIG_USBDEV_VBUSSENSING - regval = stm32l4_getreg(STM32L4_OTGFS_GOTGCTL); + regval = stm32l4_getreg(STM32_OTGFS_GOTGCTL); regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); - stm32l4_putreg(regval, STM32L4_OTGFS_GOTGCTL); + stm32l4_putreg(regval, STM32_OTGFS_GOTGCTL); #endif /* Force Device Mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FHMOD; regval |= OTGFS_GUSBCFG_FDMOD; - stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG); + stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); up_mdelay(50); /* Initialize device mode */ /* Restart the PHY Clock */ - stm32l4_putreg(0, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(0, STM32_OTGFS_PCGCCTL); /* Device configuration register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32l4_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_PFIVL_MASK; regval |= OTGFS_DCFG_PFIVL_80PCT; - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32l4_putreg(regval, STM32_OTGFS_DCFG); /* Set full speed PHY */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32l4_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DSPD_MASK; regval |= OTGFS_DCFG_DSPD_FS; - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32l4_putreg(regval, STM32_OTGFS_DCFG); /* Set Rx FIFO size */ - stm32l4_putreg(STM32L4_RXFIFO_WORDS, STM32L4_OTGFS_GRXFSIZ); + stm32l4_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); -#if STM32L4_NENDPOINTS > 0 +#if STM32_NENDPOINTS > 0 /* EP0 TX */ - address = STM32L4_RXFIFO_WORDS; + address = STM32_RXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | - (STM32L4_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF0); + (STM32_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF0); #endif -#if STM32L4_NENDPOINTS > 1 +#if STM32_NENDPOINTS > 1 /* EP1 TX */ - address += STM32L4_EP0_TXFIFO_WORDS; + address += STM32_EP0_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(1)); + (STM32_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(1)); #endif -#if STM32L4_NENDPOINTS > 2 +#if STM32_NENDPOINTS > 2 /* EP2 TX */ - address += STM32L4_EP1_TXFIFO_WORDS; + address += STM32_EP1_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(2)); + (STM32_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(2)); #endif -#if STM32L4_NENDPOINTS > 3 +#if STM32_NENDPOINTS > 3 /* EP3 TX */ - address += STM32L4_EP2_TXFIFO_WORDS; + address += STM32_EP2_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(3)); + (STM32_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(3)); #endif -#if STM32L4_NENDPOINTS > 4 +#if STM32_NENDPOINTS > 4 /* EP4 TX */ - address += STM32L4_EP3_TXFIFO_WORDS; + address += STM32_EP3_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(4)); + (STM32_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(4)); #endif -#if STM32L4_NENDPOINTS > 5 +#if STM32_NENDPOINTS > 5 /* EP5 TX */ - address += STM32L4_EP4_TXFIFO_WORDS; + address += STM32_EP4_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(5)); + (STM32_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(5)); #endif /* Flush the FIFOs */ @@ -5530,17 +5530,17 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Clear all pending Device Interrupts */ - stm32l4_putreg(0, STM32L4_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); - stm32l4_putreg(0, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); /* Configure all IN endpoints */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(i)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(i)); if ((regval & OTGFS_DIEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5552,16 +5552,16 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(i)); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPTSIZ(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(i)); + stm32l4_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); } /* Configure all OUT endpoints */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(i)); + regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(i)); if ((regval & OTGFS_DOEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5573,24 +5573,24 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(i)); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPTSIZ(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(i)); + stm32l4_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } /* Disable all interrupts. */ - stm32l4_putreg(0, STM32L4_OTGFS_GINTMSK); + stm32l4_putreg(0, STM32_OTGFS_GINTMSK); /* Clear any pending USB_OTG Interrupts */ - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_GOTGINT); + stm32l4_putreg(0xffffffff, STM32_OTGFS_GOTGINT); /* Clear any pending interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); + regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); regval &= OTGFS_GINT_RESERVED; - stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32L4_OTGFS_GINTSTS); + stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); /* Enable the interrupts in the INTMSK */ @@ -5613,7 +5613,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GINT_MMIS; #endif - stm32l4_putreg(regval, STM32L4_OTGFS_GINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_GINTMSK); /* Enable the USB global interrupt by setting GINTMSK in the global OTG * FS AHB configuration register; Set the TXFELVL bit in the GAHBCFG @@ -5622,7 +5622,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) */ stm32l4_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, - STM32L4_OTGFS_GAHBCFG); + STM32_OTGFS_GAHBCFG); } /**************************************************************************** @@ -5703,7 +5703,7 @@ void arm_usbinitialize(void) /* Attach the OTG FS interrupt handler */ - ret = irq_attach(STM32L4_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); + ret = irq_attach(STM32_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); if (ret < 0) { uerr("ERROR: irq_attach failed: %d\n", ret); @@ -5724,7 +5724,7 @@ void arm_usbinitialize(void) /* Enable USB controller interrupts at the NVIC */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); return; errout: @@ -5752,7 +5752,7 @@ void arm_usbuninitialize(void) if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } @@ -5764,22 +5764,22 @@ void arm_usbuninitialize(void) /* Disable and detach IRQs */ - up_disable_irq(STM32L4_IRQ_OTGFS); - irq_detach(STM32L4_IRQ_OTGFS); + up_disable_irq(STM32_IRQ_OTGFS); + irq_detach(STM32_IRQ_OTGFS); /* Disable all endpoint interrupts */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } - stm32l4_putreg(0, STM32L4_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DAINTMSK); - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); + stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); + stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Flush the FIFOs */ @@ -5819,13 +5819,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -5839,14 +5839,14 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); priv->driver = NULL; } else { /* Enable USB controller interrupts */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set * the RS bit to enable the controller. It kind of makes sense @@ -5891,7 +5891,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_FEATURES if (driver != priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -5911,7 +5911,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupts */ flags = enter_critical_section(); - up_disable_irq(STM32L4_IRQ_OTGFS); + up_disable_irq(STM32_IRQ_OTGFS); /* Disconnect device */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index fa712e9494478..955e9d78d8054 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -131,20 +131,20 @@ /* Hardware capabilities */ -#define STM32L4_NHOST_CHANNELS 8 /* Number of host channels */ -#define STM32L4_MAX_PACKET_SIZE 64 /* Full speed max packet size */ -#define STM32L4_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ -#define STM32L4_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ -#define STM32L4_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ -#define STM32L4_MAX_PKTCOUNT 256 /* Max packet count */ -#define STM32L4_RETRY_COUNT 3 /* Number of ctrl transfer retries */ +#define STM32_NHOST_CHANNELS 8 /* Number of host channels */ +#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ +#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ +#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ +#define STM32_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ +#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ +#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ /* Delays *******************************************************************/ -#define STM32L4_READY_DELAY 200000 /* In loop counts */ -#define STM32L4_FLUSH_DELAY 200000 /* In loop counts */ -#define STM32L4_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ -#define STM32L4_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_READY_DELAY 200000 /* In loop counts */ +#define STM32_FLUSH_DELAY 200000 /* In loop counts */ +#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ /**************************************************************************** * Private Types @@ -260,7 +260,7 @@ struct stm32l4_usbhost_s /* The state of each host channel */ - struct stm32l4_chan_s chan[STM32L4_MAX_TX_FIFOS]; + struct stm32l4_chan_s chan[STM32_MAX_TX_FIFOS]; }; /**************************************************************************** @@ -659,7 +659,7 @@ static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) /* Search the table of channels */ - for (chidx = 0; chidx < STM32L4_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { /* Is this channel available? */ @@ -687,7 +687,7 @@ static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) static void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, int chidx) { - DEBUGASSERT((unsigned)chidx < STM32L4_NHOST_CHANNELS); + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); /* Halt the channel */ @@ -712,7 +712,7 @@ static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) /* Free all host channels */ - for (chidx = 2; chidx < STM32L4_NHOST_CHANNELS; chidx++) + for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) { stm32l4_chan_free(priv, chidx); } @@ -736,7 +736,7 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, /* Clear any old pending interrupts for this host channel. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), 0xffffffff); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); /* Enable channel interrupts required for transfers on this channel. */ @@ -836,15 +836,15 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, break; } - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Enable the top level host channel interrupt. */ - stm32l4_modifyreg(STM32L4_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); + stm32l4_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); /* Make sure host channel interrupts are enabled. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); /* Program the HCCHAR register */ @@ -876,7 +876,7 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, /* Write the channel configuration */ - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } /**************************************************************************** @@ -913,7 +913,7 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, * transaction that has already been started on the USB." */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); hcchar |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); /* Get the endpoint type from the HCCHAR register */ @@ -935,14 +935,14 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS) & + avail = stm32l4_getreg(STM32_OTGFS_HNPTXSTS) & OTGFS_HNPTXSTS_NPTXFSAV_MASK; } else { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS) & + avail = stm32l4_getreg(STM32_OTGFS_HPTXSTS) & OTGFS_HPTXSTS_PTXFSAVL_MASK; } @@ -957,13 +957,13 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, /* Unmask the CHannel Halted (CHH) interrupt */ - intmsk = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + intmsk = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); intmsk |= OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), intmsk); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), hcchar); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } /**************************************************************************** @@ -1193,7 +1193,7 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, chan->funcaddr = funcaddr; chan->speed = speed; chan->interval = 0; - chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1218,7 +1218,7 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, chan->funcaddr = funcaddr; chan->speed = speed; chan->interval = 0; - chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1413,10 +1413,10 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, * packets that can be transferred (this should not happen). */ - if (npackets > STM32L4_MAX_PKTCOUNT) + if (npackets > STM32_MAX_PKTCOUNT) { - npackets = STM32L4_MAX_PKTCOUNT; - chan->buflen = STM32L4_MAX_PKTCOUNT * maxpacket; + npackets = STM32_MAX_PKTCOUNT; + chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; usbhost_trace2(OTGFS_TRACE2_CLIP, chidx, chan->buflen); } } @@ -1453,18 +1453,18 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval = ((uint32_t)chan->buflen << OTGFS_HCTSIZ_XFRSIZ_SHIFT) | ((uint32_t)npackets << OTGFS_HCTSIZ_PKTCNT_SHIFT) | ((uint32_t)chan->pid << OTGFS_HCTSIZ_DPID_SHIFT); - stm32l4_putreg(STM32L4_OTGFS_HCTSIZ(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); /* Setup the HCCHAR register: Frame oddness and host channel enable */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd * Frame. This field is applicable for only periodic (isochronous and * interrupt) channels. */ - if ((stm32l4_getreg(STM32L4_OTGFS_HFNUM) & 1) == 0) + if ((stm32l4_getreg(STM32_OTGFS_HFNUM) & 1) == 0) { regval |= OTGFS_HCCHAR_ODDFRM; } @@ -1475,7 +1475,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval &= ~OTGFS_HCCHAR_CHDIS; regval |= OTGFS_HCCHAR_CHENA; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* If this is an out transfer, then we need to do more.. we need to copy * the outgoing data into the correct TxFIFO. @@ -1496,7 +1496,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; } @@ -1509,7 +1509,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; } @@ -1572,7 +1572,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, static inline uint16_t stm32l4_getframe(void) { return (uint16_t) - (stm32l4_getreg(STM32L4_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); + (stm32l4_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); } #endif @@ -1647,7 +1647,7 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_SETUP_DELAY); + while (elapsed < STM32_SETUP_DELAY); return -ETIMEDOUT; } @@ -1893,7 +1893,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, */ clock_t elapsed = clock_systime_ticks() - start; - if (elapsed >= STM32L4_DATANAK_DELAY) + if (elapsed >= STM32_DATANAK_DELAY) { /* Timeout out... break out returning the NAK as * as a failure. @@ -2247,7 +2247,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, elapsed = clock_systime_ticks() - start; if (ret != -EAGAIN || /* Not a NAK condition OR */ - elapsed >= STM32L4_DATANAK_DELAY || /* Timeout has elapsed OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ chan->xfrd > 0) /* Data has been partially * transferred */ { @@ -2419,7 +2419,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, /* Get the address of the Tx FIFO associated with this channel */ - fifo = STM32L4_OTGFS_DFIFO_HCH(chidx); + fifo = STM32_OTGFS_DFIFO_HCH(chidx); /* Transfer all of the data into the Tx FIFO */ @@ -2465,8 +2465,8 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32L4_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2480,7 +2480,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2489,7 +2489,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the NAK and STALL Conditions. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_STALL)); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is @@ -2517,7 +2517,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the NAK and data toggle error conditions */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_DTERR)); } @@ -2531,7 +2531,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the FRaMe OverRun (FRMOR) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2540,7 +2540,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the TransFeR Completed (XFRC) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); /* Then handle the transfer completion event based on the endpoint */ @@ -2556,15 +2556,15 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * logic as each packet was received. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } else if (chan->eptype == OTGFS_EPTYPE_INTR) { /* Force the next transfer on an ODD frame */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_ODDFRM; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* Set the request done state */ @@ -2578,9 +2578,9 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Update the request state based on the host state machine state */ @@ -2618,7 +2618,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the CHannel Halted (CHH) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2633,7 +2633,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the Transaction ERror (TXERR) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a pending NAK response received (NAK) interrupt */ @@ -2671,10 +2671,10 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * TODO: set channel reason to NACK? */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_CHENA; regval &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } #else @@ -2685,7 +2685,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the NAK condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a transfer complete event */ @@ -2723,8 +2723,8 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32L4_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2738,7 +2738,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ @@ -2751,7 +2751,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2772,7 +2772,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the TransFeR Completed (XFRC) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2781,7 +2781,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending STALL response receive (STALL) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is * received on the channel. @@ -2800,7 +2800,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the NAK response received (NAK) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2815,7 +2815,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the Transaction ERror (TXERR) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a NYET interrupt */ @@ -2829,7 +2829,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the NYET interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); } #endif @@ -2845,7 +2845,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_DTERR | OTGFS_HCINT_NAK)); } @@ -2855,9 +2855,9 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); if (chan->chreason == CHREASON_XFRC) { @@ -2869,7 +2869,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * the endpoint type. */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Is it a bulk endpoint? Were an odd number of packets * transferred? @@ -2913,7 +2913,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the CHannel Halted (CHH) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a transfer complete event */ @@ -3018,7 +3018,7 @@ static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) /* Clear pending SOF interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_SOF); + stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); } #endif @@ -3045,13 +3045,13 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Disable the RxFIFO non-empty interrupt */ - intmsk = stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + intmsk = stm32l4_getreg(STM32_OTGFS_GINTMSK); intmsk &= ~OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, intmsk); + stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); /* Read and pop the next status from the Rx FIFO */ - grxsts = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP); + grxsts = stm32l4_getreg(STM32_OTGFS_GRXSTSP); uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); /* Isolate the channel number/index in the status word */ @@ -3060,7 +3060,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Get the host channel characteristics register (HCCHAR) */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Then process the interrupt according to the packet status */ @@ -3077,7 +3077,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Transfer the packet from the Rx FIFO into the user buffer */ dest = (uint32_t *)priv->chan[chidx].buffer; - fifo = STM32L4_OTGFS_DFIFO_HCH(0); + fifo = STM32_OTGFS_DFIFO_HCH(0); bcnt32 = (bcnt + 3) >> 2; for (i = 0; i < bcnt32; i++) @@ -3098,14 +3098,14 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Check if more packets are expected */ - hctsiz = stm32l4_getreg(STM32L4_OTGFS_HCTSIZ(chidx)); + hctsiz = stm32l4_getreg(STM32_OTGFS_HCTSIZ(chidx)); if ((hctsiz & OTGFS_HCTSIZ_PKTCNT_MASK) != 0) { /* Re-activate the channel when more packets are expected */ hcchar |= OTGFS_HCCHAR_CHENA; hcchar &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), hcchar); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } } } @@ -3121,7 +3121,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Re-enable the RxFIFO non-empty interrupt */ intmsk |= OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, intmsk); + stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); } /**************************************************************************** @@ -3164,13 +3164,13 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); return; } /* Read the status from the top of the non-periodic TxFIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); /* Extract the number of bytes available in the non-periodic Tx FIFO. */ @@ -3202,7 +3202,7 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3254,13 +3254,13 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); return; } /* Read the status from the top of the periodic TxFIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); /* Extract the number of bytes available in the periodic Tx FIFO. */ @@ -3292,7 +3292,7 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3319,12 +3319,12 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) int i = 0; /* Read the Host all channels interrupt register and test each bit in the - * register. Each bit i, i=0...(STM32L4_NHOST_CHANNELS-1), corresponds to + * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to * a pending interrupt on channel i. */ - haint = stm32l4_getreg(STM32L4_OTGFS_HAINT); - for (i = 0; i < STM32L4_NHOST_CHANNELS; i++) + haint = stm32l4_getreg(STM32_OTGFS_HAINT); + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { /* Is an interrupt pending on this channel? */ @@ -3332,7 +3332,7 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) { /* Yes... read the HCCHAR register to get the direction bit */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(i)); + hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(i)); /* Was this an interrupt on an IN or an OUT channel? */ @@ -3370,7 +3370,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Read the port status and control register (HPRT) */ - hprt = stm32l4_getreg(STM32L4_OTGFS_HPRT); + hprt = stm32l4_getreg(STM32_OTGFS_HPRT); /* Setup to clear the interrupt bits in GINTSTS by setting the * corresponding bits in the HPRT. The HCINT interrupt bit is cleared @@ -3425,7 +3425,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Check the Host ConFiGuration register (HCFG) */ - hcfg = stm32l4_getreg(STM32L4_OTGFS_HCFG); + hcfg = stm32l4_getreg(STM32_OTGFS_HCFG); /* Is this a low speed or full speed connection (OTG FS does not * support high speed) @@ -3436,7 +3436,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Set the Host Frame Interval Register for the 6KHz speed */ usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSDEV, 0); - stm32l4_putreg(STM32L4_OTGFS_HFIR, 6000); + stm32l4_putreg(STM32_OTGFS_HFIR, 6000); /* Are we switching from FS to LS? */ @@ -3449,7 +3449,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_LS6MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, hcfg); + stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ @@ -3459,7 +3459,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) else /* if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_FS) */ { usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSDEV, 0); - stm32l4_putreg(STM32L4_OTGFS_HFIR, 48000); + stm32l4_putreg(STM32_OTGFS_HFIR, 48000); /* Are we switching from LS to FS? */ @@ -3472,7 +3472,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, hcfg); + stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ @@ -3484,7 +3484,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Clear port interrupts by setting bits in the HPRT */ - stm32l4_putreg(STM32L4_OTGFS_HPRT, newhprt); + stm32l4_putreg(STM32_OTGFS_HPRT, newhprt); } /**************************************************************************** @@ -3503,7 +3503,7 @@ static inline void stm32l4_gint_discisr(struct stm32l4_usbhost_s *priv) /* Clear the dicsonnect interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_DISC); + stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); } /**************************************************************************** @@ -3522,13 +3522,13 @@ static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv) * CHDIS : Set to stop transmitting/receiving data on a channel */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(0)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(0)); regval |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(0), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(0), regval); /* Clear the incomplete isochronous OUT interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); + stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); } /**************************************************************************** @@ -3564,8 +3564,8 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) { /* Get the unmasked bits in the GINT status */ - pending = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); - pending &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + pending = stm32l4_getreg(STM32_OTGFS_GINTSTS); + pending &= stm32l4_getreg(STM32_OTGFS_GINTMSK); /* Return from the interrupt when there are no further pending * interrupts. @@ -3669,9 +3669,9 @@ static void stm32l4_gint_enable(void) /* Set the GINTMSK bit to unmask the interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_GAHBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); regval |= OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32L4_OTGFS_GAHBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); } static void stm32l4_gint_disable(void) @@ -3680,9 +3680,9 @@ static void stm32l4_gint_disable(void) /* Clear the GINTMSK bit to mask the interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_GAHBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); regval &= ~OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32L4_OTGFS_GAHBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); } /**************************************************************************** @@ -3705,19 +3705,19 @@ static inline void stm32l4_hostinit_enable(void) /* Disable all interrupts. */ - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, 0); + stm32l4_putreg(STM32_OTGFS_GINTMSK, 0); /* Clear any pending interrupts. */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, 0xffffffff); + stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); /* Clear any pending USB OTG Interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GOTGINT, 0xffffffff); + stm32l4_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); /* Clear any pending USB OTG interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, 0xbfffffff); + stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); /* Enable the host interrupts */ @@ -3753,7 +3753,7 @@ static inline void stm32l4_hostinit_enable(void) regval |= (OTGFS_GINT_RXFLVL | OTGFS_GINT_IPXFR | OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); #endif - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, regval); + stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); } /**************************************************************************** @@ -3793,7 +3793,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_GINTMSK); switch (chan->eptype) { default: @@ -3810,7 +3810,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Enable interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, regval); + stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); leave_critical_section(flags); } @@ -3972,7 +3972,7 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, /* Get the current device speed */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32l4_getreg(STM32_OTGFS_HPRT); if ((regval & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) { priv->rhport.hport.speed = USB_SPEED_LOW; @@ -4205,11 +4205,11 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ret = nxmutex_lock(&priv->lock); /* A single channel is represent by an index in the range of 0 to - * STM32L4_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an + * STM32_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an * allocated control endpoint structure. */ - if ((uintptr_t)ep < STM32L4_MAX_TX_FIFOS) + if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) { /* Halt the channel and mark the channel available */ @@ -4480,7 +4480,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Loop, retrying until the retry time expires */ - for (retries = 0; retries < STM32L4_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send the SETUP request */ @@ -4526,7 +4526,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_DATANAK_DELAY); + while (elapsed < STM32_DATANAK_DELAY); } /* All failures exit here after all retries and timeouts are exhausted */ @@ -4569,7 +4569,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Loop, retrying until the retry time expires */ - for (retries = 0; retries < STM32L4_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send the SETUP request */ @@ -4619,7 +4619,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_DATANAK_DELAY); + while (elapsed < STM32_DATANAK_DELAY); } /* All failures exit here after all retries and timeouts are exhausted */ @@ -4678,7 +4678,7 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0); + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); /* We must have exclusive access to the USB host hardware and structures */ @@ -4750,7 +4750,7 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0); + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); /* We must have exclusive access to the USB host hardware and structures */ @@ -4804,7 +4804,7 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) uvdbg("chidx: %u: %d\n", chidx); - DEBUGASSERT(priv && chidx < STM32L4_MAX_TX_FIFOS); + DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); chan = &priv->chan[chidx]; /* We need to disable interrupts to avoid race conditions with the @@ -4976,16 +4976,16 @@ static void stm32l4_portreset(struct stm32l4_usbhost_s *priv) { uint32_t regval; - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32l4_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); regval |= OTGFS_HPRT_PRST; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); regval &= ~OTGFS_HPRT_PRST; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); } @@ -5012,13 +5012,13 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, regval); + stm32l4_putreg(STM32_OTGFS_GRSTCTL, regval); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5051,13 +5051,13 @@ static void stm32l4_flush_rxfifo(void) /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); + stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5094,20 +5094,20 @@ static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, bool state) /* Turn on the Host port power. */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32l4_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); if (((regval & OTGFS_HPRT_PPWR) == 0) && state) { regval |= OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); } if (((regval & OTGFS_HPRT_PPWR) != 0) && !state) { regval &= ~OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); } up_mdelay(200); @@ -5138,14 +5138,14 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Restart the PHY Clock */ - stm32l4_putreg(STM32L4_OTGFS_PCGCCTL, 0); + stm32l4_putreg(STM32_OTGFS_PCGCCTL, 0); /* Initialize Host Configuration (HCFG) register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCFG); + regval = stm32l4_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSPCS_MASK; regval |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, regval); + stm32l4_putreg(STM32_OTGFS_HCFG, regval); /* Reset the host port */ @@ -5153,9 +5153,9 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Clear the FS-/LS-only support bit in the HCFG register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCFG); + regval = stm32l4_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSS; - stm32l4_putreg(STM32L4_OTGFS_HCFG, regval); + stm32l4_putreg(STM32_OTGFS_HCFG, regval); /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic * Tx FIFOs @@ -5163,7 +5163,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32l4_putreg(STM32L4_OTGFS_GRXFSIZ, CONFIG_STM32L4_OTGFS_RXFIFO_SIZE); + stm32l4_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32L4_OTGFS_RXFIFO_SIZE); offset = CONFIG_STM32L4_OTGFS_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ @@ -5171,7 +5171,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) regval = (offset | (CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)); - stm32l4_putreg(STM32L4_OTGFS_HNPTXFSIZ, regval); + stm32l4_putreg(STM32_OTGFS_HNPTXFSIZ, regval); offset += CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ @@ -5179,7 +5179,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) regval = (offset | (CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE << OTGFS_HPTXFSIZ_PTXFD_SHIFT)); - stm32l4_putreg(STM32L4_OTGFS_HPTXFSIZ, regval); + stm32l4_putreg(STM32_OTGFS_HPTXFSIZ, regval); /* If OTG were supported, we should need to clear HNP enable bit in the * USB_OTG control register about here. @@ -5192,10 +5192,10 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Clear all pending HC Interrupts */ - for (i = 0; i < STM32L4_NHOST_CHANNELS; i++) + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { - stm32l4_putreg(STM32L4_OTGFS_HCINT(i), 0xffffffff); - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(i), 0); + stm32l4_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(i), 0); } /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG @@ -5275,11 +5275,11 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) /* Put all of the channels back in their initial, allocated state */ memset(priv->chan, 0, - STM32L4_MAX_TX_FIFOS * sizeof(struct stm32l4_chan_s)); + STM32_MAX_TX_FIFOS * sizeof(struct stm32l4_chan_s)); /* Initialize each channel */ - for (i = 0; i < STM32L4_MAX_TX_FIFOS; i++) + for (i = 0; i < STM32_MAX_TX_FIFOS; i++) { struct stm32l4_chan_s *chan = &priv->chan[i]; @@ -5311,18 +5311,18 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) * transceiver: "This bit is always 1 with write-only access" */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval |= OTGFS_GUSBCFG_PHYSEL; - stm32l4_putreg(STM32L4_OTGFS_GUSBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state. */ - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5331,10 +5331,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5355,7 +5355,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) #ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT regval |= OTGFS_GCCFG_SOFOUTEN; #endif - stm32l4_putreg(STM32L4_OTGFS_GCCFG, regval); + stm32l4_putreg(STM32_OTGFS_GCCFG, regval); up_mdelay(20); /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP @@ -5364,10 +5364,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Force Host Mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FDMOD; regval |= OTGFS_GUSBCFG_FHMOD; - stm32l4_putreg(STM32L4_OTGFS_GUSBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); up_mdelay(50); /* Initialize host mode and return success */ @@ -5467,7 +5467,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32L4_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) + if (irq_attach(STM32_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) { usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); return NULL; @@ -5479,7 +5479,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Enable interrupts at the interrupt controller */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); return &g_usbconn; } diff --git a/arch/arm/src/stm32l4/stm32l4_pmlpr.c b/arch/arm/src/stm32l4/stm32l4_pmlpr.c index 100de46b5d0af..d43ae86f66ffb 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmlpr.c +++ b/arch/arm/src/stm32l4/stm32l4_pmlpr.c @@ -75,7 +75,7 @@ int stm32l4_pmlpr(void) /* Enable MSI clock */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; /* Set MSI clock to 2 MHz */ @@ -83,27 +83,27 @@ int stm32l4_pmlpr(void) regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */ regval |= RCC_CR_MSIRGSEL; /* Select new MSIRANGE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Select MSI clock as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_MSI; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the MSI source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI) { } /* Enable Low-Power Run */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval |= PWR_CR1_LPR; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_pmstandby.c b/arch/arm/src/stm32l4/stm32l4_pmstandby.c index da50343ec3956..0866f7a2f5a53 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstandby.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstandby.c @@ -79,15 +79,15 @@ int stm32l4_pmstandby(void) regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5; - putreg32(regval, STM32L4_PWR_SCR); + putreg32(regval, STM32_PWR_SCR); /* Select Standby mode */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STANDBY; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set SLEEPDEEP bit of Cortex System Control Register */ diff --git a/arch/arm/src/stm32l4/stm32l4_pmstop.c b/arch/arm/src/stm32l4/stm32l4_pmstop.c index 8718d575322f4..c67a19a27aaff 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstop.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstop.c @@ -114,7 +114,7 @@ int stm32l4_pmstop(bool lpds) * register 1. */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; /* Select Stop 1 mode with low-power regulator if so requested */ @@ -124,7 +124,7 @@ int stm32l4_pmstop(bool lpds) regval |= PWR_CR1_LPMS_STOP1LPR; } - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } @@ -149,7 +149,7 @@ int stm32l4_pmstop2(void) { uint32_t regval; - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); #ifdef CONFIG_STM32L4_SRAM3_HEAP /* SRAM3 is used as heap, so it must not be powered off in Stop 2 mode. */ @@ -160,7 +160,7 @@ int stm32l4_pmstop2(void) regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STOP2; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.c b/arch/arm/src/stm32l4/stm32l4_pulsecount.c index 08807a2334e21..866af2489de9f 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.c +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.c @@ -233,9 +233,9 @@ static struct stm32l4_tim_s g_pulsecount1dev = .timid = 1, .timtype = TIMTYPE_TIM1, .t_dts = CONFIG_STM32L4_TIM1_PULSECOUNT_TDTS, - .irq = STM32L4_IRQ_TIM1UP, - .base = STM32L4_TIM1_BASE, - .pclk = STM32L4_APB2_TIM1_CLKIN, + .irq = STM32_IRQ_TIM1UP, + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; #endif /* CONFIG_STM32L4_TIM1_PULSECOUNT */ @@ -284,9 +284,9 @@ static struct stm32l4_tim_s g_pulsecount8dev = .timid = 8, .timtype = TIMTYPE_TIM8, .t_dts = CONFIG_STM32L4_TIM8_PULSECOUNT_TDTS, - .irq = STM32L4_IRQ_TIM8UP, - .base = STM32L4_TIM8_BASE, - .pclk = STM32L4_APB2_TIM8_CLKIN, + .irq = STM32_IRQ_TIM8UP, + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; #endif /* CONFIG_STM32L4_TIM8_PULSECOUNT */ @@ -407,30 +407,30 @@ static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, _info("%s:\n", msg); _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_SR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_EGR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); _info(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pulsecount_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_DCR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } #endif @@ -450,25 +450,25 @@ static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, { case 1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } case 2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } case 3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } case 4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } @@ -520,7 +520,7 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, /* Get the reload values */ - reload = pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET); + reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); /* Duty cycle: * @@ -617,8 +617,8 @@ static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, /* Set the reload and prescaler values */ - pulsecount_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); - pulsecount_putreg(priv, STM32L4_GTIM_PSC_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); + pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); return OK; @@ -638,7 +638,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) /* Set up the advanced timer CR1 register. */ - cr1 = pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); /* Pulsecount always uses edge-aligned up-counting mode. */ @@ -653,7 +653,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) /* Write CR1 */ - pulsecount_putreg(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); return OK; } @@ -689,14 +689,14 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, case 1: case 2: { - offset = STM32L4_GTIM_CCMR1_OFFSET; + offset = STM32_GTIM_CCMR1_OFFSET; break; } case 3: case 4: { - offset = STM32L4_GTIM_CCMR2_OFFSET; + offset = STM32_GTIM_CCMR2_OFFSET; break; } @@ -773,8 +773,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, /* Get current registers state */ - cr2 = pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); /* | OISx | IDLE | advanced timers | CR2 register * | CCxP | POL | all pulsecount timers | CCER register @@ -807,8 +807,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, /* Write registers */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR2_OFFSET, 0, cr2); - pulsecount_modifyreg(priv, STM32L4_GTIM_CCER_OFFSET, 0, ccer); + pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); return OK; } @@ -838,7 +838,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, /* Get current register state */ - ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); /* Get outputs configuration */ @@ -865,7 +865,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, /* Write register */ - pulsecount_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); return OK; } @@ -881,11 +881,11 @@ static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, if (enable) { - pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } else { - pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); } } @@ -933,7 +933,7 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) /* Disable the timer until we get it configured */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); /* Get configured outputs */ @@ -1015,8 +1015,8 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, /* Disable all interrupts and DMA requests, clear all pending status */ - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Set timer frequency */ @@ -1051,14 +1051,14 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, */ priv->prev = pulsecount_count(info->count); - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1); /* Generate an update event to reload the prescaler. This should * preload the RCR into active repetition counter. */ - pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Now set the value of the RCR that will be loaded on the next * update event. @@ -1066,7 +1066,7 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, priv->count = info->count; priv->curr = pulsecount_count(info->count - priv->prev); - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -1076,11 +1076,11 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, { /* Set the repetition counter to zero */ - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ - pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); } /* Get configured outputs */ @@ -1105,12 +1105,12 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, { /* Clear all pending interrupts and enable the update interrupt. */ - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); /* Enable the timer */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); /* And enable timer interrupts at the NVIC */ @@ -1144,12 +1144,12 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) /* Verify that this is an update interrupt. Nothing else is expected. */ - regval = pulsecount_getreg(priv, STM32L4_ATIM_SR_OFFSET); + regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - pulsecount_putreg(priv, STM32L4_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); + pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); /* Calculate the new count by subtracting the number of pulses * since the last interrupt. @@ -1161,9 +1161,9 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * quickly as possible. */ - regval = pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET); + regval = pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); regval &= ~ATIM_BDTR_MOE; - pulsecount_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, regval); + pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval); /* Disable first interrupts, stop and reset the timer */ @@ -1194,7 +1194,7 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) priv->prev = priv->curr; priv->curr = pulsecount_count(priv->count - priv->prev); - pulsecount_putreg(priv, STM32L4_ATIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -1311,7 +1311,7 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, #ifdef CONFIG_STM32L4_TIM1_PULSECOUNT case 1: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; } @@ -1320,7 +1320,7 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, #ifdef CONFIG_STM32L4_TIM8_PULSECOUNT case 8: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM8EN; break; } @@ -1484,13 +1484,13 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) { #ifdef CONFIG_STM32L4_TIM1_PULSECOUNT case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif #ifdef CONFIG_STM32L4_TIM8_PULSECOUNT case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif @@ -1506,8 +1506,8 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) /* Disable further interrupts and stop the timer */ - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Reset the timer - stopping the output and putting the timer back * into a state where pulsecount_start() can be called. diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 46d0aff819376..edb4452d0a24b 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -451,11 +451,11 @@ static struct stm32l4_pwmtimer_s g_pwm1dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = CONFIG_STM32L4_TIM1_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM1_TRGO) - .trgo = STM32L4_TIM1_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) + .trgo = STM32_TIM1_TRGO, #endif - .base = STM32L4_TIM1_BASE, - .pclk = STM32L4_APB2_TIM1_CLKIN, + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; #endif /* CONFIG_STM32L4_TIM1_PWM */ @@ -547,11 +547,11 @@ static struct stm32l4_pwmtimer_s g_pwm2dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM2_TRGO) - .trgo = STM32L4_TIM2_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM2_TRGO) + .trgo = STM32_TIM2_TRGO, #endif - .base = STM32L4_TIM2_BASE, - .pclk = STM32L4_APB1_TIM2_CLKIN, + .base = STM32_TIM2_BASE, + .pclk = STM32_APB1_TIM2_CLKIN, }; #endif /* CONFIG_STM32L4_TIM2_PWM */ @@ -644,11 +644,11 @@ static struct stm32l4_pwmtimer_s g_pwm3dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM3_TRGO) - .trgo = STM32L4_TIM3_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM3_TRGO) + .trgo = STM32_TIM3_TRGO, #endif - .base = STM32L4_TIM3_BASE, - .pclk = STM32L4_APB1_TIM3_CLKIN, + .base = STM32_TIM3_BASE, + .pclk = STM32_APB1_TIM3_CLKIN, }; #endif /* CONFIG_STM32L4_TIM3_PWM */ @@ -740,11 +740,11 @@ static struct stm32l4_pwmtimer_s g_pwm4dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM4_TRGO) - .trgo = STM32L4_TIM4_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM4_TRGO) + .trgo = STM32_TIM4_TRGO, #endif - .base = STM32L4_TIM4_BASE, - .pclk = STM32L4_APB1_TIM4_CLKIN, + .base = STM32_TIM4_BASE, + .pclk = STM32_APB1_TIM4_CLKIN, }; #endif /* CONFIG_STM32L4_TIM4_PWM */ @@ -834,11 +834,11 @@ static struct stm32l4_pwmtimer_s g_pwm5dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM5_TRGO) - .trgo = STM32L4_TIM5_TRGO +#if defined(HAVE_TRGO) && defined(STM32_TIM5_TRGO) + .trgo = STM32_TIM5_TRGO #endif - .base = STM32L4_TIM5_BASE, - .pclk = STM32L4_APB1_TIM5_CLKIN, + .base = STM32_TIM5_BASE, + .pclk = STM32_APB1_TIM5_CLKIN, }; #endif /* CONFIG_STM32L4_TIM5_PWM */ @@ -997,11 +997,11 @@ static struct stm32l4_pwmtimer_s g_pwm8dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = CONFIG_STM32L4_TIM8_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM8_TRGO) - .trgo = STM32L4_TIM8_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) + .trgo = STM32_TIM8_TRGO, #endif - .base = STM32L4_TIM8_BASE, - .pclk = STM32L4_APB2_TIM8_CLKIN, + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; #endif /* CONFIG_STM32L4_TIM8_PWM */ @@ -1073,17 +1073,17 @@ static struct stm32l4_pwmtimer_s g_pwm15dev = .chan_num = PWM_TIM15_NCHANNELS, .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = CONFIG_STM32L4_TIM15_LOCK, .t_dts = CONFIG_STM32L4_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = CONFIG_STM32L4_TIM15_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM15_TRGO) - .trgo = STM32L4_TIM15_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) + .trgo = STM32_TIM15_TRGO, #endif - .base = STM32L4_TIM15_BASE, - .pclk = STM32L4_APB2_TIM15_CLKIN, + .base = STM32_TIM15_BASE, + .pclk = STM32_APB2_TIM15_CLKIN, }; #endif /* CONFIG_STM32L4_TIM15_PWM */ @@ -1139,7 +1139,7 @@ static struct stm32l4_pwmtimer_s g_pwm16dev = .chan_num = PWM_TIM16_NCHANNELS, .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = CONFIG_STM32L4_TIM16_LOCK, .t_dts = CONFIG_STM32L4_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY @@ -1148,8 +1148,8 @@ static struct stm32l4_pwmtimer_s g_pwm16dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ #endif - .base = STM32L4_TIM16_BASE, - .pclk = STM32L4_APB2_TIM16_CLKIN, + .base = STM32_TIM16_BASE, + .pclk = STM32_APB2_TIM16_CLKIN, }; #endif /* CONFIG_STM32L4_TIM16_PWM */ @@ -1205,7 +1205,7 @@ static struct stm32l4_pwmtimer_s g_pwm17dev = .chan_num = PWM_TIM17_NCHANNELS, .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = CONFIG_STM32L4_TIM17_LOCK, .t_dts = CONFIG_STM32L4_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY @@ -1214,8 +1214,8 @@ static struct stm32l4_pwmtimer_s g_pwm17dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ #endif - .base = STM32L4_TIM17_BASE, - .pclk = STM32L4_APB2_TIM17_CLKIN, + .base = STM32_TIM17_BASE, + .pclk = STM32_APB2_TIM17_CLKIN, }; #endif /* CONFIG_STM32L4_TIM17_PWM */ @@ -1253,7 +1253,7 @@ static struct stm32l4_pwmtimer_s g_pwmlp1dev = .chan_num = PWM_LPTIM1_NCHANNELS, .channels = g_pwmlp1channels, .timtype = TIMTYPE_LPTIM1, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -1262,15 +1262,15 @@ static struct stm32l4_pwmtimer_s g_pwmlp1dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for LPTIM1 */ #endif - .base = STM32L4_LPTIM1_BASE, + .base = STM32_LPTIM1_BASE, #if defined(CONFIG_STM32L4_LPTIM1_CLK_APB1) - .pclk = STM32L4_PCLK1_FREQUENCY, + .pclk = STM32_PCLK1_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSE) - .pclk = STM32L4_LSE_FREQUENCY, + .pclk = STM32_LSE_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSI) - .pclk = STM32L4_LSI_FREQUENCY, + .pclk = STM32_LSI_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM1_CLK_HSI) - .pclk = STM32L4_HSI_FREQUENCY, + .pclk = STM32_HSI_FREQUENCY, #endif }; #endif /* CONFIG_STM32L4_LPTIM1_PWM */ @@ -1309,7 +1309,7 @@ static struct stm32l4_pwmtimer_s g_pwmlp2dev = .chan_num = PWM_LPTIM2_NCHANNELS, .channels = g_pwmlp2channels, .timtype = TIMTYPE_LPTIM2, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -1318,15 +1318,15 @@ static struct stm32l4_pwmtimer_s g_pwmlp2dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for LPTIM2 */ #endif - .base = STM32L4_LPTIM2_BASE, + .base = STM32_LPTIM2_BASE, #if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) - .pclk = STM32L4_PCLK1_FREQUENCY, + .pclk = STM32_PCLK1_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSE) - .pclk = STM32L4_LSE_FREQUENCY, + .pclk = STM32_LSE_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSI) - .pclk = STM32L4_LSI_FREQUENCY, + .pclk = STM32_LSI_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM2_CLK_HSI) - .pclk = STM32L4_HSI_FREQUENCY, + .pclk = STM32_HSI_FREQUENCY, #endif }; #endif /* CONFIG_STM32L4_LPTIM2_PWM */ @@ -1374,12 +1374,12 @@ static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, uint16_t value) { if (priv->timtype == TIMTYPE_GENERAL32 && - (offset == STM32L4_GTIM_CNT_OFFSET || - offset == STM32L4_GTIM_ARR_OFFSET || - offset == STM32L4_GTIM_CCR1_OFFSET || - offset == STM32L4_GTIM_CCR2_OFFSET || - offset == STM32L4_GTIM_CCR3_OFFSET || - offset == STM32L4_GTIM_CCR4_OFFSET)) + (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET)) { /* a 32 bit access is required for a 32 bit register: * if only a 16 bit write would be performed, then the @@ -1416,12 +1416,12 @@ static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits) { if (priv->timtype == TIMTYPE_GENERAL32 && - (offset == STM32L4_GTIM_CNT_OFFSET || - offset == STM32L4_GTIM_ARR_OFFSET || - offset == STM32L4_GTIM_CCR1_OFFSET || - offset == STM32L4_GTIM_CCR2_OFFSET || - offset == STM32L4_GTIM_CCR3_OFFSET || - offset == STM32L4_GTIM_CCR4_OFFSET)) + (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET)) { /* a 32 bit access is required for a 32 bit register: * if only a 16 bit write would be performed, then the @@ -1462,52 +1462,52 @@ static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, { pwminfo("%s:\n", msg); pwminfo(" CFGR: %04x CR: %04x CMP: %04x ARR: %04x\n", - pwm_getreg(priv, STM32L4_LPTIM_CFGR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CMP_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_ARR_OFFSET)); + pwm_getreg(priv, STM32_LPTIM_CFGR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CMP_OFFSET), + pwm_getreg(priv, STM32_LPTIM_ARR_OFFSET)); pwminfo(" ISR: %04x CNT: %04x\n", - pwm_getreg(priv, STM32L4_LPTIM_ISR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CNT_OFFSET)); + pwm_getreg(priv, STM32_LPTIM_ISR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CNT_OFFSET)); } else { pwminfo("%s:\n", msg); pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_SR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_EGR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), + pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), + pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), + pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); #if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET), + pwm_getreg(priv, STM32_ATIM_DCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { pwminfo(" DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } } @@ -1528,7 +1528,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, { /* REVISIT: What about index? Is it necessary for LPTIM? */ - offset = STM32L4_LPTIM_CMP_OFFSET; + offset = STM32_LPTIM_CMP_OFFSET; pwm_putreg(priv, offset, ccr); return OK; @@ -1547,39 +1547,39 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, switch (index) { - case STM32L4_PWM_CHAN1: + case STM32_PWM_CHAN1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } - case STM32L4_PWM_CHAN3: + case STM32_PWM_CHAN3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN5: { - offset = STM32L4_ATIM_CCR5_OFFSET; + offset = STM32_ATIM_CCR5_OFFSET; break; } - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCR6_OFFSET; + offset = STM32_ATIM_CCR6_OFFSET; break; } @@ -1609,39 +1609,39 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) switch (index) { - case STM32L4_PWM_CHAN1: + case STM32_PWM_CHAN1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } - case STM32L4_PWM_CHAN3: + case STM32_PWM_CHAN3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN5: { - offset = STM32L4_ATIM_CCR5_OFFSET; + offset = STM32_ATIM_CCR5_OFFSET; break; } - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCR6_OFFSET; + offset = STM32_ATIM_CCR6_OFFSET; break; } @@ -1670,11 +1670,11 @@ static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) if (priv->timtype == TIMTYPE_LOWPOWER) { - pwm_putreg(priv, STM32L4_LPTIM_ARR_OFFSET, arr); + pwm_putreg(priv, STM32_LPTIM_ARR_OFFSET, arr); } else { - pwm_putreg(priv, STM32L4_GTIM_ARR_OFFSET, arr); + pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, arr); } return OK; @@ -1690,11 +1690,11 @@ static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) if (priv->timtype == TIMTYPE_LOWPOWER) { - return pwm_getreg(priv, STM32L4_LPTIM_ARR_OFFSET); + return pwm_getreg(priv, STM32_LPTIM_ARR_OFFSET); } else { - return pwm_getreg(priv, STM32L4_GTIM_ARR_OFFSET); + return pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); } } @@ -1766,13 +1766,13 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { /* Enable timer counter */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable timer counter */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } #ifdef HAVE_LPTIM } @@ -1782,13 +1782,13 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { /* Enable timer counter */ - pwm_modifyreg(priv, STM32L4_LPTIM_CR_OFFSET, 0, LPTIM_CR_ENABLE); + pwm_modifyreg(priv, STM32_LPTIM_CR_OFFSET, 0, LPTIM_CR_ENABLE); } else { /* Disable timer counter */ - pwm_modifyreg(priv, STM32L4_LPTIM_CR_OFFSET, LPTIM_CR_ENABLE, 0); + pwm_modifyreg(priv, STM32_LPTIM_CR_OFFSET, LPTIM_CR_ENABLE, 0); } } #endif @@ -1849,9 +1849,9 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, * intended so multiply by x2 */ - if ((priv->mode == STM32L4_TIMMODE_CENTER1) || - (priv->mode == STM32L4_TIMMODE_CENTER2) || - (priv->mode == STM32L4_TIMMODE_CENTER3)) + if ((priv->mode == STM32_TIMMODE_CENTER1) || + (priv->mode == STM32_TIMMODE_CENTER2) || + (priv->mode == STM32_TIMMODE_CENTER3)) { frequency = frequency * 2; } @@ -1889,7 +1889,7 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, /* Set the reload and prescaler values */ pwm_arr_update(dev, reload); - pwm_putreg(priv, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); return OK; } @@ -1961,12 +1961,12 @@ static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, /* Set the prescaler value */ - cfgr = pwm_getreg(priv, STM32L4_LPTIM_CFGR_OFFSET); + cfgr = pwm_getreg(priv, STM32_LPTIM_CFGR_OFFSET); cfgr &= ~LPTIM_CFGR_PRESC_MASK; cfgr |= (prescaler << LPTIM_CFGR_PRESC_SHIFT); - pwm_putreg(priv, STM32L4_LPTIM_CFGR_OFFSET, cfgr); + pwm_putreg(priv, STM32_LPTIM_CFGR_OFFSET, cfgr); return OK; } @@ -1994,7 +1994,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN */ - cr1 = pwm_getreg(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); /* Set the counter mode for the advanced timers (1,8) and most general * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 @@ -2016,31 +2016,31 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) switch (priv->mode) { - case STM32L4_TIMMODE_COUNTUP: + case STM32_TIMMODE_COUNTUP: { cr1 |= GTIM_CR1_EDGE; break; } - case STM32L4_TIMMODE_COUNTDOWN: + case STM32_TIMMODE_COUNTDOWN: { cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; break; } - case STM32L4_TIMMODE_CENTER1: + case STM32_TIMMODE_CENTER1: { cr1 |= GTIM_CR1_CENTER1; break; } - case STM32L4_TIMMODE_CENTER2: + case STM32_TIMMODE_CENTER2: { cr1 |= GTIM_CR1_CENTER2; break; } - case STM32L4_TIMMODE_CENTER3: + case STM32_TIMMODE_CENTER3: { cr1 |= GTIM_CR1_CENTER3; break; @@ -2064,7 +2064,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) /* Write CR1 */ - pwm_putreg(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); errout: return ret; @@ -2104,76 +2104,76 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, switch (mode) { - case STM32L4_CHANMODE_FRZN: + case STM32_CHANMODE_FRZN: { chanmode = GTIM_CCMR_MODE_FRZN; break; } - case STM32L4_CHANMODE_CHACT: + case STM32_CHANMODE_CHACT: { chanmode = GTIM_CCMR_MODE_CHACT; break; } - case STM32L4_CHANMODE_CHINACT: + case STM32_CHANMODE_CHINACT: { chanmode = GTIM_CCMR_MODE_CHINACT; break; } - case STM32L4_CHANMODE_OCREFTOG: + case STM32_CHANMODE_OCREFTOG: { chanmode = GTIM_CCMR_MODE_OCREFTOG; break; } - case STM32L4_CHANMODE_OCREFLO: + case STM32_CHANMODE_OCREFLO: { chanmode = GTIM_CCMR_MODE_OCREFLO; break; } - case STM32L4_CHANMODE_OCREFHI: + case STM32_CHANMODE_OCREFHI: { chanmode = GTIM_CCMR_MODE_OCREFHI; break; } - case STM32L4_CHANMODE_PWM1: + case STM32_CHANMODE_PWM1: { chanmode = GTIM_CCMR_MODE_PWM1; break; } - case STM32L4_CHANMODE_PWM2: + case STM32_CHANMODE_PWM2: { chanmode = GTIM_CCMR_MODE_PWM2; break; } - case STM32L4_CHANMODE_COMBINED1: + case STM32_CHANMODE_COMBINED1: { chanmode = ATIM_CCMR_MODE_COMBINED1; ocmbit = true; break; } - case STM32L4_CHANMODE_COMBINED2: + case STM32_CHANMODE_COMBINED2: { chanmode = ATIM_CCMR_MODE_COMBINED2; ocmbit = true; break; } - case STM32L4_CHANMODE_ASYMMETRIC1: + case STM32_CHANMODE_ASYMMETRIC1: { chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; ocmbit = true; break; } - case STM32L4_CHANMODE_ASYMMETRIC2: + case STM32_CHANMODE_ASYMMETRIC2: { chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; ocmbit = true; @@ -2194,24 +2194,24 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, { /* Get CCMR offset */ - case STM32L4_PWM_CHAN1: - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCMR1_OFFSET; + offset = STM32_GTIM_CCMR1_OFFSET; break; } - case STM32L4_PWM_CHAN3: - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCMR2_OFFSET; + offset = STM32_GTIM_CCMR2_OFFSET; break; } - case STM32L4_PWM_CHAN5: - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN5: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCMR3_OFFSET; + offset = STM32_ATIM_CCMR3_OFFSET; break; } @@ -2235,9 +2235,9 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, { /* Configure channel 1/3/5 */ - case STM32L4_PWM_CHAN1: - case STM32L4_PWM_CHAN3: - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN5: { /* Reset current channel 1/3/5 mode configuration */ @@ -2271,9 +2271,9 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, /* Configure channel 2/4/6 */ - case STM32L4_PWM_CHAN2: - case STM32L4_PWM_CHAN4: - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN2: + case STM32_PWM_CHAN4: + case STM32_PWM_CHAN6: { /* Reset current channel 2/4/6 mode configuration */ @@ -2334,8 +2334,8 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Get current registers state */ - cr2 = pwm_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccer = pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + cr2 = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); /* | OISx/OISxN | IDLE | for ADVANCED and COUNTUP16 | CR2 register * | CCxP/CCxNP | POL | all PWM timers | CCER register @@ -2343,7 +2343,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Configure output polarity (all PWM timers) */ - if (priv->channels[channel - 1].out1.pol == STM32L4_POL_NEG) + if (priv->channels[channel - 1].out1.pol == STM32_POL_NEG) { ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); } @@ -2358,7 +2358,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, { /* Configure output IDLE State */ - if (priv->channels[channel - 1].out1.idle == STM32L4_IDLE_ACTIVE) + if (priv->channels[channel - 1].out1.idle == STM32_IDLE_ACTIVE) { cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); } @@ -2370,7 +2370,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, #ifdef HAVE_PWM_COMPLEMENTARY /* Configure complementary output IDLE state */ - if (priv->channels[channel - 1].out2.idle == STM32L4_IDLE_ACTIVE) + if (priv->channels[channel - 1].out2.idle == STM32_IDLE_ACTIVE) { cr2 |= (ATIM_CR2_OIS1N << ((channel - 1) * 2)); } @@ -2381,7 +2381,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Configure complementary output polarity */ - if (priv->channels[channel - 1].out2.pol == STM32L4_POL_NEG) + if (priv->channels[channel - 1].out2.pol == STM32_POL_NEG) { ccer |= (ATIM_CCER_CC1NP << ((channel - 1) * 4)); } @@ -2417,8 +2417,8 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Write registers */ - pwm_modifyreg(priv, STM32L4_GTIM_CR2_OFFSET, 0, cr2); - pwm_modifyreg(priv, STM32L4_GTIM_CCER_OFFSET, 0, ccer); + pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); return OK; } @@ -2448,23 +2448,23 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, /* Get current register state */ - ccer = pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); /* Get outputs configuration */ - regval |= ((outputs & STM32L4_PWM_OUT1) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & STM32L4_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT2) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & STM32L4_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT3) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & STM32L4_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT4) ? GTIM_CCER_CC4E : 0); + regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0); + regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); + regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0); + regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); + regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0); + regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); + regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0); /* NOTE: CC4N does not exist, but some docs show configuration bits for it */ - regval |= ((outputs & STM32L4_PWM_OUT5) ? ATIM_CCER_CC5E : 0); - regval |= ((outputs & STM32L4_PWM_OUT6) ? ATIM_CCER_CC6E : 0); + regval |= ((outputs & STM32_PWM_OUT5) ? ATIM_CCER_CC5E : 0); + regval |= ((outputs & STM32_PWM_OUT6) ? ATIM_CCER_CC6E : 0); if (state == true) { @@ -2481,7 +2481,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, /* Write register */ - pwm_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); return OK; } @@ -2508,7 +2508,7 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) /* Get current register state */ - bdtr = pwm_getreg(priv, STM32L4_ATIM_BDTR_OFFSET); + bdtr = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); /* TODO: check if BDTR not locked */ @@ -2519,7 +2519,7 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) /* Write BDTR register */ - pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr); + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); errout: return ret; @@ -2538,7 +2538,7 @@ static int pwm_soft_update(struct pwm_lowerhalf_s *dev) { struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; - pwm_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); return OK; } @@ -2565,13 +2565,13 @@ static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) { /* Reset MOE bit */ - pwm_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); } else { /* Set MOE bit */ - pwm_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } return OK; @@ -2606,7 +2606,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) if (priv->channels[i].out1.in_use == 1) { - outputs |= (STM32L4_PWM_OUT1 << ((channel - 1) * 2)); + outputs |= (STM32_PWM_OUT1 << ((channel - 1) * 2)); } #ifdef HAVE_PWM_COMPLEMENTARY @@ -2614,7 +2614,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) if (priv->channels[i].out2.in_use == 1) { - outputs |= (STM32L4_PWM_OUT1N << ((channel - 1) * 2)); + outputs |= (STM32_PWM_OUT1N << ((channel - 1) * 2)); } #endif } @@ -2644,7 +2644,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) * should be no basic timers in this context */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, priv->t_dts << GTIM_CR1_CKD_SHIFT); #ifdef HAVE_PWM_COMPLEMENTARY @@ -2664,7 +2664,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Set Break 1 polarity */ - bdtr |= (priv->brk.pol1 == STM32L4_POL_NEG ? ATIM_BDTR_BKP : 0); + bdtr |= (priv->brk.pol1 == STM32_POL_NEG ? ATIM_BDTR_BKP : 0); } /* Configure Break 1 */ @@ -2677,7 +2677,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Set Break 2 polarity */ - bdtr |= (priv->brk.pol2 == STM32L4_POL_NEG ? ATIM_BDTR_BK2P : 0); + bdtr |= (priv->brk.pol2 == STM32_POL_NEG ? ATIM_BDTR_BK2P : 0); /* Configure BRK2 filter */ @@ -2699,7 +2699,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Write BDTR register at once */ - pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr); + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); return OK; } @@ -2956,7 +2956,7 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, /* Set the repetition counter to zero */ - pwm_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ @@ -3047,9 +3047,9 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, /* Start counter */ - cr = pwm_getreg(priv, STM32L4_LPTIM_CR_OFFSET); + cr = pwm_getreg(priv, STM32_LPTIM_CR_OFFSET); cr |= LPTIM_CR_CNTSTRT; - pwm_putreg(priv, STM32L4_LPTIM_CR_OFFSET, cr); + pwm_putreg(priv, STM32_LPTIM_CR_OFFSET, cr); pwm_dumpregs(dev, "After starting"); @@ -3086,7 +3086,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM1_PWM case 1: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; } @@ -3095,7 +3095,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM2_PWM case 2: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM2EN; break; } @@ -3104,7 +3104,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM3_PWM case 3: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM3EN; break; } @@ -3113,7 +3113,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM4_PWM case 4: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM4EN; break; } @@ -3122,7 +3122,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM5_PWM case 5: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM5EN; break; } @@ -3131,7 +3131,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM8_PWM case 8: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM8EN; break; } @@ -3140,7 +3140,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM15_PWM case 15: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM15EN; break; } @@ -3149,7 +3149,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM16_PWM case 16: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM16EN; break; } @@ -3158,7 +3158,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM17_PWM case 17: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM17EN; break; } @@ -3198,12 +3198,12 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, if (on) { - modifyreg32(STM32L4_RCC_APB1ENR1, + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); } else { - modifyreg32(STM32L4_RCC_APB1ENR1, + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); } @@ -3217,7 +3217,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #endif /* Choose which clock will be used for LPTIM1 */ - modifyreg32(STM32L4_RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, + modifyreg32(STM32_RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, clock_bits); break; } @@ -3231,12 +3231,12 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, if (on) { - modifyreg32(STM32L4_RCC_APB1ENR2, + modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); } else { - modifyreg32(STM32L4_RCC_APB1ENR2, + modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); } @@ -3250,7 +3250,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #endif /* Choose which clock will be used for LPTIM2 */ - modifyreg32(STM32L4_RCC_CCIPR, RCC_CCIPR_LPTIM2SEL_MASK, + modifyreg32(STM32_RCC_CCIPR, RCC_CCIPR_LPTIM2SEL_MASK, clock_bits); break; } @@ -3543,49 +3543,49 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { #ifdef CONFIG_STM32L4_TIM1_PWM case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif #ifdef CONFIG_STM32L4_TIM2_PWM case 2: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif #ifdef CONFIG_STM32L4_TIM3_PWM case 3: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif #ifdef CONFIG_STM32L4_TIM4_PWM case 4: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif #ifdef CONFIG_STM32L4_TIM5_PWM case 5: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif #ifdef CONFIG_STM32L4_TIM8_PWM case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif #ifdef CONFIG_STM32L4_TIM16_PWM case 16: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM16RST; break; #endif #ifdef CONFIG_STM32L4_TIM17_PWM case 17: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM17RST; break; #endif @@ -3599,13 +3599,13 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { #ifdef CONFIG_STM32L4_LPTIM1_PWM case 1: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_LPTIM1RST; break; #endif #ifdef CONFIG_STM32L4_LPTIM2_PWM case 2: - regaddr = STM32L4_RCC_APB1RSTR2; + regaddr = STM32_RCC_APB1RSTR2; resetbit = RCC_APB1RSTR2_LPTIM2RST; break; #endif @@ -3626,8 +3626,8 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) /* Disable further interrupts and stop the timer */ - pwm_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pwm_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Reset the timer - stopping the output and putting the timer back * into a state where pwm_start() can be called. diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index 14c75affd5f17..08b8e021a4f0e 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -844,80 +844,80 @@ enum stm32l4_timmode_e { - STM32L4_TIMMODE_COUNTUP = 0, - STM32L4_TIMMODE_COUNTDOWN = 1, - STM32L4_TIMMODE_CENTER1 = 2, - STM32L4_TIMMODE_CENTER2 = 3, - STM32L4_TIMMODE_CENTER3 = 4, + STM32_TIMMODE_COUNTUP = 0, + STM32_TIMMODE_COUNTDOWN = 1, + STM32_TIMMODE_CENTER1 = 2, + STM32_TIMMODE_CENTER2 = 3, + STM32_TIMMODE_CENTER3 = 4, }; /* Timer output polarity */ enum stm32l4_pwm_pol_e { - STM32L4_POL_POS = 0, - STM32L4_POL_NEG = 1, + STM32_POL_POS = 0, + STM32_POL_NEG = 1, }; /* Timer output IDLE state */ enum stm32l4_pwm_idle_e { - STM32L4_IDLE_INACTIVE = 0, - STM32L4_IDLE_ACTIVE = 1 + STM32_IDLE_INACTIVE = 0, + STM32_IDLE_ACTIVE = 1 }; /* PWM channel mode */ enum stm32l4_chanmode_e { - STM32L4_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ - STM32L4_CHANMODE_CHACT = 1, /* OCxREF active on match */ - STM32L4_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ - STM32L4_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ - STM32L4_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ - STM32L4_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ - STM32L4_CHANMODE_PWM1 = 6, /* PWM mode 1 */ - STM32L4_CHANMODE_PWM2 = 7, /* PWM mode 2 */ - STM32L4_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ - STM32L4_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ - STM32L4_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ - STM32L4_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ + STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ + STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ + STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ + STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ + STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ + STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ + STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */ + STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */ + STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ + STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ + STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ + STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ }; /* PWM timer channel */ enum stm32l4_pwm_chan_e { - STM32L4_PWM_CHAN1 = 1, - STM32L4_PWM_CHAN2 = 2, - STM32L4_PWM_CHAN3 = 3, - STM32L4_PWM_CHAN4 = 4, - STM32L4_PWM_CHAN5 = 5, - STM32L4_PWM_CHAN6 = 6, + STM32_PWM_CHAN1 = 1, + STM32_PWM_CHAN2 = 2, + STM32_PWM_CHAN3 = 3, + STM32_PWM_CHAN4 = 4, + STM32_PWM_CHAN5 = 5, + STM32_PWM_CHAN6 = 6, }; /* PWM timer channel output */ enum stm32l4_pwm_output_e { - STM32L4_PWM_OUT1 = (1 << 0), - STM32L4_PWM_OUT1N = (1 << 1), - STM32L4_PWM_OUT2 = (1 << 2), - STM32L4_PWM_OUT2N = (1 << 3), - STM32L4_PWM_OUT3 = (1 << 4), - STM32L4_PWM_OUT3N = (1 << 5), - STM32L4_PWM_OUT4 = (1 << 6), + STM32_PWM_OUT1 = (1 << 0), + STM32_PWM_OUT1N = (1 << 1), + STM32_PWM_OUT2 = (1 << 2), + STM32_PWM_OUT2N = (1 << 3), + STM32_PWM_OUT3 = (1 << 4), + STM32_PWM_OUT3N = (1 << 5), + STM32_PWM_OUT4 = (1 << 6), /* 1 << 7 reserved - no complementary output for CH4 */ /* Only available inside micro */ - STM32L4_PWM_OUT5 = (1 << 8), + STM32_PWM_OUT5 = (1 << 8), /* 1 << 9 reserved - no complementary output for CH5 */ - STM32L4_PWM_OUT6 = (1 << 10), + STM32_PWM_OUT6 = (1 << 10), /* 1 << 11 reserved - no complementary output for CH6 */ }; diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index cd78d8d6d436d..1da59b2797ad3 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -41,12 +41,12 @@ static inline uint16_t stm32l4_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32L4_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32L4_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } /**************************************************************************** @@ -75,7 +75,7 @@ bool stm32l4_pwr_enableclk(bool enable) uint32_t regval; bool wasenabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); /* Power interface clock enable. */ @@ -85,14 +85,14 @@ bool stm32l4_pwr_enableclk(bool enable) /* Disable power interface clock */ regval &= ~RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } else if (!wasenabled && enable) { /* Enable power interface clock */ regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } return wasenabled; @@ -120,7 +120,7 @@ bool stm32l4_pwr_enablebkp(bool writable) /* Get the current state of the STM32L4 PWR control register 1 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR1_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l4_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -169,7 +169,7 @@ bool stm32l4_pwr_enableusv(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -179,7 +179,7 @@ bool stm32l4_pwr_enableusv(bool set) /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,14 +189,14 @@ bool stm32l4_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -228,7 +228,7 @@ bool stm32l4_pwr_enable_pvme2(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -238,7 +238,7 @@ bool stm32l4_pwr_enable_pvme2(bool set) /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_PVME2) != 0); /* Enable or disable the ability to write */ @@ -248,14 +248,14 @@ bool stm32l4_pwr_enable_pvme2(bool set) /* Disable the Vddio2 monitoring */ regval &= ~PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddio2 monitoring */ regval |= PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -283,7 +283,7 @@ bool stm32l4_pwr_get_pvmo2(void) uint32_t regval; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -293,7 +293,7 @@ bool stm32l4_pwr_get_pvmo2(void) /* Get the current state of the STM32L4 SR2 control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_SR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_SR2_OFFSET); if (!was_clk_enabled) { @@ -325,7 +325,7 @@ bool stm32l4_pwr_vddio2_valid(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -335,7 +335,7 @@ bool stm32l4_pwr_vddio2_valid(bool set) /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -345,14 +345,14 @@ bool stm32l4_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -392,7 +392,7 @@ void stm32_pwr_setvos(int vos) return; } - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; if (vos == 1) @@ -404,5 +404,5 @@ void stm32_pwr_setvos(int vos) regval |= PWR_CR1_VOS_RANGE2; } - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); } diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 7f12c3b3990b8..d3e065ba9c490 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -94,62 +94,62 @@ #ifdef CONFIG_STM32L4_QENCODER_FILTER # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_1) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_CKINT) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_2) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_4) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_2) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_4) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_8) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_16) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_32) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif -# ifndef STM32L4_QENCODER_ICF +# ifndef STM32_QENCODER_ICF # warning "Invalid encoder filter combination, filter disabled" # endif #endif -#ifndef STM32L4_QENCODER_ICF -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifndef STM32_QENCODER_ICF +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT #endif -#define STM32L4_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) +#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) /* Debug ********************************************************************/ @@ -275,11 +275,11 @@ static const struct qe_ops_s g_qecallbacks = static const struct stm32l4_qeconfig_s g_tim1config = { .timid = 1, - .irq = STM32L4_IRQ_TIM1UP, + .irq = STM32_IRQ_TIM1UP, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM1_BITWIDTH, #endif - .base = STM32L4_TIM1_BASE, + .base = STM32_TIM1_BASE, .psc = CONFIG_STM32L4_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, @@ -299,11 +299,11 @@ static struct stm32l4_lowerhalf_s g_tim1lower = static const struct stm32l4_qeconfig_s g_tim2config = { .timid = 2, - .irq = STM32L4_IRQ_TIM2, + .irq = STM32_IRQ_TIM2, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM2_BITWIDTH, #endif - .base = STM32L4_TIM2_BASE, + .base = STM32_TIM2_BASE, .psc = CONFIG_STM32L4_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, @@ -323,11 +323,11 @@ static struct stm32l4_lowerhalf_s g_tim2lower = static const struct stm32l4_qeconfig_s g_tim3config = { .timid = 3, - .irq = STM32L4_IRQ_TIM3, + .irq = STM32_IRQ_TIM3, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM3_BITWIDTH, #endif - .base = STM32L4_TIM3_BASE, + .base = STM32_TIM3_BASE, .psc = CONFIG_STM32L4_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, @@ -347,11 +347,11 @@ static struct stm32l4_lowerhalf_s g_tim3lower = static const struct stm32l4_qeconfig_s g_tim4config = { .timid = 4, - .irq = STM32L4_IRQ_TIM4, + .irq = STM32_IRQ_TIM4, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM4_BITWIDTH, #endif - .base = STM32L4_TIM4_BASE, + .base = STM32_TIM4_BASE, .psc = CONFIG_STM32L4_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, @@ -371,11 +371,11 @@ static struct stm32l4_lowerhalf_s g_tim4lower = static const struct stm32l4_qeconfig_s g_tim5config = { .timid = 5, - .irq = STM32L4_IRQ_TIM5, + .irq = STM32_IRQ_TIM5, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM5_BITWIDTH, #endif - .base = STM32L4_TIM5_BASE, + .base = STM32_TIM5_BASE, .psc = CONFIG_STM32L4_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, @@ -395,11 +395,11 @@ static struct stm32l4_lowerhalf_s g_tim5lower = static const struct stm32l4_qeconfig_s g_tim8config = { .timid = 8, - .irq = STM32L4_IRQ_TIM8UP, + .irq = STM32_IRQ_TIM8UP, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM8_BITWIDTH, #endif - .base = STM32L4_TIM8_BASE, + .base = STM32_TIM8_BASE, .psc = CONFIG_STM32L4_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, @@ -531,43 +531,43 @@ static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv, { sninfo("%s:\n", msg); sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CR2_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_CR2_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET)); sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 " CCMR2: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_EGR_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCMR2_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_EGR_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" " ARR: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_ARR_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_PSC_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_ARR_OFFSET)); sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32L4_GTIM_CCR1_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCR2_OFFSET)); + stm32l4_getreg32(priv, STM32_GTIM_CCR1_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCR4_OFFSET)); + stm32l4_getreg32(priv, STM32_GTIM_CCR3_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); #if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32L4_ATIM_RCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_BDTR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_DMAR_OFFSET)); + stm32l4_getreg16(priv, STM32_ATIM_RCR_OFFSET), + stm32l4_getreg16(priv, STM32_ATIM_BDTR_OFFSET), + stm32l4_getreg16(priv, STM32_ATIM_DCR_OFFSET), + stm32l4_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { sninfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32L4_GTIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_DMAR_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_DCR_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -635,18 +635,18 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) * Nothing else is expected. */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); + regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Check the direction bit in the CR1 register and add or subtract the * maximum value, as appropriate. */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + regval = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); if ((regval & ATIM_CR1_DIR) != 0) { priv->position -= (int32_t)0x0000ffff; @@ -690,7 +690,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Timer base configuration */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); /* Clear the direction bit (0=count up) and select the Counter Mode * (0=Edge aligned) @@ -698,23 +698,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) */ cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Set the Autoreload value */ #if defined(HAVE_MIXEDWIDTH_TIMERS) if (priv->config->width == 32) { - stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); + stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); } else { - stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); + stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); } #elif defined(HAVE_32BIT_TIMERS) - stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); + stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); #else - stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); + stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); #endif /* Set the timer prescaler value. @@ -737,14 +737,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) */ stm32l4_putreg16(priv, - STM32L4_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); + STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); #if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ - stm32l4_putreg16(priv, STM32L4_ATIM_RCR_OFFSET, 0); + stm32l4_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); } #endif @@ -752,7 +752,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * and the repetition counter (only for TIM1 and TIM8) value immediately */ - stm32l4_putreg16(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + stm32l4_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* GPIO pin configuration */ @@ -761,27 +761,27 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Set the encoder Mode 3 */ - smcr = stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET); + smcr = stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET); smcr &= ~GTIM_SMCR_SMS_MASK; smcr |= GTIM_SMCR_ENCMD3; - stm32l4_putreg32(priv, STM32L4_GTIM_SMCR_OFFSET, smcr); + stm32l4_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); /* TI1 Channel Configuration */ /* Disable the Channel 1: Reset the CC1E Bit */ - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC1E; - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; /* Select the Polarity=rising and set the CC1E Bit */ @@ -790,34 +790,34 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* TI2 Channel Configuration */ /* Disable the Channel 2: Reset the CC2E Bit */ - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC2E; - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; /* Select the Polarity=rising and set the CC2E Bit */ @@ -826,23 +826,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* Disable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier &= ~GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); /* There is no need for interrupts with 32-bit timers */ @@ -868,14 +868,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Reset the Update Disable Bit */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 &= ~GTIM_CR1_UDIS; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Reset the URS Bit */ cr1 &= ~GTIM_CR1_URS; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* There is no need for interrupts with 32-bit timers */ @@ -886,22 +886,22 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Clear any pending update interrupts */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); + stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Then enable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier |= GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); } #endif /* Enable the TIM Counter */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 |= GTIM_CR1_CEN; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); stm32l4_dumpregs(priv, "After setup"); @@ -943,8 +943,8 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) /* Disable further interrupts and stop the timer */ - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, 0); - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, 0); + stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); /* Determine which timer to reset */ @@ -952,37 +952,37 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) { #ifdef CONFIG_STM32L4_TIM1_QE case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif #ifdef CONFIG_STM32L4_TIM2_QE case 2: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif #ifdef CONFIG_STM32L4_TIM3_QE case 3: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif #ifdef CONFIG_STM32L4_TIM4_QE case 4: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif #ifdef CONFIG_STM32L4_TIM5_QE case 5: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif #ifdef CONFIG_STM32L4_TIM8_QE case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif @@ -1010,14 +1010,14 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) /* Put the TI1 GPIO pin back to its default state */ pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32L4_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32l4_configgpio(pincfg); /* Put the TI2 GPIO pin back to its default state */ pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32L4_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32l4_configgpio(pincfg); return OK; @@ -1050,7 +1050,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, do { position = priv->position; - count = stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); + count = stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); verify = priv->position; } while (position != verify); @@ -1062,7 +1062,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, #else /* Return the counter value */ - *pos = (int32_t)stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); + *pos = (int32_t)stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); #endif return OK; } @@ -1090,7 +1090,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) */ flags = spin_lock_irqsave(&priv->lock); - stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); + stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); priv->position = 0; spin_unlock_irqrestore(&priv->lock, flags); #else @@ -1099,7 +1099,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) /* Reset the counter to zero */ - stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); + stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); #endif return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 954f8b460cec1..f3d3bc994a3e1 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -80,7 +80,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(STM32L4_QSPI_INTERRUPTS) && defined(CONFIG_STM32L4_QSPI_DMA) +#if defined(STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32L4_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -162,7 +162,7 @@ struct stm32l4_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ @@ -220,7 +220,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -260,7 +260,7 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif @@ -332,11 +332,11 @@ static struct stm32l4_qspidev_s g_qspi0dev = { .ops = &g_qspi0ops, }, - .base = STM32L4_QSPI_BASE, + .base = STM32_QSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, - .irq = STM32L4_IRQ_QUADSPI, + .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, @@ -478,7 +478,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) * output. */ - regval = getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET); /* Control Register */ + regval = getreg32(priv->base + STM32_QUADSPI_CR_OFFSET); /* Control Register */ spiinfo("CR:%08" PRIx32 "\n", regval); spiinfo(" EN:%1d ABORT:%1d DMAEN:%1d TCEN:%1d SSHIFT:%1d\n" " FTHRES: %d\n" @@ -499,14 +499,14 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) (regval & QSPI_CR_PMM) ? 1 : 0, (regval & QSPI_CR_PRESCALER_MASK) >> QSPI_CR_PRESCALER_SHIFT); - regval = getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET); /* Device Configuration Register */ + regval = getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET); /* Device Configuration Register */ spiinfo("DCR:%08" PRIx32 "\n", regval); spiinfo(" CKMODE:%1d CSHT:%d FSIZE:%d\n", (regval & QSPI_DCR_CKMODE) ? 1 : 0, (regval & QSPI_DCR_CSHT_MASK) >> QSPI_DCR_CSHT_SHIFT, (regval & QSPI_DCR_FSIZE_MASK) >> QSPI_DCR_FSIZE_SHIFT); - regval = getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */ + regval = getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */ spiinfo("CCR:%08" PRIx32 "\n", regval); spiinfo(" INST:%02x IMODE:%d ADMODE:%d ADSIZE:%d ABMODE:%d\n" " ABSIZE:%d DCYC:%d DMODE:%d FMODE:%d\n" @@ -523,7 +523,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) (regval & QSPI_CCR_SIOO) ? 1 : 0, (regval & QSPI_CCR_DDRM) ? 1 : 0); - regval = getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET); /* Status Register */ + regval = getreg32(priv->base + STM32_QUADSPI_SR_OFFSET); /* Status Register */ spiinfo("SR:%08" PRIx32 "\n", regval); spiinfo(" TEF:%1d TCF:%1d FTF:%1d SMF:%1d TOF:%1d BUSY:%1d FLEVEL:%d\n", (regval & QSPI_SR_TEF) ? 1 : 0, @@ -537,19 +537,19 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) #else spiinfo(" CR:%08" PRIx32 " DCR:%08" PRIx32 " CCR:%08" PRIx32 " SR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET), /* Control Register */ - getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET), /* Device Configuration Register */ - getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */ - getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET)); /* Status Register */ + getreg32(priv->base + STM32_QUADSPI_CR_OFFSET), /* Control Register */ + getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET), /* Device Configuration Register */ + getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */ + getreg32(priv->base + STM32_QUADSPI_SR_OFFSET)); /* Status Register */ spiinfo(" DLR:%08" PRIx32 " ABR:%08" PRIx32 " PSMKR:%08" PRIx32 " PSMAR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_DLR_OFFSET), /* Data Length Register */ - getreg32(priv->base + STM32L4_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */ - getreg32(priv->base + STM32L4_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */ - getreg32(priv->base + STM32L4_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */ + getreg32(priv->base + STM32_QUADSPI_DLR_OFFSET), /* Data Length Register */ + getreg32(priv->base + STM32_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */ + getreg32(priv->base + STM32_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */ + getreg32(priv->base + STM32_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */ spiinfo(" PIR:%08" PRIx32 " LPTR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_PIR_OFFSET), /* Polling Interval Register */ - getreg32(priv->base + STM32L4_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */ + getreg32(priv->base + STM32_QUADSPI_PIR_OFFSET), /* Polling Interval Register */ + getreg32(priv->base + STM32_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */ UNUSED(regval); #endif } @@ -561,22 +561,22 @@ static void qspi_dumpgpioconfig(const char *msg) uint32_t regval; spiinfo("%s:\n", msg); - regval = getreg32(STM32L4_GPIOE_MODER); + regval = getreg32(STM32_GPIOE_MODER); spiinfo("E_MODER:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_OTYPER); + regval = getreg32(STM32_GPIOE_OTYPER); spiinfo("E_OTYPER:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_OSPEED); + regval = getreg32(STM32_GPIOE_OSPEED); spiinfo("E_OSPEED:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_PUPDR); + regval = getreg32(STM32_GPIOE_PUPDR); spiinfo("E_PUPDR:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_AFRL); + regval = getreg32(STM32_GPIOE_AFRL); spiinfo("E_AFRL:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_AFRH); + regval = getreg32(STM32_GPIOE_AFRH); spiinfo("E_AFRH:%08" PRIx32 "\n", regval); } #endif @@ -787,7 +787,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -918,7 +918,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -951,12 +951,12 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv, if (polarity) { - while (!((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) + while (!((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET)) & mask)); } else { - while (((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) + while (((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET)) & mask)); } } @@ -979,9 +979,9 @@ static void qspi_abort(struct stm32l4_qspidev_s *priv) { uint32_t regval; - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_ABORT; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /**************************************************************************** @@ -1010,14 +1010,14 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, if (CCR_DMODE_NONE != xctn->datamode && CCR_FMODE_MEMMAP != fctn) { - qspi_putreg(priv, xctn->datasize - 1, STM32L4_QUADSPI_DLR_OFFSET); + qspi_putreg(priv, xctn->datasize - 1, STM32_QUADSPI_DLR_OFFSET); } /* If we have alternate bytes, stick them in now */ if (CCR_ABMODE_NONE != xctn->altbytesmode) { - qspi_putreg(priv, xctn->altbytes, STM32L4_QUADSPI_ABR_OFFSET); + qspi_putreg(priv, xctn->altbytes, STM32_QUADSPI_ABR_OFFSET); } /* Build the CCR value and set it */ @@ -1033,17 +1033,17 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, QSPI_CCR_FMODE(fctn) | (xctn->isddr ? QSPI_CCR_SIOO : 0) | (xctn->issioo ? QSPI_CCR_DDRM : 0); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET); /* If we have and need and address, set that now, too */ if (CCR_ADMODE_NONE != xctn->addrmode && CCR_FMODE_MEMMAP != fctn) { - qspi_putreg(priv, xctn->addr, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, xctn->addr, STM32_QUADSPI_AR_OFFSET); } } -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1068,22 +1068,22 @@ static int qspi0_interrupt(int irq, void *context, void *arg) /* Let's find out what is going on */ - status = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET); - cr = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + status = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET); + cr = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); /* Is it 'FIFO Threshold'? */ if ((status & QSPI_SR_FTF) && (cr & QSPI_CR_FTIE)) { volatile uint32_t *datareg = (volatile uint32_t *) - (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); + (g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET); if (g_qspi0dev.xctn->function == CCR_FMODE_INDWR) { /* Write data until we have no more or have no place to put it */ while ((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1105,7 +1105,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) /* Read data until we have no more or have no place to put it */ while ((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1131,27 +1131,27 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer * complete Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Do the last bit of read if needed */ if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD) { volatile uint32_t *datareg = (volatile uint32_t *) - (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); + (g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET); /* Read any remaining data */ while (((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) & + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FLEVEL_MASK) != 0) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1189,7 +1189,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32_QUADSPI_FCR); /* If 'automatic poll mode stop' is activated, we're done */ @@ -1197,9 +1197,9 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Disable the QSPI Transfer Error and Status Match Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_SMIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Set success status */ @@ -1223,14 +1223,14 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32_QUADSPI_FCR); /* Disable all the QSPI Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Set error status; 'transfer error' means that, in 'indirect mode', * an invalid address is attempted to be accessed. 'Invalid' is @@ -1251,7 +1251,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR); /* XXX this interrupt simply means that, in 'memory mapped mode', * the QSPI memory has not been accessed for a while, and the @@ -1426,16 +1426,16 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, } stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv, - STM32L4_QUADSPI_DR_OFFSET), + STM32_QUADSPI_DR_OFFSET), (uint32_t)meminfo->buffer, meminfo->buflen, dmaflags); qspi_dma_sample(priv, DMA_AFTER_SETUP); /* Enable the memory transfer */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Set up the Communications Configuration Register as per command info */ @@ -1481,9 +1481,9 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, if (ret < 0) { DEBUGPANIC(); - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); return ret; } @@ -1512,9 +1512,9 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, stm32l4_dmastop(priv->dmach); - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Complain if the DMA fails */ @@ -1527,7 +1527,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, } #endif -#if !defined(STM32L4_QSPI_INTERRUPTS) +#if !defined(STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -1548,12 +1548,12 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, { int ret = OK; volatile uint32_t *datareg = - (volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET); + (volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET); uint8_t *dest = (uint8_t *)xctn->buffer; uint32_t addrval; uint32_t regval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); if (dest != NULL) { /* Counter of remaining data */ @@ -1562,14 +1562,14 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, /* Ensure CCR register specifies indirect read */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CCR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CCR_OFFSET); regval &= ~QSPI_CCR_FMODE_MASK; regval |= QSPI_CCR_FMODE(CCR_FMODE_INDRD); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET); /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Transfer loop */ @@ -1589,7 +1589,7 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, /* Wait for transfer complete, then clear it */ qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); - qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Use Abort to clear the busy flag, and ditch any extra bytes in * fifo @@ -1626,7 +1626,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, { int ret = OK; volatile uint32_t *datareg = - (volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET); + (volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET); uint8_t *src = (uint8_t *)xctn->buffer; if (src != NULL) @@ -1652,7 +1652,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, /* Wait for transfer complete, then clear it */ qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); - qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Use Abort to clear the Busy flag */ @@ -1765,7 +1765,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) * prescaler = STL32L4_QSPI_CLOCK / frequency * * Where prescaler can have the range 1 to 256 and the - * STM32L4_QUADSPI_CR_OFFSET register field holds prescaler - 1. + * STM32_QUADSPI_CR_OFFSET register field holds prescaler - 1. * NOTE that a "ceiling" type of calculation is performed. * 'frequency' is treated as a not-to-exceed value. */ @@ -1785,10 +1785,10 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) /* Save the new prescaler value (minus one) */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_PRESCALER_MASK); regval |= (prescaler - 1) << QSPI_CR_PRESCALER_SHIFT; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Calculate the new actual frequency */ @@ -1850,7 +1850,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) * 3 1 1 */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR); + regval = qspi_getreg(priv, STM32_QUADSPI_DCR); regval &= ~(QSPI_DCR_CKMODE); switch (mode) @@ -1870,7 +1870,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) return; } - qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR); + qspi_putreg(priv, regval, STM32_QUADSPI_DCR); spiinfo("DCR=%08" PRIx32 "\n", regval); /* Save the mode so that subsequent re-configurations will be faster */ @@ -1957,9 +1957,9 @@ static int qspi_command(struct qspi_dev_s *dev, qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, - STM32L4_QUADSPI_FCR); + STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -1983,16 +1983,16 @@ static int qspi_command(struct qspi_dev_s *dev, * Complete' interrupts. */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } else { uint32_t regval; uint32_t addrval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2002,15 +2002,15 @@ static int qspi_command(struct qspi_dev_s *dev, /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer * Complete' interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } } else @@ -2023,9 +2023,9 @@ static int qspi_command(struct qspi_dev_s *dev, /* Enable 'Transfer Error' and 'Transfer Complete' interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2139,9 +2139,9 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, - STM32L4_QUADSPI_FCR); + STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2163,16 +2163,16 @@ static int qspi_memory(struct qspi_dev_s *dev, * interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } else { uint32_t regval; uint32_t addrval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2182,15 +2182,15 @@ static int qspi_memory(struct qspi_dev_s *dev, /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' * interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /* Wait for the interrupt routine to finish it's magic */ @@ -2356,7 +2356,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval = 0; regval &= ~(QSPI_CR_EN); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2364,7 +2364,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) /* Disable all interrupt sources for starters */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE); @@ -2373,7 +2373,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval &= ~(QSPI_CR_FTHRES_MASK); regval |= ((CONFIG_STM32L4_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2381,15 +2381,15 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) /* Configure QSPI Clock Prescaler and Sample Shift */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_PRESCALER_MASK | QSPI_CR_SSHIFT); regval |= (0x01 << QSPI_CR_PRESCALER_SHIFT); regval |= (0x00); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Configure QSPI Flash Size, CS High Time and Clock Mode */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); regval |= ((CONFIG_STM32L4_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); @@ -2406,13 +2406,13 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval |= ((nlog2size - 1) << QSPI_DCR_FSIZE_SHIFT); } - qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_DCR_OFFSET); /* Enable QSPI */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_EN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2467,18 +2467,18 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) /* Enable clocking to the QSPI peripheral */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); regval |= RCC_AHB3ENR_QSPIEN; - putreg32(regval, STM32L4_RCC_AHB3ENR); - regval = getreg32(STM32L4_RCC_AHB3ENR); + putreg32(regval, STM32_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); /* Reset the QSPI peripheral */ - regval = getreg32(STM32L4_RCC_AHB3RSTR); + regval = getreg32(STM32_RCC_AHB3RSTR); regval |= RCC_AHB3RSTR_QSPIRST; - putreg32(regval, STM32L4_RCC_AHB3RSTR); + putreg32(regval, STM32_RCC_AHB3RSTR); regval &= ~RCC_AHB3RSTR_QSPIRST; - putreg32(regval, STM32L4_RCC_AHB3RSTR); + putreg32(regval, STM32_RCC_AHB3RSTR); /* Configure multiplexed pins as connected on the board. */ @@ -2515,7 +2515,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) } #endif -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2541,7 +2541,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2549,7 +2549,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: @@ -2614,32 +2614,32 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * CS if memory is not accessed for a while) */ - qspi_putreg(priv, lpto, STM32L4_QUADSPI_LPTR_OFFSET); + qspi_putreg(priv, lpto, STM32_QUADSPI_LPTR_OFFSET); /* Clear Timeout interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TCEN | QSPI_CR_TOIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); #endif } else { - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_TCEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /* create a transaction object */ qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index f59a6be1753c8..04af2e8fcfe61 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -108,14 +108,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32l4_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32L4_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32L4_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -128,19 +128,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32L4_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32L4_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32l4_pwr_enablebkp(false); diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index 29c8257c00bbc..e17ed34b7b181 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -88,10 +88,10 @@ static inline void stm32l4_mcoconfig(uint32_t source) /* Set MCO source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCO_MASK); regval |= (source & RCC_CFGR_MCO_MASK); - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index 142890ddad972..c5480f1af84ac 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -93,7 +93,7 @@ static int stm32l4_rng_initialize(void) { _info("Initializing RNG\n"); - if (irq_attach(STM32L4_IRQ_RNG, stm32l4_rnginterrupt, NULL)) + if (irq_attach(STM32_IRQ_RNG, stm32l4_rnginterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -113,24 +113,24 @@ static void stm32l4_rngenable(void) /* Enable generation and interrupts */ - regval = getreg32(STM32L4_RNG_CR); + regval = getreg32(STM32_RNG_CR); regval |= RNG_CR_RNGEN; regval |= RNG_CR_IE; - putreg32(regval, STM32L4_RNG_CR); + putreg32(regval, STM32_RNG_CR); - up_enable_irq(STM32L4_IRQ_RNG); + up_enable_irq(STM32_IRQ_RNG); } static void stm32l4_rngdisable(void) { uint32_t regval; - up_disable_irq(STM32L4_IRQ_RNG); + up_disable_irq(STM32_IRQ_RNG); - regval = getreg32(STM32L4_RNG_CR); + regval = getreg32(STM32_RNG_CR); regval &= ~RNG_CR_IE; regval &= ~RNG_CR_RNGEN; - putreg32(regval, STM32L4_RNG_CR); + putreg32(regval, STM32_RNG_CR); } static int stm32l4_rnginterrupt(int irq, void *context, void *arg) @@ -138,12 +138,12 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) uint32_t rngsr; uint32_t data; - rngsr = getreg32(STM32L4_RNG_SR); + rngsr = getreg32(STM32_RNG_SR); if (rngsr & RNG_SR_CEIS) /* Check for clock error int stat */ { /* Clear it, we will try again. */ - putreg32(rngsr & ~RNG_SR_CEIS, STM32L4_RNG_SR); + putreg32(rngsr & ~RNG_SR_CEIS, STM32_RNG_SR); return OK; } @@ -153,12 +153,12 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) /* Clear seed error, then disable/enable the rng and try again. */ - putreg32(rngsr & ~RNG_SR_SEIS, STM32L4_RNG_SR); - crval = getreg32(STM32L4_RNG_CR); + putreg32(rngsr & ~RNG_SR_SEIS, STM32_RNG_SR); + crval = getreg32(STM32_RNG_CR); crval &= ~RNG_CR_RNGEN; - putreg32(crval, STM32L4_RNG_CR); + putreg32(crval, STM32_RNG_CR); crval |= RNG_CR_RNGEN; - putreg32(crval, STM32L4_RNG_CR); + putreg32(crval, STM32_RNG_CR); return OK; } @@ -169,7 +169,7 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) return OK; } - data = getreg32(STM32L4_RNG_DR); + data = getreg32(STM32_RNG_DR); /* As required by the FIPS PUB (Federal Information Processing Standard * Publication) 140-2, the first random number generated after setting the diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.c b/arch/arm/src/stm32l4/stm32l4_rtc.c index 17cd5e349f3a4..bc554c7564bee 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc.c @@ -142,23 +142,23 @@ static inline void rtc_enable_alarm(void); static void rtc_dumpregs(const char *msg) { rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32L4_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_WUTR)); - - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CALR)); - rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TAMPCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBSSR)); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); + + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAMPCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); } #else @@ -220,8 +220,8 @@ static void rtc_wprunlock(void) * Writing a wrong key re-activates the write protection. */ - putreg32(0xca, STM32L4_RTC_WPR); - putreg32(0x53, STM32L4_RTC_WPR); + putreg32(0xca, STM32_RTC_WPR); + putreg32(0x53, STM32_RTC_WPR); } /**************************************************************************** @@ -242,7 +242,7 @@ static inline void rtc_wprlock(void) { /* Writing any wrong key re-activates the write protection. */ - putreg32(0xff, STM32L4_RTC_WPR); + putreg32(0xff, STM32_RTC_WPR); /* Disable write access to the backup domain. */ @@ -272,16 +272,16 @@ static int rtc_synchwait(void) /* Clear Registers synchronization flag (RSF) */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Now wait the registers to become synchronised */ ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_RSF) != 0) { /* Synchronized */ @@ -316,21 +316,21 @@ static int rtc_enterinit(void) /* Check if the Initialization mode is already set */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); ret = OK; if ((regval & RTC_ISR_INITF) == 0) { /* Set the Initialization mode */ - putreg32(RTC_ISR_INIT, STM32L4_RTC_ISR); + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); /* Wait until the RTC is in the INIT state (or a timeout occurs) */ ret = -ETIMEDOUT; for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_INITF) != 0) { ret = OK; @@ -360,9 +360,9 @@ static void rtc_exitinit(void) { uint32_t regval; - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); } /**************************************************************************** @@ -434,13 +434,13 @@ static void rtc_resume(void) /* Clear the RTC alarm flags */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Clear the EXTI Line 18 Pending bit (Connected internally to RTC Alarm) */ - putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR); #endif } @@ -478,10 +478,10 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* Check for EXTI from Alarm A or B and handle according */ - cr = getreg32(STM32L4_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRAIE) != 0) { - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRAF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMA]; @@ -500,17 +500,17 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRAF; - putreg32(isr, STM32L4_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #if CONFIG_RTC_NALARMS > 1 - cr = getreg32(STM32L4_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRBIE) != 0) { - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRBF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMB]; @@ -529,9 +529,9 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRBF; - putreg32(isr, STM32L4_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #endif @@ -574,7 +574,7 @@ static int rtchw_check_alrawf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRAWF) != 0) { ret = OK; @@ -600,7 +600,7 @@ static int rtchw_check_alrbwf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRBWF) != 0) { ret = OK; @@ -639,12 +639,12 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Disable RTC alarm A & Interrupt A */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); /* Ensure Alarm A flag reset; this is edge triggered */ - isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm A to be writable */ @@ -656,13 +656,13 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm A register */ - putreg32(alarmreg, STM32L4_RTC_ALRMAR); - putreg32(0, STM32L4_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR)); + putreg32(alarmreg, STM32_RTC_ALRMAR); + putreg32(0, STM32_RTC_ALRMASSR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ - modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); errout_with_wprunlock: rtc_wprlock(); @@ -682,12 +682,12 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Disable RTC alarm B & Interrupt B */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); /* Ensure Alarm B flag reset; this is edge triggered */ - isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm B to be writable */ @@ -699,13 +699,13 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm B register */ - putreg32(alarmreg, STM32L4_RTC_ALRMBR); - putreg32(0, STM32L4_RTC_ALRMBSSR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR)); + putreg32(alarmreg, STM32_RTC_ALRMBR); + putreg32(0, STM32_RTC_ALRMBSSR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); /* Enable RTC alarm B */ - modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); rtchw_set_alrmbr_exit: rtc_wprlock(); @@ -870,13 +870,13 @@ int up_rtc_initialize(void) stm32l4_pwr_enablebkp(true); #if defined(CONFIG_STM32L4_RTC_HSECLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); #elif defined(CONFIG_STM32L4_RTC_LSICLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); #elif defined(CONFIG_STM32L4_RTC_LSECLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else # error "No clock for RTC!" @@ -884,7 +884,7 @@ int up_rtc_initialize(void) /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_RTCEN); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* Disable the write protection for RTC registers */ @@ -912,9 +912,9 @@ int up_rtc_initialize(void) { /* Clear RTC_CR FMT, OSEL and POL Bits */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Configure RTC pre-scaler with the required values */ @@ -930,7 +930,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); + STM32_RTC_PRER); #elif defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) @@ -938,13 +938,13 @@ int up_rtc_initialize(void) putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); + STM32_RTC_PRER); #else /* defined(CONFIG_STM32L4_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); + STM32_RTC_PRER); #endif /* Exit Initialization mode */ @@ -1038,18 +1038,18 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, do { - dr = getreg32(STM32L4_RTC_DR); - tr = getreg32(STM32L4_RTC_TR); + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); #ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32L4_RTC_SSR); - tmp = getreg32(STM32L4_RTC_TR); + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); if (tmp != tr) { continue; } #endif - tmp = getreg32(STM32L4_RTC_DR); + tmp = getreg32(STM32_RTC_DR); if (tmp == dr) { break; @@ -1108,7 +1108,7 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, uint32_t prediv_s; uint32_t usecs; - prediv_s = getreg32(STM32L4_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; ssr &= RTC_SSR_MASK; @@ -1255,8 +1255,8 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) { /* Set the RTC TR and DR registers */ - putreg32(tr, STM32L4_RTC_TR); - putreg32(dr, STM32L4_RTC_DR); + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); /* Exit Initialization mode and wait for the RTC Time and Date * registers to be synchronized with RTC APB clock. @@ -1452,7 +1452,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); ret = rtchw_check_alrawf(); if (ret < 0) @@ -1462,8 +1462,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(-1, STM32L4_RTC_ALRMAR); - modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRAF, 0); + putreg32(-1, STM32_RTC_ALRMAR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); rtc_wprlock(); ret = OK; } @@ -1483,7 +1483,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); ret = rtchw_check_alrbwf(); if (ret < 0) @@ -1493,8 +1493,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(-1, STM32L4_RTC_ALRMBR); - modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRBF, 0); + putreg32(-1, STM32_RTC_ALRMBR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); rtc_wprlock(); ret = OK; } @@ -1541,7 +1541,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { case RTC_ALARMA: { - alarmreg = STM32L4_RTC_ALRMAR; + alarmreg = STM32_RTC_ALRMAR; ret = stm32l4_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1550,7 +1550,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #if CONFIG_RTC_NALARMS > 1 case RTC_ALARMB: { - alarmreg = STM32L4_RTC_ALRMBR; + alarmreg = STM32_RTC_ALRMBR; ret = stm32l4_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1588,9 +1588,9 @@ static int stm32l4_rtc_wakeup_handler(int irq, void *context, stm32l4_pwr_enablebkp(true); - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); stm32l4_pwr_enablebkp(false); @@ -1636,10 +1636,10 @@ static inline void rtc_set_wcksel(unsigned int wucksel) { uint32_t regval = 0; - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUCKSEL_MASK; regval |= wucksel; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); } #endif @@ -1675,7 +1675,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" #elif defined(CONFIG_STM32L4_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / - STM32L4_LSE_FREQUENCY; + STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1713,9 +1713,9 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, /* Clear WUTE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUTE; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1724,7 +1724,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1748,7 +1748,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, /* Get number of ticks. */ - ticks = millisecs * STM32L4_LSE_FREQUENCY / (16 * 1000); + ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); /* Wake-up is after WUT+1 ticks. */ @@ -1769,17 +1769,17 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, * selection. */ - putreg32(wutr_val, STM32L4_RTC_WUTR); + putreg32(wutr_val, STM32_RTC_WUTR); - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval |= RTC_CR_WUTIE | RTC_CR_WUTE; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Just in case resets the WUTF flag in RTC_ISR */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); rtc_wprlock(); @@ -1811,9 +1811,9 @@ int stm32l4_rtc_cancelperiodic(void) /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1822,7 +1822,7 @@ int stm32l4_rtc_cancelperiodic(void) ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1834,9 +1834,9 @@ int stm32l4_rtc_cancelperiodic(void) /* Clears RTC_WUTR register */ - regval = getreg32(STM32L4_RTC_WUTR); + regval = getreg32(STM32_RTC_WUTR); regval &= ~RTC_WUTR_MASK; - putreg32(regval, STM32L4_RTC_WUTR); + putreg32(regval, STM32_RTC_WUTR); rtc_wprlock(); diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index b89807b7c0768..7a202e90d2273 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -38,8 +38,8 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ -#define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ #if !defined(CONFIG_STM32L4_RTC_MAGIC) # define CONFIG_STM32L4_RTC_MAGIC (0xfacefeee) @@ -55,7 +55,7 @@ #define RTC_MAGIC CONFIG_STM32L4_RTC_MAGIC #define RTC_MAGIC_TIME_SET CONFIG_STM32L4_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32L4_RTC_BKR(CONFIG_STM32L4_RTC_MAGIC_REG) +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32L4_RTC_MAGIC_REG) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c index bac80beef62f9..27e3aaabfc0ec 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_NALARMS 2 +#define STM32_NALARMS 2 /**************************************************************************** * Private Types @@ -81,7 +81,7 @@ struct stm32l4_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32l4_cbinfo_s cbinfo[STM32L4_NALARMS]; + struct stm32l4_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c index 5344b764b36ae..f30d0564e7927 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.c +++ b/arch/arm/src/stm32l4/stm32l4_sai.c @@ -233,9 +233,9 @@ static const struct i2s_ops_s g_i2sops = static struct stm32l4_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else @@ -254,9 +254,9 @@ static struct stm32l4_sai_s g_sai1a_priv = static struct stm32l4_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else @@ -277,9 +277,9 @@ static struct stm32l4_sai_s g_sai1b_priv = static struct stm32l4_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else @@ -298,9 +298,9 @@ static struct stm32l4_sai_s g_sai2a_priv = static struct stm32l4_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else @@ -433,14 +433,14 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg) i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32L4_SAI_CR1_OFFSET), - sai_getreg(priv, STM32L4_SAI_CR2_OFFSET), - sai_getreg(priv, STM32L4_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32L4_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32L4_SAI_IM_OFFSET), - sai_getreg(priv, STM32L4_SAI_SR_OFFSET), - sai_getreg(priv, STM32L4_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); } #endif @@ -474,7 +474,7 @@ static void sai_mckdivider(struct stm32l4_sai_s *priv) mckdiv = priv->frequency / (priv->samplerate * 2 * 256); - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -621,7 +621,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32l4_dmasetup(priv->dma, priv->base + STM32L4_SAI_DR_OFFSET, + stm32l4_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -634,7 +634,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -901,9 +901,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -981,7 +981,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1086,7 +1086,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1275,21 +1275,21 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) priv->dma = stm32l4_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32L4_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32L4_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index 49e54607c3400..c1a1de20f1bb5 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -561,8 +561,8 @@ struct stm32_dev_s g_sdmmcdev1 = #endif #endif }, - .base = STM32L4_SDMMC1_BASE, - .nirq = STM32L4_IRQ_SDMMC1, + .base = STM32_SDMMC1_BASE, + .nirq = STM32_IRQ_SDMMC1, #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC1_D0, #endif diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index bf78be0ddf899..084ae78ac5008 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -467,13 +467,13 @@ static struct stm32l4_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32L4_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -529,13 +529,13 @@ static struct stm32l4_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32L4_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32L4_PCLK2_FREQUENCY, - .usartbase = STM32L4_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -591,13 +591,13 @@ static struct stm32l4_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32L4_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -653,13 +653,13 @@ static struct stm32l4_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32L4_IRQ_USART3, + .irq = STM32_IRQ_USART3, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) @@ -715,7 +715,7 @@ static struct stm32l4_serial_s g_uart4priv = .priv = &g_uart4priv, }, - .irq = STM32L4_IRQ_UART4, + .irq = STM32_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, @@ -728,8 +728,8 @@ static struct stm32l4_serial_s g_uart4priv = .rts_gpio = GPIO_UART4_RTS, # endif .baud = CONFIG_UART4_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, # ifdef CONFIG_UART4_RXDMA @@ -777,7 +777,7 @@ static struct stm32l4_serial_s g_uart5priv = .priv = &g_uart5priv, }, - .irq = STM32L4_IRQ_UART5, + .irq = STM32_IRQ_UART5, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, @@ -790,8 +790,8 @@ static struct stm32l4_serial_s g_uart5priv = .rts_gpio = GPIO_UART5_RTS, # endif .baud = CONFIG_UART5_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, # ifdef CONFIG_UART5_RXDMA @@ -814,7 +814,7 @@ static struct stm32l4_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ static struct stm32l4_serial_s * -const g_uart_devs[STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART] = +const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -891,15 +891,15 @@ void stm32l4serial_setusartint(struct stm32l4_serial_s *priv, * enable/usage table above) */ - cr = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + cr = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -959,8 +959,8 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - cr3 = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -1035,8 +1035,8 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - brr = stm32l4serial_getreg(priv, STM32L4_USART_BRR_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32l4serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -1062,8 +1062,8 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); - stm32l4serial_putreg(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif @@ -1099,7 +1099,7 @@ static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32l4serial_putreg(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32l4serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif @@ -1122,7 +1122,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) /* Set baud rate */ #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32L4_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { stm32l4serial_setbaud_lpuart(priv); } @@ -1134,7 +1134,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) /* Configure parity mode */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -1172,11 +1172,11 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -1184,11 +1184,11 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L4_FLOWCONTROL_BROKEN) @@ -1205,7 +1205,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) } #endif - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1250,7 +1250,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + while ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -1356,7 +1356,7 @@ static void stm32l4serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l4_serial_s *priv = g_uart_devs[n]; @@ -1396,39 +1396,39 @@ static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) default: return; #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER - case STM32L4_LPUART1_BASE: + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32L4_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif #ifdef CONFIG_STM32L4_USART1_SERIALDRIVER - case STM32L4_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif #ifdef CONFIG_STM32L4_USART2_SERIALDRIVER - case STM32L4_USART2_BASE: + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_USART3_SERIALDRIVER - case STM32L4_USART3_BASE: + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_UART4_SERIALDRIVER - case STM32L4_UART4_BASE: + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_UART5_SERIALDRIVER - case STM32L4_UART5_BASE: + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1515,7 +1515,7 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1526,26 +1526,26 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1553,9 +1553,9 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1608,7 +1608,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1619,7 +1619,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1633,9 +1633,9 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1693,9 +1693,9 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1859,7 +1859,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET); + priv->sr = stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1931,7 +1931,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32l4serial_putreg(priv, STM32L4_USART_ICR_OFFSET, + stm32l4serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2002,19 +2002,19 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -2050,11 +2050,11 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2071,17 +2071,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -2101,11 +2101,11 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2122,17 +2122,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -2143,11 +2143,11 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2304,8 +2304,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2317,8 +2317,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2354,7 +2354,7 @@ static int stm32l4serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32l4serial_getreg(priv, STM32L4_USART_RDR_OFFSET); + rdr = stm32l4serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2444,7 +2444,7 @@ static bool stm32l4serial_rxavailable(struct uart_dev_s *dev) struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; - return ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2607,7 +2607,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2618,7 +2618,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2787,7 +2787,7 @@ static void stm32l4serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32l4serial_putreg(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)ch); + stm32l4serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2875,7 +2875,7 @@ static bool stm32l4serial_txready(struct uart_dev_s *dev) { struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; - return ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2918,11 +2918,11 @@ static void stm32l4serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET); + priv->sr = stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32l4serial_putreg(priv, STM32L4_USART_ICR_OFFSET, + stm32l4serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -3058,7 +3058,7 @@ static int stm32l4serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l4_serial_s *priv = g_uart_devs[n]; @@ -3128,7 +3128,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -3197,7 +3197,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index b53213580ea0b..c2864c40c2c76 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -285,10 +285,10 @@ static struct stm32l4_spidev_s g_spi1dev = { .ops = &g_spi1ops, }, - .spibase = STM32L4_SPI1_BASE, - .spiclock = STM32L4_PCLK2_FREQUENCY, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, #ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI1, + .spiirq = STM32_IRQ_SPI1, #endif #ifdef CONFIG_STM32L4_SPI_DMA /* lines must be configured in board.h */ @@ -343,10 +343,10 @@ static struct stm32l4_spidev_s g_spi2dev = { .ops = &g_spi2ops, }, - .spibase = STM32L4_SPI2_BASE, - .spiclock = STM32L4_PCLK1_FREQUENCY, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI2, + .spiirq = STM32_IRQ_SPI2, #endif #ifdef CONFIG_STM32L4_SPI_DMA .rxch = DMACHAN_SPI2_RX, @@ -399,10 +399,10 @@ static struct stm32l4_spidev_s g_spi3dev = { .ops = &g_spi3ops, }, - .spibase = STM32L4_SPI3_BASE, - .spiclock = STM32L4_PCLK1_FREQUENCY, + .spibase = STM32_SPI3_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI3, + .spiirq = STM32_IRQ_SPI3, #endif #ifdef CONFIG_STM32L4_SPI_DMA .rxch = DMACHAN_SPI3_RX, @@ -522,11 +522,11 @@ static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32L4_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -547,11 +547,11 @@ static inline uint8_t spi_readbyte(struct stm32l4_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32L4_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -574,11 +574,11 @@ static inline void spi_writeword(struct stm32l4_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32L4_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -601,11 +601,11 @@ static inline void spi_writebyte(struct stm32l4_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32L4_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -809,7 +809,7 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, /* Configure the RX DMA */ - stm32l4_dmasetup(priv->rxdma, priv->spibase + STM32L4_SPI_DR_OFFSET, + stm32l4_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -861,7 +861,7 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, /* Setup the TX DMA */ - stm32l4_dmasetup(priv->txdma, priv->spibase + STM32L4_SPI_DR_OFFSET, + stm32l4_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -985,11 +985,11 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32L4_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32L4_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32L4_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -1055,9 +1055,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, actual = priv->spiclock >> 8; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1127,9 +1127,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster. @@ -1193,9 +1193,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so that subsequent re-configurations will be * faster. @@ -1248,9 +1248,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1316,7 +1316,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32L4_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1738,11 +1738,11 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1754,7 +1754,7 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32L4_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32L4_SPI_DMA /* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA @@ -1769,13 +1769,13 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) priv->txdma = stm32l4_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index 64aacd7fc9a01..cda08e167a468 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -60,8 +60,8 @@ * the stack + 4; */ -#define SRAM2_START STM32L4_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 6facb4e747f88..24776426fabe3 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -309,16 +309,16 @@ static const struct stm32l4_tim_ops_s stm32l4_tim_ops = struct stm32l4_tim_priv_s stm32l4_tim1_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM2 struct stm32l4_tim_priv_s stm32l4_tim2_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -326,8 +326,8 @@ struct stm32l4_tim_priv_s stm32l4_tim2_priv = struct stm32l4_tim_priv_s stm32l4_tim3_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -335,8 +335,8 @@ struct stm32l4_tim_priv_s stm32l4_tim3_priv = struct stm32l4_tim_priv_s stm32l4_tim4_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -344,8 +344,8 @@ struct stm32l4_tim_priv_s stm32l4_tim4_priv = struct stm32l4_tim_priv_s stm32l4_tim5_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -353,8 +353,8 @@ struct stm32l4_tim_priv_s stm32l4_tim5_priv = struct stm32l4_tim_priv_s stm32l4_tim6_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -362,8 +362,8 @@ struct stm32l4_tim_priv_s stm32l4_tim6_priv = struct stm32l4_tim_priv_s stm32l4_tim7_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -371,8 +371,8 @@ struct stm32l4_tim_priv_s stm32l4_tim7_priv = struct stm32l4_tim_priv_s stm32l4_tim8_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -380,8 +380,8 @@ struct stm32l4_tim_priv_s stm32l4_tim8_priv = struct stm32l4_tim_priv_s stm32l4_tim15_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -389,8 +389,8 @@ struct stm32l4_tim_priv_s stm32l4_tim15_priv = struct stm32l4_tim_priv_s stm32l4_tim16_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -398,8 +398,8 @@ struct stm32l4_tim_priv_s stm32l4_tim16_priv = struct stm32l4_tim_priv_s stm32l4_tim17_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -487,9 +487,9 @@ static inline void stm32l4_putreg32(struct stm32l4_tim_dev_s *dev, static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_EGR_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l4_putreg16(dev, STM32L4_GTIM_EGR_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -498,11 +498,11 @@ static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -511,9 +511,9 @@ static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -527,7 +527,7 @@ static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev) { - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_DISABLED; + ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32l4_tim_disable(dev); } @@ -547,7 +547,7 @@ static void stm32l4_tim_gpioconfig(uint32_t cfg, * Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32L4_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32l4_configgpio(cfg); } @@ -567,42 +567,42 @@ static void stm32l4_tim_dumpregs(struct stm32l4_tim_dev_s *dev) struct stm32l4_tim_priv_s *priv = (struct stm32l4_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CR2_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_SMCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_DIER_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CR2_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_SMCR_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCMR2_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CNT_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_ARR_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CNT_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CCR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR2_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR4_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_CCR1_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCR2_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCR3_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCR4_OFFSET) ); - if (priv->base == STM32L4_TIM1_BASE || priv->base == STM32L4_TIM8_BASE) + if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32L4_ATIM_RCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_BDTR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_DMAR_OFFSET)); + stm32l4_getreg16(dev, STM32_ATIM_RCR_OFFSET), + stm32l4_getreg16(dev, STM32_ATIM_BDTR_OFFSET), + stm32l4_getreg16(dev, STM32_ATIM_DCR_OFFSET), + stm32l4_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_DMAR_OFFSET)); + stm32l4_getreg16(dev, STM32_GTIM_DCR_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); } } @@ -621,13 +621,13 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L4_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L4_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L4_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -636,21 +636,21 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32L4_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32L4_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32L4_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; break; - case STM32L4_TIM_MODE_UP: + case STM32_TIM_MODE_UP: val &= ~GTIM_CR1_DIR; break; - case STM32L4_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: @@ -659,7 +659,7 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, break; - case STM32L4_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -668,15 +668,15 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, } stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32L4_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM1_BASE || - ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM8_BASE) + if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l4_modifyreg16(dev, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32l4_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -714,66 +714,66 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -838,8 +838,8 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, /* Set the reload and prescaler values */ - stm32l4_putreg16(dev, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - stm32l4_putreg16(dev, STM32L4_GTIM_ARR_OFFSET, reload); + stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); + stm32l4_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); return (timclk / reload); } @@ -873,66 +873,66 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -963,7 +963,7 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, prescaler = 0xffff; } - stm32l4_putreg16(dev, STM32L4_GTIM_PSC_OFFSET, prescaler); + stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); return prescaler; } @@ -987,64 +987,64 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -1054,7 +1054,7 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -1066,7 +1066,7 @@ static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l4_putreg32(dev, STM32L4_GTIM_ARR_OFFSET, period); + stm32l4_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -1076,7 +1076,7 @@ static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, static uint32_t stm32l4_tim_getperiod (struct stm32l4_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l4_getreg32 (dev, STM32L4_GTIM_ARR_OFFSET); + return stm32l4_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -1086,7 +1086,7 @@ static uint32_t stm32l4_tim_getperiod (struct stm32l4_tim_dev_s *dev) static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l4_getreg32(dev, STM32L4_GTIM_CNT_OFFSET); + uint32_t counter = stm32l4_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -1096,10 +1096,10 @@ static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -1123,7 +1123,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -1136,7 +1136,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET); + ccer_val = stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -1144,13 +1144,13 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L4_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L4_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L4_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -1159,12 +1159,12 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32L4_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32L4_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32L4_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -1176,7 +1176,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32L4_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -1191,21 +1191,21 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32L4_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32l4_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32l4_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l4_putreg16(dev, STM32L4_GTIM_CCER_OFFSET, ccer_val); + stm32l4_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1238,7 +1238,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1271,7 +1271,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1304,7 +1304,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1336,7 +1336,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1369,7 +1369,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1402,7 +1402,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1435,7 +1435,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1468,7 +1468,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1520,19 +1520,19 @@ static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR1_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR2_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR3_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR4_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1554,16 +1554,16 @@ static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR1_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR2_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR3_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR4_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1584,66 +1584,66 @@ static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: - vectorno = STM32L4_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: - vectorno = STM32L4_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: - vectorno = STM32L4_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: - vectorno = STM32L4_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: - vectorno = STM32L4_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: - vectorno = STM32L4_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: - vectorno = STM32L4_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: - vectorno = STM32L4_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: - vectorno = STM32L4_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: - vectorno = STM32L4_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: - vectorno = STM32L4_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1676,7 +1676,7 @@ static void stm32l4_tim_enableint(struct stm32l4_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1687,7 +1687,7 @@ static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1696,7 +1696,7 @@ static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, int source) { - stm32l4_putreg16(dev, STM32L4_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32l4_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1706,7 +1706,7 @@ static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, int source) static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, int source) { - uint16_t regval = stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET); + uint16_t regval = stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1729,76 +1729,76 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) #ifdef CONFIG_STM32L4_TIM1 case 1: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim1_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32L4_TIM2 case 2: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim2_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32L4_TIM3 case 3: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim3_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32L4_TIM4 case 4: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim4_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32L4_TIM5 case 5: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim5_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32L4_TIM6 case 6: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim6_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32L4_TIM7 case 7: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim7_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32L4_TIM8 case 8: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim8_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32L4_TIM15 case 15: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim15_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32L4_TIM16 case 16: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim16_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32L4_TIM17 case 17: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim17_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1808,7 +1808,7 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l4_tim_priv_s *)dev)->mode != STM32L4_TIM_MODE_UNUSED) + if (((struct stm32l4_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1834,67 +1834,67 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1904,7 +1904,7 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_UNUSED; + ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index 06a800a351951..338ca644aa2cc 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -38,24 +38,24 @@ /* Helpers ******************************************************************/ -#define STM32L4_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L4_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32L4_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L4_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32L4_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L4_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32L4_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L4_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32L4_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32L4_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32L4_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32L4_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32L4_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32L4_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32L4_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32L4_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32L4_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32L4_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) /**************************************************************************** * Public Types @@ -83,34 +83,34 @@ struct stm32l4_tim_dev_s enum stm32l4_tim_mode_e { - STM32L4_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32L4_TIM_MODE_MASK = 0x0310, - STM32L4_TIM_MODE_DISABLED = 0x0000, - STM32L4_TIM_MODE_UP = 0x0100, - STM32L4_TIM_MODE_DOWN = 0x0110, - STM32L4_TIM_MODE_UPDOWN = 0x0200, - STM32L4_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32L4_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32L4_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32L4_TIM_MODE_CK_EXT = 0x0800, - STM32L4_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32L4_TIM_MODE_CK_CHINVALID = 0x0000, - STM32L4_TIM_MODE_CK_CH1 = 0x0001, - STM32L4_TIM_MODE_CK_CH2 = 0x0002, - STM32L4_TIM_MODE_CK_CH3 = 0x0003, - STM32L4_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -120,32 +120,32 @@ enum stm32l4_tim_mode_e enum stm32l4_tim_channel_e { - STM32L4_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32L4_TIM_CH_POLARITY_POS = 0x00, - STM32L4_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32L4_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32L4_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active * high when counter < compare */ #if 0 - STM32L4_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32L4_TIM_CH_INCAPTURE = 0x10, - STM32L4_TIM_CH_INPWM = 0x20 - STM32L4_TIM_CH_DRIVE_OC = open collector mode + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC = open collector mode #endif }; diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index 0f2d6376b29e5..35f42694a4aa2 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -71,17 +71,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_TIM1_RES 16 -#define STM32L4_TIM2_RES 32 -#define STM32L4_TIM3_RES 16 -#define STM32L4_TIM4_RES 16 -#define STM32L4_TIM5_RES 32 -#define STM32L4_TIM6_RES 16 -#define STM32L4_TIM7_RES 16 -#define STM32L4_TIM8_RES 16 -#define STM32L4_TIM15_RES 16 -#define STM32L4_TIM16_RES 16 -#define STM32L4_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -141,7 +141,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -149,7 +149,7 @@ static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -157,7 +157,7 @@ static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif @@ -165,7 +165,7 @@ static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif @@ -173,7 +173,7 @@ static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif @@ -181,7 +181,7 @@ static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif @@ -189,7 +189,7 @@ static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif @@ -197,7 +197,7 @@ static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif @@ -205,7 +205,7 @@ static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif @@ -213,7 +213,7 @@ static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -221,7 +221,7 @@ static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -247,13 +247,13 @@ static int stm32l4_timer_handler(int irq, void *context, void *arg) (struct stm32l4_lowerhalf_s *) arg; uint32_t next_interval_us = 0; - STM32L4_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32L4_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -286,12 +286,12 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32L4_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); - STM32L4_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -325,9 +325,9 @@ static int stm32l4_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_DISABLEINT(priv->tim, 0); - STM32L4_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -382,8 +382,8 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32L4_TIM_GETCLOCK(priv->tim); - period = STM32L4_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -399,7 +399,7 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32L4_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -436,13 +436,13 @@ static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32L4_TIM_SETCLOCK(priv->tim, freq); - STM32L4_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32L4_TIM_SETCLOCK(priv->tim, 1000000); - STM32L4_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -482,13 +482,13 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32L4_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); - STM32L4_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32L4_TIM_DISABLEINT(priv->tim, 0); - STM32L4_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l4/stm32l4_timerisr.c b/arch/arm/src/stm32l4/stm32l4_timerisr.c index 1a37a689243e4..d943d75bb3d33 100644 --- a/arch/arm/src/stm32l4/stm32l4_timerisr.c +++ b/arch/arm/src/stm32l4/stm32l4_timerisr.c @@ -58,9 +58,9 @@ /* And I don't know now to re-configure it yet */ #ifdef CONFIG_STM32L4_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32L4_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32L4_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -134,7 +134,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32L4_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); /* Enable SysTick interrupts */ @@ -143,5 +143,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32L4_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32l4/stm32l4_uid.c b/arch/arm/src/stm32l4/stm32l4_uid.c index ef9d52da06400..eb955770cb610 100644 --- a/arch/arm/src/stm32l4/stm32l4_uid.c +++ b/arch/arm/src/stm32l4/stm32l4_uid.c @@ -44,7 +44,7 @@ #include "hardware/stm32l4_memorymap.h" #include "stm32l4_uid.h" -#ifdef STM32L4_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -56,8 +56,8 @@ void stm32l4_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32L4_SYSMEM_UID)+i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID)+i); } } -#endif /* STM32L4_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c index f3424f388a3e5..2df8f8bd83f1e 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.c +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c @@ -75,17 +75,17 @@ /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ -#define STM32L4_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) +#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) /* Endpoint identifiers. The STM32L4 supports up to 16 mono-directional or 8 * bidirectional endpoints. However, when you take into account PMA buffer * usage (see below) and the fact that EP0 is bidirectional, then there is * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll - * define STM32L4_NENDPOINTS to be 8, however, because that is how many + * define STM32_NENDPOINTS to be 8, however, because that is how many * endpoint register sets there are. */ -#define STM32L4_NENDPOINTS (8) +#define STM32_NENDPOINTS (8) #define EP0 (0) #define EP1 (1) #define EP2 (2) @@ -95,47 +95,47 @@ #define EP6 (6) #define EP7 (7) -#define STM32L4_ENDP_BIT(ep) (1 << (ep)) -#define STM32L4_ENDP_ALLSET 0xff +#define STM32_ENDP_BIT(ep) (1 << (ep)) +#define STM32_ENDP_ALLSET 0xff /* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ -#define STM32L4_MAXPACKET_SHIFT (6) -#define STM32L4_MAXPACKET_SIZE (1 << (STM32L4_MAXPACKET_SHIFT)) -#define STM32L4_MAXPACKET_MASK (STM32L4_MAXPACKET_SIZE-1) +#define STM32_MAXPACKET_SHIFT (6) +#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) +#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) -#define STM32L4_EP0MAXPACKET STM32L4_MAXPACKET_SIZE +#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE /* Buffer descriptor table. * The buffer table is positioned at the beginning of the 1024-byte - * USB memory. We will use the first STM32L4_NENDPOINTS*8 bytes for + * USB memory. We will use the first STM32_NENDPOINTS*8 bytes for * the buffer table. That is exactly 64 bytes, leaving 15*64 bytes for * endpoint buffers. */ -#define STM32L4_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB +#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB * RAM */ -#define STM32L4_DESC_SIZE (8) /* Each descriptor is 4*2=8 +#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 * bytes in size */ -#define STM32L4_BTABLE_SIZE (STM32L4_NENDPOINTS*STM32L4_DESC_SIZE) +#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) /* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), * then we have space for only 7 buffers; endpoint 0 will require two * buffers, leaving 5 for other endpoints. */ -#define STM32L4_BUFFER_START STM32L4_BTABLE_SIZE -#define STM32L4_EP0_RXADDR STM32L4_BUFFER_START -#define STM32L4_EP0_TXADDR (STM32L4_EP0_RXADDR+STM32L4_EP0MAXPACKET) +#define STM32_BUFFER_START STM32_BTABLE_SIZE +#define STM32_EP0_RXADDR STM32_BUFFER_START +#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) -#define STM32L4_BUFFER_EP0 0x03 -#define STM32L4_NBUFFERS 7 -#define STM32L4_BUFFER_BIT(bn) (1 << (bn)) -#define STM32L4_BUFFER_ALLSET 0x7f -#define STM32L4_BUFNO2BUF(bn) (STM32L4_BUFFER_START+((bn)<ep.eplog)); /* Save the result in the request structure */ @@ -1333,7 +1333,7 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, * requests to send. */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINQEMPTY), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); return -ENOENT; } @@ -1449,7 +1449,7 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) priv->ep0state = EP0STATE_SETUP_READY; priv->ep0datlen = readlen; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUTDATA), readlen); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), readlen); stm32l4_ep0setup(priv); priv->ep0datlen = 0; /* mark the date consumed */ @@ -1482,7 +1482,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, * soon. */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTQEMPTY), epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); return -ENOENT; } @@ -1493,7 +1493,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, if (privreq->req.len == 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTNULLPACKET), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); stm32l4_reqcomplete(privep, OK); return OK; } @@ -1556,7 +1556,7 @@ static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) { int ret; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); if (priv && priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -1567,7 +1567,7 @@ static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1584,7 +1584,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* Decode and service non control endpoints interrupt */ - epr = stm32l4_getreg(STM32L4_USB_EPR(epno)); + epr = stm32l4_getreg(STM32_USB_EPR(epno)); privep = &priv->eplist[epno]; /* OUT: host-to-device @@ -1594,7 +1594,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); /* Handle read requests. First check if a read request is available to * accept the host data. @@ -1618,7 +1618,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) if (stm32l4_rqempty(privep)) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTPENDING), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16_t)epno); /* Mark the RX processing as pending and NAK any OUT actions @@ -1648,7 +1648,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* Clear interrupt status */ stm32l4_clrepctrtx(epno); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); /* Handle write requests */ @@ -1678,7 +1678,7 @@ static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) /* Set address in every allocated endpoint */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { if (stm32l4_epreserved(priv, epno)) { @@ -1688,7 +1688,7 @@ static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) /* Set the device address and enable function */ - stm32l4_putreg(value | USB_DADDR_EF, STM32L4_USB_DADDR); + stm32l4_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); } /**************************************************************************** @@ -1755,7 +1755,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUT), len.w); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); /* At this point priv->ctrl is the setup packet. */ @@ -1772,7 +1772,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_NOSTDREQ), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); /* Let the class implementation handle all non-standar requests */ @@ -1795,12 +1795,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), priv->ctrl.type); if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || index.b[MSB] != 0 || value.w != 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } else @@ -1810,12 +1810,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) case USB_REQ_RECIPIENT_ENDPOINT: { epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPGETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), epno); - if (epno >= STM32L4_NENDPOINTS) + if (epno >= STM32_NENDPOINTS) { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADEPGETSTATUS), + STM32_TRACEERR_BADEPGETSTATUS), epno); priv->ep0state = EP0STATE_STALLED; } @@ -1855,7 +1855,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if (index.w == 0) { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_DEVGETSTATUS), + STM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup=YES; selfpowered=? */ @@ -1869,7 +1869,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) else { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADDEVGETSTATUS), + STM32_TRACEERR_BADDEVGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } @@ -1878,7 +1878,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) case USB_REQ_RECIPIENT_INTERFACE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IFGETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); response.w = 0; nbytes = 2; /* Response size: 2 bytes */ @@ -1887,7 +1887,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } break; @@ -1904,7 +1904,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_CLEARFEATURE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) @@ -1921,7 +1921,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Endpoint recipient */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; @@ -1930,7 +1930,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADCLEARFEATURE), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } @@ -1946,7 +1946,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETFEATURE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), priv->ctrl.type); if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && value.w == USB_FEATURE_TESTMODE) @@ -1970,7 +1970,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Handler recipient=endpoint */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; @@ -1979,7 +1979,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1994,13 +1994,13 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPSETADDRESS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), value.w); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE || index.w != 0 || len.w != 0 || value.w > 127) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); priv->ep0state = EP0STATE_STALLED; } @@ -2026,7 +2026,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETDESC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), priv->ctrl.type); /* The request seems valid... @@ -2046,7 +2046,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETCONFIG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2061,7 +2061,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2075,7 +2075,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETCONFIG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && index.w == 0 && len.w == 0) @@ -2089,7 +2089,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2112,7 +2112,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* Let the class implementation handle the request */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETIF), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), priv->ctrl.type); stm32l4_dispatchrequest(priv); handled = true; @@ -2127,13 +2127,13 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDCTRLREQ), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); priv->ep0state = EP0STATE_STALLED; } @@ -2288,7 +2288,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, { /* EP0 IN: device-to-host (DIR=0) */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0IN), istr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); stm32l4_clrepctrtx(EP0); stm32l4_ep0in(priv); } @@ -2296,7 +2296,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, { /* EP0 OUT: host-to-device (DIR=1) */ - epr = stm32l4_getreg(STM32L4_USB_EPR(EP0)); + epr = stm32l4_getreg(STM32_USB_EPR(EP0)); /* CTR_TX is set when an IN transaction successfully * completes on an endpoint @@ -2304,7 +2304,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if ((epr & USB_EPR_CTR_TX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0INDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); stm32l4_clrepctrtx(EP0); stm32l4_ep0in(priv); } @@ -2315,7 +2315,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); stm32l4_clrepctrrx(EP0); stm32l4_ep0setup(priv); } @@ -2326,7 +2326,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0OUTDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); stm32l4_clrepctrrx(EP0); stm32l4_ep0out(priv); } @@ -2335,14 +2335,14 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0BADCTR), epr); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); return; /* Does this ever happen? */ } } /* Make sure that the EP0 packet size is still OK (superstitious?) */ - stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET); + stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); /* Now figure out the new RX/TX status. Here are all possible * consequences of the above EP0 operations: @@ -2359,7 +2359,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if (priv->ep0state == EP0STATE_STALLED) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0SETUPSTALLED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); priv->rxstatus = USB_EPR_STATRX_STALL; priv->txstatus = USB_EPR_STATTX_STALL; @@ -2394,9 +2394,9 @@ static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv) /* Stay in loop while LP interrupts are pending */ - while (((istr = stm32l4_getreg(STM32L4_USB_ISTR)) & USB_ISTR_CTR) != 0) + while (((istr = stm32l4_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) { - stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32L4_USB_ISTR); + stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ @@ -2430,9 +2430,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) */ struct stm32l4_usbdev_s *priv = &g_usbdev; - uint16_t istr = stm32l4_getreg(STM32L4_USB_ISTR); + uint16_t istr = stm32l4_getreg(STM32_USB_ISTR); - usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USBINTERRUPT), istr); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USBINTERRUPT), istr); /* Handle Reset interrupts. When this event occurs, the peripheral is left * in the same conditions it is left by the system reset (but with the @@ -2443,8 +2443,8 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Reset interrupt received. Clear the RESET interrupt status. */ - stm32l4_putreg(~USB_ISTR_RESET, STM32L4_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RESET), istr); + stm32l4_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); /* Restore our power-up state and exit now because istr is no longer * valid. @@ -2464,9 +2464,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * cause of the resume is indicated in the FNR register */ - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WKUP), - stm32l4_getreg(STM32L4_USB_FNR)); + stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), + stm32l4_getreg(STM32_USB_FNR)); /* Perform the wakeup action */ @@ -2480,28 +2480,28 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) stm32l4_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32l4_putreg(~USB_CNTR_SUSPM, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); } if ((istr & USB_ISTR_SUSP & priv->imask) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSP), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); stm32l4_suspend(priv); /* Clear of the ISTR bit must be done after setting of * USB_CNTR_FSUSP */ - stm32l4_putreg(~USB_ISTR_SUSP, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); } if ((istr & USB_ISTR_ESOF & priv->imask) != 0) { - stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); /* Resume handling timing is made with ESOFs */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ESOF), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); stm32l4_esofpoll(priv); } @@ -2509,13 +2509,13 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Low priority endpoint correct transfer interrupt */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_USBCTR), istr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_USBCTR), istr); stm32l4_lptransfer(priv); } out: - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USBINTERRUPT), - stm32l4_getreg(STM32L4_USB_EP0R)); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USBINTERRUPT), + stm32l4_getreg(STM32_USB_EP0R)); return OK; } @@ -2537,10 +2537,10 @@ static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, * register (Hmmm... who is shadowing whom?) */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval &= ~USB_CNTR_ALLINTS; regval |= priv->imask; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); } /**************************************************************************** @@ -2567,15 +2567,15 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) */ stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); /* Set the FSUSP bit in the CNTR register. This activates suspend mode * within the USB peripheral and disables further SUSP interrupts. */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval |= USB_CNTR_FSUSP; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); /* If we are not a self-powered device, the got to low-power mode */ @@ -2586,9 +2586,9 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) * able to detect resume activity */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval |= USB_CNTR_LPMODE; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); } /* Let the board-specific logic know that we have entered the suspend @@ -2616,9 +2616,9 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) * hardware when a WKUP interrupt event occurs). */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_LPMODE); - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); /* Restore full power -- whatever that means for this particular board */ @@ -2626,7 +2626,7 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) /* Reset FSUSP bit and enable normal interrupt handling */ - stm32l4_putreg(STM32L4_CNTR_SETUP, STM32L4_USB_CNTR); + stm32l4_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); /* Notify the class driver of the resume event */ @@ -2651,9 +2651,9 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) /* One ESOF after internal resume requested */ case RSMSTATE_STARTED: - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval |= USB_CNTR_RESUME; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_WAITING; priv->nesofs = 10; break; @@ -2666,9 +2666,9 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) { /* Okay.. we are ready to resume normal operation */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_RESUME); - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the SUSP interrupt, and enable @@ -2677,7 +2677,7 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); } break; @@ -2711,9 +2711,9 @@ stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) * (skipping EP0) */ - for (epndx = 1; epndx < STM32L4_NENDPOINTS; epndx++) + for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) { - uint8_t bit = STM32L4_ENDP_BIT(epndx); + uint8_t bit = STM32_ENDP_BIT(epndx); if ((epset & bit) != 0) { /* Mark the endpoint no longer available */ @@ -2741,7 +2741,7 @@ stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32L4_ENDP_BIT(USB_EPNO(privep->ep.eplog)); + priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); leave_critical_section(flags); } @@ -2752,7 +2752,7 @@ stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, static inline bool stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno) { - return ((priv->epavail & STM32L4_ENDP_BIT(epno)) == 0); + return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); } /**************************************************************************** @@ -2766,11 +2766,11 @@ static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv) int bufndx; flags = enter_critical_section(); - for (bufndx = 2; bufndx < STM32L4_NBUFFERS; bufndx++) + for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) { /* Check if this buffer is available */ - uint8_t bit = STM32L4_BUFFER_BIT(bufndx); + uint8_t bit = STM32_BUFFER_BIT(bufndx); if ((priv->bufavail & bit) != 0) { /* Yes.. Mark the endpoint no longer available */ @@ -2796,7 +2796,7 @@ static inline void stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32L4_ENDP_BIT(privep->bufno); + priv->epavail |= STM32_ENDP_BIT(privep->bufno); leave_critical_section(flags); } @@ -2821,7 +2821,7 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !desc) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p desc=%p\n", ep, desc); return -EINVAL; } @@ -2855,7 +2855,7 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, break; default: - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPTYPE), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), (uint16_t)desc->type); return -EINVAL; } @@ -2865,12 +2865,12 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, /* Get the address of the PMA buffer allocated for this endpoint */ #warning "REVISIT: Should configure BULK EPs using double buffer feature" - pma = STM32L4_BUFNO2BUF(privep->bufno); + pma = STM32_BUFNO2BUF(privep->bufno); /* Get the maxpacket size of the endpoint. */ maxpacket = GETUINT16(desc->mxpacketsize); - DEBUGASSERT(maxpacket <= STM32L4_MAXPACKET_SIZE); + DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); ep->maxpacket = maxpacket; /* Get the subset matching the requested direction */ @@ -2918,7 +2918,7 @@ static int stm32l4_epdisable(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p\n", ep); return -EINVAL; } @@ -2953,7 +2953,7 @@ static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -2963,7 +2963,7 @@ static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) privreq = kmm_malloc(sizeof(struct stm32l4_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } @@ -2983,7 +2983,7 @@ static void stm32l4_epfreereq(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -3009,7 +3009,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -3022,7 +3022,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); uerr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; @@ -3123,7 +3123,7 @@ static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_USB if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3151,7 +3151,7 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) #ifdef CONFIG_DEBUG_USB if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3180,7 +3180,7 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) if (status == 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPDISABLED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); if (epno == 0) { @@ -3291,14 +3291,14 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, { struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; struct stm32l4_ep_s *privep = NULL; - uint8_t epset = STM32L4_ENDP_ALLSET; + uint8_t epset = STM32_ENDP_ALLSET; int bufno; usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -3319,9 +3319,9 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, * by the hardware. */ - if (epno >= STM32L4_NENDPOINTS) + if (epno >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPNO), (uint16_t)epno); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); return NULL; } @@ -3330,7 +3330,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, * the IN/OUT pair for this logical address. */ - epset = STM32L4_ENDP_BIT(epno); + epset = STM32_ENDP_BIT(epno); } /* Check if the selected endpoint number is available */ @@ -3338,7 +3338,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, privep = stm32l4_epreserve(priv, epset); if (!privep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPRESERVE), (uint16_t)epset); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); goto errout; } @@ -3348,7 +3348,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, bufno = stm32l4_epallocpma(priv); if (bufno < 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPBUFFER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); goto errout_with_ep; } @@ -3373,7 +3373,7 @@ static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_USB if (!dev || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -3405,14 +3405,14 @@ static int stm32l4_getframe(struct usbdev_s *dev) #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif /* Return the last frame number detected by the hardware */ - fnr = stm32l4_getreg(STM32L4_USB_FNR); + fnr = stm32l4_getreg(STM32_USB_FNR); usbtrace(TRACE_DEVGETFRAME, fnr); return (fnr & USB_FNR_FN_MASK); } @@ -3430,7 +3430,7 @@ static int stm32l4_wakeup(struct usbdev_s *dev) #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3450,7 +3450,7 @@ static int stm32l4_wakeup(struct usbdev_s *dev) */ stm32l4_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); leave_critical_section(flags); return OK; } @@ -3468,7 +3468,7 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -3489,7 +3489,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); flags = enter_critical_section(); - regval = stm32l4_getreg(STM32L4_USB_BCDR); + regval = stm32l4_getreg(STM32_USB_BCDR); if (enable) { /* Connect the device by setting the DP pull-up bit in the BCDR @@ -3507,7 +3507,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval &= ~USB_BCDR_DPPU; } - stm32l4_putreg(regval, STM32L4_USB_BCDR); + stm32l4_putreg(regval, STM32_USB_BCDR); leave_critical_section(flags); return OK; } @@ -3526,7 +3526,7 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Put the USB controller in reset, disable all interrupts */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Tell the class driver that we are disconnected. The class driver * should then accept any new configurations. @@ -3542,7 +3542,7 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Reset endpoints */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { struct stm32l4_ep_s *privep = &priv->eplist[epno]; @@ -3578,24 +3578,24 @@ static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv) { /* Put the USB controller into reset, clear all interrupt enables */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Disable interrupts (and perhaps take the USB controller out of reset) */ priv->imask = 0; - stm32l4_putreg(priv->imask, STM32L4_USB_CNTR); + stm32l4_putreg(priv->imask, STM32_USB_CNTR); /* Set the STM32 BTABLE address */ - stm32l4_putreg(STM32L4_BTABLE_ADDRESS & 0xfff8, STM32L4_USB_BTABLE); + stm32l4_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); /* Initialize EP0 */ stm32l4_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32l4_seteprxaddr(EP0, STM32L4_EP0_RXADDR); - stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET); - stm32l4_seteptxaddr(EP0, STM32L4_EP0_TXADDR); + stm32l4_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32l4_seteptxaddr(EP0, STM32_EP0_TXADDR); stm32l4_clrstatusout(EP0); stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_VALID); @@ -3605,12 +3605,12 @@ static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv) /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32L4_USB_ISTR); + stm32l4_putreg(0, STM32_USB_ISTR); /* Enable interrupts at the USB controller */ - stm32l4_setimask(priv, STM32L4_CNTR_SETUP, - (USB_CNTR_ALLINTS & ~STM32L4_CNTR_SETUP)); + stm32l4_setimask(priv, STM32_CNTR_SETUP, + (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); stm32l4_dumpep(EP0); } @@ -3626,7 +3626,7 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * all USB interrupts */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); /* Disconnect the device / disable the pull-up. We don't want the * host to enumerate us until the class driver is registered. @@ -3642,12 +3642,12 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) memset(priv, 0, sizeof(struct stm32l4_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->eplist[EP0].ep; - priv->epavail = STM32L4_ENDP_ALLSET & ~STM32L4_ENDP_BIT(EP0); - priv->bufavail = STM32L4_BUFFER_ALLSET & ~STM32L4_BUFFER_EP0; + priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); + priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; /* Initialize the endpoint list */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -3664,13 +3664,13 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * packet size can be selected when the endpoint is configured. */ - priv->eplist[epno].ep.maxpacket = STM32L4_MAXPACKET_SIZE; + priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; } /* Select a smaller endpoint size for EP0 */ -#if STM32L4_EP0MAXPACKET < STM32L4_MAXPACKET_SIZE - priv->eplist[EP0].ep.maxpacket = STM32L4_EP0MAXPACKET; +#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE + priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; #endif /* Configure the USB controller. USB uses the following GPIO pins: @@ -3691,7 +3691,7 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * class driver has been bound. */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); up_mdelay(5); } @@ -3705,11 +3705,11 @@ static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv) /* Disable all interrupts and force the USB controller into reset */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32L4_USB_ISTR); + stm32l4_putreg(0, STM32_USB_ISTR); /* Disconnect the device / disable the pull-up */ @@ -3717,7 +3717,7 @@ static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv) /* Power down the USB controller */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); } /**************************************************************************** @@ -3757,10 +3757,10 @@ void arm_usbinitialize(void) * driver is bound. */ - if (irq_attach(STM32L4_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0) + if (irq_attach(STM32_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32L4_IRQ_USB_FS); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USB_FS); arm_usbuninitialize(); } } @@ -3788,12 +3788,12 @@ void arm_usbuninitialize(void) /* Disable and detach the USB IRQ */ - up_disable_irq(STM32L4_IRQ_USB_FS); - irq_detach(STM32L4_IRQ_USB_FS); + up_disable_irq(STM32_IRQ_USB_FS); + irq_detach(STM32_IRQ_USB_FS); if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } @@ -3833,13 +3833,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -3853,7 +3853,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); } else { @@ -3865,7 +3865,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) /* Enable USB controller interrupt at the NVIC */ - up_enable_irq(STM32L4_IRQ_USB_FS); + up_enable_irq(STM32_IRQ_USB_FS); /* Enable pull-up to connect the device. * The host should enumerate us some time after this @@ -3904,7 +3904,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_USB if (driver != priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3922,7 +3922,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupt (but keep attached) */ - up_disable_irq(STM32L4_IRQ_USB_FS); + up_disable_irq(STM32_IRQ_USB_FS); /* Put the hardware in an inactive state. Then bring the hardware back up * in the reset state (this is probably not necessary, the stm32l4_reset() diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index 31e48e84d61aa..99cce2c222b5e 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,7 +128,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L4_DMA1 /* DMA 1 clock enable */ @@ -154,7 +154,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -173,26 +173,26 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif /* These chips have no GPIOF, GPIOG or GPIOI */ -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); @@ -216,7 +216,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -235,7 +235,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L4_QSPI /* QuadSPI module clock enable */ @@ -243,7 +243,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -262,7 +262,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L4_TIM2 /* TIM2 clock enable */ @@ -354,8 +354,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_USBFSEN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -387,11 +387,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L4_LPUART1 /* Low power uart clock enable */ @@ -417,7 +417,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -436,7 +436,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) /* System configuration controller, comparators, and voltage reference @@ -500,7 +500,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -520,9 +520,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -541,16 +541,16 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) @@ -572,20 +572,20 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C4 - regval = getreg32(STM32L4_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; regval |= RCC_CCIPR2_I2C4SEL_HSI; - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -606,12 +606,12 @@ static void stm32l4_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -619,7 +619,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -628,17 +628,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -649,10 +649,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -660,7 +660,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -668,12 +668,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -681,7 +681,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -690,7 +690,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -705,122 +705,122 @@ static void stm32l4_stdclockconfig(void) #if 0 /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. */ - regval = getreg32(STM32L4_PWR_CR); + regval = getreg32(STM32_PWR_CR); regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32L4_PWR_CR); + putreg32(regval, STM32_PWR_CR); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32L4_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -828,31 +828,31 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -867,18 +867,18 @@ static void stm32l4_stdclockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -889,7 +889,7 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -914,14 +914,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -939,10 +939,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index b6c1903edd909..0c90408ee344e 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -74,33 +74,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -119,7 +119,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L4_DMA1 /* DMA 1 clock enable */ @@ -145,7 +145,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -164,31 +164,31 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); @@ -212,7 +212,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -231,7 +231,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L4_FSMC /* Flexible static memory controller module clock enable */ @@ -245,7 +245,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -264,7 +264,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L4_TIM2 /* TIM2 clock enable */ @@ -386,11 +386,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L4_LPUART1 /* Low power uart clock enable */ @@ -410,7 +410,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -429,7 +429,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) /* System configuration controller, comparators, and voltage reference @@ -511,7 +511,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -531,9 +531,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -552,16 +552,16 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) @@ -577,7 +577,7 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); } /**************************************************************************** @@ -596,12 +596,12 @@ static void stm32l4_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -609,7 +609,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -618,17 +618,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -639,10 +639,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -650,7 +650,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -658,12 +658,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -671,7 +671,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -680,7 +680,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -695,122 +695,122 @@ static void stm32l4_stdclockconfig(void) #if 0 /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. */ - regval = getreg32(STM32L4_PWR_CR); + regval = getreg32(STM32_PWR_CR); regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32L4_PWR_CR); + putreg32(regval, STM32_PWR_CR); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32L4_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -818,31 +818,31 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -857,18 +857,18 @@ static void stm32l4_stdclockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -879,7 +879,7 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -904,14 +904,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index 355b3929c1ddc..61ba84d2491dd 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -48,7 +48,7 @@ ****************************************************************************/ #define DMA1_NCHANNELS 7 -#if STM32L4_NDMA > 1 +#if STM32_NDMA > 1 # define DMA2_NCHANNELS 7 # define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS) #else @@ -86,88 +86,88 @@ static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = { { .chan = 0, - .irq = STM32L4_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, - .irq = STM32L4_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, - .irq = STM32L4_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, - .irq = STM32L4_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, - .irq = STM32L4_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .chan = 5, - .irq = STM32L4_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .chan = 6, - .irq = STM32L4_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, -#if STM32L4_NDMA > 1 +#if STM32_NDMA > 1 { .chan = 0, - .irq = STM32L4_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, - .irq = STM32L4_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, - .irq = STM32L4_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, - .irq = STM32L4_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, - .irq = STM32L4_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .chan = 5, - .irq = STM32L4_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .chan = 6, - .irq = STM32L4_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -226,17 +226,17 @@ static void stm32l4_dmachandisable(struct stm32l4_dma_s *dmach) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmach->chan)); } @@ -256,19 +256,19 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Get the channel structure from the interrupt number */ - if (irq >= STM32L4_IRQ_DMA1CH1 && irq <= STM32L4_IRQ_DMA1CH7) + if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - chndx = irq - STM32L4_IRQ_DMA1CH1; + chndx = irq - STM32_IRQ_DMA1CH1; } else -#if STM32L4_NDMA > 1 - if (irq >= STM32L4_IRQ_DMA2CH1 && irq <= STM32L4_IRQ_DMA2CH5) +#if STM32_NDMA > 1 + if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - chndx = irq - STM32L4_IRQ_DMA2CH1 + DMA1_NCHANNELS; + chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS; } - else if (irq >= STM32L4_IRQ_DMA2CH6 && irq <= STM32L4_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - chndx = irq - STM32L4_IRQ_DMA2CH6 + DMA1_NCHANNELS + 5; + chndx = irq - STM32_IRQ_DMA2CH6 + DMA1_NCHANNELS + 5; } #endif else @@ -280,7 +280,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan); /* Invoke the callback */ @@ -293,7 +293,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -457,28 +457,28 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * disabled. */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -486,7 +486,7 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * interrupt after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -494,14 +494,14 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* define peripheral indicated in dmach->function */ - regval = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET); + regval = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); regval &= ~(0x0f << (dmach->chan << 2)); regval |= (dmach->function << (dmach->chan << 2)); - dmabase_putreg(dmach, STM32L4_DMA_CSELR_OFFSET, regval); + dmabase_putreg(dmach, STM32_DMA_CSELR_OFFSET, regval); } /**************************************************************************** @@ -534,7 +534,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -567,7 +567,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** @@ -604,7 +604,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) { struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; - return dmachan_getreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** @@ -667,22 +667,22 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) /* Verify that the transfer is to a memory region that supports DMA. */ - if ((maddr & STM32L4_REGION_MASK) != (mend & STM32L4_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32L4_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32L4_PERIPH_BASE: - case STM32L4_FSMC_BASE: - case STM32L4_FSMC_BANK1: - case STM32L4_FSMC_BANK2: - case STM32L4_FSMC_BANK3: - case STM32L4_FSMC_BANK4: - case STM32L4_SRAM_BASE: - case STM32L4_SRAM2_BASE: - case STM32L4_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_FSMC_BANK4: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ @@ -715,12 +715,12 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) irqstate_t flags; flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET); - regs->cselr = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET); - regs->ccr = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmach, STM32L4_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmach, STM32L4_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET); + regs->cselr = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); + regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET); leave_critical_section(flags); } #endif @@ -745,16 +745,16 @@ void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, dmainfo("DMA Registers: %s\n", msg); dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr); + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CSELR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_CSELR_OFFSET, regs->cselr); + dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr); + dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar); + dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CMAR_OFFSET, regs->cmar); + dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 1673c9a2abd16..c89579c15ac7f 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,7 +128,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L4_DMA1 /* DMA 1 clock enable */ @@ -160,7 +160,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DMA2DEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -179,34 +179,34 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32L4_NPORTS > 8 +#if STM32_NPORTS > 8 | RCC_AHB2ENR_GPIOIEN #endif ); @@ -248,7 +248,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -267,7 +267,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L4_FSMC /* Flexible static memory controller module clock enable */ @@ -281,7 +281,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -300,7 +300,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L4_TIM2 /* TIM2 clock enable */ @@ -410,8 +410,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_CAN2EN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -443,11 +443,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L4_LPUART1 /* Low power uart clock enable */ @@ -473,7 +473,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -492,7 +492,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) /* System configuration controller, comparators, and voltage reference @@ -574,7 +574,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -594,9 +594,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -615,16 +615,16 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) @@ -640,20 +640,20 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C4 - regval = getreg32(STM32L4_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; regval |= RCC_CCIPR2_I2C4SEL_HSI; - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -689,23 +689,23 @@ static void stm32l4_stdclockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Wait until the requested number of wait states is set */ - while ((getreg32(STM32L4_FLASH_ACR) & FLASH_ACR_LATENCY_MASK) != + while ((getreg32(STM32_FLASH_ACR) & FLASH_ACR_LATENCY_MASK) != FLASH_ACR_LATENCY_4) { } /* Proceed to clock configuration */ -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -713,7 +713,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -722,17 +722,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -743,18 +743,18 @@ static void stm32l4_stdclockconfig(void) /* Choose MSI frequency */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSIRGSEL); - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSIRGSEL); + putreg32(regval, STM32_RCC_CR); if (!(regval & RCC_CR_MSION)) { /* Enable MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -762,7 +762,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -771,12 +771,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -784,7 +784,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -793,7 +793,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -804,7 +804,7 @@ static void stm32l4_stdclockconfig(void) if (timeout > 0) { - if (STM32L4_SYSCLK_FREQUENCY > 24000000ul) + if (STM32_SYSCLK_FREQUENCY > 24000000ul) { /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. @@ -828,75 +828,75 @@ static void stm32l4_stdclockconfig(void) /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); -#ifndef STM32L4_BOARD_NOPLL +#ifndef STM32_BOARD_NOPLL /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif /* Use the main PLL as SYSCLK, so enable it first */ - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #endif @@ -904,34 +904,34 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -939,60 +939,60 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif /* Select the system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; -#ifndef STM32L4_BOARD_NOPLL +#ifndef STM32_BOARD_NOPLL regval |= RCC_CFGR_SW_PLL; -#elif STM32L4_BOARD_USEMSI +#elif STM32_BOARD_USEMSI regval |= RCC_CFGR_SW_MSI; -#elif STM32L4_BOARD_USEHSI +#elif STM32_BOARD_USEHSI regval |= RCC_CFGR_SW_HSI; -#elif STM32L4_BOARD_USEHSE +#elif STM32_BOARD_USEHSE regval |= RCC_CFGR_SW_HSE; #endif - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != -#ifndef STM32L4_BOARD_NOPLL + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != +#ifndef STM32_BOARD_NOPLL RCC_CFGR_SWS_PLL -#elif STM32L4_BOARD_USEMSI +#elif STM32_BOARD_USEMSI RCC_CFGR_SWS_MSI -#elif STM32L4_BOARD_USEHSI +#elif STM32_BOARD_USEHSI RCC_CFGR_SWS_HSI -#elif STM32L4_BOARD_USEHSE +#elif STM32_BOARD_USEHSE RCC_CFGR_SWS_HSE #endif ) @@ -1005,15 +1005,15 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Enable wake-up to HSI from Stop modes */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval |= RCC_CFGR_STOPWUCK_HSI; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -1038,14 +1038,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -1063,10 +1063,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c index 38ecf403e11ac..056a18024d38b 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c @@ -260,7 +260,7 @@ static const struct stm32l4_dmamux_s g_dmamux[DMAMUX_NUM] = { .id = 1, .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ - .base = STM32L4_DMAMUX1_BASE + .base = STM32_DMAMUX1_BASE } }; @@ -271,7 +271,7 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* 0 - DMA1 */ { - .base = STM32L4_DMA1_BASE, + .base = STM32_DMA1_BASE, .first = DMA1_FIRST, .nchan = DMA1_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ @@ -281,7 +281,7 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* 1 - DMA2 */ { - .base = STM32L4_DMA2_BASE, + .base = STM32_DMA2_BASE, .first = DMA2_FIRST, .nchan = DMA2_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ @@ -299,57 +299,57 @@ static struct stm32l4_dmach_s g_dmach[DMA_NCHANNELS] = { .ctrl = DMA1, .chan = 0, - .irq = STM32L4_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA1, .chan = 1, - .irq = STM32L4_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA1, .chan = 2, - .irq = STM32L4_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA1, .chan = 3, - .irq = STM32L4_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA1, .chan = 4, - .irq = STM32L4_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA1, .chan = 5, - .irq = STM32L4_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA1, .chan = 6, - .irq = STM32L4_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #endif @@ -359,57 +359,57 @@ static struct stm32l4_dmach_s g_dmach[DMA_NCHANNELS] = { .ctrl = DMA2, .chan = 0, - .irq = STM32L4_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA2, .chan = 1, - .irq = STM32L4_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA2, .chan = 2, - .irq = STM32L4_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA2, .chan = 3, - .irq = STM32L4_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA2, .chan = 4, - .irq = STM32L4_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA2, .chan = 5, - .irq = STM32L4_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA2, .chan = 6, - .irq = STM32L4_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -589,17 +589,17 @@ static void stm32l4_dma12_disable(DMA_CHANNEL dmachan) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmachan, STM32L4_DMA_IFCR_OFFSET, + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmachan->chan)); } @@ -624,21 +624,21 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) { } #ifdef CONFIG_STM32L4_DMA1 - else if (irq >= STM32L4_IRQ_DMA1CH1 && irq <= STM32L4_IRQ_DMA1CH7) + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - channel = irq - STM32L4_IRQ_DMA1CH1; + channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif #ifdef CONFIG_STM32L4_DMA2 - else if (irq >= STM32L4_IRQ_DMA2CH1 && irq <= STM32L4_IRQ_DMA2CH5) + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - channel = irq - STM32L4_IRQ_DMA2CH1; + channel = irq - STM32_IRQ_DMA2CH1; controller = DMA2; } - else if (irq >= STM32L4_IRQ_DMA2CH6 && irq <= STM32L4_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - channel = irq - STM32L4_IRQ_DMA2CH6 + (6 - 1); + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); controller = DMA2; } #endif @@ -654,7 +654,7 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmachan, STM32L4_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmachan->chan); /* Invoke the callback */ @@ -667,7 +667,7 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmachan, STM32L4_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -704,28 +704,28 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * disabled. */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -733,7 +733,7 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -741,7 +741,7 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); } /**************************************************************************** @@ -769,7 +769,7 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -803,7 +803,7 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** @@ -816,7 +816,7 @@ static size_t stm32l4_dma12_residual(DMA_HANDLE handle) DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - return dmachan_getreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** @@ -831,11 +831,11 @@ void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmachan, STM32L4_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32L4_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32L4_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); stm32l4_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, @@ -864,19 +864,19 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, dmachan->ctrl + 1, msg); dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_ISR_OFFSET, + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CCR_OFFSET, + dmachan->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CNDTR_OFFSET, + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CPAR_OFFSET, + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CMAR_OFFSET, + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); stm32l4_dmamux_dump(g_dma[dmachan->ctrl].dmamux, @@ -895,13 +895,13 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, struct stm32l4_dmaregs_s *regs) { - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32L4_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RGSR_OFFSET); + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); } #endif @@ -915,20 +915,20 @@ static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_CXCR_OFFSET(channel), + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), regs->dmamux.ccr); dmainfo(" CSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); dmainfo(" RG0CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); dmainfo(" RG1CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); dmainfo(" RG2CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); dmainfo(" RG3CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); dmainfo(" RGSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); }; #endif @@ -1186,7 +1186,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, /* DMAMUX Set DMA channel source */ regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); /* Enable DMA channel */ @@ -1231,7 +1231,7 @@ void stm32l4_dmastop(DMA_HANDLE handle) /* DMAMUX Clear DMA channel source */ - dmamux_putreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); } /**************************************************************************** @@ -1322,23 +1322,23 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) mend = maddr + (count << msize_shift) - 1; - if ((maddr & STM32L4_REGION_MASK) != (mend & STM32L4_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32L4_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32L4_PERIPH_BASE: - case STM32L4_FSMC_BASE: - case STM32L4_FSMC_BANK1: - case STM32L4_FSMC_BANK2: - case STM32L4_FSMC_BANK3: - case STM32L4_QSPI_BANK: - case STM32L4_SRAM_BASE: - case STM32L4_SRAM2_BASE: - case STM32L4_SRAM3_BASE: - case STM32L4_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_QSPI_BANK: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_SRAM3_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index 0add98c900356..607f2e9cc1b15 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,7 +128,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L4_DMAMUX1 /* DMAMUX 1 clock enable */ @@ -166,7 +166,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DMA2DEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -185,34 +185,34 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32L4_NPORTS > 8 +#if STM32_NPORTS > 8 | RCC_AHB2ENR_GPIOIEN #endif ); @@ -260,7 +260,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_SDMMC1EN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -279,7 +279,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L4_FSMC /* Flexible static memory controller module clock enable */ @@ -287,7 +287,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FSMCEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -306,7 +306,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L4_TIM2 /* TIM2 clock enable */ @@ -404,8 +404,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -437,11 +437,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L4_LPUART1 /* Low power uart clock enable */ @@ -461,7 +461,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -480,7 +480,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) /* System configuration controller, comparators, and voltage reference @@ -556,7 +556,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -576,9 +576,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -597,16 +597,16 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) @@ -616,13 +616,13 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* Some peripherals have their clock selection in CCIPR2 register. */ - regval = getreg32(STM32L4_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C4 /* Select HSI16 as I2C4 clock source. */ @@ -642,7 +642,7 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR2_DFSDMSEL_PCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); } /**************************************************************************** @@ -661,12 +661,12 @@ static void stm32l4_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -674,7 +674,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -683,17 +683,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { @@ -705,10 +705,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -716,7 +716,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -724,12 +724,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -737,7 +737,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -746,7 +746,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -760,9 +760,9 @@ static void stm32l4_stdclockconfig(void) #warning todo: regulator voltage according to clock freq /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Switch to Range 1 boost mode to support system frequencies up to * 120 MHz. @@ -772,115 +772,115 @@ static void stm32l4_stdclockconfig(void) * Range 2 is not supported. */ -#if STM32L4_SYSCLK_FREQUENCY > 80000000 || \ +#if STM32_SYSCLK_FREQUENCY > 80000000 || \ (defined(BOARD_MAX_PLL_FREQUENCY) && BOARD_MAX_PLL_FREQUENCY > 80000000) - regval = getreg32(STM32L4_PWR_CR5); + regval = getreg32(STM32_PWR_CR5); regval &= ~PWR_CR5_R1MODE; - putreg32(regval, STM32L4_PWR_CR5); + putreg32(regval, STM32_PWR_CR5); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32L4_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -888,31 +888,31 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -932,18 +932,18 @@ static void stm32l4_stdclockconfig(void) #else regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -954,7 +954,7 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -969,14 +969,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -994,10 +994,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l5/chip.h b/arch/arm/src/stm32l5/chip.h index a8a0ea513909d..33c22b102cab3 100644 --- a/arch/arm/src/stm32l5/chip.h +++ b/arch/arm/src/stm32l5/chip.h @@ -48,6 +48,6 @@ * arch/stm32l5/chip.h header file. */ -#define ARMV8M_PERIPHERAL_INTERRUPTS STM32L5_IRQ_NEXTINTS +#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS #endif /* __ARCH_ARM_SRC_STM32L5_CHIP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h index 9f1f886562999..3e2b1449eb8bf 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h @@ -37,89 +37,89 @@ /* Register Offsets *********************************************************/ -#define STM32L5_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L5_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L5_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L5_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L5_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L5_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ -#define STM32L5_RCC_SECCFGR_OFFSET 0x00b8 /* Secure configuration register */ -#define STM32L5_RCC_SECSR_OFFSET 0x00bc /* Secure status register */ -#define STM32L5_RCC_AHB1SECSR_OFFSET 0x00e8 /* AHB1 security status register */ -#define STM32L5_RCC_AHB2SECSR_OFFSET 0x00ec /* AHB2 security status register */ -#define STM32L5_RCC_AHB3SECSR_OFFSET 0x00f0 /* AHB3 security status register */ -#define STM32L5_RCC_APB1SECSR1_OFFSET 0x00f8 /* APB1 security status register 1 */ -#define STM32L5_RCC_APB1SECSR2_OFFSET 0x00fc /* APB1 security status register 2 */ -#define STM32L5_RCC_APB2SECSR_OFFSET 0x0100 /* APB2 security status register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_SECCFGR_OFFSET 0x00b8 /* Secure configuration register */ +#define STM32_RCC_SECSR_OFFSET 0x00bc /* Secure status register */ +#define STM32_RCC_AHB1SECSR_OFFSET 0x00e8 /* AHB1 security status register */ +#define STM32_RCC_AHB2SECSR_OFFSET 0x00ec /* AHB2 security status register */ +#define STM32_RCC_AHB3SECSR_OFFSET 0x00f0 /* AHB3 security status register */ +#define STM32_RCC_APB1SECSR1_OFFSET 0x00f8 /* APB1 security status register 1 */ +#define STM32_RCC_APB1SECSR2_OFFSET 0x00fc /* APB1 security status register 2 */ +#define STM32_RCC_APB2SECSR_OFFSET 0x0100 /* APB2 security status register */ /* Register Addresses *******************************************************/ -#define STM32L5_RCC_CR (STM32L5_RCC_BASE + STM32L5_RCC_CR_OFFSET) -#define STM32L5_RCC_ICSCR (STM32L5_RCC_BASE + STM32L5_RCC_ICSCR_OFFSET) -#define STM32L5_RCC_CFGR (STM32L5_RCC_BASE + STM32L5_RCC_CFGR_OFFSET) -#define STM32L5_RCC_PLLCFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLCFG_OFFSET) -#define STM32L5_RCC_PLLSAI1CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI1CFG_OFFSET) -#define STM32L5_RCC_PLLSAI2CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI2CFG_OFFSET) -#define STM32L5_RCC_CIER (STM32L5_RCC_BASE + STM32L5_RCC_CIER_OFFSET) -#define STM32L5_RCC_CIFR (STM32L5_RCC_BASE + STM32L5_RCC_CIFR_OFFSET) -#define STM32L5_RCC_CICR (STM32L5_RCC_BASE + STM32L5_RCC_CICR_OFFSET) -#define STM32L5_RCC_AHB1RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1RSTR_OFFSET) -#define STM32L5_RCC_AHB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2RSTR_OFFSET) -#define STM32L5_RCC_AHB3RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3RSTR_OFFSET) -#define STM32L5_RCC_APB1RSTR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR1_OFFSET) -#define STM32L5_RCC_APB1RSTR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR2_OFFSET) -#define STM32L5_RCC_APB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_APB2RSTR_OFFSET) -#define STM32L5_RCC_AHB1ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1ENR_OFFSET) -#define STM32L5_RCC_AHB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2ENR_OFFSET) -#define STM32L5_RCC_AHB3ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3ENR_OFFSET) -#define STM32L5_RCC_APB1ENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR1_OFFSET) -#define STM32L5_RCC_APB1ENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR2_OFFSET) -#define STM32L5_RCC_APB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2ENR_OFFSET) -#define STM32L5_RCC_AHB1SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SMENR_OFFSET) -#define STM32L5_RCC_AHB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SMENR_OFFSET) -#define STM32L5_RCC_AHB3SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SMENR_OFFSET) -#define STM32L5_RCC_APB1SMENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR1_OFFSET) -#define STM32L5_RCC_APB1SMENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR2_OFFSET) -#define STM32L5_RCC_APB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SMENR_OFFSET) -#define STM32L5_RCC_CCIPR (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR_OFFSET) -#define STM32L5_RCC_BDCR (STM32L5_RCC_BASE + STM32L5_RCC_BDCR_OFFSET) -#define STM32L5_RCC_CSR (STM32L5_RCC_BASE + STM32L5_RCC_CSR_OFFSET) -#define STM32L5_RCC_CRRCR (STM32L5_RCC_BASE + STM32L5_RCC_CRRCR_OFFSET) -#define STM32L5_RCC_CCIPR2 (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR2_OFFSET) -#define STM32L5_RCC_SECCFGR (STM32L5_RCC_BASE + STM32L5_RCC_SECCFGR_OFFSET) -#define STM32L5_RCC_SECSR (STM32L5_RCC_BASE + STM32L5_RCC_SECSR_OFFSET) -#define STM32L5_RCC_AHB1SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SECSR_OFFSET) -#define STM32L5_RCC_AHB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SECSR_OFFSET) -#define STM32L5_RCC_AHB3SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SECSR_OFFSET) -#define STM32L5_RCC_APB1SECSR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR1_OFFSET) -#define STM32L5_RCC_APB1SECSR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR2_OFFSET) -#define STM32L5_RCC_APB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SECSR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET) +#define STM32_RCC_SECCFGR (STM32_RCC_BASE + STM32_RCC_SECCFGR_OFFSET) +#define STM32_RCC_SECSR (STM32_RCC_BASE + STM32_RCC_SECSR_OFFSET) +#define STM32_RCC_AHB1SECSR (STM32_RCC_BASE + STM32_RCC_AHB1SECSR_OFFSET) +#define STM32_RCC_AHB2SECSR (STM32_RCC_BASE + STM32_RCC_AHB2SECSR_OFFSET) +#define STM32_RCC_AHB3SECSR (STM32_RCC_BASE + STM32_RCC_AHB3SECSR_OFFSET) +#define STM32_RCC_APB1SECSR1 (STM32_RCC_BASE + STM32_RCC_APB1SECSR1_OFFSET) +#define STM32_RCC_APB1SECSR2 (STM32_RCC_BASE + STM32_RCC_APB1SECSR2_OFFSET) +#define STM32_RCC_APB2SECSR (STM32_RCC_BASE + STM32_RCC_APB2SECSR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h index db365f949741f..fd82d211a5858 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h @@ -38,31 +38,31 @@ /* Register Offsets *********************************************************/ -#define STM32L5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32L5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32L5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32L5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32L5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32L5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32L5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32L5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32L5_SYSCFG_SECCFGR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SECCFGR_OFFSET) -#define STM32L5_SYSCFG_CFGR1 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR1_OFFSET) -#define STM32L5_SYSCFG_FPUIMR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_FPUIMR_OFFSET) -#define STM32L5_SYSCFG_CNSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CNSLCKR_OFFSET) -#define STM32L5_SYSCFG_CSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CSLCKR_OFFSET) -#define STM32L5_SYSCFG_CFGR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR2_OFFSET) -#define STM32L5_SYSCFG_SCSR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SCSR_OFFSET) -#define STM32L5_SYSCFG_SKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SKR_OFFSET) -#define STM32L5_SYSCFG_SWPR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR_OFFSET) -#define STM32L5_SYSCFG_SWPR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR2_OFFSET) -#define STM32L5_SYSCFG_RSSCMDR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h b/arch/arm/src/stm32l5/hardware/stm32l5_exti.h index b321ad3f4cc7f..11b113e55e55f 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_exti.h @@ -36,55 +36,55 @@ /* Register Offsets *********************************************************/ -#define STM32L5_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ -#define STM32L5_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ -#define STM32L5_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ -#define STM32L5_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ -#define STM32L5_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ -#define STM32L5_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ -#define STM32L5_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ -#define STM32L5_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ -#define STM32L5_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ -#define STM32L5_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ -#define STM32L5_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ -#define STM32L5_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ -#define STM32L5_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ -#define STM32L5_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ -#define STM32L5_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ -#define STM32L5_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */ -#define STM32L5_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */ -#define STM32L5_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */ -#define STM32L5_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ -#define STM32L5_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ -#define STM32L5_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ -#define STM32L5_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ -#define STM32L5_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ +#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ +#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ +#define STM32_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ +#define STM32_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ +#define STM32_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ +#define STM32_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ +#define STM32_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ +#define STM32_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ +#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ +#define STM32_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */ +#define STM32_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */ +#define STM32_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */ +#define STM32_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ +#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ +#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ +#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ +#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ /* Register Addresses *******************************************************/ -#define STM32L5_EXTI_RTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR1_OFFSET) -#define STM32L5_EXTI_FTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR1_OFFSET) -#define STM32L5_EXTI_SWIER1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER1_OFFSET) -#define STM32L5_EXTI_RPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR1_OFFSET) -#define STM32L5_EXTI_FPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR1_OFFSET) -#define STM32L5_EXTI_SECCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR1_OFFSET) -#define STM32L5_EXTI_PRIVCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR1_OFFSET) -#define STM32L5_EXTI_RTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR2_OFFSET) -#define STM32L5_EXTI_FTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR2_OFFSET) -#define STM32L5_EXTI_SWIER2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER2_OFFSET) -#define STM32L5_EXTI_RPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR2_OFFSET) -#define STM32L5_EXTI_FPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR2_OFFSET) -#define STM32L5_EXTI_SECCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR2_OFFSET) -#define STM32L5_EXTI_PRIVCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR2_OFFSET) -#define STM32L5_EXTI_EXTICR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR1_OFFSET) -#define STM32L5_EXTI_EXTICR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR2_OFFSET) -#define STM32L5_EXTI_EXTICR3 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR3_OFFSET) -#define STM32L5_EXTI_EXTICR4 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR4_OFFSET) -#define STM32L5_EXTI_LOCKR (STM32L5_EXTI_BASE + STM32L5_EXTI_LOCKR_OFFSET) -#define STM32L5_EXTI_IMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR1_OFFSET) -#define STM32L5_EXTI_EMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR1_OFFSET) -#define STM32L5_EXTI_IMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR2_OFFSET) -#define STM32L5_EXTI_EMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_RPR1 (STM32_EXTI_BASE + STM32_EXTI_RPR1_OFFSET) +#define STM32_EXTI_FPR1 (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET) +#define STM32_EXTI_SECCFGR1 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR1_OFFSET) +#define STM32_EXTI_PRIVCFGR1 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_RPR2 (STM32_EXTI_BASE + STM32_EXTI_RPR2_OFFSET) +#define STM32_EXTI_FPR2 (STM32_EXTI_BASE + STM32_EXTI_FPR2_OFFSET) +#define STM32_EXTI_SECCFGR2 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR2_OFFSET) +#define STM32_EXTI_PRIVCFGR2 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR2_OFFSET) +#define STM32_EXTI_EXTICR1 (STM32_EXTI_BASE + STM32_EXTI_EXTICR1_OFFSET) +#define STM32_EXTI_EXTICR2 (STM32_EXTI_BASE + STM32_EXTI_EXTICR2_OFFSET) +#define STM32_EXTI_EXTICR3 (STM32_EXTI_BASE + STM32_EXTI_EXTICR3_OFFSET) +#define STM32_EXTI_EXTICR4 (STM32_EXTI_BASE + STM32_EXTI_EXTICR4_OFFSET) +#define STM32_EXTI_LOCKR (STM32_EXTI_BASE + STM32_EXTI_LOCKR_OFFSET) +#define STM32_EXTI_IMR1 (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET) +#define STM32_EXTI_EMR1 (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET) +#define STM32_EXTI_IMR2 (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET) +#define STM32_EXTI_EMR2 (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h index 3f9c343e0e7f7..4020e6807819a 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h @@ -70,90 +70,90 @@ /* Define the valid configuration */ #if defined(CONFIG_STM32L5_FLASH_CONFIG_C) /* 256 kB */ -# define STM32L5_FLASH_NPAGES 64 -# define STM32L5_FLASH_PAGESIZE 4096 +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 4096 #elif defined(CONFIG_STM32L5_FLASH_CONFIG_E) /* 512 kB */ -# define STM32L5_FLASH_NPAGES 128 -# define STM32L5_FLASH_PAGESIZE 4096 +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 4096 #else # error "unknown flash configuration!" #endif -#ifdef STM32L5_FLASH_PAGESIZE -# define STM32L5_FLASH_SIZE (STM32L5_FLASH_NPAGES * STM32L5_FLASH_PAGESIZE) +#ifdef STM32_FLASH_PAGESIZE +# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif /* Register Offsets *********************************************************/ -#define STM32L5_FLASH_ACR_OFFSET 0x0000 -#define STM32L5_FLASH_PDKEYR_OFFSET 0x0004 -#define STM32L5_FLASH_NSKEYR_OFFSET 0x0008 -#define STM32L5_FLASH_SECKEYR_OFFSET 0x000c -#define STM32L5_FLASH_OPTKEYR_OFFSET 0x0010 -#define STM32L5_FLASH_LVEKEYR_OFFSET 0x0014 -#define STM32L5_FLASH_NSSR_OFFSET 0x0020 -#define STM32L5_FLASH_SECSR_OFFSET 0x0024 -#define STM32L5_FLASH_NSCR_OFFSET 0x0028 -#define STM32L5_FLASH_SECCR_OFFSET 0x002c -#define STM32L5_FLASH_ECCR_OFFSET 0x0030 -#define STM32L5_FLASH_OPTR_OFFSET 0x0040 -#define STM32L5_FLASH_NSBOOTADDR0R_OFFSET 0x0044 -#define STM32L5_FLASH_NSBOOTADDR1R_OFFSET 0x0048 -#define STM32L5_FLASH_SECBOOTADDR0R_OFFSET 0x004c -#define STM32L5_FLASH_SECWM1R1_OFFSET 0x0050 -#define STM32L5_FLASH_SECWM1R2_OFFSET 0x0054 -#define STM32L5_FLASH_WRP1AR_OFFSET 0x0058 -#define STM32L5_FLASH_WRP1BR_OFFSET 0x005c -#define STM32L5_FLASH_SECWM2R1_OFFSET 0x0060 -#define STM32L5_FLASH_SECWM2R2_OFFSET 0x0064 -#define STM32L5_FLASH_WRP2AR_OFFSET 0x0068 -#define STM32L5_FLASH_WRP2BR_OFFSET 0x006c -#define STM32L5_FLASH_SECBB1R1_OFFSET 0x0080 -#define STM32L5_FLASH_SECBB1R2_OFFSET 0x0084 -#define STM32L5_FLASH_SECBB1R3_OFFSET 0x0088 -#define STM32L5_FLASH_SECBB1R4_OFFSET 0x008c -#define STM32L5_FLASH_SECBB2R1_OFFSET 0x00a0 -#define STM32L5_FLASH_SECBB2R2_OFFSET 0x00a4 -#define STM32L5_FLASH_SECBB2R3_OFFSET 0x00a8 -#define STM32L5_FLASH_SECBB2R4_OFFSET 0x00ac -#define STM32L5_FLASH_SECHDPCR_OFFSET 0x00c0 -#define STM32L5_FLASH_PRIVCFGR_OFFSET 0x00c4 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_PDKEYR_OFFSET 0x0004 +#define STM32_FLASH_NSKEYR_OFFSET 0x0008 +#define STM32_FLASH_SECKEYR_OFFSET 0x000c +#define STM32_FLASH_OPTKEYR_OFFSET 0x0010 +#define STM32_FLASH_LVEKEYR_OFFSET 0x0014 +#define STM32_FLASH_NSSR_OFFSET 0x0020 +#define STM32_FLASH_SECSR_OFFSET 0x0024 +#define STM32_FLASH_NSCR_OFFSET 0x0028 +#define STM32_FLASH_SECCR_OFFSET 0x002c +#define STM32_FLASH_ECCR_OFFSET 0x0030 +#define STM32_FLASH_OPTR_OFFSET 0x0040 +#define STM32_FLASH_NSBOOTADDR0R_OFFSET 0x0044 +#define STM32_FLASH_NSBOOTADDR1R_OFFSET 0x0048 +#define STM32_FLASH_SECBOOTADDR0R_OFFSET 0x004c +#define STM32_FLASH_SECWM1R1_OFFSET 0x0050 +#define STM32_FLASH_SECWM1R2_OFFSET 0x0054 +#define STM32_FLASH_WRP1AR_OFFSET 0x0058 +#define STM32_FLASH_WRP1BR_OFFSET 0x005c +#define STM32_FLASH_SECWM2R1_OFFSET 0x0060 +#define STM32_FLASH_SECWM2R2_OFFSET 0x0064 +#define STM32_FLASH_WRP2AR_OFFSET 0x0068 +#define STM32_FLASH_WRP2BR_OFFSET 0x006c +#define STM32_FLASH_SECBB1R1_OFFSET 0x0080 +#define STM32_FLASH_SECBB1R2_OFFSET 0x0084 +#define STM32_FLASH_SECBB1R3_OFFSET 0x0088 +#define STM32_FLASH_SECBB1R4_OFFSET 0x008c +#define STM32_FLASH_SECBB2R1_OFFSET 0x00a0 +#define STM32_FLASH_SECBB2R2_OFFSET 0x00a4 +#define STM32_FLASH_SECBB2R3_OFFSET 0x00a8 +#define STM32_FLASH_SECBB2R4_OFFSET 0x00ac +#define STM32_FLASH_SECHDPCR_OFFSET 0x00c0 +#define STM32_FLASH_PRIVCFGR_OFFSET 0x00c4 /* Register Addresses *******************************************************/ -#define STM32L5_FLASH_ACR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ACR_OFFSET) -#define STM32L5_FLASH_PDKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PDKEYR_OFFSET) -#define STM32L5_FLASH_NSKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSKEYR_OFFSET) -#define STM32L5_FLASH_SECKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECKEYR_OFFSET) -#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTKEYR_OFFSET) -#define STM32L5_FLASH_LVEKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_LVEKEYR_OFFSET) -#define STM32L5_FLASH_NSSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSSR_OFFSET) -#define STM32L5_FLASH_SECSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECSR_OFFSET) -#define STM32L5_FLASH_NSCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSCR_OFFSET) -#define STM32L5_FLASH_SECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECCR_OFFSET) -#define STM32L5_FLASH_ECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ECCR_OFFSET) -#define STM32L5_FLASH_OPTR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTR_OFFSET) -#define STM32L5_FLASH_NSBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR0R_OFFSET) -#define STM32L5_FLASH_NSBOOTADDR1R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR1R_OFFSET) -#define STM32L5_FLASH_SECBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBOOTADDR0R_OFFSET) -#define STM32L5_FLASH_SECWM1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R1_OFFSET) -#define STM32L5_FLASH_SECWM1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R2_OFFSET) -#define STM32L5_FLASH_WRP1AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1AR_OFFSET) -#define STM32L5_FLASH_WRP1BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1BR_OFFSET) -#define STM32L5_FLASH_SECWM2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R1_OFFSET) -#define STM32L5_FLASH_SECWM2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R2_OFFSET) -#define STM32L5_FLASH_WRP2AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2AR_OFFSET) -#define STM32L5_FLASH_WRP2BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2BR_OFFSET) -#define STM32L5_FLASH_SECBB1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R1_OFFSET) -#define STM32L5_FLASH_SECBB1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R2_OFFSET) -#define STM32L5_FLASH_SECBB1R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R3_OFFSET) -#define STM32L5_FLASH_SECBB1R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R4_OFFSET) -#define STM32L5_FLASH_SECBB2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R1_OFFSET) -#define STM32L5_FLASH_SECBB2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R2_OFFSET) -#define STM32L5_FLASH_SECBB2R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R3_OFFSET) -#define STM32L5_FLASH_SECBB2R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R4_OFFSET) -#define STM32L5_FLASH_SECHDPCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECHDPCR_OFFSET) -#define STM32L5_FLASH_PRIVCFGR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PRIVCFGR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE + STM32_FLASH_PDKEYR_OFFSET) +#define STM32_FLASH_NSKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSKEYR_OFFSET) +#define STM32_FLASH_SECKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECKEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_LVEKEYR (STM32_FLASHIF_BASE + STM32_FLASH_LVEKEYR_OFFSET) +#define STM32_FLASH_NSSR (STM32_FLASHIF_BASE + STM32_FLASH_NSSR_OFFSET) +#define STM32_FLASH_SECSR (STM32_FLASHIF_BASE + STM32_FLASH_SECSR_OFFSET) +#define STM32_FLASH_NSCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCR_OFFSET) +#define STM32_FLASH_SECCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE + STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE + STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_NSBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR0R_OFFSET) +#define STM32_FLASH_NSBOOTADDR1R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR1R_OFFSET) +#define STM32_FLASH_SECBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTADDR0R_OFFSET) +#define STM32_FLASH_SECWM1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R1_OFFSET) +#define STM32_FLASH_SECWM1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R2_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_SECWM2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R1_OFFSET) +#define STM32_FLASH_SECWM2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R2_OFFSET) +#define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2AR_OFFSET) +#define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2BR_OFFSET) +#define STM32_FLASH_SECBB1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R1_OFFSET) +#define STM32_FLASH_SECBB1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R2_OFFSET) +#define STM32_FLASH_SECBB1R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R3_OFFSET) +#define STM32_FLASH_SECBB1R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R4_OFFSET) +#define STM32_FLASH_SECBB2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R1_OFFSET) +#define STM32_FLASH_SECBB2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R2_OFFSET) +#define STM32_FLASH_SECBB2R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R3_OFFSET) +#define STM32_FLASH_SECBB2R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R4_OFFSET) +#define STM32_FLASH_SECHDPCR (STM32_FLASHIF_BASE + STM32_FLASH_SECHDPCR_OFFSET) +#define STM32_FLASH_PRIVCFGR (STM32_FLASHIF_BASE + STM32_FLASH_PRIVCFGR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h b/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h index 0037ae1ad08d3..7b4d880bca02a 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h @@ -36,154 +36,154 @@ /* Register Offsets *********************************************************/ -#define STM32L5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32L5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32L5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32L5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32L5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32L5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32L5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32L5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32L5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32L5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32L5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32L5_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ /* Register Addresses *******************************************************/ -#if STM32L5_NPORTS > 0 -# define STM32L5_GPIOA_MODER (STM32L5_GPIOA_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOA_OTYPER (STM32L5_GPIOA_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOA_OSPEED (STM32L5_GPIOA_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOA_PUPDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOA_IDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOA_ODR (STM32L5_GPIOA_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOA_BSRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOA_LCKR (STM32L5_GPIOA_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOA_AFRL (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOA_AFRH (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOA_BRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOA_SECCFGR (STM32L5_GPIOA_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 1 -# define STM32L5_GPIOB_MODER (STM32L5_GPIOB_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOB_OTYPER (STM32L5_GPIOB_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOB_OSPEED (STM32L5_GPIOB_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOB_PUPDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOB_IDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOB_ODR (STM32L5_GPIOB_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOB_BSRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOB_LCKR (STM32L5_GPIOB_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOB_AFRL (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOB_AFRH (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOB_BRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOB_SECCFGR (STM32L5_GPIOB_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 2 -# define STM32L5_GPIOC_MODER (STM32L5_GPIOC_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOC_OTYPER (STM32L5_GPIOC_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOC_OSPEED (STM32L5_GPIOC_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOC_PUPDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOC_IDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOC_ODR (STM32L5_GPIOC_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOC_BSRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOC_LCKR (STM32L5_GPIOC_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOC_AFRL (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOC_AFRH (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOC_BRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOC_SECCFGR (STM32L5_GPIOC_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 3 -# define STM32L5_GPIOD_MODER (STM32L5_GPIOD_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOD_OTYPER (STM32L5_GPIOD_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOD_OSPEED (STM32L5_GPIOD_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOD_PUPDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOD_IDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOD_ODR (STM32L5_GPIOD_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOD_BSRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOD_LCKR (STM32L5_GPIOD_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOD_AFRL (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOD_AFRH (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOD_BRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOD_SECCFGR (STM32L5_GPIOD_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 4 -# define STM32L5_GPIOE_MODER (STM32L5_GPIOE_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOE_OTYPER (STM32L5_GPIOE_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOE_OSPEED (STM32L5_GPIOE_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOE_PUPDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOE_IDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOE_ODR (STM32L5_GPIOE_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOE_BSRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOE_LCKR (STM32L5_GPIOE_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOE_AFRL (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOE_AFRH (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOE_BRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOE_SECCFGR (STM32L5_GPIOE_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 5 -# define STM32L5_GPIOF_MODER (STM32L5_GPIOF_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOF_OTYPER (STM32L5_GPIOF_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOF_OSPEED (STM32L5_GPIOF_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOF_PUPDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOF_IDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOF_ODR (STM32L5_GPIOF_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOF_BSRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOF_LCKR (STM32L5_GPIOF_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOF_AFRL (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOF_AFRH (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOF_BRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOF_SECCFGR (STM32L5_GPIOF_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 6 -# define STM32L5_GPIOG_MODER (STM32L5_GPIOG_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOG_OTYPER (STM32L5_GPIOG_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOG_OSPEED (STM32L5_GPIOG_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOG_PUPDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOG_IDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOG_ODR (STM32L5_GPIOG_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOG_BSRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOG_LCKR (STM32L5_GPIOG_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOG_AFRL (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOG_AFRH (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOG_BRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOG_SECCFGR (STM32L5_GPIOG_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 7 -# define STM32L5_GPIOH_MODER (STM32L5_GPIOH_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOH_OTYPER (STM32L5_GPIOH_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOH_OSPEED (STM32L5_GPIOH_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOH_PUPDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOH_IDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOH_ODR (STM32L5_GPIOH_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOH_BSRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOH_LCKR (STM32L5_GPIOH_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOH_AFRL (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOH_AFRH (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOH_BRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOH_SECCFGR (STM32L5_GPIOH_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 8 -# define STM32L5_GPIOI_MODER (STM32L5_GPIOI_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOI_OTYPER (STM32L5_GPIOI_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOI_OSPEED (STM32L5_GPIOI_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOI_PUPDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOI_IDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOI_ODR (STM32L5_GPIOI_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOI_BSRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOI_LCKR (STM32L5_GPIOI_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOI_AFRL (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOI_AFRH (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOI_BRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOI_SECCFGR (STM32L5_GPIOI_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOI_BRR (STM32_GPIOI_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOI_SECCFGR (STM32_GPIOI_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h b/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h index 4fefb89201fed..b697627f594d9 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h @@ -29,127 +29,127 @@ /* STM32L5XXX Address Blocks ************************************************/ -#define STM32L5_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32L5_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ -#define STM32L5_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ -#define STM32L5_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ -# define STM32L5_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ -#define STM32L5_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ -# define STM32L5_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ -# define STM32L5_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ -#define STM32L5_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ - -#define STM32L5_REGION_MASK 0xF0000000 -#define STM32L5_IS_SRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_SRAM_BASE) -#define STM32L5_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_FMC_BANK1) +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ +# define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ +#define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xF0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) /* Code Base Addresses ******************************************************/ -#define STM32L5_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ -#define STM32L5_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */ -#define STM32L5_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ -#define STM32L5_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */ +#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ +#define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ /* System Memory Addresses **************************************************/ -#define STM32L5_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */ -#define STM32L5_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */ -#define STM32L5_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */ +#define STM32_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */ +#define STM32_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */ /* Peripheral Base Addresses ************************************************/ -#define STM32L5_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */ -#define STM32L5_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */ -#define STM32L5_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */ -#define STM32L5_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */ -#define STM32L5_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */ +#define STM32_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */ +#define STM32_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */ /* APB1 Base Addresses ******************************************************/ -#define STM32L5_UCPD1_BASE 0x4000DC00 -#define STM32L5_USB_SRAM_BASE 0x4000D800 -#define STM32L5_USB_FS_BASE 0x4000D400 -#define STM32L5_FDCAN_RAM_BASE 0x4000AC00 -#define STM32L5_FDCAN1_BASE 0x4000A400 -#define STM32L5_LPTIM3_BASE 0x40009800 -#define STM32L5_LPTIM2_BASE 0x40009400 -#define STM32L5_I2C4_BASE 0x40008400 -#define STM32L5_LPUART1_BASE 0x40008000 -#define STM32L5_LPTIM1_BASE 0x40007C00 -#define STM32L5_OPAMP_BASE 0x40007800 -#define STM32L5_DAC_BASE 0x40007400 -#define STM32L5_PWR_BASE 0x40007000 -#define STM32L5_CRS_BASE 0x40006000 -#define STM32L5_I2C3_BASE 0x40005C00 -#define STM32L5_I2C2_BASE 0x40005800 -#define STM32L5_I2C1_BASE 0x40005400 -#define STM32L5_UART5_BASE 0x40005000 -#define STM32L5_UART4_BASE 0x40004C00 -#define STM32L5_USART3_BASE 0x40004800 -#define STM32L5_USART2_BASE 0x40004400 -#define STM32L5_SPI3_BASE 0x40003C00 -#define STM32L5_SPI2_BASE 0x40003800 -#define STM32L5_TAMP_BASE 0x40003400 -#define STM32L5_IWDG_BASE 0x40003000 -#define STM32L5_WWDG_BASE 0x40002C00 -#define STM32L5_RTC_BASE 0x40002800 -#define STM32L5_TIM7_BASE 0x40001400 -#define STM32L5_TIM6_BASE 0x40001000 -#define STM32L5_TIM5_BASE 0x40000C00 -#define STM32L5_TIM4_BASE 0x40000800 -#define STM32L5_TIM3_BASE 0x40000400 -#define STM32L5_TIM2_BASE 0x40000000 +#define STM32_UCPD1_BASE 0x4000DC00 +#define STM32_USB_SRAM_BASE 0x4000D800 +#define STM32_USB_FS_BASE 0x4000D400 +#define STM32_FDCAN_RAM_BASE 0x4000AC00 +#define STM32_FDCAN1_BASE 0x4000A400 +#define STM32_LPTIM3_BASE 0x40009800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_I2C4_BASE 0x40008400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007C00 +#define STM32_OPAMP_BASE 0x40007800 +#define STM32_DAC_BASE 0x40007400 +#define STM32_PWR_BASE 0x40007000 +#define STM32_CRS_BASE 0x40006000 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_UART5_BASE 0x40005000 +#define STM32_UART4_BASE 0x40004C00 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI3_BASE 0x40003C00 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_TAMP_BASE 0x40003400 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002C00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM5_BASE 0x40000C00 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32L5_DFSDM1_BASE 0x40016000 -#define STM32L5_SAI2_BASE 0x40015800 -#define STM32L5_SAI1_BASE 0x40015400 -#define STM32L5_TIM17_BASE 0x40014800 -#define STM32L5_TIM16_BASE 0x40014400 -#define STM32L5_TIM15_BASE 0x40014000 -#define STM32L5_USART1_BASE 0x40013800 -#define STM32L5_TIM8_BASE 0x40013400 -#define STM32L5_SPI1_BASE 0x40013000 -#define STM32L5_TIM1_BASE 0x40012C00 -#define STM32L5_COMP_BASE 0x40010200 -#define STM32L5_VREFBUF_BASE 0x40010100 -#define STM32L5_SYSCFG_BASE 0x40010000 +#define STM32_DFSDM1_BASE 0x40016000 +#define STM32_SAI2_BASE 0x40015800 +#define STM32_SAI1_BASE 0x40015400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM8_BASE 0x40013400 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012C00 +#define STM32_COMP_BASE 0x40010200 +#define STM32_VREFBUF_BASE 0x40010100 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32L5_GTZC_BASE 0x40032400 -#define STM32L5_ICACHE_BASE 0x40030400 -#define STM32L5_EXTI_BASE 0x4002F400 -#define STM32L5_TSC_BASE 0x40024000 -#define STM32L5_CRC_BASE 0x40023000 -#define STM32L5_FLASHIF_BASE 0x40022000 -#define STM32L5_RCC_BASE 0x40021000 -#define STM32L5_DMAMUX1_BASE 0x40020800 -#define STM32L5_DMA2_BASE 0x40020400 -#define STM32L5_DMA1_BASE 0x40020000 +#define STM32_GTZC_BASE 0x40032400 +#define STM32_ICACHE_BASE 0x40030400 +#define STM32_EXTI_BASE 0x4002F400 +#define STM32_TSC_BASE 0x40024000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_FLASHIF_BASE 0x40022000 +#define STM32_RCC_BASE 0x40021000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32L5_SDMMC1_BASE 0x420C8000 -#define STM32L5_OTFDEC1_BASE 0x420C5000 -#define STM32L5_PKA_BASE 0x420C2000 -#define STM32L5_RNG_BASE 0x420C0800 -#define STM32L5_HASH_BASE 0x420C0400 -#define STM32L5_AES_BASE 0x420C0000 -#define STM32L5_ADC_BASE 0x42028000 -#define STM32L5_GPIOH_BASE 0x42021C00 -#define STM32L5_GPIOG_BASE 0x42021800 -#define STM32L5_GPIOF_BASE 0x42021400 -#define STM32L5_GPIOE_BASE 0x42021000 -#define STM32L5_GPIOD_BASE 0x42020c00 -#define STM32L5_GPIOC_BASE 0x42020800 -#define STM32L5_GPIOB_BASE 0x42020400 -#define STM32L5_GPIOA_BASE 0x42020000 +#define STM32_SDMMC1_BASE 0x420C8000 +#define STM32_OTFDEC1_BASE 0x420C5000 +#define STM32_PKA_BASE 0x420C2000 +#define STM32_RNG_BASE 0x420C0800 +#define STM32_HASH_BASE 0x420C0400 +#define STM32_AES_BASE 0x420C0000 +#define STM32_ADC_BASE 0x42028000 +#define STM32_GPIOH_BASE 0x42021C00 +#define STM32_GPIOG_BASE 0x42021800 +#define STM32_GPIOF_BASE 0x42021400 +#define STM32_GPIOE_BASE 0x42021000 +#define STM32_GPIOD_BASE 0x42020c00 +#define STM32_GPIOC_BASE 0x42020800 +#define STM32_GPIOB_BASE 0x42020400 +#define STM32_GPIOA_BASE 0x42020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32L5_OCTOSPI1_BASE 0x44021000 -#define STM32L5_FMC_BASE 0x44020000 +#define STM32_OCTOSPI1_BASE 0x44021000 +#define STM32_FMC_BASE 0x44020000 #endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h index 44cbde1b5985e..9ef6dc03f31f1 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h @@ -36,59 +36,59 @@ /* Register Offsets *********************************************************/ -#define STM32L5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32L5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32L5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32L5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32L5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32L5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32L5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32L5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32L5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32L5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32L5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32L5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32L5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32L5_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32L5_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32L5_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32L5_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ -#define STM32L5_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ -#define STM32L5_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ -#define STM32L5_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ -#define STM32L5_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ -#define STM32L5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32L5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32L5_PWR_SECCFGR_OFFSET 0x0078 /* Power secure configuration register */ -#define STM32L5_PWR_PRIVCFGR_OFFSET 0x0078 /* Power privilege configuration register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ +#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ +#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ +#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_SECCFGR_OFFSET 0x0078 /* Power secure configuration register */ +#define STM32_PWR_PRIVCFGR_OFFSET 0x0078 /* Power privilege configuration register */ /* Register Addresses *******************************************************/ -#define STM32L5_PWR_CR1 (STM32L5_PWR_BASE + STM32L5_PWR_CR1_OFFSET) -#define STM32L5_PWR_CR2 (STM32L5_PWR_BASE + STM32L5_PWR_CR2_OFFSET) -#define STM32L5_PWR_CR3 (STM32L5_PWR_BASE + STM32L5_PWR_CR3_OFFSET) -#define STM32L5_PWR_CR4 (STM32L5_PWR_BASE + STM32L5_PWR_CR4_OFFSET) -#define STM32L5_PWR_SR1 (STM32L5_PWR_BASE + STM32L5_PWR_SR1_OFFSET) -#define STM32L5_PWR_SR2 (STM32L5_PWR_BASE + STM32L5_PWR_SR2_OFFSET) -#define STM32L5_PWR_SCR (STM32L5_PWR_BASE + STM32L5_PWR_SCR_OFFSET) -#define STM32L5_PWR_PUCRA (STM32L5_PWR_BASE + STM32L5_PWR_PUCRA_OFFSET) -#define STM32L5_PWR_PDCRA (STM32L5_PWR_BASE + STM32L5_PWR_PDCRA_OFFSET) -#define STM32L5_PWR_PUCRB (STM32L5_PWR_BASE + STM32L5_PWR_PUCRB_OFFSET) -#define STM32L5_PWR_PDCRB (STM32L5_PWR_BASE + STM32L5_PWR_PDCRB_OFFSET) -#define STM32L5_PWR_PUCRC (STM32L5_PWR_BASE + STM32L5_PWR_PUCRC_OFFSET) -#define STM32L5_PWR_PDCRC (STM32L5_PWR_BASE + STM32L5_PWR_PDCRC_OFFSET) -#define STM32L5_PWR_PUCRD (STM32L5_PWR_BASE + STM32L5_PWR_PUCRD_OFFSET) -#define STM32L5_PWR_PDCRD (STM32L5_PWR_BASE + STM32L5_PWR_PDCRD_OFFSET) -#define STM32L5_PWR_PUCRE (STM32L5_PWR_BASE + STM32L5_PWR_PUCRE_OFFSET) -#define STM32L5_PWR_PDCRE (STM32L5_PWR_BASE + STM32L5_PWR_PDCRE_OFFSET) -#define STM32L5_PWR_PUCRF (STM32L5_PWR_BASE + STM32L5_PWR_PUCRF_OFFSET) -#define STM32L5_PWR_PDCRF (STM32L5_PWR_BASE + STM32L5_PWR_PDCRF_OFFSET) -#define STM32L5_PWR_PUCRG (STM32L5_PWR_BASE + STM32L5_PWR_PUCRG_OFFSET) -#define STM32L5_PWR_PDCRG (STM32L5_PWR_BASE + STM32L5_PWR_PDCRG_OFFSET) -#define STM32L5_PWR_PUCRH (STM32L5_PWR_BASE + STM32L5_PWR_PUCRH_OFFSET) -#define STM32L5_PWR_PDCRH (STM32L5_PWR_BASE + STM32L5_PWR_PDCRH_OFFSET) -#define STM32L5_PWR_SECCFGR (STM32L5_PWR_BASE + STM32L5_PWR_SECCFGR_OFFSET) -#define STM32L5_PWR_PRIVCFGR (STM32L5_PWR_BASE + STM32L5_PWR_PRIVCFGR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE + STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE + STM32_PWR_PDCRF_OFFSET) +#define STM32_PWR_PUCRG (STM32_PWR_BASE + STM32_PWR_PUCRG_OFFSET) +#define STM32_PWR_PDCRG (STM32_PWR_BASE + STM32_PWR_PDCRG_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE + STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE + STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_SECCFGR (STM32_PWR_BASE + STM32_PWR_SECCFGR_OFFSET) +#define STM32_PWR_PRIVCFGR (STM32_PWR_BASE + STM32_PWR_PRIVCFGR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h index 91b92dc5a6a65..e449f201f10a2 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h @@ -37,51 +37,51 @@ /* Maximum allowed speed as per specifications for all SPIs */ #if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_SPI_CLK_MAX 55000000UL +# define STM32_SPI_CLK_MAX 55000000UL #else # error "Unsupported STM32 L5 chip" #endif /* Register Offsets *********************************************************/ -#define STM32L5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32L5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32L5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32L5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32L5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32L5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32L5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#if STM32L5_NSPI > 0 -# define STM32L5_SPI1_CR1 (STM32L5_SPI1_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI1_CR2 (STM32L5_SPI1_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI1_SR (STM32L5_SPI1_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI1_DR (STM32L5_SPI1_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI1_CRCPR (STM32L5_SPI1_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI1_RXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI1_TXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L5_NSPI > 1 -# define STM32L5_SPI2_CR1 (STM32L5_SPI2_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI2_CR2 (STM32L5_SPI2_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI2_SR (STM32L5_SPI2_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI2_DR (STM32L5_SPI2_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI2_CRCPR (STM32L5_SPI2_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI2_RXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI2_TXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L5_NSPI > 2 -# define STM32L5_SPI3_CR1 (STM32L5_SPI3_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI3_CR2 (STM32L5_SPI3_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI3_SR (STM32L5_SPI3_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI3_DR (STM32L5_SPI3_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI3_CRCPR (STM32L5_SPI3_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI3_RXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI3_TXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h index 1e99dba009a77..bb27ee0f1c13e 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32L5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32L5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32L5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32L5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32L5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32L5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32L5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32L5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32L5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32L5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32L5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32L5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32L5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32L5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32L5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32L5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32L5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32L5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32L5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32L5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32L5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32L5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32L5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32L5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32L5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L5_TIM1_CR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR1_OFFSET) -#define STM32L5_TIM1_CR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR2_OFFSET) -#define STM32L5_TIM1_SMCR (STM32L5_TIM1_BASE + STM32L5_ATIM_SMCR_OFFSET) -#define STM32L5_TIM1_DIER (STM32L5_TIM1_BASE + STM32L5_ATIM_DIER_OFFSET) -#define STM32L5_TIM1_SR (STM32L5_TIM1_BASE + STM32L5_ATIM_SR_OFFSET) -#define STM32L5_TIM1_EGR (STM32L5_TIM1_BASE + STM32L5_ATIM_EGR_OFFSET) -#define STM32L5_TIM1_CCMR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR1_OFFSET) -#define STM32L5_TIM1_CCMR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR2_OFFSET) -#define STM32L5_TIM1_CCER (STM32L5_TIM1_BASE + STM32L5_ATIM_CCER_OFFSET) -#define STM32L5_TIM1_CNT (STM32L5_TIM1_BASE + STM32L5_ATIM_CNT_OFFSET) -#define STM32L5_TIM1_PSC (STM32L5_TIM1_BASE + STM32L5_ATIM_PSC_OFFSET) -#define STM32L5_TIM1_ARR (STM32L5_TIM1_BASE + STM32L5_ATIM_ARR_OFFSET) -#define STM32L5_TIM1_RCR (STM32L5_TIM1_BASE + STM32L5_ATIM_RCR_OFFSET) -#define STM32L5_TIM1_CCR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR1_OFFSET) -#define STM32L5_TIM1_CCR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR2_OFFSET) -#define STM32L5_TIM1_CCR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR3_OFFSET) -#define STM32L5_TIM1_CCR4 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR4_OFFSET) -#define STM32L5_TIM1_BDTR (STM32L5_TIM1_BASE + STM32L5_ATIM_BDTR_OFFSET) -#define STM32L5_TIM1_DCR (STM32L5_TIM1_BASE + STM32L5_ATIM_DCR_OFFSET) -#define STM32L5_TIM1_DMAR (STM32L5_TIM1_BASE + STM32L5_ATIM_DMAR_OFFSET) -#define STM32L5_TIM1_OR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR1_OFFSET) -#define STM32L5_TIM1_CCMR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR3_OFFSET) -#define STM32L5_TIM1_CCR5 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR5_OFFSET) -#define STM32L5_TIM1_CCR6 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR6_OFFSET) -#define STM32L5_TIM1_OR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR2_OFFSET) -#define STM32L5_TIM1_OR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR3_OFFSET) - -#define STM32L5_TIM8_CR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR1_OFFSET) -#define STM32L5_TIM8_CR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR2_OFFSET) -#define STM32L5_TIM8_SMCR (STM32L5_TIM8_BASE + STM32L5_ATIM_SMCR_OFFSET) -#define STM32L5_TIM8_DIER (STM32L5_TIM8_BASE + STM32L5_ATIM_DIER_OFFSET) -#define STM32L5_TIM8_SR (STM32L5_TIM8_BASE + STM32L5_ATIM_SR_OFFSET) -#define STM32L5_TIM8_EGR (STM32L5_TIM8_BASE + STM32L5_ATIM_EGR_OFFSET) -#define STM32L5_TIM8_CCMR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR1_OFFSET) -#define STM32L5_TIM8_CCMR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR2_OFFSET) -#define STM32L5_TIM8_CCER (STM32L5_TIM8_BASE + STM32L5_ATIM_CCER_OFFSET) -#define STM32L5_TIM8_CNT (STM32L5_TIM8_BASE + STM32L5_ATIM_CNT_OFFSET) -#define STM32L5_TIM8_PSC (STM32L5_TIM8_BASE + STM32L5_ATIM_PSC_OFFSET) -#define STM32L5_TIM8_ARR (STM32L5_TIM8_BASE + STM32L5_ATIM_ARR_OFFSET) -#define STM32L5_TIM8_RCR (STM32L5_TIM8_BASE + STM32L5_ATIM_RCR_OFFSET) -#define STM32L5_TIM8_CCR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR1_OFFSET) -#define STM32L5_TIM8_CCR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR2_OFFSET) -#define STM32L5_TIM8_CCR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR3_OFFSET) -#define STM32L5_TIM8_CCR4 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR4_OFFSET) -#define STM32L5_TIM8_BDTR (STM32L5_TIM8_BASE + STM32L5_ATIM_BDTR_OFFSET) -#define STM32L5_TIM8_DCR (STM32L5_TIM8_BASE + STM32L5_ATIM_DCR_OFFSET) -#define STM32L5_TIM8_DMAR (STM32L5_TIM8_BASE + STM32L5_ATIM_DMAR_OFFSET) -#define STM32L5_TIM8_OR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR1_OFFSET) -#define STM32L5_TIM8_CCMR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR3_OFFSET) -#define STM32L5_TIM8_CCR5 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR5_OFFSET) -#define STM32L5_TIM8_CCR6 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR6_OFFSET) -#define STM32L5_TIM8_OR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR2_OFFSET) -#define STM32L5_TIM8_OR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE + STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE + STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L5_TIM2_CR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM2_CR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM2_SMCR (STM32L5_TIM2_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM2_DIER (STM32L5_TIM2_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM2_SR (STM32L5_TIM2_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM2_EGR (STM32L5_TIM2_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM2_CCMR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM2_CCMR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM2_CCER (STM32L5_TIM2_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM2_CNT (STM32L5_TIM2_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM2_PSC (STM32L5_TIM2_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM2_ARR (STM32L5_TIM2_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM2_CCR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM2_CCR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM2_CCR3 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM2_CCR4 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM2_DCR (STM32L5_TIM2_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM2_DMAR (STM32L5_TIM2_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM2_OR (STM32L5_TIM2_BASE + STM32L5_GTIM_OR_OFFSET) - -#define STM32L5_TIM3_CR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM3_CR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM3_SMCR (STM32L5_TIM3_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM3_DIER (STM32L5_TIM3_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM3_SR (STM32L5_TIM3_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM3_EGR (STM32L5_TIM3_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM3_CCMR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM3_CCMR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM3_CCER (STM32L5_TIM3_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM3_CNT (STM32L5_TIM3_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM3_PSC (STM32L5_TIM3_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM3_ARR (STM32L5_TIM3_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM3_CCR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM3_CCR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM3_CCR3 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM3_CCR4 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM3_DCR (STM32L5_TIM3_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM3_DMAR (STM32L5_TIM3_BASE + STM32L5_GTIM_DMAR_OFFSET) - -#define STM32L5_TIM4_CR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM4_CR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM4_SMCR (STM32L5_TIM4_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM4_DIER (STM32L5_TIM4_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM4_SR (STM32L5_TIM4_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM4_EGR (STM32L5_TIM4_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM4_CCMR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM4_CCMR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM4_CCER (STM32L5_TIM4_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM4_CNT (STM32L5_TIM4_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM4_PSC (STM32L5_TIM4_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM4_ARR (STM32L5_TIM4_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM4_CCR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM4_CCR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM4_CCR3 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM4_CCR4 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM4_DCR (STM32L5_TIM4_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM4_DMAR (STM32L5_TIM4_BASE + STM32L5_GTIM_DMAR_OFFSET) - -#define STM32L5_TIM5_CR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM5_CR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM5_SMCR (STM32L5_TIM5_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM5_DIER (STM32L5_TIM5_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM5_SR (STM32L5_TIM5_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM5_EGR (STM32L5_TIM5_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM5_CCMR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM5_CCMR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM5_CCER (STM32L5_TIM5_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM5_CNT (STM32L5_TIM5_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM5_PSC (STM32L5_TIM5_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM5_ARR (STM32L5_TIM5_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM5_CCR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM5_CCR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM5_CCR3 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM5_CCR4 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM5_DCR (STM32L5_TIM5_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM5_DMAR (STM32L5_TIM5_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM5_OR (STM32L5_TIM5_BASE + STM32L5_GTIM_OR_OFFSET) - -#define STM32L5_TIM15_CR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM15_CR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM15_SMCR (STM32L5_TIM15_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM15_DIER (STM32L5_TIM15_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM15_SR (STM32L5_TIM15_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM15_EGR (STM32L5_TIM15_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM15_CCMR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM15_CCER (STM32L5_TIM15_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM15_CNT (STM32L5_TIM15_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM15_PSC (STM32L5_TIM15_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM15_ARR (STM32L5_TIM15_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM15_RCR (STM32L5_TIM15_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM15_CCR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM15_CCR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM15_BDTR (STM32L5_TIM15_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM15_DCR (STM32L5_TIM15_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM15_DMAR (STM32L5_TIM15_BASE + STM32L5_GTIM_DMAR_OFFSET) - -#define STM32L5_TIM16_CR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM16_CR2 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM16_DIER (STM32L5_TIM16_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM16_SR (STM32L5_TIM16_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM16_EGR (STM32L5_TIM16_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM16_CCMR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM16_CCER (STM32L5_TIM16_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM16_CNT (STM32L5_TIM16_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM16_PSC (STM32L5_TIM16_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM16_ARR (STM32L5_TIM16_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM16_RCR (STM32L5_TIM16_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM16_CCR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM16_BDTR (STM32L5_TIM16_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM16_DCR (STM32L5_TIM16_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM16_DMAR (STM32L5_TIM16_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM16_OR (STM32L5_TIM16_BASE + STM32L5_GTIM_OR_OFFSET) - -#define STM32L5_TIM17_CR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM17_CR2 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM17_DIER (STM32L5_TIM17_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM17_SR (STM32L5_TIM17_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM17_EGR (STM32L5_TIM17_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM17_CCMR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM17_CCER (STM32L5_TIM17_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM17_CNT (STM32L5_TIM17_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM17_PSC (STM32L5_TIM17_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM17_ARR (STM32L5_TIM17_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM17_RCR (STM32L5_TIM17_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM17_CCR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM17_BDTR (STM32L5_TIM17_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM17_DCR (STM32L5_TIM17_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM17_DMAR (STM32L5_TIM17_BASE + STM32L5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32L5_TIM6_CR1 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR1_OFFSET) -#define STM32L5_TIM6_CR2 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR2_OFFSET) -#define STM32L5_TIM6_DIER (STM32L5_TIM6_BASE + STM32L5_BTIM_DIER_OFFSET) -#define STM32L5_TIM6_SR (STM32L5_TIM6_BASE + STM32L5_BTIM_SR_OFFSET) -#define STM32L5_TIM6_EGR (STM32L5_TIM6_BASE + STM32L5_BTIM_EGR_OFFSET) -#define STM32L5_TIM6_CNT (STM32L5_TIM6_BASE + STM32L5_BTIM_CNT_OFFSET) -#define STM32L5_TIM6_PSC (STM32L5_TIM6_BASE + STM32L5_BTIM_PSC_OFFSET) -#define STM32L5_TIM6_ARR (STM32L5_TIM6_BASE + STM32L5_BTIM_ARR_OFFSET) - -#define STM32L5_TIM7_CR1 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR1_OFFSET) -#define STM32L5_TIM7_CR2 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR2_OFFSET) -#define STM32L5_TIM7_DIER (STM32L5_TIM7_BASE + STM32L5_BTIM_DIER_OFFSET) -#define STM32L5_TIM7_SR (STM32L5_TIM7_BASE + STM32L5_BTIM_SR_OFFSET) -#define STM32L5_TIM7_EGR (STM32L5_TIM7_BASE + STM32L5_BTIM_EGR_OFFSET) -#define STM32L5_TIM7_CNT (STM32L5_TIM7_BASE + STM32L5_BTIM_CNT_OFFSET) -#define STM32L5_TIM7_PSC (STM32L5_TIM7_BASE + STM32L5_BTIM_PSC_OFFSET) -#define STM32L5_TIM7_ARR (STM32L5_TIM7_BASE + STM32L5_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_uart.h b/arch/arm/src/stm32l5/hardware/stm32l5_uart.h index b987bc439211e..65880b3175f24 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_uart.h @@ -37,94 +37,94 @@ /* Register Offsets *********************************************************/ -#define STM32L5_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32L5_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32L5_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32L5_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32L5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32L5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32L5_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32L5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32L5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32L5_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32L5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ -#define STM32L5_USART_PRESC_OFFSET 0x002c /* Prescaler register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */ /* Register Addresses *******************************************************/ -#if STM32L5_NUSART > 0 -# define STM32L5_USART1_CR1 (STM32L5_USART1_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART1_CR2 (STM32L5_USART1_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART1_CR3 (STM32L5_USART1_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART1_BRR (STM32L5_USART1_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART1_GTPR (STM32L5_USART1_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART1_RTOR (STM32L5_USART1_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART1_RQR (STM32L5_USART1_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART1_ISR (STM32L5_USART1_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART1_ICR (STM32L5_USART1_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART1_RDR (STM32L5_USART1_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART1_TDR (STM32L5_USART1_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART1_PRESC (STM32L5_USART1_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 1 -# define STM32L5_USART2_CR1 (STM32L5_USART2_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART2_CR2 (STM32L5_USART2_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART2_CR3 (STM32L5_USART2_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART2_BRR (STM32L5_USART2_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART2_GTPR (STM32L5_USART2_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART2_RTOR (STM32L5_USART2_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART2_RQR (STM32L5_USART2_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART2_ISR (STM32L5_USART2_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART2_ICR (STM32L5_USART2_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART2_RDR (STM32L5_USART2_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART2_TDR (STM32L5_USART2_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART2_PRESC (STM32L5_USART2_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 2 -# define STM32L5_USART3_CR1 (STM32L5_USART3_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART3_CR2 (STM32L5_USART3_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART3_CR3 (STM32L5_USART3_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART3_BRR (STM32L5_USART3_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART3_GTPR (STM32L5_USART3_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART3_RTOR (STM32L5_USART3_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART3_RQR (STM32L5_USART3_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART3_ISR (STM32L5_USART3_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART3_ICR (STM32L5_USART3_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART3_RDR (STM32L5_USART3_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART3_TDR (STM32L5_USART3_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART3_PRESC (STM32L5_USART3_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 3 -# define STM32L5_UART4_CR1 (STM32L5_UART4_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_UART4_CR2 (STM32L5_UART4_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_UART4_CR3 (STM32L5_UART4_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_UART4_BRR (STM32L5_UART4_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_UART4_GTPR (STM32L5_UART4_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_UART4_RTOR (STM32L5_UART4_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_UART4_RQR (STM32L5_UART4_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_UART4_ISR (STM32L5_UART4_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_UART4_ICR (STM32L5_UART4_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_UART4_RDR (STM32L5_UART4_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_UART4_TDR (STM32L5_UART4_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_UART4_PRESC (STM32L5_UART4_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 3 +# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET) +# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET) +# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET) +# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET) +# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) +# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 4 -# define STM32L5_UART5_CR1 (STM32L5_UART5_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_UART5_CR2 (STM32L5_UART5_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_UART5_CR3 (STM32L5_UART5_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_UART5_BRR (STM32L5_UART5_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_UART5_GTPR (STM32L5_UART5_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_UART5_RTOR (STM32L5_UART5_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_UART5_RQR (STM32L5_UART5_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_UART5_ISR (STM32L5_UART5_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_UART5_ICR (STM32L5_UART5_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_UART5_RDR (STM32L5_UART5_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_UART5_TDR (STM32L5_UART5_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_UART5_PRESC (STM32L5_UART5_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 4 +# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET) +# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET) +# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET) +# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET) +# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) +# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/stm32l562xx_rcc.c b/arch/arm/src/stm32l5/stm32l562xx_rcc.c index b1f582519e6ec..39636e5771999 100644 --- a/arch/arm/src/stm32l5/stm32l562xx_rcc.c +++ b/arch/arm/src/stm32l5/stm32l562xx_rcc.c @@ -56,13 +56,13 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* HSE divisor to yield ~1MHz RTC clock */ -#define HSE_DIVISOR (STM32L5_HSE_FREQUENCY + 500000) / 1000000 +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L5_HAVE_HSI48) && defined(STM32L5_USE_CLK48) -# if STM32L5_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L5_USE_HSI48 +#if defined(CONFIG_STM32L5_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -90,7 +90,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L5_DMA1 /* DMA 1 clock enable */ @@ -134,7 +134,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_GTZEN; #endif - putreg32(regval, STM32L5_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -153,31 +153,31 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L5_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L5_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L5_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); @@ -225,7 +225,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_SDMMC1EN; #endif - putreg32(regval, STM32L5_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -244,7 +244,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L5_FMC /* Flexible memory controller clock enable */ @@ -258,7 +258,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_OSPI1EN; #endif - putreg32(regval, STM32L5_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -277,7 +277,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L5_TIM2 /* TIM2 clock enable */ @@ -381,8 +381,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef STM32L5_USE_HSI48 - if (STM32L5_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -414,11 +414,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L5_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L5_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L5_LPUART1 /* Low power uart clock enable */ @@ -462,7 +462,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_UCPD1EN; #endif - putreg32(regval, STM32L5_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -481,7 +481,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L5_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L5_SYSCFG) || defined(CONFIG_STM32L5_COMP) /* System configuration controller, comparators, and voltage reference @@ -551,7 +551,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L5_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -604,12 +604,12 @@ void stm32l5_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32L5_BOARD_USEHSI) || defined(STM32L5_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -617,7 +617,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -626,17 +626,17 @@ void stm32l5_stdclockconfig(void) } #endif -#if defined(STM32L5_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L5_RCC_CR)), + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -647,9 +647,9 @@ void stm32l5_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L5_RCC_CR); - regval |= (STM32L5_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -657,7 +657,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -665,12 +665,12 @@ void stm32l5_stdclockconfig(void) } } -#elif defined(STM32L5_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -678,7 +678,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -687,7 +687,7 @@ void stm32l5_stdclockconfig(void) } #else -# error stm32l5_stdclockconfig(), must have one of STM32L5_BOARD_USEHSI, STM32L5_BOARD_USEMSI, STM32L5_BOARD_USEHSE defined +# error stm32l5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -708,14 +708,14 @@ void stm32l5_stdclockconfig(void) /* Select correct main regulator range */ - regval = getreg32(STM32L5_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - if (STM32L5_SYSCLK_FREQUENCY > 80000000) + if (STM32_SYSCLK_FREQUENCY > 80000000) { regval |= PWR_CR1_VOS_RANGE0; } - else if (STM32L5_SYSCLK_FREQUENCY > 26000000) + else if (STM32_SYSCLK_FREQUENCY > 26000000) { regval |= PWR_CR1_VOS_RANGE1; } @@ -724,125 +724,125 @@ void stm32l5_stdclockconfig(void) regval |= PWR_CR1_VOS_RANGE0; } - putreg32(regval, STM32L5_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Wait for voltage regulator to stabilize */ - while (getreg32(STM32L5_PWR_SR2) & PWR_SR2_VOSF) + while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L5_RCC_CFGR_HPRE; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L5_RCC_CFGR_PPRE2; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L5_RCC_CFGR_PPRE1; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); #ifdef CONFIG_STM32L5_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif /* Set the PLL source and main divider */ - regval = getreg32(STM32L5_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L5_PLLCFG_PLLM | STM32L5_PLLCFG_PLLN | - STM32L5_PLLCFG_PLLP | STM32L5_PLLCFG_PLLQ | - STM32L5_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L5_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L5_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L5_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L5_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L5_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32L5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L5_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L5_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32L5_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L5_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L5_PLLSAI1CFG_PLLN | STM32L5_PLLSAI1CFG_PLLP - | STM32L5_PLLSAI1CFG_PLLQ | STM32L5_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L5_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L5_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L5_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L5_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -850,31 +850,31 @@ void stm32l5_stdclockconfig(void) #ifdef CONFIG_STM32L5_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L5_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L5_PLLSAI2CFG_PLLN | STM32L5_PLLSAI2CFG_PLLP | - STM32L5_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L5_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L5_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L5_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -882,18 +882,18 @@ void stm32l5_stdclockconfig(void) /* Enable FLASH 5 wait states */ regval = FLASH_ACR_LATENCY_5; - putreg32(regval, STM32L5_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L5_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -904,7 +904,7 @@ void stm32l5_stdclockconfig(void) stm32l5_rcc_enablelsi(); #endif -#if defined(STM32L5_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -929,14 +929,14 @@ void stm32l5_stdclockconfig(void) stm32l5_rcc_enablelse(); -# if defined(STM32L5_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L5_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif diff --git a/arch/arm/src/stm32l5/stm32l5_allocateheap.c b/arch/arm/src/stm32l5/stm32l5_allocateheap.c index 8809fc4a2004f..5547109564ee2 100644 --- a/arch/arm/src/stm32l5/stm32l5_allocateheap.c +++ b/arch/arm/src/stm32l5/stm32l5_allocateheap.c @@ -96,19 +96,19 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32L5_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32L5_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ -#define SRAM2_START STM32L5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Set the range of SRAM3, requiring a third memory region */ -#ifdef STM32L5_SRAM3_SIZE -# define SRAM3_START STM32L5_SRAM3_BASE -# define SRAM3_END (SRAM3_START + STM32L5_SRAM3_SIZE) +#ifdef STM32_SRAM3_SIZE +# define SRAM3_START STM32_SRAM3_BASE +# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify diff --git a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c index 0c79a6cc60d49..f5dc0ed6ce791 100644 --- a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c +++ b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c @@ -50,31 +50,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32L5_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { -#if STM32L5_NPORTS > 11 +#if STM32_NPORTS > 11 # error "Additional support required for this number of GPIOs" -#elif STM32L5_NPORTS > 10 +#elif STM32_NPORTS > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32L5_NPORTS > 9 +#elif STM32_NPORTS > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32L5_NPORTS > 8 +#elif STM32_NPORTS > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32L5_NPORTS > 7 +#elif STM32_NPORTS > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32L5_NPORTS > 6 +#elif STM32_NPORTS > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32L5_NPORTS > 5 +#elif STM32_NPORTS > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32L5_NPORTS > 4 +#elif STM32_NPORTS > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32L5_NPORTS > 3 +#elif STM32_NPORTS > 3 'A', 'B', 'C', 'D' -#elif STM32L5_NPORTS > 2 +#elif STM32_NPORTS > 2 'A', 'B', 'C' -#elif STM32L5_NPORTS > 1 +#elif STM32_NPORTS > 1 'A', 'B' -#elif STM32L5_NPORTS > 0 +#elif STM32_NPORTS > 0 'A' #else # error "Bad number of GPIOs" @@ -108,33 +108,33 @@ int stm32l5_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32L5_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32L5_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_MODER_OFFSET), - getreg32(base + STM32L5_GPIO_OTYPER_OFFSET), - getreg32(base + STM32L5_GPIO_OSPEED_OFFSET), - getreg32(base + STM32L5_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_IDR_OFFSET), - getreg32(base + STM32L5_GPIO_ODR_OFFSET), - getreg32(base + STM32L5_GPIO_BSRR_OFFSET), - getreg32(base + STM32L5_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_AFRH_OFFSET), - getreg32(base + STM32L5_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32L5_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c index cc632e2df5ad9..67a6a051e235a 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c @@ -72,13 +72,13 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) int ret = OK; int exti; - exti = irq - STM32L5_IRQ_EXTI0; + exti = irq - STM32_IRQ_EXTI0; DEBUGASSERT((exti >= 0) && (exti <= 15)); /* Clear the pending interrupt for both rising and falling edges. */ - putreg32(0x0001 << exti, STM32L5_EXTI_RPR1); - putreg32(0x0001 << exti, STM32L5_EXTI_FPR1); + putreg32(0x0001 << exti, STM32_EXTI_RPR1); + putreg32(0x0001 << exti, STM32_EXTI_FPR1); /* And dispatch the interrupt to the handler */ @@ -125,7 +125,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { uint32_t pin = pinset & GPIO_PIN_MASK; uint32_t exti = 1 << pin; - int irq = STM32L5_IRQ_EXTI0 + pin; + int irq = STM32_IRQ_EXTI0 + pin; g_gpio_handlers[pin].callback = func; g_gpio_handlers[pin].arg = arg; @@ -155,19 +155,19 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32L5_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32L5_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L5_EXTI_EMR1, + modifyreg32(STM32_EXTI_EMR1, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32L5_EXTI_IMR1, + modifyreg32(STM32_EXTI_IMR1, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index 62f7f86370582..d7d9915e709c1 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -69,7 +69,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32L5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #if FLASH_PAGE_SIZE == 2048 @@ -79,7 +79,7 @@ #elif FLASH_PAGE_SIZE == 8192 # define FLASH_PAGE_SHIFT (13) /* 2**13 = 8192B */ #else -# error Unsupported STM32L5_FLASH_PAGESIZE +# error Unsupported STM32_FLASH_PAGESIZE #endif #define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT) @@ -105,35 +105,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } - if (getreg32(STM32L5_FLASH_NSCR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32L5_FLASH_NSKEYR); - putreg32(FLASH_KEY2, STM32L5_FLASH_NSKEYR); + putreg32(FLASH_KEY1, STM32_FLASH_NSKEYR); + putreg32(FLASH_KEY2, STM32_FLASH_NSKEYR); } } static void flash_lock(void) { - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32L5_FLASH_NSCR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32L5_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32L5_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -150,16 +150,16 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page)); - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page)); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_START); - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** @@ -214,20 +214,20 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32L5_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%x\n", (unsigned)regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32L5_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%x\n", (unsigned)regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } @@ -240,42 +240,42 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32L5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32L5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32L5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32L5_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32L5_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32L5_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32L5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32L5_FLASH_PAGESIZE + STM32L5_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32L5_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -285,7 +285,7 @@ bool up_progmem_isuniform(void) ssize_t up_progmem_eraseblock(size_t block) { - if (block >= STM32L5_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -318,7 +318,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32L5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -351,12 +351,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32L5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32L5_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32L5_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -422,23 +422,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_PG); for (i = 0; i < FLASH_PAGE_WORDS; i += 2) { *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } /* Verify */ - if (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_NSSR) & FLASH_SR_WRITE_PROTECTION_ERROR) { - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); ret = -EROFS; goto out; } @@ -446,13 +446,13 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (getreg32(dest - 1) != *(src - 1) || getreg32(dest - 2) != *(src - 2)) { - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); ret = -EIO; goto out; } } - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); /* Adjust pointers and counts for the next time through the loop */ @@ -473,8 +473,8 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%x\n", ret, - (unsigned)getreg32(STM32L5_FLASH_NSSR)); - modifyreg32(STM32L5_FLASH_NSSR, 0, FLASH_SR_ALLERRS); + (unsigned)getreg32(STM32_FLASH_NSSR)); + modifyreg32(STM32_FLASH_NSSR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c index 581a5b6bfc0fc..2d9afa34849a0 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_gpio.c @@ -54,31 +54,31 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32L5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32L5_NPORTS > 0 - STM32L5_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32L5_NPORTS > 1 - STM32L5_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32L5_NPORTS > 2 - STM32L5_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32L5_NPORTS > 3 - STM32L5_GPIOD_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, #endif -#if STM32L5_NPORTS > 4 - STM32L5_GPIOE_BASE, +#if STM32_NPORTS > 4 + STM32_GPIOE_BASE, #endif -#if STM32L5_NPORTS > 5 - STM32L5_GPIOF_BASE, +#if STM32_NPORTS > 5 + STM32_GPIOF_BASE, #endif -#if STM32L5_NPORTS > 6 - STM32L5_GPIOG_BASE, +#if STM32_NPORTS > 6 + STM32_GPIOG_BASE, #endif -#if STM32L5_NPORTS > 7 - STM32L5_GPIOH_BASE, +#if STM32_NPORTS > 7 + STM32_GPIOH_BASE, #endif }; @@ -141,7 +141,7 @@ int stm32l5_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32L5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -190,10 +190,10 @@ int stm32l5_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32L5_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -216,10 +216,10 @@ int stm32l5_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32L5_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -234,12 +234,12 @@ int stm32l5_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32L5_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32L5_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -277,14 +277,14 @@ int stm32l5_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32L5_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32L5_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -297,7 +297,7 @@ int stm32l5_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32L5_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; @@ -352,7 +352,7 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -373,7 +373,7 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32L5_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -392,7 +392,7 @@ bool stm32l5_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -401,7 +401,7 @@ bool stm32l5_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32L5_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h index e14436202a596..2bb1f03565190 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/stm32l5_gpio.h @@ -241,7 +241,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32L5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index 757b7315fff41..f42f2dda2ab8e 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -186,13 +186,13 @@ static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32L5_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32L5_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -202,19 +202,19 @@ static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32L5_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32L5_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32L5_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32L5_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -244,7 +244,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32L5_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -298,14 +298,14 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32L5_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32L5_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32L5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif @@ -316,23 +316,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32L5_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32L5_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32L5_IRQ_NMI, stm32l5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32l5_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32L5_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32L5_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32L5_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32L5_IRQ_PENDSV, stm32l5_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32l5_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32L5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32L5_IRQ_RESERVED, stm32l5_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32l5_reserved, NULL); #endif stm32l5_dumpnvic("initial", NR_IRQS); @@ -368,7 +368,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -403,7 +403,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -446,10 +446,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32L5_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32L5_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -462,7 +462,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32L5_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.c b/arch/arm/src/stm32l5/stm32l5_lowputc.c index bcc1075c80ace..6229979f9a2e3 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.c +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.c @@ -46,127 +46,127 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_LPUART1_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR2 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32L5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32L5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32L5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART1_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK2_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB2ENR -# define STM32L5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART1_TX -# define STM32L5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART2_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART2_TX -# define STM32L5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART3_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART3EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART3_TX -# define STM32L5_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_UART4_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART4EN -# define STM32L5_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32L5_CONSOLE_TX GPIO_UART4_TX -# define STM32L5_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_UART5_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART5EN -# define STM32L5_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32L5_CONSOLE_TX GPIO_UART5_TX -# define STM32L5_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32L5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32L5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -174,9 +174,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32L5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32L5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -192,7 +192,7 @@ /* CR2 settings */ -# if STM32L5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -232,8 +232,8 @@ * LPUARTDIV must be in range [0x300, 0xFFFFF]. */ -# define STM32L5_BRR_VALUE \ - ((((uint64_t)STM32L5_APBCLOCK << 8) + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) +# define STM32_BRR_VALUE \ + ((((uint64_t)STM32_APBCLOCK << 8) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) # else @@ -249,19 +249,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32L5_USARTDIV8 \ - (((STM32L5_APBCLOCK << 1) + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) -# define STM32L5_USARTDIV16 \ - ((STM32L5_APBCLOCK + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32L5_USARTDIV8 > 2000 -# define STM32L5_BRR_VALUE STM32L5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32L5_BRR_VALUE \ - ((STM32L5_USARTDIV8 & 0xfff0) | ((STM32L5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif /* CONFIG_LPUART1_SERIAL_CONSOLE */ @@ -305,22 +305,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32L5_CONSOLE_RS485_DIR - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - STM32L5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32L5_CONSOLE_BASE + STM32L5_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32L5_CONSOLE_RS485_DIR - while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - !STM32L5_CONSOLE_RS485_DIR_POLARITY); + stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -346,7 +346,7 @@ void stm32l5_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32L5_CONSOLE_APBREG, 0, STM32L5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -355,17 +355,17 @@ void stm32l5_lowsetup(void) * stm32l5_rcc.c */ -#ifdef STM32L5_CONSOLE_TX - stm32l5_configgpio(STM32L5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32l5_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32L5_CONSOLE_RX - stm32l5_configgpio(STM32L5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32l5_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32L5_CONSOLE_RS485_DIR - stm32l5_configgpio(STM32L5_CONSOLE_RS485_DIR); - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - !STM32L5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l5_configgpio(STM32_CONSOLE_RS485_DIR); + stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -373,42 +373,42 @@ void stm32l5_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32L5_BRR_VALUE, - STM32L5_CONSOLE_BASE + STM32L5_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index b990134a4f783..f3e6827279b0c 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -88,7 +88,7 @@ void stm32l5_rcc_enablelse(void) * clock are already running. */ - regval = getreg32(STM32L5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY | RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) != @@ -116,7 +116,7 @@ void stm32l5_rcc_enablelse(void) regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif @@ -125,11 +125,11 @@ void stm32l5_rcc_enablelse(void) { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= drives[drive++]; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready (or until a timeout elapsed) */ @@ -138,7 +138,7 @@ void stm32l5_rcc_enablelse(void) { /* Check if the LSERDY flag is the set in the BDCR */ - regval = getreg32(STM32L5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if (regval & RCC_BDCR_LSERDY) { @@ -166,11 +166,11 @@ void stm32l5_rcc_enablelse(void) regval |= RCC_BDCR_LSESYSEN; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE system clock to be ready */ - while (!((regval = getreg32(STM32L5_RCC_BDCR)) & + while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { stm32l5_waste(); @@ -183,7 +183,7 @@ void stm32l5_rcc_enablelse(void) regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c index 507e7a1a8b2d5..a47bd5ea1dd47 100644 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ b/arch/arm/src/stm32l5/stm32l5_lsi.c @@ -46,11 +46,11 @@ void stm32l5_rcc_enablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L5_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32L5_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** @@ -67,7 +67,7 @@ void stm32l5_rcc_disablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L5_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.c b/arch/arm/src/stm32l5/stm32l5_pwr.c index 925be6f7c9006..3b306923e8e67 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.c +++ b/arch/arm/src/stm32l5/stm32l5_pwr.c @@ -41,12 +41,12 @@ static inline uint16_t stm32l5_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32L5_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32L5_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } /**************************************************************************** @@ -75,7 +75,7 @@ bool stm32l5_pwr_enableclk(bool enable) uint32_t regval; bool wasenabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); /* Power interface clock enable. */ @@ -85,14 +85,14 @@ bool stm32l5_pwr_enableclk(bool enable) /* Disable power interface clock */ regval &= ~RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L5_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } else if (!wasenabled && enable) { /* Enable power interface clock */ regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L5_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } return wasenabled; @@ -120,7 +120,7 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Get the current state of the STM32L5 PWR control register 1 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR1_OFFSET); + regval = stm32l5_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -169,7 +169,7 @@ bool stm32l5_pwr_enableusv(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -179,7 +179,7 @@ bool stm32l5_pwr_enableusv(bool set) /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET); + regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,14 +189,14 @@ bool stm32l5_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -229,7 +229,7 @@ bool stm32l5_pwr_vddio2_valid(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -239,7 +239,7 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET); + regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -249,14 +249,14 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index c2f6421d7cce5..8164097f5a018 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -93,14 +93,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32l5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32L5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32L5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32L5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -113,19 +113,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32L5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32L5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32L5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32L5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32l5_pwr_enablebkp(false); diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index b756d9656d02e..5157e85ce533f 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -81,10 +81,10 @@ static inline void stm32l5_mcoconfig(uint32_t source) /* Set MCO source */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCOSEL_MASK); regval |= (source & RCC_CFGR_MCOSEL_MASK); - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index 514c57477d5d4..e39dad2f74e57 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -471,13 +471,13 @@ static struct stm32l5_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32L5_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -531,13 +531,13 @@ static struct stm32l5_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32L5_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32L5_PCLK2_FREQUENCY, - .usartbase = STM32L5_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -593,13 +593,13 @@ static struct stm32l5_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32L5_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -655,13 +655,13 @@ static struct stm32l5_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32L5_IRQ_USART3, + .irq = STM32_IRQ_USART3, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) @@ -717,7 +717,7 @@ static struct stm32l5_serial_s g_uart4priv = .priv = &g_uart4priv, }, - .irq = STM32L5_IRQ_UART4, + .irq = STM32_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, @@ -730,8 +730,8 @@ static struct stm32l5_serial_s g_uart4priv = .rts_gpio = GPIO_UART4_RTS, # endif .baud = CONFIG_UART4_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, # ifdef CONFIG_UART4_RXDMA @@ -779,7 +779,7 @@ static struct stm32l5_serial_s g_uart5priv = .priv = &g_uart5priv, }, - .irq = STM32L5_IRQ_UART5, + .irq = STM32_IRQ_UART5, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, @@ -792,8 +792,8 @@ static struct stm32l5_serial_s g_uart5priv = .rts_gpio = GPIO_UART5_RTS, # endif .baud = CONFIG_UART5_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, # ifdef CONFIG_UART5_RXDMA @@ -816,7 +816,7 @@ static struct stm32l5_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ static struct stm32l5_serial_s * const - g_uart_devs[STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -896,15 +896,15 @@ void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, * above) */ - cr = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + cr = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -959,8 +959,8 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - cr3 = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -1022,20 +1022,20 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) uint32_t brr; #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32L5_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { /* LPUART BRR = 256 * fCK / baud */ brr = (((uint64_t)priv->apbclock << 8) + (priv->baud >> 1)) / priv->baud; - stm32l5serial_putreg(priv, STM32L5_USART_BRR_OFFSET, brr); + stm32l5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } else #endif { usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 2000) { brr = (usartdiv8 + 1) >> 1; @@ -1048,13 +1048,13 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) cr1 |= USART_CR1_OVER8; } - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); - stm32l5serial_putreg(priv, STM32L5_USART_BRR_OFFSET, brr); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } /* Configure parity mode */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -1092,11 +1092,11 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -1104,11 +1104,11 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) @@ -1125,7 +1125,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) } #endif - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1170,7 +1170,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + while ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_DMA @@ -1276,7 +1276,7 @@ static void stm32l5serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l5_serial_s *priv = g_uart_devs[n]; @@ -1316,39 +1316,39 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) default: return; #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER - case STM32L5_LPUART1_BASE: + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32L5_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif #ifdef CONFIG_STM32L5_USART1_SERIALDRIVER - case STM32L5_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L5_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif #ifdef CONFIG_STM32L5_USART2_SERIALDRIVER - case STM32L5_USART2_BASE: + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L5_USART3_SERIALDRIVER - case STM32L5_USART3_BASE: + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L5_UART4_SERIALDRIVER - case STM32L5_UART4_BASE: + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L5_UART5_SERIALDRIVER - case STM32L5_UART5_BASE: + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1435,7 +1435,7 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1446,26 +1446,26 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1473,9 +1473,9 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1528,7 +1528,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1539,7 +1539,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1553,9 +1553,9 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1613,9 +1613,9 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1780,7 +1780,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET); + priv->sr = stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1847,7 +1847,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32l5serial_putreg(priv, STM32L5_USART_ICR_OFFSET, + stm32l5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1920,19 +1920,19 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1977,11 +1977,11 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1998,17 +1998,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -2028,11 +2028,11 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2049,17 +2049,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -2070,11 +2070,11 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2231,8 +2231,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2244,8 +2244,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2281,7 +2281,7 @@ static int stm32l5serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32l5serial_getreg(priv, STM32L5_USART_RDR_OFFSET); + rdr = stm32l5serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2368,7 +2368,7 @@ static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; - return ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2531,7 +2531,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2542,7 +2542,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2711,7 +2711,7 @@ static void stm32l5serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32l5serial_putreg(priv, STM32L5_USART_TDR_OFFSET, (uint32_t)ch); + stm32l5serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2796,7 +2796,7 @@ static bool stm32l5serial_txready(struct uart_dev_s *dev) struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; - return ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2838,11 +2838,11 @@ static void stm32l5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET); + priv->sr = stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32l5serial_putreg(priv, STM32L5_USART_ICR_OFFSET, + stm32l5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2978,7 +2978,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l5_serial_s *priv = g_uart_devs[n]; @@ -3048,7 +3048,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -3117,7 +3117,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index 80f3005edea37..6fc62e9eaab4d 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -285,10 +285,10 @@ static struct stm32l5_spidev_s g_spi1dev = { .ops = &g_spi1ops, }, - .spibase = STM32L5_SPI1_BASE, - .spiclock = STM32L5_PCLK2_FREQUENCY, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, #ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI1, + .spiirq = STM32_IRQ_SPI1, #endif #ifdef CONFIG_STM32L5_SPI_DMA /* lines must be configured in board.h */ @@ -343,10 +343,10 @@ static struct stm32l5_spidev_s g_spi2dev = { .ops = &g_spi2ops, }, - .spibase = STM32L5_SPI2_BASE, - .spiclock = STM32L5_PCLK1_FREQUENCY, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI2, + .spiirq = STM32_IRQ_SPI2, #endif #ifdef CONFIG_STM32L5_SPI_DMA .rxch = DMACHAN_SPI2_RX, @@ -399,10 +399,10 @@ static struct stm32l5_spidev_s g_spi3dev = { .ops = &g_spi3ops, }, - .spibase = STM32L5_SPI3_BASE, - .spiclock = STM32L5_PCLK1_FREQUENCY, + .spibase = STM32_SPI3_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI3, + .spiirq = STM32_IRQ_SPI3, #endif #ifdef CONFIG_STM32L5_SPI_DMA .rxch = DMACHAN_SPI3_RX, @@ -522,11 +522,11 @@ static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32L5_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -547,11 +547,11 @@ static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32L5_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -574,11 +574,11 @@ static inline void spi_writeword(struct stm32l5_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32L5_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -601,11 +601,11 @@ static inline void spi_writebyte(struct stm32l5_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32L5_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -805,7 +805,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, /* Configure the RX DMA */ - stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32L5_SPI_DR_OFFSET, + stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -856,7 +856,7 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, /* Setup the TX DMA */ - stm32l5_dmasetup(priv->txdma, priv->spibase + STM32L5_SPI_DR_OFFSET, + stm32l5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -983,11 +983,11 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32L5_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32L5_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32L5_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -1053,9 +1053,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, actual = priv->spiclock >> 8; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1125,9 +1125,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster @@ -1192,9 +1192,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so the subsequence re-configurations will be * faster @@ -1247,9 +1247,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1315,7 +1315,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32L5_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1730,11 +1730,11 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) SPI_CR1_BR_MASK | SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1746,7 +1746,7 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32L5_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32L5_SPI_DMA /* Get DMA channels. @@ -1763,13 +1763,13 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) priv->txdma = stm32l5_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 94e500d149a16..6978b6013b403 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -62,8 +62,8 @@ * 0x2003:ffff - End of internal SRAM2 */ -#define SRAM2_START STM32L5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index a53bf043a3400..7e2d91bc1fd49 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -305,16 +305,16 @@ static const struct stm32l5_tim_ops_s stm32l5_tim_ops = struct stm32l5_tim_priv_s stm32l5_tim1_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM2 struct stm32l5_tim_priv_s stm32l5_tim2_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -322,8 +322,8 @@ struct stm32l5_tim_priv_s stm32l5_tim2_priv = struct stm32l5_tim_priv_s stm32l5_tim3_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -331,8 +331,8 @@ struct stm32l5_tim_priv_s stm32l5_tim3_priv = struct stm32l5_tim_priv_s stm32l5_tim4_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -340,8 +340,8 @@ struct stm32l5_tim_priv_s stm32l5_tim4_priv = struct stm32l5_tim_priv_s stm32l5_tim5_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -349,8 +349,8 @@ struct stm32l5_tim_priv_s stm32l5_tim5_priv = struct stm32l5_tim_priv_s stm32l5_tim6_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -358,8 +358,8 @@ struct stm32l5_tim_priv_s stm32l5_tim6_priv = struct stm32l5_tim_priv_s stm32l5_tim7_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -367,8 +367,8 @@ struct stm32l5_tim_priv_s stm32l5_tim7_priv = struct stm32l5_tim_priv_s stm32l5_tim8_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -376,8 +376,8 @@ struct stm32l5_tim_priv_s stm32l5_tim8_priv = struct stm32l5_tim_priv_s stm32l5_tim15_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -385,8 +385,8 @@ struct stm32l5_tim_priv_s stm32l5_tim15_priv = struct stm32l5_tim_priv_s stm32l5_tim16_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -394,8 +394,8 @@ struct stm32l5_tim_priv_s stm32l5_tim16_priv = struct stm32l5_tim_priv_s stm32l5_tim17_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_EGR_OFFSET); + uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l5_putreg16(dev, STM32L5_GTIM_EGR_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) { - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32L5_TIM_MODE_DISABLED; + ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32l5_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32l5_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32L5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32l5_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L5_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L5_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32L5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32L5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32L5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32L5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32L5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, break; - case STM32L5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, } stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32L5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM1_BASE || - ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM8_BASE) + if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l5_modifyreg16(dev, STM32L5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32l5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -655,66 +655,66 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, prescaler = 0xffff; } - stm32l5_putreg16(dev, STM32L5_GTIM_PSC_OFFSET, prescaler); + stm32l5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32l5_tim_enable(dev); return prescaler; @@ -770,64 +770,64 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l5_getreg16(dev, STM32L5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32l5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l5_putreg32(dev, STM32L5_GTIM_ARR_OFFSET, period); + stm32l5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l5_getreg32 (dev, STM32L5_GTIM_ARR_OFFSET); + return stm32l5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,7 +869,7 @@ static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l5_getreg32(dev, STM32L5_GTIM_CNT_OFFSET); + uint32_t counter = stm32l5_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -879,10 +879,10 @@ static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l5_getreg16(dev, STM32L5_GTIM_CCER_OFFSET); + ccer_val = stm32l5_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L5_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L5_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32L5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32L5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32L5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32L5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32L5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32l5_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32l5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l5_putreg16(dev, STM32L5_GTIM_CCER_OFFSET, ccer_val); + stm32l5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1021,7 +1021,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1054,7 +1054,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1087,7 +1087,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1119,7 +1119,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1152,7 +1152,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1185,7 +1185,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1218,7 +1218,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1251,7 +1251,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR1_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR2_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR3_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR4_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR1_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR2_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR3_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR4_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1367,66 +1367,66 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: - vectorno = STM32L5_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: - vectorno = STM32L5_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: - vectorno = STM32L5_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: - vectorno = STM32L5_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: - vectorno = STM32L5_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: - vectorno = STM32L5_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: - vectorno = STM32L5_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: - vectorno = STM32L5_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: - vectorno = STM32L5_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: - vectorno = STM32L5_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: - vectorno = STM32L5_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) { - stm32l5_putreg16(dev, STM32L5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32l5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, int source) { - uint16_t regval = stm32l5_getreg16(dev, STM32L5_GTIM_SR_OFFSET); + uint16_t regval = stm32l5_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1512,76 +1512,76 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) #ifdef CONFIG_STM32L5_TIM1 case 1: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim1_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32L5_TIM2 case 2: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim2_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32L5_TIM3 case 3: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim3_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32L5_TIM4 case 4: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim4_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32L5_TIM5 case 5: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim5_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32L5_TIM6 case 6: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim6_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32L5_TIM7 case 7: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim7_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32L5_TIM8 case 8: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim8_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32L5_TIM15 case 15: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim15_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32L5_TIM16 case 16: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim16_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32L5_TIM17 case 17: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim17_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32L5_TIM_MODE_UNUSED) + if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1617,67 +1617,67 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,7 +1687,7 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32L5_TIM_MODE_UNUSED; + ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h index f114ff9c6183c..9e420265f79d6 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/stm32l5_tim.h @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32L5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32L5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32L5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32L5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32L5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32L5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32L5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32L5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32L5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32L5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32l5_tim_dev_s enum stm32l5_tim_mode_e { - STM32L5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32L5_TIM_MODE_MASK = 0x0310, - STM32L5_TIM_MODE_DISABLED = 0x0000, - STM32L5_TIM_MODE_UP = 0x0100, - STM32L5_TIM_MODE_DOWN = 0x0110, - STM32L5_TIM_MODE_UPDOWN = 0x0200, - STM32L5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32L5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32L5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32L5_TIM_MODE_CK_EXT = 0x0800, - STM32L5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32L5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32L5_TIM_MODE_CK_CH1 = 0x0001, - STM32L5_TIM_MODE_CK_CH2 = 0x0002, - STM32L5_TIM_MODE_CK_CH3 = 0x0003, - STM32L5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,30 +118,30 @@ enum stm32l5_tim_mode_e enum stm32l5_tim_channel_e { - STM32L5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32L5_TIM_CH_POLARITY_POS = 0x00, - STM32L5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32L5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32L5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32L5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32L5_TIM_CH_INCAPTURE = 0x10, - STM32L5_TIM_CH_INPWM = 0x20 - STM32L5_TIM_CH_DRIVE_OC = open collector mode + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC = open collector mode #endif }; diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c index 0d21c17b04906..b5e7ebcf7593b 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c @@ -52,17 +52,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L5_TIM1_RES 16 -#define STM32L5_TIM2_RES 32 -#define STM32L5_TIM3_RES 16 -#define STM32L5_TIM4_RES 16 -#define STM32L5_TIM5_RES 32 -#define STM32L5_TIM6_RES 16 -#define STM32L5_TIM7_RES 16 -#define STM32L5_TIM8_RES 16 -#define STM32L5_TIM15_RES 16 -#define STM32L5_TIM16_RES 16 -#define STM32L5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -122,7 +122,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -130,7 +130,7 @@ static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -138,7 +138,7 @@ static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif @@ -146,7 +146,7 @@ static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif @@ -154,7 +154,7 @@ static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif @@ -162,7 +162,7 @@ static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif @@ -170,7 +170,7 @@ static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif @@ -178,7 +178,7 @@ static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif @@ -186,7 +186,7 @@ static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif @@ -194,7 +194,7 @@ static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -202,7 +202,7 @@ static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) (struct stm32l5_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32L5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32L5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32L5_TIM_SETMODE(priv->tim, STM32L5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32L5_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); - STM32L5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32L5_TIM_SETMODE(priv->tim, STM32L5_TIM_MODE_DISABLED); - STM32L5_TIM_DISABLEINT(priv->tim, 0); - STM32L5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32L5_TIM_GETCLOCK(priv->tim); - period = STM32L5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32L5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32L5_TIM_SETCLOCK(priv->tim, freq); - STM32L5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32L5_TIM_SETCLOCK(priv->tim, 1000000); - STM32L5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32L5_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); - STM32L5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32L5_TIM_DISABLEINT(priv->tim, 0); - STM32L5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l5/stm32l5_timerisr.c b/arch/arm/src/stm32l5/stm32l5_timerisr.c index 4ee9481fb829d..85089050ec038 100644 --- a/arch/arm/src/stm32l5/stm32l5_timerisr.c +++ b/arch/arm/src/stm32l5/stm32l5_timerisr.c @@ -61,9 +61,9 @@ #undef CONFIG_STM32L5_SYSTICK_HCLKd8 #ifdef CONFIG_STM32L5_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -137,7 +137,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32L5_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); /* Enable SysTick interrupts */ @@ -146,5 +146,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32L5_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32l5/stm32l5_uid.c b/arch/arm/src/stm32l5/stm32l5_uid.c index e8242cd559faf..1b354bc4b7b5b 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.c +++ b/arch/arm/src/stm32l5/stm32l5_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32l5_memorymap.h" #include "stm32l5_uid.h" -#ifdef STM32L5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32l5_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32L5_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32L5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32n6/stm32_gpio.c b/arch/arm/src/stm32n6/stm32_gpio.c index 4127545303266..c22839ad7812a 100644 --- a/arch/arm/src/stm32n6/stm32_gpio.c +++ b/arch/arm/src/stm32n6/stm32_gpio.c @@ -55,7 +55,7 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; * 8-11). Note that there is no GPIOI-M on this chip. */ -const uint32_t g_gpiobase[STM32N6_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { STM32_GPIOA_BASE, /* Port A - index 0 */ STM32_GPIOB_BASE, /* Port B - index 1 */ @@ -110,7 +110,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32N6_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -318,7 +318,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32N6_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -358,7 +358,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32N6_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ diff --git a/arch/arm/src/stm32n6/stm32_gpio.h b/arch/arm/src/stm32n6/stm32_gpio.h index 4c32f43d43c2d..64ad271b3f1a4 100644 --- a/arch/arm/src/stm32n6/stm32_gpio.h +++ b/arch/arm/src/stm32n6/stm32_gpio.h @@ -243,7 +243,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32N6_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32n6/stm32_serial.c b/arch/arm/src/stm32n6/stm32_serial.c index 220a34dc3acb6..75dc8c8c857bd 100644 --- a/arch/arm/src/stm32n6/stm32_serial.c +++ b/arch/arm/src/stm32n6/stm32_serial.c @@ -274,7 +274,7 @@ static struct stm32_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ static struct stm32_serial_s * const - g_uart_devs[STM32N6_NUSART] = + g_uart_devs[STM32_NUSART] = { #ifdef CONFIG_STM32N6_USART1_SERIALDRIVER [0] = &g_usart1priv, @@ -639,7 +639,7 @@ static void stm32serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32N6_NUSART; n++) + for (n = 0; n < STM32_NUSART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -1559,7 +1559,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32N6_NUSART; n++) + for (n = 0; n < STM32_NUSART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -1629,7 +1629,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32N6_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -1694,7 +1694,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32N6_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h index 616cb5e855e4a..90fe085d6eead 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h @@ -40,8 +40,8 @@ #define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ #define STM32_REGION_MASK 0xF0000000 -#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_SRAM_BASE) -#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_FMC_BANK1) +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) /* Code Base Addresses ******************************************************/ diff --git a/arch/arm/src/stm32u5/hardware/stm32_tim.h b/arch/arm/src/stm32u5/hardware/stm32_tim.h index d9adc748102f6..e180a60d773a3 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32u5/hardware/stm32_tim.h @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32U5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32U5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32U5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32U5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32U5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32U5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32U5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32U5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32U5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32U5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32U5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32U5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32U5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32U5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32U5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32U5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32U5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32U5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32U5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32U5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32U5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32U5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32U5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_TIM1_CR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM1_CR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM1_SMCR (STM32U5_TIM1_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM1_DIER (STM32U5_TIM1_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM1_SR (STM32U5_TIM1_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM1_EGR (STM32U5_TIM1_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM1_CCMR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM1_CCMR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM1_CCER (STM32U5_TIM1_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM1_CNT (STM32U5_TIM1_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM1_PSC (STM32U5_TIM1_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM1_ARR (STM32U5_TIM1_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM1_RCR (STM32U5_TIM1_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM1_CCR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM1_CCR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM1_CCR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM1_CCR4 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM1_BDTR (STM32U5_TIM1_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM1_DCR (STM32U5_TIM1_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM1_DMAR (STM32U5_TIM1_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM1_OR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM1_CCMR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM1_CCR5 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM1_CCR6 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM1_OR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM1_OR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR3_OFFSET) - -#define STM32U5_TIM8_CR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM8_CR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM8_SMCR (STM32U5_TIM8_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM8_DIER (STM32U5_TIM8_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM8_SR (STM32U5_TIM8_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM8_EGR (STM32U5_TIM8_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM8_CCMR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM8_CCMR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM8_CCER (STM32U5_TIM8_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM8_CNT (STM32U5_TIM8_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM8_PSC (STM32U5_TIM8_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM8_ARR (STM32U5_TIM8_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM8_RCR (STM32U5_TIM8_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM8_CCR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM8_CCR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM8_CCR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM8_CCR4 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM8_BDTR (STM32U5_TIM8_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM8_DCR (STM32U5_TIM8_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM8_DMAR (STM32U5_TIM8_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM8_OR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM8_CCMR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM8_CCR5 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM8_CCR6 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM8_OR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM8_OR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE + STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE + STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_TIM2_CR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM2_CR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM2_SMCR (STM32U5_TIM2_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM2_DIER (STM32U5_TIM2_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM2_SR (STM32U5_TIM2_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM2_EGR (STM32U5_TIM2_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM2_CCMR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM2_CCMR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM2_CCER (STM32U5_TIM2_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM2_CNT (STM32U5_TIM2_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM2_PSC (STM32U5_TIM2_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM2_ARR (STM32U5_TIM2_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM2_CCR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM2_CCR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM2_CCR3 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM2_CCR4 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM2_DCR (STM32U5_TIM2_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM2_DMAR (STM32U5_TIM2_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM2_OR (STM32U5_TIM2_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM3_CR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM3_CR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM3_SMCR (STM32U5_TIM3_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM3_DIER (STM32U5_TIM3_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM3_SR (STM32U5_TIM3_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM3_EGR (STM32U5_TIM3_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM3_CCMR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM3_CCMR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM3_CCER (STM32U5_TIM3_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM3_CNT (STM32U5_TIM3_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM3_PSC (STM32U5_TIM3_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM3_ARR (STM32U5_TIM3_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM3_CCR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM3_CCR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM3_CCR3 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM3_CCR4 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM3_DCR (STM32U5_TIM3_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM3_DMAR (STM32U5_TIM3_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM4_CR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM4_CR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM4_SMCR (STM32U5_TIM4_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM4_DIER (STM32U5_TIM4_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM4_SR (STM32U5_TIM4_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM4_EGR (STM32U5_TIM4_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM4_CCMR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM4_CCMR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM4_CCER (STM32U5_TIM4_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM4_CNT (STM32U5_TIM4_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM4_PSC (STM32U5_TIM4_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM4_ARR (STM32U5_TIM4_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM4_CCR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM4_CCR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM4_CCR3 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM4_CCR4 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM4_DCR (STM32U5_TIM4_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM4_DMAR (STM32U5_TIM4_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM5_CR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM5_CR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM5_SMCR (STM32U5_TIM5_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM5_DIER (STM32U5_TIM5_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM5_SR (STM32U5_TIM5_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM5_EGR (STM32U5_TIM5_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM5_CCMR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM5_CCMR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM5_CCER (STM32U5_TIM5_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM5_CNT (STM32U5_TIM5_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM5_PSC (STM32U5_TIM5_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM5_ARR (STM32U5_TIM5_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM5_CCR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM5_CCR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM5_CCR3 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM5_CCR4 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM5_DCR (STM32U5_TIM5_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM5_DMAR (STM32U5_TIM5_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM5_OR (STM32U5_TIM5_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM15_CR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM15_CR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM15_SMCR (STM32U5_TIM15_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM15_DIER (STM32U5_TIM15_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM15_SR (STM32U5_TIM15_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM15_EGR (STM32U5_TIM15_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM15_CCMR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM15_CCER (STM32U5_TIM15_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM15_CNT (STM32U5_TIM15_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM15_PSC (STM32U5_TIM15_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM15_ARR (STM32U5_TIM15_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM15_RCR (STM32U5_TIM15_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM15_CCR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM15_CCR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM15_BDTR (STM32U5_TIM15_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM15_DCR (STM32U5_TIM15_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM15_DMAR (STM32U5_TIM15_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM16_CR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM16_CR2 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM16_DIER (STM32U5_TIM16_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM16_SR (STM32U5_TIM16_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM16_EGR (STM32U5_TIM16_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM16_CCMR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM16_CCER (STM32U5_TIM16_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM16_CNT (STM32U5_TIM16_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM16_PSC (STM32U5_TIM16_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM16_ARR (STM32U5_TIM16_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM16_RCR (STM32U5_TIM16_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM16_CCR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM16_BDTR (STM32U5_TIM16_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM16_DCR (STM32U5_TIM16_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM16_DMAR (STM32U5_TIM16_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM16_OR (STM32U5_TIM16_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM17_CR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM17_CR2 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM17_DIER (STM32U5_TIM17_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM17_SR (STM32U5_TIM17_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM17_EGR (STM32U5_TIM17_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM17_CCMR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM17_CCER (STM32U5_TIM17_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM17_CNT (STM32U5_TIM17_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM17_PSC (STM32U5_TIM17_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM17_ARR (STM32U5_TIM17_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM17_RCR (STM32U5_TIM17_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM17_CCR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM17_BDTR (STM32U5_TIM17_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM17_DCR (STM32U5_TIM17_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM17_DMAR (STM32U5_TIM17_BASE + STM32U5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_TIM6_CR1 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM6_CR2 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM6_DIER (STM32U5_TIM6_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM6_SR (STM32U5_TIM6_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM6_EGR (STM32U5_TIM6_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM6_CNT (STM32U5_TIM6_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM6_PSC (STM32U5_TIM6_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM6_ARR (STM32U5_TIM6_BASE + STM32U5_BTIM_ARR_OFFSET) - -#define STM32U5_TIM7_CR1 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM7_CR2 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM7_DIER (STM32U5_TIM7_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM7_SR (STM32U5_TIM7_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM7_EGR (STM32U5_TIM7_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM7_CNT (STM32U5_TIM7_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM7_PSC (STM32U5_TIM7_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM7_ARR (STM32U5_TIM7_BASE + STM32U5_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index 56fc25f062412..20bb8da66544c 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -41,31 +41,31 @@ /* Register Offsets *********************************************************/ -#define STM32U5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32U5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32U5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32U5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32U5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32U5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32U5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32U5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32U5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32U5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32U5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32U5_SYSCFG_SECCFGR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SECCFGR_OFFSET) -#define STM32U5_SYSCFG_CFGR1 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR1_OFFSET) -#define STM32U5_SYSCFG_FPUIMR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_FPUIMR_OFFSET) -#define STM32U5_SYSCFG_CNSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CNSLCKR_OFFSET) -#define STM32U5_SYSCFG_CSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CSLCKR_OFFSET) -#define STM32U5_SYSCFG_CFGR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR2_OFFSET) -#define STM32U5_SYSCFG_SCSR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SCSR_OFFSET) -#define STM32U5_SYSCFG_SKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SKR_OFFSET) -#define STM32U5_SYSCFG_SWPR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR_OFFSET) -#define STM32U5_SYSCFG_SWPR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR2_OFFSET) -#define STM32U5_SYSCFG_RSSCMDR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/stm32_rcc.c b/arch/arm/src/stm32u5/stm32_rcc.c index aa334d993051d..2b2972cde7247 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.c +++ b/arch/arm/src/stm32u5/stm32_rcc.c @@ -93,14 +93,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32U5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32U5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -113,19 +113,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32U5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32U5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32U5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32U5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32_pwr_enablebkp(false); diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 5e15c461d1872..7dbdba50ce4dc 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -305,16 +305,16 @@ static const struct stm32_tim_ops_s stm32_tim_ops = struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32U5_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -322,8 +322,8 @@ struct stm32_tim_priv_s stm32_tim2_priv = struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -331,8 +331,8 @@ struct stm32_tim_priv_s stm32_tim3_priv = struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -340,8 +340,8 @@ struct stm32_tim_priv_s stm32_tim4_priv = struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -349,8 +349,8 @@ struct stm32_tim_priv_s stm32_tim5_priv = struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -358,8 +358,8 @@ struct stm32_tim_priv_s stm32_tim6_priv = struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -367,8 +367,8 @@ struct stm32_tim_priv_s stm32_tim7_priv = struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -376,8 +376,8 @@ struct stm32_tim_priv_s stm32_tim8_priv = struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -385,8 +385,8 @@ struct stm32_tim_priv_s stm32_tim15_priv = struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -394,8 +394,8 @@ struct stm32_tim_priv_s stm32_tim16_priv = struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32U5_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32_tim_enable(struct stm32_tim_dev_s *dev) static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32_tim_disable(struct stm32_tim_dev_s *dev) static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_DISABLED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32U5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32U5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32U5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32U5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32U5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32U5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, break; - case STM32U5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32U5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32_modifyreg16(dev, STM32U5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -655,66 +655,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, prescaler = 0xffff; } - stm32_putreg16(dev, STM32U5_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -770,64 +770,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32_getreg16(dev, STM32U5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32U5_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32U5_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,7 +869,7 @@ static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32U5_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -879,10 +879,10 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32U5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32_getreg16(dev, STM32U5_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32U5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32U5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32U5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32U5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32U5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32U5_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1021,7 +1021,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1054,7 +1054,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1087,7 +1087,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1119,7 +1119,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1152,7 +1152,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1185,7 +1185,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1218,7 +1218,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1251,7 +1251,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - stm32_putreg32(dev, STM32U5_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32_putreg32(dev, STM32U5_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32_putreg32(dev, STM32U5_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32_putreg32(dev, STM32U5_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - return stm32_getreg32(dev, STM32U5_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32_getreg32(dev, STM32U5_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32_getreg32(dev, STM32U5_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32_getreg32(dev, STM32U5_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1367,66 +1367,66 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - vectorno = STM32U5_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - vectorno = STM32U5_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - vectorno = STM32U5_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - vectorno = STM32U5_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - vectorno = STM32U5_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - vectorno = STM32U5_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - vectorno = STM32U5_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - vectorno = STM32U5_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - vectorno = STM32U5_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - vectorno = STM32U5_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - vectorno = STM32U5_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32U5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32_getreg16(dev, STM32U5_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1512,76 +1512,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) #ifdef CONFIG_STM32U5_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32U5_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32U5_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32U5_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32U5_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32U5_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32U5_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32U5_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32U5_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32U5_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32U5_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32_tim_priv_s *)dev)->mode != STM32U5_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1617,67 +1617,67 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,7 +1687,7 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32u5/stm32_tim.h b/arch/arm/src/stm32u5/stm32_tim.h index e043e98f0e0b3..f61751552dd49 100644 --- a/arch/arm/src/stm32u5/stm32_tim.h +++ b/arch/arm/src/stm32u5/stm32_tim.h @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32U5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32U5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32U5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32U5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32U5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32U5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32U5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32U5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32U5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32U5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32U5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32U5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32U5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32U5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32_tim_dev_s enum stm32_tim_mode_e { - STM32U5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32U5_TIM_MODE_MASK = 0x0310, - STM32U5_TIM_MODE_DISABLED = 0x0000, - STM32U5_TIM_MODE_UP = 0x0100, - STM32U5_TIM_MODE_DOWN = 0x0110, - STM32U5_TIM_MODE_UPDOWN = 0x0200, - STM32U5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32U5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32U5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32U5_TIM_MODE_CK_EXT = 0x0800, - STM32U5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32U5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32U5_TIM_MODE_CK_CH1 = 0x0001, - STM32U5_TIM_MODE_CK_CH2 = 0x0002, - STM32U5_TIM_MODE_CK_CH3 = 0x0003, - STM32U5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,22 +118,22 @@ enum stm32_tim_mode_e enum stm32_tim_channel_e { - STM32U5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32U5_TIM_CH_POLARITY_POS = 0x00, - STM32U5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32U5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32U5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32U5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ diff --git a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c index 92e5739a23329..7752a4fda1bce 100644 --- a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c @@ -52,17 +52,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32U5_TIM1_RES 16 -#define STM32U5_TIM2_RES 32 -#define STM32U5_TIM3_RES 16 -#define STM32U5_TIM4_RES 16 -#define STM32U5_TIM5_RES 32 -#define STM32U5_TIM6_RES 16 -#define STM32U5_TIM7_RES 16 -#define STM32U5_TIM8_RES 16 -#define STM32U5_TIM15_RES 16 -#define STM32U5_TIM16_RES 16 -#define STM32U5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -122,7 +122,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -130,7 +130,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -138,7 +138,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif @@ -146,7 +146,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif @@ -154,7 +154,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif @@ -162,7 +162,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif @@ -170,7 +170,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif @@ -178,7 +178,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif @@ -186,7 +186,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif @@ -194,7 +194,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -202,7 +202,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32_timer_handler(int irq, void *context, void *arg) (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32U5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32U5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_DISABLED); - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32U5_TIM_GETCLOCK(priv->tim); - period = STM32U5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32U5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32U5_TIM_SETCLOCK(priv->tim, freq); - STM32U5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32U5_TIM_SETCLOCK(priv->tim, 1000000); - STM32U5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32u5/stm32_uid.c b/arch/arm/src/stm32u5/stm32_uid.c index 55b3aa8e82a53..479826dafd2a5 100644 --- a/arch/arm/src/stm32u5/stm32_uid.c +++ b/arch/arm/src/stm32u5/stm32_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32_memorymap.h" #include "stm32_uid.h" -#ifdef STM32U5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32U5_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32U5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32wb/chip.h b/arch/arm/src/stm32wb/chip.h index 1c263402e683c..cddd9871d0351 100644 --- a/arch/arm/src/stm32wb/chip.h +++ b/arch/arm/src/stm32wb/chip.h @@ -49,7 +49,7 @@ * arch/stm32wb/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WB_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32WB */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_crs.h b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h index fcac2dde6db3f..946f0fe73c762 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_crs.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h @@ -29,17 +29,17 @@ /* Register Offsets *********************************************************/ -#define STM32WB_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32WB_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32WB_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32WB_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ /* Register Addresses *******************************************************/ -#define STM32WB_CRS_CR (STM32WB_CRS_BASE + STM32WB_CRS_CR_OFFSET) -#define STM32WB_CRS_CFGR (STM32WB_CRS_BASE + STM32WB_CRS_CFGR_OFFSET) -#define STM32WB_CRS_ISR (STM32WB_CRS_BASE + STM32WB_CRS_ISR_OFFSET) -#define STM32WB_CRS_ICR (STM32WB_CRS_BASE + STM32WB_CRS_ICR_OFFSET) +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dma.h b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h index dfd6e1050dbfe..a87c1aaf3d1a1 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h @@ -41,139 +41,139 @@ /* Register Offsets *********************************************************/ -#define STM32WB_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32WB_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32WB_DMACHAN_OFFSET(n) (0x0014 * (n)) -#define STM32WB_DMACHAN1_OFFSET 0x0000 -#define STM32WB_DMACHAN2_OFFSET 0x0014 -#define STM32WB_DMACHAN3_OFFSET 0x0028 -#define STM32WB_DMACHAN4_OFFSET 0x003c -#define STM32WB_DMACHAN5_OFFSET 0x0050 -#define STM32WB_DMACHAN6_OFFSET 0x0064 -#define STM32WB_DMACHAN7_OFFSET 0x0078 - -#define STM32WB_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32WB_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32WB_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32WB_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32WB_DMA_CCR_OFFSET(n) (STM32WB_DMACHAN_CCR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CNDTR_OFFSET(n) (STM32WB_DMACHAN_CNDTR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CPAR_OFFSET(n) (STM32WB_DMACHAN_CPAR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CMAR_OFFSET(n) (STM32WB_DMACHAN_CMAR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) - -#define STM32WB_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32WB_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32WB_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32WB_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32WB_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32WB_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32WB_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32WB_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32WB_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32WB_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32WB_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32WB_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32WB_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32WB_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32WB_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32WB_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32WB_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32WB_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32WB_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32WB_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32WB_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32WB_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32WB_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32WB_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32WB_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32WB_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32WB_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32WB_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014 * (n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ /* Register Addresses *******************************************************/ -#define STM32WB_DMA1_ISRC (STM32WB_DMA1_BASE + STM32WB_DMA_ISR_OFFSET) -#define STM32WB_DMA1_IFCR (STM32WB_DMA1_BASE + STM32WB_DMA_IFCR_OFFSET) - -#define STM32WB_DMA1_CCR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CCR_OFFSET(n)) -#define STM32WB_DMA1_CCR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR1_OFFSET) -#define STM32WB_DMA1_CCR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR2_OFFSET) -#define STM32WB_DMA1_CCR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR3_OFFSET) -#define STM32WB_DMA1_CCR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR4_OFFSET) -#define STM32WB_DMA1_CCR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR5_OFFSET) -#define STM32WB_DMA1_CCR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR6_OFFSET) -#define STM32WB_DMA1_CCR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR7_OFFSET) - -#define STM32WB_DMA1_CNDTR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR_OFFSET(n)) -#define STM32WB_DMA1_CNDTR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR1_OFFSET) -#define STM32WB_DMA1_CNDTR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR2_OFFSET) -#define STM32WB_DMA1_CNDTR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR3_OFFSET) -#define STM32WB_DMA1_CNDTR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR4_OFFSET) -#define STM32WB_DMA1_CNDTR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR5_OFFSET) -#define STM32WB_DMA1_CNDTR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR6_OFFSET) -#define STM32WB_DMA1_CNDTR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR7_OFFSET) - -#define STM32WB_DMA1_CPAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR_OFFSET(n)) -#define STM32WB_DMA1_CPAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR1_OFFSET) -#define STM32WB_DMA1_CPAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR2_OFFSET) -#define STM32WB_DMA1_CPAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR3_OFFSET) -#define STM32WB_DMA1_CPAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR4_OFFSET) -#define STM32WB_DMA1_CPAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR5_OFFSET) -#define STM32WB_DMA1_CPAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR6_OFFSET) -#define STM32WB_DMA1_CPAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR7_OFFSET) - -#define STM32WB_DMA1_CMAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR_OFFSET(n)) -#define STM32WB_DMA1_CMAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR1_OFFSET) -#define STM32WB_DMA1_CMAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR2_OFFSET) -#define STM32WB_DMA1_CMAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR3_OFFSET) -#define STM32WB_DMA1_CMAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR4_OFFSET) -#define STM32WB_DMA1_CMAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR5_OFFSET) -#define STM32WB_DMA1_CMAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR6_OFFSET) -#define STM32WB_DMA1_CMAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR7_OFFSET) - -#define STM32WB_DMA2_ISRC (STM32WB_DMA2_BASE + STM32WB_DMA_ISR_OFFSET) -#define STM32WB_DMA2_IFCR (STM32WB_DMA2_BASE + STM32WB_DMA_IFCR_OFFSET) - -#define STM32WB_DMA2_CCR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CCR_OFFSET(n)) -#define STM32WB_DMA2_CCR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR1_OFFSET) -#define STM32WB_DMA2_CCR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR2_OFFSET) -#define STM32WB_DMA2_CCR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR3_OFFSET) -#define STM32WB_DMA2_CCR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR4_OFFSET) -#define STM32WB_DMA2_CCR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR5_OFFSET) -#define STM32WB_DMA2_CCR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR6_OFFSET) -#define STM32WB_DMA2_CCR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR7_OFFSET) - -#define STM32WB_DMA2_CNDTR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR_OFFSET(n)) -#define STM32WB_DMA2_CNDTR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR1_OFFSET) -#define STM32WB_DMA2_CNDTR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR2_OFFSET) -#define STM32WB_DMA2_CNDTR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR3_OFFSET) -#define STM32WB_DMA2_CNDTR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR4_OFFSET) -#define STM32WB_DMA2_CNDTR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR5_OFFSET) -#define STM32WB_DMA2_CNDTR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR6_OFFSET) -#define STM32WB_DMA2_CNDTR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR7_OFFSET) - -#define STM32WB_DMA2_CPAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR_OFFSET(n)) -#define STM32WB_DMA2_CPAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR1_OFFSET) -#define STM32WB_DMA2_CPAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR2_OFFSET) -#define STM32WB_DMA2_CPAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR3_OFFSET) -#define STM32WB_DMA2_CPAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR4_OFFSET) -#define STM32WB_DMA2_CPAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR5_OFFSET) -#define STM32WB_DMA2_CPAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR6_OFFSET) -#define STM32WB_DMA2_CPAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR7_OFFSET) - -#define STM32WB_DMA2_CMAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR_OFFSET(n)) -#define STM32WB_DMA2_CMAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR1_OFFSET) -#define STM32WB_DMA2_CMAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR2_OFFSET) -#define STM32WB_DMA2_CMAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR3_OFFSET) -#define STM32WB_DMA2_CMAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR4_OFFSET) -#define STM32WB_DMA2_CMAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR5_OFFSET) -#define STM32WB_DMA2_CMAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR6_OFFSET) -#define STM32WB_DMA2_CMAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE + STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE + STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE + STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE + STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h index f4a8b5d47c9e2..929269f5a6d93 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h @@ -39,64 +39,65 @@ /* Register Offsets *********************************************************/ -#define STM32WB_DMAMUX_CXCR_OFFSET(x) (0x0000 + 0x0004 * (x)) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32WB_DMAMUX_C0CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(0) -#define STM32WB_DMAMUX_C1CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(1) -#define STM32WB_DMAMUX_C2CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(2) -#define STM32WB_DMAMUX_C3CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(3) -#define STM32WB_DMAMUX_C4CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(4) -#define STM32WB_DMAMUX_C5CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(5) -#define STM32WB_DMAMUX_C6CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(6) -#define STM32WB_DMAMUX_C7CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(7) -#define STM32WB_DMAMUX_C8CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(8) -#define STM32WB_DMAMUX_C9CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(9) -#define STM32WB_DMAMUX_C10CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(10) -#define STM32WB_DMAMUX_C11CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(11) -#define STM32WB_DMAMUX_C12CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(12) -#define STM32WB_DMAMUX_C13CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(13) - /* 0x034-0x07C: Reserved */ -#define STM32WB_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32WB_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ - -#define STM32WB_DMAMUX_RGXCR_OFFSET(x) (0x0100 + 0x004 * (x)) /* DMAMUX1 request generator channel x configuration register */ -#define STM32WB_DMAMUX_RG0CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(0) -#define STM32WB_DMAMUX_RG1CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(1) -#define STM32WB_DMAMUX_RG2CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(2) -#define STM32WB_DMAMUX_RG3CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(3) -#define STM32WB_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32WB_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3fc: Reserved */ +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000 + 0x0004 * (x)) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) +/* 0x034-0x07C: Reserved */ + +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ + +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100 + 0x004 * (x)) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3fc: Reserved */ /* Register Addresses *******************************************************/ -#define STM32WB_DMAMUX1_CXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CXCR_OFFSET(x)) -#define STM32WB_DMAMUX1_C0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C0CR_OFFSET) -#define STM32WB_DMAMUX1_C1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C1CR_OFFSET) -#define STM32WB_DMAMUX1_C2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C2CR_OFFSET) -#define STM32WB_DMAMUX1_C3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C3CR_OFFSET) -#define STM32WB_DMAMUX1_C4CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C4CR_OFFSET) -#define STM32WB_DMAMUX1_C5CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C5CR_OFFSET) -#define STM32WB_DMAMUX1_C6CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C6CR_OFFSET) -#define STM32WB_DMAMUX1_C7CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C7CR_OFFSET) -#define STM32WB_DMAMUX1_C8CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C8CR_OFFSET) -#define STM32WB_DMAMUX1_C9CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C9CR_OFFSET) -#define STM32WB_DMAMUX1_C10CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C10CR_OFFSET) -#define STM32WB_DMAMUX1_C11CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C11CR_OFFSET) -#define STM32WB_DMAMUX1_C12CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C12CR_OFFSET) -#define STM32WB_DMAMUX1_C13CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C13CR_OFFSET) - -#define STM32WB_DMAMUX1_CSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CSR_OFFSET) -#define STM32WB_DMAMUX1_CFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CFR_OFFSET) - -#define STM32WB_DMAMUX1_RGXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGXCR_OFFSET(x)) -#define STM32WB_DMAMUX1_RG0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG0CR_OFFSET) -#define STM32WB_DMAMUX1_RG1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG1CR_OFFSET) -#define STM32WB_DMAMUX1_RG2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG2CR_OFFSET) -#define STM32WB_DMAMUX1_RG3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG3CR_OFFSET) - -#define STM32WB_DMAMUX1_RGSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGSR_OFFSET) -#define STM32WB_DMAMUX1_RGCFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGCFR_OFFSET) +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C13CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGCFR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_exti.h b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h index 1169438501b3d..2c6bba71c1d79 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_exti.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h @@ -36,41 +36,41 @@ /* Register Offsets *********************************************************/ -#define STM32WB_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection register 1 */ -#define STM32WB_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection register 1 */ -#define STM32WB_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ -#define STM32WB_EXTI_PR1_OFFSET 0x000c /* Pending register 1 */ -#define STM32WB_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection register 2 */ -#define STM32WB_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection register 2 */ -#define STM32WB_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event register 2 */ -#define STM32WB_EXTI_PR2_OFFSET 0x002c /* Pending register 2 */ -#define STM32WB_EXTI_C1IMR1_OFFSET 0x0080 /* CPU1 wakeup with interrupt mask register 1 */ -#define STM32WB_EXTI_C1EMR1_OFFSET 0x0084 /* CPU1 wakeup with event mask register 1 */ -#define STM32WB_EXTI_C1IMR2_OFFSET 0x0090 /* CPU1 wakeup with interrupt mask register 2 */ -#define STM32WB_EXTI_C1EMR2_OFFSET 0x0094 /* CPU1 wakeup with event mask register 2 */ -#define STM32WB_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU2 wakeup with interrupt mask register 1 */ -#define STM32WB_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU2 wakeup with event mask register 1 */ -#define STM32WB_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU2 wakeup with interrupt mask register 2 */ -#define STM32WB_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU2 wakeup with event mask register 2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection register 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection register 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ +#define STM32_EXTI_PR1_OFFSET 0x000c /* Pending register 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection register 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection register 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event register 2 */ +#define STM32_EXTI_PR2_OFFSET 0x002c /* Pending register 2 */ +#define STM32_EXTI_C1IMR1_OFFSET 0x0080 /* CPU1 wakeup with interrupt mask register 1 */ +#define STM32_EXTI_C1EMR1_OFFSET 0x0084 /* CPU1 wakeup with event mask register 1 */ +#define STM32_EXTI_C1IMR2_OFFSET 0x0090 /* CPU1 wakeup with interrupt mask register 2 */ +#define STM32_EXTI_C1EMR2_OFFSET 0x0094 /* CPU1 wakeup with event mask register 2 */ +#define STM32_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU2 wakeup with interrupt mask register 1 */ +#define STM32_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU2 wakeup with event mask register 1 */ +#define STM32_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU2 wakeup with interrupt mask register 2 */ +#define STM32_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU2 wakeup with event mask register 2 */ /* Register Addresses *******************************************************/ -#define STM32WB_EXTI_RTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR1_OFFSET) -#define STM32WB_EXTI_FTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR1_OFFSET) -#define STM32WB_EXTI_SWIER1 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER1_OFFSET) -#define STM32WB_EXTI_PR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR1_OFFSET) -#define STM32WB_EXTI_RTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR2_OFFSET) -#define STM32WB_EXTI_FTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR2_OFFSET) -#define STM32WB_EXTI_SWIER2 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER2_OFFSET) -#define STM32WB_EXTI_PR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR2_OFFSET) -#define STM32WB_EXTI_C1IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR1_OFFSET) -#define STM32WB_EXTI_C1EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR1_OFFSET) -#define STM32WB_EXTI_C1IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR2_OFFSET) -#define STM32WB_EXTI_C1EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR2_OFFSET) -#define STM32WB_EXTI_C2IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR1_OFFSET) -#define STM32WB_EXTI_C2EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR1_OFFSET) -#define STM32WB_EXTI_C2IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR2_OFFSET) -#define STM32WB_EXTI_C2EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_PR1 (STM32_EXTI_BASE + STM32_EXTI_PR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_PR2 (STM32_EXTI_BASE + STM32_EXTI_PR2_OFFSET) +#define STM32_EXTI_C1IMR1 (STM32_EXTI_BASE + STM32_EXTI_C1IMR1_OFFSET) +#define STM32_EXTI_C1EMR1 (STM32_EXTI_BASE + STM32_EXTI_C1EMR1_OFFSET) +#define STM32_EXTI_C1IMR2 (STM32_EXTI_BASE + STM32_EXTI_C1IMR2_OFFSET) +#define STM32_EXTI_C1EMR2 (STM32_EXTI_BASE + STM32_EXTI_C1EMR2_OFFSET) +#define STM32_EXTI_C2IMR1 (STM32_EXTI_BASE + STM32_EXTI_C2IMR1_OFFSET) +#define STM32_EXTI_C2EMR1 (STM32_EXTI_BASE + STM32_EXTI_C2EMR1_OFFSET) +#define STM32_EXTI_C2IMR2 (STM32_EXTI_BASE + STM32_EXTI_C2IMR2_OFFSET) +#define STM32_EXTI_C2EMR2 (STM32_EXTI_BASE + STM32_EXTI_C2EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h index 8f2fe45b9dd27..90991b1ee21e9 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h @@ -87,67 +87,67 @@ /* Define the valid configuration */ -#define STM32WB_FLASH_PAGESIZE 4096 +#define STM32_FLASH_PAGESIZE 4096 #if defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) /* 256 kB */ -# define STM32WB_FLASH_NPAGES 64 +# define STM32_FLASH_NPAGES 64 #elif defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) /* 320 kB */ -# define STM32WB_FLASH_NPAGES 80 +# define STM32_FLASH_NPAGES 80 #elif defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) /* 512 kB */ -# define STM32WB_FLASH_NPAGES 128 +# define STM32_FLASH_NPAGES 128 #elif defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) /* 640 kB */ -# define STM32WB_FLASH_NPAGES 160 +# define STM32_FLASH_NPAGES 160 #elif defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) /* 1 MB */ -# define STM32WB_FLASH_NPAGES 256 +# define STM32_FLASH_NPAGES 256 #else # error "Unknown flash configuration!" #endif -#define STM32WB_FLASH_SIZE (STM32WB_FLASH_NPAGES * STM32WB_FLASH_PAGESIZE) +#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) /* Register Offsets *********************************************************/ -#define STM32WB_FLASH_ACR_OFFSET 0x0000 /* Flash Access Control Register */ -#define STM32WB_FLASH_KEYR_OFFSET 0x0008 /* Flash Key Register */ -#define STM32WB_FLASH_OPTKEYR_OFFSET 0x000c /* Flash Option Key Register */ -#define STM32WB_FLASH_SR_OFFSET 0x0010 /* Flash Status Register */ -#define STM32WB_FLASH_CR_OFFSET 0x0014 /* Flash Control Register */ -#define STM32WB_FLASH_ECCR_OFFSET 0x0018 /* Flash ECC Register */ -#define STM32WB_FLASH_OPTR_OFFSET 0x0020 /* Flash Option Register */ -#define STM32WB_FLASH_PCROP1ASR_OFFSET 0x0024 /* Flash PCROP zone A Start address Register */ -#define STM32WB_FLASH_PCROP1AER_OFFSET 0x0028 /* Flash PCROP zone A End address Register */ -#define STM32WB_FLASH_WRP1AR_OFFSET 0x002c /* Flash WRP area A Address Register */ -#define STM32WB_FLASH_WRP1BR_OFFSET 0x0030 /* Flash WRP area B Address Register */ -#define STM32WB_FLASH_PCROP1BSR_OFFSET 0x0034 /* Flash PCROP zone B Start address Register */ -#define STM32WB_FLASH_PCROP1BER_OFFSET 0x0038 /* Flash PCROP zone B End address Register */ -#define STM32WB_FLASH_IPCCBR_OFFSET 0x003C /* Flash IPCC mailbox data buffer address Register */ -#define STM32WB_FLASH_C2ACR_OFFSET 0x005C /* CPU2 flash Access Control Register */ -#define STM32WB_FLASH_C2SR_OFFSET 0x0060 /* CPU2 flash Status Register */ -#define STM32WB_FLASH_C2CR_OFFSET 0x0064 /* CPU2 flash Control Register */ -#define STM32WB_FLASH_SFR_OFFSET 0x0080 /* Secure Flash start address Register */ -#define STM32WB_FLASH_SRRVR_OFFSET 0x0084 /* SRAM2 start address and CPU2 Reset Vector Register */ +#define STM32_FLASH_ACR_OFFSET 0x0000 /* Flash Access Control Register */ +#define STM32_FLASH_KEYR_OFFSET 0x0008 /* Flash Key Register */ +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c /* Flash Option Key Register */ +#define STM32_FLASH_SR_OFFSET 0x0010 /* Flash Status Register */ +#define STM32_FLASH_CR_OFFSET 0x0014 /* Flash Control Register */ +#define STM32_FLASH_ECCR_OFFSET 0x0018 /* Flash ECC Register */ +#define STM32_FLASH_OPTR_OFFSET 0x0020 /* Flash Option Register */ +#define STM32_FLASH_PCROP1ASR_OFFSET 0x0024 /* Flash PCROP zone A Start address Register */ +#define STM32_FLASH_PCROP1AER_OFFSET 0x0028 /* Flash PCROP zone A End address Register */ +#define STM32_FLASH_WRP1AR_OFFSET 0x002c /* Flash WRP area A Address Register */ +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 /* Flash WRP area B Address Register */ +#define STM32_FLASH_PCROP1BSR_OFFSET 0x0034 /* Flash PCROP zone B Start address Register */ +#define STM32_FLASH_PCROP1BER_OFFSET 0x0038 /* Flash PCROP zone B End address Register */ +#define STM32_FLASH_IPCCBR_OFFSET 0x003C /* Flash IPCC mailbox data buffer address Register */ +#define STM32_FLASH_C2ACR_OFFSET 0x005C /* CPU2 flash Access Control Register */ +#define STM32_FLASH_C2SR_OFFSET 0x0060 /* CPU2 flash Status Register */ +#define STM32_FLASH_C2CR_OFFSET 0x0064 /* CPU2 flash Control Register */ +#define STM32_FLASH_SFR_OFFSET 0x0080 /* Secure Flash start address Register */ +#define STM32_FLASH_SRRVR_OFFSET 0x0084 /* SRAM2 start address and CPU2 Reset Vector Register */ /* Register Addresses *******************************************************/ -#define STM32WB_FLASH_ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ACR_OFFSET) -#define STM32WB_FLASH_KEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_KEYR_OFFSET) -#define STM32WB_FLASH_OPTKEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTKEYR_OFFSET) -#define STM32WB_FLASH_SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SR_OFFSET) -#define STM32WB_FLASH_CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_CR_OFFSET) -#define STM32WB_FLASH_ECCR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ECCR_OFFSET) -#define STM32WB_FLASH_OPTR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTR_OFFSET) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1ASR_OFFSET) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1AER_OFFSET) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1AR_OFFSET) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1BR_OFFSET) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BSR_OFFSET) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BER_OFFSET) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_IPCCBR_OFFSET) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2ACR_OFFSET) -#define STM32WB_FLASH_C2SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2SR_OFFSET) -#define STM32WB_FLASH_C2CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2CR_OFFSET) -#define STM32WB_FLASH_SFR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SFR_OFFSET) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SRRVR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHREG_BASE + STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHREG_BASE + STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHREG_BASE + STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHREG_BASE + STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHREG_BASE + STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHREG_BASE + STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHREG_BASE + STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1ASR (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1ASR_OFFSET) +#define STM32_FLASH_PCROP1AER (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1AER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHREG_BASE + STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHREG_BASE + STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_PCROP1BSR (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1BSR_OFFSET) +#define STM32_FLASH_PCROP1BER (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1BER_OFFSET) +#define STM32_FLASH_IPCCBR (STM32_FLASHREG_BASE + STM32_FLASH_IPCCBR_OFFSET) +#define STM32_FLASH_C2ACR (STM32_FLASHREG_BASE + STM32_FLASH_C2ACR_OFFSET) +#define STM32_FLASH_C2SR (STM32_FLASHREG_BASE + STM32_FLASH_C2SR_OFFSET) +#define STM32_FLASH_C2CR (STM32_FLASHREG_BASE + STM32_FLASH_C2CR_OFFSET) +#define STM32_FLASH_SFR (STM32_FLASHREG_BASE + STM32_FLASH_SFR_OFFSET) +#define STM32_FLASH_SRRVR (STM32_FLASHREG_BASE + STM32_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h index cc3b862168732..390dc47c2e028 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32WB_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32WB_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32WB_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32WB_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32WB_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32WB_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32WB_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32WB_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32WB_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32WB_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32WB_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32WB_GPIOA_MODER (STM32WB_GPIOA_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOA_OTYPER (STM32WB_GPIOA_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOA_OSPEED (STM32WB_GPIOA_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOA_PUPDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOA_IDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOA_ODR (STM32WB_GPIOA_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOA_BSRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOA_LCKR (STM32WB_GPIOA_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOA_AFRL (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOA_AFRH (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOA_BRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BRR_OFFSET) - -#define STM32WB_GPIOB_MODER (STM32WB_GPIOB_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOB_OTYPER (STM32WB_GPIOB_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOB_OSPEED (STM32WB_GPIOB_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOB_PUPDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOB_IDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOB_ODR (STM32WB_GPIOB_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOB_BSRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOB_LCKR (STM32WB_GPIOB_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOB_AFRL (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOB_AFRH (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOB_BRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BRR_OFFSET) - -#define STM32WB_GPIOC_MODER (STM32WB_GPIOC_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOC_OTYPER (STM32WB_GPIOC_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOC_OSPEED (STM32WB_GPIOC_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOC_PUPDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOC_IDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOC_ODR (STM32WB_GPIOC_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOC_BSRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOC_LCKR (STM32WB_GPIOC_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOC_AFRL (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOC_AFRH (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOC_BRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) + +#define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) + +#define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) #if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) -# define STM32WB_GPIOD_MODER (STM32WB_GPIOD_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOD_OTYPER (STM32WB_GPIOD_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOD_OSPEED (STM32WB_GPIOD_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOD_PUPDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOD_IDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOD_ODR (STM32WB_GPIOD_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOD_BSRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOD_LCKR (STM32WB_GPIOD_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOD_AFRL (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOD_AFRH (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRH_OFFSET) -# define STM32WB_GPIOD_BRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BRR_OFFSET) +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) #endif #if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_GPIOE_MODER (STM32WB_GPIOE_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOE_OTYPER (STM32WB_GPIOE_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOE_OSPEED (STM32WB_GPIOE_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOE_PUPDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOE_IDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOE_ODR (STM32WB_GPIOE_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOE_BSRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOE_LCKR (STM32WB_GPIOE_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOE_AFRL (STM32WB_GPIOE_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOE_BRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BRR_OFFSET) +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) #endif -#define STM32WB_GPIOH_MODER (STM32WB_GPIOH_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOH_OTYPER (STM32WB_GPIOH_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOH_OSPEED (STM32WB_GPIOH_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOH_PUPDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOH_IDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOH_ODR (STM32WB_GPIOH_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOH_BSRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOH_LCKR (STM32WB_GPIOH_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOH_AFRL (STM32WB_GPIOH_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOH_BRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h index 0e86bb6467542..d5e25cae2f57c 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h @@ -29,44 +29,44 @@ /* Register Offsets *********************************************************/ -#define STM32WB_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32WB_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32WB_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32WB_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32WB_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32WB_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32WB_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32WB_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32WB_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32WB_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32WB_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#define STM32WB_I2C1_CR1 (STM32WB_I2C1_BASE + STM32WB_I2C_CR1_OFFSET) -#define STM32WB_I2C1_CR2 (STM32WB_I2C1_BASE + STM32WB_I2C_CR2_OFFSET) -#define STM32WB_I2C1_OAR1 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR1_OFFSET) -#define STM32WB_I2C1_OAR2 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR2_OFFSET) -#define STM32WB_I2C1_TIMINGR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMINGR_OFFSET) -#define STM32WB_I2C1_TIMEOUTR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -#define STM32WB_I2C1_ISR (STM32WB_I2C1_BASE + STM32WB_I2C_ISR_OFFSET) -#define STM32WB_I2C1_ICR (STM32WB_I2C1_BASE + STM32WB_I2C_ICR_OFFSET) -#define STM32WB_I2C1_PECR (STM32WB_I2C1_BASE + STM32WB_I2C_PECR_OFFSET) -#define STM32WB_I2C1_RXDR (STM32WB_I2C1_BASE + STM32WB_I2C_RXDR_OFFSET) -#define STM32WB_I2C1_TXDR (STM32WB_I2C1_BASE + STM32WB_I2C_TXDR_OFFSET) +#define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) +#define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET) +#define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET) +#define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET) +#define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET) +#define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET) +#define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET) +#define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET) +#define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET) +#define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) +#define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) #ifdef CONFIG_STM32WB_HAVE_I2C3 -# define STM32WB_I2C3_CR1 (STM32WB_I2C3_BASE + STM32WB_I2C_CR1_OFFSET) -# define STM32WB_I2C3_CR2 (STM32WB_I2C3_BASE + STM32WB_I2C_CR2_OFFSET) -# define STM32WB_I2C3_OAR1 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR1_OFFSET) -# define STM32WB_I2C3_OAR2 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR2_OFFSET) -# define STM32WB_I2C3_TIMINGR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMINGR_OFFSET) -# define STM32WB_I2C3_TIMEOUTR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -# define STM32WB_I2C3_ISR (STM32WB_I2C3_BASE + STM32WB_I2C_ISR_OFFSET) -# define STM32WB_I2C3_ICR (STM32WB_I2C3_BASE + STM32WB_I2C_ICR_OFFSET) -# define STM32WB_I2C3_PECR (STM32WB_I2C3_BASE + STM32WB_I2C_PECR_OFFSET) -# define STM32WB_I2C3_RXDR (STM32WB_I2C3_BASE + STM32WB_I2C_RXDR_OFFSET) -# define STM32WB_I2C3_TXDR (STM32WB_I2C3_BASE + STM32WB_I2C_TXDR_OFFSET) +# define STM32_I2C3_CR1 (STM32_I2C3_BASE + STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE + STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE + STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE + STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE + STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE + STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE + STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE + STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE + STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE + STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE + STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h index 6e1d597ff1c1b..8e42686f3106d 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h @@ -29,25 +29,25 @@ /* Register Offsets *********************************************************/ -#define STM32WB_IPCC_C1CR_OFFSET 0x0000 /* CPU1 control register */ -#define STM32WB_IPCC_C1MR_OFFSET 0x0004 /* CPU1 mask register */ -#define STM32WB_IPCC_C1SCR_OFFSET 0x0008 /* CPU1 status set/clear register */ -#define STM32WB_IPCC_C1TOC2SR_OFFSET 0x000c /* CPU1 to CPU2 status register */ -#define STM32WB_IPCC_C2CR_OFFSET 0x0010 /* CPU2 control register */ -#define STM32WB_IPCC_C2MR_OFFSET 0x0014 /* CPU2 mask register */ -#define STM32WB_IPCC_C2SCR_OFFSET 0x0018 /* CPU2 status set/clear register */ -#define STM32WB_IPCC_C2TOC1SR_OFFSET 0x001c /* CPU2 to CPU1 status register */ +#define STM32_IPCC_C1CR_OFFSET 0x0000 /* CPU1 control register */ +#define STM32_IPCC_C1MR_OFFSET 0x0004 /* CPU1 mask register */ +#define STM32_IPCC_C1SCR_OFFSET 0x0008 /* CPU1 status set/clear register */ +#define STM32_IPCC_C1TOC2SR_OFFSET 0x000c /* CPU1 to CPU2 status register */ +#define STM32_IPCC_C2CR_OFFSET 0x0010 /* CPU2 control register */ +#define STM32_IPCC_C2MR_OFFSET 0x0014 /* CPU2 mask register */ +#define STM32_IPCC_C2SCR_OFFSET 0x0018 /* CPU2 status set/clear register */ +#define STM32_IPCC_C2TOC1SR_OFFSET 0x001c /* CPU2 to CPU1 status register */ /* Register Addresses *******************************************************/ -#define STM32WB_IPCC_C1CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1CR_OFFSET) -#define STM32WB_IPCC_C1MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1MR_OFFSET) -#define STM32WB_IPCC_C1SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1SCR_OFFSET) -#define STM32WB_IPCC_C1TOC2SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1TOC2SR_OFFSET) -#define STM32WB_IPCC_C2CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2CR_OFFSET) -#define STM32WB_IPCC_C2MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2MR_OFFSET) -#define STM32WB_IPCC_C2SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2SCR_OFFSET) -#define STM32WB_IPCC_C2TOC1SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2TOC1SR_OFFSET) +#define STM32_IPCC_C1CR (STM32_IPCC_BASE + STM32_IPCC_C1CR_OFFSET) +#define STM32_IPCC_C1MR (STM32_IPCC_BASE + STM32_IPCC_C1MR_OFFSET) +#define STM32_IPCC_C1SCR (STM32_IPCC_BASE + STM32_IPCC_C1SCR_OFFSET) +#define STM32_IPCC_C1TOC2SR (STM32_IPCC_BASE + STM32_IPCC_C1TOC2SR_OFFSET) +#define STM32_IPCC_C2CR (STM32_IPCC_BASE + STM32_IPCC_C2CR_OFFSET) +#define STM32_IPCC_C2MR (STM32_IPCC_BASE + STM32_IPCC_C2MR_OFFSET) +#define STM32_IPCC_C2SCR (STM32_IPCC_BASE + STM32_IPCC_C2SCR_OFFSET) +#define STM32_IPCC_C2TOC1SR (STM32_IPCC_BASE + STM32_IPCC_C2TOC1SR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h index 58d3d249b66be..474f7a9051079 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h @@ -29,33 +29,33 @@ /* STM32WBXXX Address Blocks ************************************************/ -#define STM32WB_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32WB_SRAM_BASE 0x20000000 /* 0x20000000-0x2003ffff: 256k RAM block */ -#define STM32WB_PERIPH_BASE 0x40000000 /* Peripheral base address */ -#define STM32WB_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x2003ffff: 256k RAM block */ +#define STM32_PERIPH_BASE 0x40000000 /* Peripheral base address */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ /* Code Base Addresses ******************************************************/ -#define STM32WB_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ -#define STM32WB_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ -#define STM32WB_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ -#define STM32WB_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192к RAM1 block */ -#define STM32WB_SRAM2A_BASE 0x20030000 /* 0x20030000-0x20037fff: 32k RAM2a block */ -#define STM32WB_SRAM2B_BASE 0x20038000 /* 0x20038000-0x2003ffff: 32k RAM2b block */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ +#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192к RAM1 block */ +#define STM32_SRAM2A_BASE 0x20030000 /* 0x20030000-0x20037fff: 32k RAM2a block */ +#define STM32_SRAM2B_BASE 0x20038000 /* 0x20038000-0x2003ffff: 32k RAM2b block */ -#define STM32WB_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x20006fff: System memory */ -#define STM32WB_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ -#define STM32WB_OPTION_BASE 0x1fff8000 /* 0x1fff8000-0x1fff8fff: Option bytes */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x20006fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ +#define STM32_OPTION_BASE 0x1fff8000 /* 0x1fff8000-0x1fff8fff: Option bytes */ /* System Memory Addresses **************************************************/ -#define STM32WB_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32WB_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. */ -#define STM32WB_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. 5 LSB corresponds to: * 0x11: WLCSP100 / UFBGA129 * 0x13: VFQFPN68 @@ -64,96 +64,96 @@ /* SRAM Base Addresses ******************************************************/ -#define STM32WB_SRAMBB_BASE 0x22000000 /* 0x22000000-0x227fffff: SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000-0x227fffff: SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32WB_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ - /* 0x40009800-0x4000ffff: Reserved */ -#define STM32WB_APB2_BASE 0x40010000 /* 0x40010000-0x400157ff: APB2 */ - /* 0x40015800-0x4001ffff: Reserved */ -#define STM32WB_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: AHB1 */ - /* 0x40024400-0x47ffffff: Reserved */ -#define STM32WB_AHB2_BASE 0x48000000 /* 0x48000000-0x500603ff: AHB2 */ - /* 0x50060400-0x57ffffff: Reserved */ -#define STM32WB_AHB4_BASE 0x58000000 /* 0x58000000-0x580043ff: AHB4 */ - /* 0x58004400-0x5fffffff: Reserved */ -#define STM32WB_APB3_BASE 0x60000000 /* 0x60000000-0x60001fff: APB3 */ - /* 0x60002000-0x8fffffff: Reserved */ -#define STM32WB_AHB3_BASE 0x90000000 /* 0x90000000-0xA00013ff: AHB3 */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ + /* 0x40009800-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400157ff: APB2 */ + /* 0x40015800-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: AHB1 */ + /* 0x40024400-0x47ffffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x500603ff: AHB2 */ + /* 0x50060400-0x57ffffff: Reserved */ +#define STM32_AHB4_BASE 0x58000000 /* 0x58000000-0x580043ff: AHB4 */ + /* 0x58004400-0x5fffffff: Reserved */ +#define STM32_APB3_BASE 0x60000000 /* 0x60000000-0x60001fff: APB3 */ + /* 0x60002000-0x8fffffff: Reserved */ +#define STM32_AHB3_BASE 0x90000000 /* 0x90000000-0xA00013ff: AHB3 */ /* APB1 Base Addresses ******************************************************/ -#define STM32WB_TIM2_BASE 0x40000000 -#define STM32WB_LCD_BASE 0x40002400 -#define STM32WB_RTC_BASE 0x40002800 -#define STM32WB_WWDG_BASE 0x40002c00 -#define STM32WB_IWDG_BASE 0x40003000 -#define STM32WB_SPI2_BASE 0x40003800 -#define STM32WB_I2C1_BASE 0x40005400 -#define STM32WB_I2C3_BASE 0x40005c00 -#define STM32WB_CRS_BASE 0x40006000 -#define STM32WB_USB1_BASE 0x40006800 -#define STM32WB_USB1_PMAADDR 0x40006c00 -#define STM32WB_LPTIM1_BASE 0x40007c00 -#define STM32WB_LPUART1_BASE 0x40008000 -#define STM32WB_LPTIM2_BASE 0x40009400 +#define STM32_TIM2_BASE 0x40000000 +#define STM32_LCD_BASE 0x40002400 +#define STM32_RTC_BASE 0x40002800 +#define STM32_WWDG_BASE 0x40002c00 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C3_BASE 0x40005c00 +#define STM32_CRS_BASE 0x40006000 +#define STM32_USB1_BASE 0x40006800 +#define STM32_USB1_PMAADDR 0x40006c00 +#define STM32_LPTIM1_BASE 0x40007c00 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM2_BASE 0x40009400 /* APB2 Base Addresses ******************************************************/ -#define STM32WB_SYSCFG_BASE 0x40010000 -#define STM32WB_VREFBUF_BASE 0x40010030 -#define STM32WB_COMP1_BASE 0x40010200 -#define STM32WB_COMP2_BASE 0x40010204 -#define STM32WB_TIM1_BASE 0x40012c00 -#define STM32WB_SPI1_BASE 0x40013000 -#define STM32WB_USART1_BASE 0x40013800 -#define STM32WB_TIM16_BASE 0x40014400 -#define STM32WB_TIM17_BASE 0x40014800 -#define STM32WB_SAI1_BASE 0x40015400 +#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_COMP1_BASE 0x40010200 +#define STM32_COMP2_BASE 0x40010204 +#define STM32_TIM1_BASE 0x40012c00 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_SAI1_BASE 0x40015400 /* AHB1 Base Addresses ******************************************************/ -#define STM32WB_DMA1_BASE 0x40020000 -#define STM32WB_DMA2_BASE 0x40020400 -#define STM32WB_DMAMUX1_BASE 0x40020800 -#define STM32WB_CRC_BASE 0x40023000 -#define STM32WB_TSC_BASE 0x40024000 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_CRC_BASE 0x40023000 +#define STM32_TSC_BASE 0x40024000 /* AHB2 Base Addresses ******************************************************/ -#define STM32WB_GPIOA_BASE 0x48000000 -#define STM32WB_GPIOB_BASE 0x48000400 -#define STM32WB_GPIOC_BASE 0x48000800 -#define STM32WB_GPIOD_BASE 0x48000c00 -#define STM32WB_GPIOE_BASE 0x48001000 -#define STM32WB_GPIOH_BASE 0x48001c00 -#define STM32WB_ADC1_BASE 0x50040000 -#define STM32WB_AES1_BASE 0x50060000 +#define STM32_GPIOA_BASE 0x48000000 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOD_BASE 0x48000c00 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOH_BASE 0x48001c00 +#define STM32_ADC1_BASE 0x50040000 +#define STM32_AES1_BASE 0x50060000 /* AHB4 Base Addresses ******************************************************/ -#define STM32WB_RCC_BASE 0x58000000 -#define STM32WB_PWR_BASE 0x58000400 -#define STM32WB_EXTI_BASE 0x58000800 -#define STM32WB_IPCC_BASE 0x58000c00 -#define STM32WB_RNG_BASE 0x58001000 -#define STM32WB_HSEM_BASE 0x58001400 -#define STM32WB_AES2_BASE 0x58001800 -#define STM32WB_PKA_BASE 0x58002000 -#define STM32WB_FLASHREG_BASE 0x58004000 +#define STM32_RCC_BASE 0x58000000 +#define STM32_PWR_BASE 0x58000400 +#define STM32_EXTI_BASE 0x58000800 +#define STM32_IPCC_BASE 0x58000c00 +#define STM32_RNG_BASE 0x58001000 +#define STM32_HSEM_BASE 0x58001400 +#define STM32_AES2_BASE 0x58001800 +#define STM32_PKA_BASE 0x58002000 +#define STM32_FLASHREG_BASE 0x58004000 /* APB3 Base Addresses ******************************************************/ -#define STM32WB_BLE_BASE 0x60000000 -#define STM32WB_RADIO_BASE 0x60000400 -#define STM32WB_802154_BASE 0x60001000 +#define STM32_BLE_BASE 0x60000000 +#define STM32_RADIO_BASE 0x60000400 +#define STM32_802154_BASE 0x60001000 /* AHB3 Base Addresses ******************************************************/ -#define STM32WB_QSPI_BASE 0x90000000 -#define STM32WB_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QSPI memory mapping */ -#define STM32WB_QSPIREF_BASE 0xa0001000 +#define STM32_QSPI_BASE 0x90000000 +#define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QSPI memory mapping */ +#define STM32_QSPIREF_BASE 0xa0001000 /* Cortex-M4 Base Addresses *************************************************/ @@ -161,7 +161,7 @@ * this address range */ -#define STM32WB_SCS_BASE 0xe000e000 -#define STM32WB_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 #endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h index 8e161735c05cf..6fb75537322c4 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h @@ -36,54 +36,54 @@ /* Register Offsets *********************************************************/ -#define STM32WB_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32WB_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32WB_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32WB_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32WB_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32WB_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32WB_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32WB_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ -#define STM32WB_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32WB_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32WB_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32WB_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32WB_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32WB_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32WB_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32WB_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32WB_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32WB_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32WB_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32WB_PWR_C2CR1_OFFSET 0x0080 /* CPU2 control register 1 */ -#define STM32WB_PWR_C2CR3_OFFSET 0x0084 /* CPU2 control register 3 */ -#define STM32WB_PWR_EXTSCR_OFFSET 0x0088 /* Extended status and status clear register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_C2CR1_OFFSET 0x0080 /* CPU2 control register 1 */ +#define STM32_PWR_C2CR3_OFFSET 0x0084 /* CPU2 control register 3 */ +#define STM32_PWR_EXTSCR_OFFSET 0x0088 /* Extended status and status clear register */ /* Register Addresses *******************************************************/ -#define STM32WB_PWR_CR1 (STM32WB_PWR_BASE + STM32WB_PWR_CR1_OFFSET) -#define STM32WB_PWR_CR2 (STM32WB_PWR_BASE + STM32WB_PWR_CR2_OFFSET) -#define STM32WB_PWR_CR3 (STM32WB_PWR_BASE + STM32WB_PWR_CR3_OFFSET) -#define STM32WB_PWR_CR4 (STM32WB_PWR_BASE + STM32WB_PWR_CR4_OFFSET) -#define STM32WB_PWR_SR1 (STM32WB_PWR_BASE + STM32WB_PWR_SR1_OFFSET) -#define STM32WB_PWR_SR2 (STM32WB_PWR_BASE + STM32WB_PWR_SR2_OFFSET) -#define STM32WB_PWR_SCR (STM32WB_PWR_BASE + STM32WB_PWR_SCR_OFFSET) -#define STM32WB_PWR_CR5 (STM32WB_PWR_BASE + STM32WB_PWR_CR5_OFFSET) -#define STM32WB_PWR_PUCRA (STM32WB_PWR_BASE + STM32WB_PWR_PUCRA_OFFSET) -#define STM32WB_PWR_PDCRA (STM32WB_PWR_BASE + STM32WB_PWR_PDCRA_OFFSET) -#define STM32WB_PWR_PUCRB (STM32WB_PWR_BASE + STM32WB_PWR_PUCRB_OFFSET) -#define STM32WB_PWR_PDCRB (STM32WB_PWR_BASE + STM32WB_PWR_PDCRB_OFFSET) -#define STM32WB_PWR_PUCRC (STM32WB_PWR_BASE + STM32WB_PWR_PUCRC_OFFSET) -#define STM32WB_PWR_PDCRC (STM32WB_PWR_BASE + STM32WB_PWR_PDCRC_OFFSET) -#define STM32WB_PWR_PUCRD (STM32WB_PWR_BASE + STM32WB_PWR_PUCRD_OFFSET) -#define STM32WB_PWR_PDCRD (STM32WB_PWR_BASE + STM32WB_PWR_PDCRD_OFFSET) -#define STM32WB_PWR_PUCRE (STM32WB_PWR_BASE + STM32WB_PWR_PUCRE_OFFSET) -#define STM32WB_PWR_PDCRE (STM32WB_PWR_BASE + STM32WB_PWR_PDCRE_OFFSET) -#define STM32WB_PWR_PUCRH (STM32WB_PWR_BASE + STM32WB_PWR_PUCRH_OFFSET) -#define STM32WB_PWR_PDCRH (STM32WB_PWR_BASE + STM32WB_PWR_PDCRH_OFFSET) -#define STM32WB_PWR_C2CR1 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR1_OFFSET) -#define STM32WB_PWR_C2CR3 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR3_OFFSET) -#define STM32WB_PWR_EXTSCR (STM32WB_PWR_BASE + STM32WB_PWR_EXTSCR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET) +#define STM32_PWR_CR5 (STM32_PWR_BASE + STM32_PWR_CR5_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE + STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE + STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_C2CR1 (STM32_PWR_BASE + STM32_PWR_C2CR1_OFFSET) +#define STM32_PWR_C2CR3 (STM32_PWR_BASE + STM32_PWR_C2CR3_OFFSET) +#define STM32_PWR_EXTSCR (STM32_PWR_BASE + STM32_PWR_EXTSCR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h index 2f861e3fed2d2..568d362051d6f 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h @@ -35,105 +35,105 @@ /* Register Offsets *********************************************************/ -#define STM32WB_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32WB_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32WB_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32WB_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32WB_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32WB_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32WB_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32WB_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32WB_RCC_SMPSCR_OFFSET 0x0024 /* Step-down converter control register */ -#define STM32WB_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32WB_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32WB_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32WB_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32WB_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32WB_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32WB_RCC_APB3RSTR_OFFSET 0x0044 /* APB3 Peripheral reset register */ -#define STM32WB_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32WB_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32WB_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32WB_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB1SMENR_OFFSET 0x0068 /* AHB1 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_AHB2SMENR_OFFSET 0x006c /* AHB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_AHB3SMENR_OFFSET 0x0070 /* AHB3 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_APB1SMENR1_OFFSET 0x0078 /* APB1 clock enable in sleep and stop modes register 1 */ -#define STM32WB_RCC_APB1SMENR2_OFFSET 0x007c /* APB1 clock enable in sleep and stop modes register 2 */ -#define STM32WB_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */ -#define STM32WB_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32WB_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32WB_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32WB_RCC_HSECR_OFFSET 0x009c /* Clock HSE register */ -#define STM32WB_RCC_EXTCFGR_OFFSET 0x0108 /* Extended clock recovery register */ -#define STM32WB_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ -#define STM32WB_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ -#define STM32WB_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ -#define STM32WB_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ -#define STM32WB_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 AHB1 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 AHB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 AHB3 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 APB1 clock enable in sleep and stop modes register 1 */ -#define STM32WB_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 APB1 clock enable in sleep and stop modes register 2 */ -#define STM32WB_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 APB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 APB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_SMPSCR_OFFSET 0x0024 /* Step-down converter control register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_APB3RSTR_OFFSET 0x0044 /* APB3 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* AHB1 clock enable in sleep and stop modes register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* AHB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* AHB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* APB1 clock enable in sleep and stop modes register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* APB1 clock enable in sleep and stop modes register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_HSECR_OFFSET 0x009c /* Clock HSE register */ +#define STM32_RCC_EXTCFGR_OFFSET 0x0108 /* Extended clock recovery register */ +#define STM32_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ +#define STM32_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ +#define STM32_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 AHB1 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 AHB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 AHB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 APB1 clock enable in sleep and stop modes register 1 */ +#define STM32_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 APB1 clock enable in sleep and stop modes register 2 */ +#define STM32_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 APB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 APB3 clock enable in sleep and stop modes register */ /* Register Addresses *******************************************************/ -#define STM32WB_RCC_CR (STM32WB_RCC_BASE + STM32WB_RCC_CR_OFFSET) -#define STM32WB_RCC_ICSCR (STM32WB_RCC_BASE + STM32WB_RCC_ICSCR_OFFSET) -#define STM32WB_RCC_CFGR (STM32WB_RCC_BASE + STM32WB_RCC_CFGR_OFFSET) -#define STM32WB_RCC_PLLCFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLCFG_OFFSET) -#define STM32WB_RCC_PLLSAI1CFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLSAI1CFG_OFFSET) -#define STM32WB_RCC_CIER (STM32WB_RCC_BASE + STM32WB_RCC_CIER_OFFSET) -#define STM32WB_RCC_CIFR (STM32WB_RCC_BASE + STM32WB_RCC_CIFR_OFFSET) -#define STM32WB_RCC_CICR (STM32WB_RCC_BASE + STM32WB_RCC_CICR_OFFSET) -#define STM32WB_RCC_SMPSCR (STM32WB_RCC_BASE + STM32WB_RCC_SMPSCR_OFFSET) -#define STM32WB_RCC_AHB1RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1RSTR_OFFSET) -#define STM32WB_RCC_AHB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2RSTR_OFFSET) -#define STM32WB_RCC_AHB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3RSTR_OFFSET) -#define STM32WB_RCC_APB1RSTR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR1_OFFSET) -#define STM32WB_RCC_APB1RSTR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR2_OFFSET) -#define STM32WB_RCC_APB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB2RSTR_OFFSET) -#define STM32WB_RCC_APB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB3RSTR_OFFSET) -#define STM32WB_RCC_AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1ENR_OFFSET) -#define STM32WB_RCC_AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2ENR_OFFSET) -#define STM32WB_RCC_AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3ENR_OFFSET) -#define STM32WB_RCC_APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR1_OFFSET) -#define STM32WB_RCC_APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR2_OFFSET) -#define STM32WB_RCC_APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2ENR_OFFSET) -#define STM32WB_RCC_AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1SMENR_OFFSET) -#define STM32WB_RCC_AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2SMENR_OFFSET) -#define STM32WB_RCC_AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3SMENR_OFFSET) -#define STM32WB_RCC_APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR1_OFFSET) -#define STM32WB_RCC_APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR2_OFFSET) -#define STM32WB_RCC_APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2SMENR_OFFSET) -#define STM32WB_RCC_CCIPR (STM32WB_RCC_BASE + STM32WB_RCC_CCIPR_OFFSET) -#define STM32WB_RCC_BDCR (STM32WB_RCC_BASE + STM32WB_RCC_BDCR_OFFSET) -#define STM32WB_RCC_CSR (STM32WB_RCC_BASE + STM32WB_RCC_CSR_OFFSET) -#define STM32WB_RCC_CRRCR (STM32WB_RCC_BASE + STM32WB_RCC_CRRCR_OFFSET) -#define STM32WB_RCC_HSECR (STM32WB_RCC_BASE + STM32WB_RCC_HSECR_OFFSET) -#define STM32WB_RCC_EXTCFGR (STM32WB_RCC_BASE + STM32WB_RCC_EXTCFGR_OFFSET) -#define STM32WB_RCC_C2AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1ENR_OFFSET) -#define STM32WB_RCC_C2AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2ENR_OFFSET) -#define STM32WB_RCC_C2AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3ENR_OFFSET) -#define STM32WB_RCC_C2APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR1_OFFSET) -#define STM32WB_RCC_C2APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR2_OFFSET) -#define STM32WB_RCC_C2APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2ENR_OFFSET) -#define STM32WB_RCC_C2APB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3ENR_OFFSET) -#define STM32WB_RCC_C2AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1SMENR_OFFSET) -#define STM32WB_RCC_C2AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2SMENR_OFFSET) -#define STM32WB_RCC_C2AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3SMENR_OFFSET) -#define STM32WB_RCC_C2APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR1_OFFSET) -#define STM32WB_RCC_C2APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR2_OFFSET) -#define STM32WB_RCC_C2APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2SMENR_OFFSET) -#define STM32WB_RCC_C2APB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3SMENR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_SMPSCR (STM32_RCC_BASE + STM32_RCC_SMPSCR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_HSECR (STM32_RCC_BASE + STM32_RCC_HSECR_OFFSET) +#define STM32_RCC_EXTCFGR (STM32_RCC_BASE + STM32_RCC_EXTCFGR_OFFSET) +#define STM32_RCC_C2AHB1ENR (STM32_RCC_BASE + STM32_RCC_C2AHB1ENR_OFFSET) +#define STM32_RCC_C2AHB2ENR (STM32_RCC_BASE + STM32_RCC_C2AHB2ENR_OFFSET) +#define STM32_RCC_C2AHB3ENR (STM32_RCC_BASE + STM32_RCC_C2AHB3ENR_OFFSET) +#define STM32_RCC_C2APB1ENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR1_OFFSET) +#define STM32_RCC_C2APB1ENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR2_OFFSET) +#define STM32_RCC_C2APB2ENR (STM32_RCC_BASE + STM32_RCC_C2APB2ENR_OFFSET) +#define STM32_RCC_C2APB3ENR (STM32_RCC_BASE + STM32_RCC_C2APB3ENR_OFFSET) +#define STM32_RCC_C2AHB1SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB1SMENR_OFFSET) +#define STM32_RCC_C2AHB2SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB2SMENR_OFFSET) +#define STM32_RCC_C2AHB3SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB3SMENR_OFFSET) +#define STM32_RCC_C2APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR1_OFFSET) +#define STM32_RCC_C2APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR2_OFFSET) +#define STM32_RCC_C2APB2SMENR (STM32_RCC_BASE + STM32_RCC_C2APB2SMENR_OFFSET) +#define STM32_RCC_C2APB3SMENR (STM32_RCC_BASE + STM32_RCC_C2APB3SMENR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h index b02dfbcd959b9..6f8db9d0b9e64 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32WB_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32WB_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32WB_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32WB_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32WB_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32WB_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32WB_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32WB_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32WB_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32WB_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32WB_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32WB_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32WB_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32WB_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32WB_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32WB_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ -#define STM32WB_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32WB_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ -#define STM32WB_RTC_OR_OFFSET 0x004c /* RTC option register */ - -#define STM32WB_RTC_BKPR_OFFSET(n) (0x0050 + ((n) << 2)) -#define STM32WB_RTC_BKP0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32WB_RTC_BKP1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32WB_RTC_BKP2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32WB_RTC_BKP3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32WB_RTC_BKP4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32WB_RTC_BKP5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32WB_RTC_BKP6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32WB_RTC_BKP7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32WB_RTC_BKP8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32WB_RTC_BKP9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32WB_RTC_BKP10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32WB_RTC_BKP11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32WB_RTC_BKP12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32WB_RTC_BKP13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32WB_RTC_BKP14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32WB_RTC_BKP15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32WB_RTC_BKP16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32WB_RTC_BKP17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32WB_RTC_BKP18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32WB_RTC_BKP19R_OFFSET 0x009c /* RTC backup register 19 */ +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ +#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */ + +#define STM32_RTC_BKPR_OFFSET(n) (0x0050 + ((n) << 2)) +#define STM32_RTC_BKP0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BKP1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BKP2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BKP3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BKP4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BKP5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BKP6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BKP7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BKP8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BKP9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BKP10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BKP11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BKP12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BKP13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BKP14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BKP15R_OFFSET 0x008c /* RTC backup register 15 */ +#define STM32_RTC_BKP16R_OFFSET 0x0090 /* RTC backup register 16 */ +#define STM32_RTC_BKP17R_OFFSET 0x0094 /* RTC backup register 17 */ +#define STM32_RTC_BKP18R_OFFSET 0x0098 /* RTC backup register 18 */ +#define STM32_RTC_BKP19R_OFFSET 0x009c /* RTC backup register 19 */ /* Register Addresses *******************************************************/ -#define STM32WB_RTC_TR (STM32WB_RTC_BASE + STM32WB_RTC_TR_OFFSET) -#define STM32WB_RTC_DR (STM32WB_RTC_BASE + STM32WB_RTC_DR_OFFSET) -#define STM32WB_RTC_CR (STM32WB_RTC_BASE + STM32WB_RTC_CR_OFFSET) -#define STM32WB_RTC_ISR (STM32WB_RTC_BASE + STM32WB_RTC_ISR_OFFSET) -#define STM32WB_RTC_PRER (STM32WB_RTC_BASE + STM32WB_RTC_PRER_OFFSET) -#define STM32WB_RTC_WUTR (STM32WB_RTC_BASE + STM32WB_RTC_WUTR_OFFSET) -#define STM32WB_RTC_ALRMAR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMAR_OFFSET) -#define STM32WB_RTC_ALRMBR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBR_OFFSET) -#define STM32WB_RTC_WPR (STM32WB_RTC_BASE + STM32WB_RTC_WPR_OFFSET) -#define STM32WB_RTC_SSR (STM32WB_RTC_BASE + STM32WB_RTC_SSR_OFFSET) -#define STM32WB_RTC_SHIFTR (STM32WB_RTC_BASE + STM32WB_RTC_SHIFTR_OFFSET) -#define STM32WB_RTC_TSTR (STM32WB_RTC_BASE + STM32WB_RTC_TSTR_OFFSET) -#define STM32WB_RTC_TSDR (STM32WB_RTC_BASE + STM32WB_RTC_TSDR_OFFSET) -#define STM32WB_RTC_TSSSR (STM32WB_RTC_BASE + STM32WB_RTC_TSSSR_OFFSET) -#define STM32WB_RTC_CALR (STM32WB_RTC_BASE + STM32WB_RTC_CALR_OFFSET) -#define STM32WB_RTC_TAMPCR (STM32WB_RTC_BASE + STM32WB_RTC_TAMPCR_OFFSET) -#define STM32WB_RTC_ALRMASSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMASSR_OFFSET) -#define STM32WB_RTC_ALRMBSSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBSSR_OFFSET) -#define STM32WB_RTC_OR (STM32WB_RTC_BASE + STM32WB_RTC_OR_OFFSET) - -#define STM32WB_RTC_BKPR(n) (STM32WB_RTC_BASE + STM32WB_RTC_BKPR_OFFSET(n)) -#define STM32WB_RTC_BKP0R (STM32WB_RTC_BASE + STM32WB_RTC_BKP0R_OFFSET) -#define STM32WB_RTC_BKP1R (STM32WB_RTC_BASE + STM32WB_RTC_BKP1R_OFFSET) -#define STM32WB_RTC_BKP2R (STM32WB_RTC_BASE + STM32WB_RTC_BKP2R_OFFSET) -#define STM32WB_RTC_BKP3R (STM32WB_RTC_BASE + STM32WB_RTC_BKP3R_OFFSET) -#define STM32WB_RTC_BKP4R (STM32WB_RTC_BASE + STM32WB_RTC_BKP4R_OFFSET) -#define STM32WB_RTC_BKP5R (STM32WB_RTC_BASE + STM32WB_RTC_BKP5R_OFFSET) -#define STM32WB_RTC_BKP6R (STM32WB_RTC_BASE + STM32WB_RTC_BKP6R_OFFSET) -#define STM32WB_RTC_BKP7R (STM32WB_RTC_BASE + STM32WB_RTC_BKP7R_OFFSET) -#define STM32WB_RTC_BKP8R (STM32WB_RTC_BASE + STM32WB_RTC_BKP8R_OFFSET) -#define STM32WB_RTC_BKP9R (STM32WB_RTC_BASE + STM32WB_RTC_BKP9R_OFFSET) -#define STM32WB_RTC_BKP10R (STM32WB_RTC_BASE + STM32WB_RTC_BKP10R_OFFSET) -#define STM32WB_RTC_BKP11R (STM32WB_RTC_BASE + STM32WB_RTC_BKP11R_OFFSET) -#define STM32WB_RTC_BKP12R (STM32WB_RTC_BASE + STM32WB_RTC_BKP12R_OFFSET) -#define STM32WB_RTC_BKP13R (STM32WB_RTC_BASE + STM32WB_RTC_BKP13R_OFFSET) -#define STM32WB_RTC_BKP14R (STM32WB_RTC_BASE + STM32WB_RTC_BKP14R_OFFSET) -#define STM32WB_RTC_BKP15R (STM32WB_RTC_BASE + STM32WB_RTC_BKP15R_OFFSET) -#define STM32WB_RTC_BKP16R (STM32WB_RTC_BASE + STM32WB_RTC_BKP16R_OFFSET) -#define STM32WB_RTC_BKP17R (STM32WB_RTC_BASE + STM32WB_RTC_BKP17R_OFFSET) -#define STM32WB_RTC_BKP18R (STM32WB_RTC_BASE + STM32WB_RTC_BKP18R_OFFSET) -#define STM32WB_RTC_BKP19R (STM32WB_RTC_BASE + STM32WB_RTC_BKP19R_OFFSET) - -# define STM32WB_RTC_BKCOUNT 20 +#define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE + STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE + STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE + STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE + STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE + STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE + STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE + STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE + STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE + STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE + STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE + STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE + STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE + STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAMPCR (STM32_RTC_BASE + STM32_RTC_TAMPCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE + STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE + STM32_RTC_ALRMBSSR_OFFSET) +#define STM32_RTC_OR (STM32_RTC_BASE + STM32_RTC_OR_OFFSET) + +#define STM32_RTC_BKPR(n) (STM32_RTC_BASE + STM32_RTC_BKPR_OFFSET(n)) +#define STM32_RTC_BKP0R (STM32_RTC_BASE + STM32_RTC_BKP0R_OFFSET) +#define STM32_RTC_BKP1R (STM32_RTC_BASE + STM32_RTC_BKP1R_OFFSET) +#define STM32_RTC_BKP2R (STM32_RTC_BASE + STM32_RTC_BKP2R_OFFSET) +#define STM32_RTC_BKP3R (STM32_RTC_BASE + STM32_RTC_BKP3R_OFFSET) +#define STM32_RTC_BKP4R (STM32_RTC_BASE + STM32_RTC_BKP4R_OFFSET) +#define STM32_RTC_BKP5R (STM32_RTC_BASE + STM32_RTC_BKP5R_OFFSET) +#define STM32_RTC_BKP6R (STM32_RTC_BASE + STM32_RTC_BKP6R_OFFSET) +#define STM32_RTC_BKP7R (STM32_RTC_BASE + STM32_RTC_BKP7R_OFFSET) +#define STM32_RTC_BKP8R (STM32_RTC_BASE + STM32_RTC_BKP8R_OFFSET) +#define STM32_RTC_BKP9R (STM32_RTC_BASE + STM32_RTC_BKP9R_OFFSET) +#define STM32_RTC_BKP10R (STM32_RTC_BASE + STM32_RTC_BKP10R_OFFSET) +#define STM32_RTC_BKP11R (STM32_RTC_BASE + STM32_RTC_BKP11R_OFFSET) +#define STM32_RTC_BKP12R (STM32_RTC_BASE + STM32_RTC_BKP12R_OFFSET) +#define STM32_RTC_BKP13R (STM32_RTC_BASE + STM32_RTC_BKP13R_OFFSET) +#define STM32_RTC_BKP14R (STM32_RTC_BASE + STM32_RTC_BKP14R_OFFSET) +#define STM32_RTC_BKP15R (STM32_RTC_BASE + STM32_RTC_BKP15R_OFFSET) +#define STM32_RTC_BKP16R (STM32_RTC_BASE + STM32_RTC_BKP16R_OFFSET) +#define STM32_RTC_BKP17R (STM32_RTC_BASE + STM32_RTC_BKP17R_OFFSET) +#define STM32_RTC_BKP18R (STM32_RTC_BASE + STM32_RTC_BKP18R_OFFSET) +#define STM32_RTC_BKP19R (STM32_RTC_BASE + STM32_RTC_BKP19R_OFFSET) + +# define STM32_RTC_BKCOUNT 20 /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h index 62851ed763479..ddf8e305d017c 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h @@ -36,36 +36,36 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32WB_SPI_CLK_MAX 32000000ul +#define STM32_SPI_CLK_MAX 32000000ul /* Register Offsets *********************************************************/ -#define STM32WB_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32WB_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32WB_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32WB_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32WB_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32WB_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32WB_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#define STM32WB_SPI1_CR1 (STM32WB_SPI1_BASE + STM32WB_SPI_CR1_OFFSET) -#define STM32WB_SPI1_CR2 (STM32WB_SPI1_BASE + STM32WB_SPI_CR2_OFFSET) -#define STM32WB_SPI1_SR (STM32WB_SPI1_BASE + STM32WB_SPI_SR_OFFSET) -#define STM32WB_SPI1_DR (STM32WB_SPI1_BASE + STM32WB_SPI_DR_OFFSET) -#define STM32WB_SPI1_CRCPR (STM32WB_SPI1_BASE + STM32WB_SPI_CRCPR_OFFSET) -#define STM32WB_SPI1_RXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_RXCRCR_OFFSET) -#define STM32WB_SPI1_TXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_TXCRCR_OFFSET) +#define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +#define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +#define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +#define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +#define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +#define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +#define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #if CONFIG_STM32WB_HAVE_SPI2 -# define STM32WB_SPI2_CR1 (STM32WB_SPI2_BASE + STM32WB_SPI_CR1_OFFSET) -# define STM32WB_SPI2_CR2 (STM32WB_SPI2_BASE + STM32WB_SPI_CR2_OFFSET) -# define STM32WB_SPI2_SR (STM32WB_SPI2_BASE + STM32WB_SPI_SR_OFFSET) -# define STM32WB_SPI2_DR (STM32WB_SPI2_BASE + STM32WB_SPI_DR_OFFSET) -# define STM32WB_SPI2_CRCPR (STM32WB_SPI2_BASE + STM32WB_SPI_CRCPR_OFFSET) -# define STM32WB_SPI2_RXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_RXCRCR_OFFSET) -# define STM32WB_SPI2_TXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_TXCRCR_OFFSET) +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h index a4cfa546324b4..2fe834387c4c4 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h @@ -35,42 +35,42 @@ /* Register Offsets *********************************************************/ -#define STM32WB_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32WB_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32WB_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x0c)) /* Pin p = 0..15 */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x0c)) /* Pin p = 0..15 */ -#define STM32WB_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32WB_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32WB_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32WB_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32WB_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32WB_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32WB_SYSCFG_SWPR1_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register 1 */ -#define STM32WB_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32WB_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR1_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register 1 */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32WB_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG Interrupt mask register 1 */ -#define STM32WB_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG Interrupt mask register 2 */ -#define STM32WB_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG CPU2 Interrupt mask register 1 */ -#define STM32WB_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG CPU2 Interrupt mask register 2 */ -#define STM32WB_SYSCFG_SIPCR_OFFSET 0x0110 /* SYSCFG Secure IP control register */ +#define STM32_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG Interrupt mask register 1 */ +#define STM32_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG Interrupt mask register 2 */ +#define STM32_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG CPU2 Interrupt mask register 1 */ +#define STM32_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG CPU2 Interrupt mask register 2 */ +#define STM32_SYSCFG_SIPCR_OFFSET 0x0110 /* SYSCFG Secure IP control register */ /* Register Addresses *******************************************************/ -#define STM32WB_SYSCFG_MEMRMP (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_MEMRMP_OFFSET) -#define STM32WB_SYSCFG_CFGR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR1_OFFSET) -#define STM32WB_SYSCFG_EXTICR(p) (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR_OFFSET(p)) -#define STM32WB_SYSCFG_EXTICR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR1_OFFSET) -#define STM32WB_SYSCFG_EXTICR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR2_OFFSET) -#define STM32WB_SYSCFG_EXTICR3 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR3_OFFSET) -#define STM32WB_SYSCFG_EXTICR4 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR4_OFFSET) -#define STM32WB_SYSCFG_SCSR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SCSR_OFFSET) -#define STM32WB_SYSCFG_CFGR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR2_OFFSET) -#define STM32WB_SYSCFG_SWPR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR1_OFFSET) -#define STM32WB_SYSCFG_SKR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SKR_OFFSET) -#define STM32WB_SYSCFG_SWPR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE + STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR1_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h index 6e646a6dc2f75..447d8bdf78441 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h @@ -29,150 +29,150 @@ /* Register Offsets *********************************************************/ -#define STM32WB_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32WB_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32WB_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ -#define STM32WB_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ -#define STM32WB_TIM_SR_OFFSET 0x0010 /* Status register */ -#define STM32WB_TIM_EGR_OFFSET 0x0014 /* Event generation register */ -#define STM32WB_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ -#define STM32WB_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ -#define STM32WB_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32WB_TIM_CNT_OFFSET 0x0024 /* Counter */ -#define STM32WB_TIM_PSC_OFFSET 0x0028 /* Prescaler */ -#define STM32WB_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ -#define STM32WB_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ -#define STM32WB_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ -#define STM32WB_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ -#define STM32WB_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ -#define STM32WB_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ -#define STM32WB_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ -#define STM32WB_TIM_DCR_OFFSET 0x0048 /* DMA control register */ -#define STM32WB_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ -#define STM32WB_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32WB_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ -#define STM32WB_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ -#define STM32WB_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ -#define STM32WB_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ -#define STM32WB_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ -#define STM32WB_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ +#define STM32_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ +#define STM32_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ +#define STM32_TIM_SR_OFFSET 0x0010 /* Status register */ +#define STM32_TIM_EGR_OFFSET 0x0014 /* Event generation register */ +#define STM32_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ +#define STM32_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ +#define STM32_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ +#define STM32_TIM_CNT_OFFSET 0x0024 /* Counter */ +#define STM32_TIM_PSC_OFFSET 0x0028 /* Prescaler */ +#define STM32_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ +#define STM32_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ +#define STM32_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ +#define STM32_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ +#define STM32_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ +#define STM32_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ +#define STM32_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ +#define STM32_TIM_DCR_OFFSET 0x0048 /* DMA control register */ +#define STM32_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ +#define STM32_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ +#define STM32_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ +#define STM32_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ +#define STM32_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ +#define STM32_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ +#define STM32_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ /* Register Addresses *******************************************************/ /* Advanced Timer TIM1 */ -#define STM32WB_TIM1_CR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM1_CR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM1_SMCR (STM32WB_TIM1_BASE + STM32WB_TIM_SMCR_OFFSET) -#define STM32WB_TIM1_DIER (STM32WB_TIM1_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM1_SR (STM32WB_TIM1_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM1_EGR (STM32WB_TIM1_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM1_CCMR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM1_CCMR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR2_OFFSET) -#define STM32WB_TIM1_CCER (STM32WB_TIM1_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM1_CNT (STM32WB_TIM1_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM1_PSC (STM32WB_TIM1_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM1_ARR (STM32WB_TIM1_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM1_RCR (STM32WB_TIM1_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM1_CCR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM1_CCR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR2_OFFSET) -#define STM32WB_TIM1_CCR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR3_OFFSET) -#define STM32WB_TIM1_CCR4 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR4_OFFSET) -#define STM32WB_TIM1_BDTR (STM32WB_TIM1_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM1_DCR (STM32WB_TIM1_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM1_DMAR (STM32WB_TIM1_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM1_OR1 (STM32WB_TIM1_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM1_CCMR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR3_OFFSET) -#define STM32WB_TIM1_CCR5 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR5_OFFSET) -#define STM32WB_TIM1_CCR6 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR6_OFFSET) -#define STM32WB_TIM1_AF1 (STM32WB_TIM1_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM1_AF2 (STM32WB_TIM1_BASE + STM32WB_TIM_AF2_OFFSET) -#define STM32WB_TIM1_TISEL (STM32WB_TIM1_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_TIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_TIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_TIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_TIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_TIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_TIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_TIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_TIM_CCR6_OFFSET) +#define STM32_TIM1_AF1 (STM32_TIM1_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM1_AF2 (STM32_TIM1_BASE + STM32_TIM_AF2_OFFSET) +#define STM32_TIM1_TISEL (STM32_TIM1_BASE + STM32_TIM_TISEL_OFFSET) /* General 32-bit Timer TIM2 */ -#define STM32WB_TIM2_CR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM2_CR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM2_SMCR (STM32WB_TIM2_BASE + STM32WB_TIM_SMCR_OFFSET) -#define STM32WB_TIM2_DIER (STM32WB_TIM2_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM2_SR (STM32WB_TIM2_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM2_EGR (STM32WB_TIM2_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM2_CCMR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM2_CCMR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR2_OFFSET) -#define STM32WB_TIM2_CCER (STM32WB_TIM2_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM2_CNT (STM32WB_TIM2_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM2_PSC (STM32WB_TIM2_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM2_ARR (STM32WB_TIM2_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM2_CCR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM2_CCR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR2_OFFSET) -#define STM32WB_TIM2_CCR3 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR3_OFFSET) -#define STM32WB_TIM2_CCR4 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR4_OFFSET) -#define STM32WB_TIM2_DCR (STM32WB_TIM2_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM2_DMAR (STM32WB_TIM2_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM2_OR1 (STM32WB_TIM2_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM2_AF1 (STM32WB_TIM2_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM2_TISEL (STM32WB_TIM2_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_TIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_TIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_TIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_TIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_TIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM2_OR1 (STM32_TIM2_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM2_AF1 (STM32_TIM2_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM2_TISEL (STM32_TIM2_BASE + STM32_TIM_TISEL_OFFSET) /* General Timers TIM16/TIM17 */ -#define STM32WB_TIM16_CR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM16_CR2 (STM32WB_TIM16_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM16_DIER (STM32WB_TIM16_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM16_SR (STM32WB_TIM16_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM16_EGR (STM32WB_TIM16_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM16_CCMR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM16_CCER (STM32WB_TIM16_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM16_CNT (STM32WB_TIM16_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM16_PSC (STM32WB_TIM16_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM16_ARR (STM32WB_TIM16_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM16_RCR (STM32WB_TIM16_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM16_CCR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM16_BDTR (STM32WB_TIM16_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM16_DCR (STM32WB_TIM16_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM16_DMAR (STM32WB_TIM16_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM16_OR1 (STM32WB_TIM16_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM16_AF1 (STM32WB_TIM16_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM16_TISEL (STM32WB_TIM16_BASE + STM32WB_TIM_TISEL_OFFSET) - -#define STM32WB_TIM17_CR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM17_CR2 (STM32WB_TIM17_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM17_DIER (STM32WB_TIM17_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM17_SR (STM32WB_TIM17_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM17_EGR (STM32WB_TIM17_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM17_CCMR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM17_CCER (STM32WB_TIM17_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM17_CNT (STM32WB_TIM17_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM17_PSC (STM32WB_TIM17_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM17_ARR (STM32WB_TIM17_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM17_RCR (STM32WB_TIM17_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM17_CCR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM17_BDTR (STM32WB_TIM17_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM17_DCR (STM32WB_TIM17_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM17_DMAR (STM32WB_TIM17_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM17_OR1 (STM32WB_TIM17_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM17_AF1 (STM32WB_TIM17_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM17_TISEL (STM32WB_TIM17_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM16_OR1 (STM32_TIM16_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM16_AF1 (STM32_TIM16_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM16_TISEL (STM32_TIM16_BASE + STM32_TIM_TISEL_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM17_OR1 (STM32_TIM17_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM17_AF1 (STM32_TIM17_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM17_TISEL (STM32_TIM17_BASE + STM32_TIM_TISEL_OFFSET) /* Register Value Constants *************************************************/ /* Digital Filter options */ -#define STM32WB_DF_NOFILT (0x0) /* 0000: No filter */ -#define STM32WB_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ -#define STM32WB_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ -#define STM32WB_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ -#define STM32WB_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ -#define STM32WB_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ -#define STM32WB_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ -#define STM32WB_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ -#define STM32WB_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ -#define STM32WB_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ -#define STM32WB_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ -#define STM32WB_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ -#define STM32WB_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ -#define STM32WB_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ -#define STM32WB_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ -#define STM32WB_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ +#define STM32_DF_NOFILT (0x0) /* 0000: No filter */ +#define STM32_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ +#define STM32_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ +#define STM32_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ +#define STM32_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ +#define STM32_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ +#define STM32_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ +#define STM32_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ +#define STM32_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ +#define STM32_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ +#define STM32_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ +#define STM32_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ +#define STM32_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ +#define STM32_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ +#define STM32_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ +#define STM32_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ /* Register Bitfield Definitions ********************************************/ @@ -397,7 +397,7 @@ #define TIM1_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define TIM1_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define TIM1_SMCR_ETF_MASK (0xf << TIM1_SMCR_ETF_SHIFT) -# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define TIM1_SMCR_ETPS_MASK (0x3 << TIM1_SMCR_ETPS_SHIFT) @@ -450,7 +450,7 @@ #define TIM2_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define TIM2_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define TIM2_SMCR_ETF_MASK (0xf << TIM2_SMCR_ETF_SHIFT) -# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define TIM2_SMCR_ETPS_MASK (0x3 << TIM2_SMCR_ETPS_SHIFT) @@ -920,7 +920,7 @@ #define TIM1_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM1_CCMR1_IC1F_MASK (0xf << TIM1_CCMR1_IC1F_SHIFT) -# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ #define TIM1_CCMR1_IC2PSC_MASK (0x3 << TIM1_CCMR1_IC2PSC_SHIFT) @@ -931,7 +931,7 @@ #define TIM1_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ #define TIM1_CCMR1_IC2F_MASK (0xf << TIM1_CCMR1_IC2F_SHIFT) -# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ #define TIM1_CCMR2_IC3PSC_MASK (0x3 << TIM1_CCMR2_IC3PSC_SHIFT) @@ -942,7 +942,7 @@ #define TIM1_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ #define TIM1_CCMR2_IC3F_MASK (0xf << TIM1_CCMR2_IC3F_SHIFT) -# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ #define TIM1_CCMR2_IC4PSC_MASK (0x3 << TIM1_CCMR2_IC4PSC_SHIFT) @@ -953,7 +953,7 @@ #define TIM1_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ #define TIM1_CCMR2_IC4F_MASK (0xf << TIM1_CCMR2_IC4F_SHIFT) -# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM2_CCMR1_IC1PSC_MASK (0x3 << TIM2_CCMR1_IC1PSC_SHIFT) @@ -964,7 +964,7 @@ #define TIM2_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM2_CCMR1_IC1F_MASK (0xf << TIM2_CCMR1_IC1F_SHIFT) -# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ #define TIM2_CCMR1_IC2PSC_MASK (0x3 << TIM2_CCMR1_IC2PSC_SHIFT) @@ -975,7 +975,7 @@ #define TIM2_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ #define TIM2_CCMR1_IC2F_MASK (0xf << TIM2_CCMR1_IC2F_SHIFT) -# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ #define TIM2_CCMR2_IC3PSC_MASK (0x3 << TIM2_CCMR2_IC3PSC_SHIFT) @@ -986,7 +986,7 @@ #define TIM2_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ #define TIM2_CCMR2_IC3F_MASK (0xf << TIM2_CCMR2_IC3F_SHIFT) -# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ #define TIM2_CCMR2_IC4PSC_MASK (0x3 << TIM2_CCMR2_IC4PSC_SHIFT) @@ -997,7 +997,7 @@ #define TIM2_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ #define TIM2_CCMR2_IC4F_MASK (0xf << TIM2_CCMR2_IC4F_SHIFT) -# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM16_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM16_CCMR1_IC1PSC_MASK (0x3 << TIM16_CCMR1_IC1PSC_SHIFT) @@ -1008,7 +1008,7 @@ #define TIM16_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM16_CCMR1_IC1F_MASK (0xf << TIM16_CCMR1_IC1F_SHIFT) -# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM17_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM17_CCMR1_IC1PSC_MASK (0x3 << TIM17_CCMR1_IC1PSC_SHIFT) @@ -1019,7 +1019,7 @@ #define TIM17_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM17_CCMR1_IC1F_MASK (0xf << TIM17_CCMR1_IC1F_SHIFT) -# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ /* Capture/compare enable register */ @@ -1178,11 +1178,11 @@ #define TIM1_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ #define TIM1_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ #define TIM1_BDTR_BKF_MASK (0xf << TIM1_BDTR_BKF_SHIFT) -# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ #define TIM1_BDTR_BK2F_MASK (0xf << TIM1_BDTR_BK2F_SHIFT) -# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ #define TIM1_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_uart.h b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h index 2ce1c1b6268bf..e0dc620c6137b 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h @@ -37,34 +37,34 @@ /* Register Offsets *********************************************************/ -#define STM32WB_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ -#define STM32WB_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ -#define STM32WB_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ -#define STM32WB_USART_BRR_OFFSET 0x000c /* Baud Rate Register */ -#define STM32WB_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ -#define STM32WB_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ -#define STM32WB_USART_RQR_OFFSET 0x0018 /* Request Register */ -#define STM32WB_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ -#define STM32WB_USART_ICR_OFFSET 0x0020 /* Interrupt flag Clear Register */ -#define STM32WB_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ -#define STM32WB_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ -#define STM32WB_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag Clear Register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ /* Register Addresses *******************************************************/ -#if STM32WB_NUSART > 0 -# define STM32WB_USART1_CR1 (STM32WB_USART1_BASE + STM32WB_USART_CR1_OFFSET) -# define STM32WB_USART1_CR2 (STM32WB_USART1_BASE + STM32WB_USART_CR2_OFFSET) -# define STM32WB_USART1_CR3 (STM32WB_USART1_BASE + STM32WB_USART_CR3_OFFSET) -# define STM32WB_USART1_BRR (STM32WB_USART1_BASE + STM32WB_USART_BRR_OFFSET) -# define STM32WB_USART1_GTPR (STM32WB_USART1_BASE + STM32WB_USART_GTPR_OFFSET) -# define STM32WB_USART1_RTOR (STM32WB_USART1_BASE + STM32WB_USART_RTOR_OFFSET) -# define STM32WB_USART1_RQR (STM32WB_USART1_BASE + STM32WB_USART_RQR_OFFSET) -# define STM32WB_USART1_ISR (STM32WB_USART1_BASE + STM32WB_USART_ISR_OFFSET) -# define STM32WB_USART1_ICR (STM32WB_USART1_BASE + STM32WB_USART_ICR_OFFSET) -# define STM32WB_USART1_RDR (STM32WB_USART1_BASE + STM32WB_USART_RDR_OFFSET) -# define STM32WB_USART1_TDR (STM32WB_USART1_BASE + STM32WB_USART_TDR_OFFSET) -# define STM32WB_USART1_PRESC (STM32WB_USART1_BASE + STM32WB_USART_PRESC_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c index 1192100de8fc2..fb2f6dc945191 100644 --- a/arch/arm/src/stm32wb/stm32wb_allocateheap.c +++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c @@ -60,20 +60,20 @@ /* Set the range of system SRAM1 */ -#define SRAM1_START STM32WB_SRAM1_BASE -#define SRAM1_END (SRAM1_START + STM32WB_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM1_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2a as well, requires a second memory region */ #ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32WB_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) # define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) #endif /* Set the range of SRAM2b as well, requires a third memory region */ #ifdef CONFIG_STM32WB_SRAM2B_HEAP -# define SRAM2B_START STM32WB_SRAM2B_BASE +# define SRAM2B_START STM32_SRAM2B_BASE # define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) #endif @@ -83,13 +83,13 @@ */ #ifdef CONFIG_STM32WB_SRAM2A_HEAP -# if SRAM2A_END > STM32WB_SRAM2A_BASE + STM32WB_SRAM2A_SIZE +# if SRAM2A_END > STM32_SRAM2A_BASE + STM32_SRAM2A_SIZE # error "SRAM2a heap memory region is out of it's physical address space" # endif #endif #ifdef CONFIG_STM32WB_SRAM2B_HEAP -# if SRAM2B_END > STM32WB_SRAM2B_BASE + STM32WB_SRAM2B_SIZE +# if SRAM2B_END > STM32_SRAM2B_BASE + STM32_SRAM2B_SIZE # error "SRAM2b heap memory region is out of it's physical address space" # endif #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 4e5de9fc88a0e..3b41a7bee2c05 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -45,61 +45,61 @@ /* HCI event header fields helpers */ -#define STM32WB_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) -#define STM32WB_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) +#define STM32_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) +#define STM32_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) -#define STM32WB_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) -#define STM32WB_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) +#define STM32_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) +#define STM32_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) /* BLE init configuration params */ -#define STM32WB_BLE_PREP_WRITE_NUM \ - STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU) +#define STM32_BLE_PREP_WRITE_NUM \ + STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU) -#define STM32WB_C2_MEM_BLOCK_NUM \ - STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU, \ +#define STM32_C2_MEM_BLOCK_NUM \ + STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU, \ CONFIG_STM32WB_BLE_MAX_CONN, \ - STM32WB_BLE_PREP_WRITE_NUM) + STM32_BLE_PREP_WRITE_NUM) #ifdef CONFIG_STM32WB_BLE_C2HOST -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST #else -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL #endif #ifdef CONFIG_STM32WB_BLE_SVC_CHANGED_CHAR -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED #else -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED #endif #ifdef CONFIG_STM32WB_BLE_WRITABLE_DEVICE_NAME -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW #else -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO #endif #ifdef CONFIG_STM32WB_BLE_CHAN_SEL_ALG2 -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED #else -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED #endif #ifdef CONFIG_STM32WB_BLE_POWER_CLASS_1 -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 #else -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 #endif -#define STM32WB_BLE_INIT_OPTIONS \ - (STM32WB_BLE_C2HOST | STM32WB_BLE_SVC_CHANGED_CHAR | \ - STM32WB_BLE_DEVICE_NAME_MODE | STM32WB_BLE_CS_ALG2 | \ - STM32WB_BLE_POWER_CLASS) +#define STM32_BLE_INIT_OPTIONS \ + (STM32_BLE_C2HOST | STM32_BLE_SVC_CHANGED_CHAR | \ + STM32_BLE_DEVICE_NAME_MODE | STM32_BLE_CS_ALG2 | \ + STM32_BLE_POWER_CLASS) #ifdef CONFIG_STM32WB_BLE_AGC_RSSI_IMPROVED -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED #else -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY #endif /**************************************************************************** @@ -200,21 +200,21 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) switch (evt->type) { - case STM32WB_MBOX_HCIEVT: + case STM32_MBOX_HCIEVT: len = sizeof(evt->evt_hdr) + evt->evt_hdr.len; if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_COMPLETE) { wlinfo("received command COMPLETE event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); } else if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_STATUS) { wlinfo("received command STATUS event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); #ifdef CONFIG_NIMBLE /* During initialisation NimBLE host stack sends unsupported @@ -223,18 +223,18 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) * with minimal impact we shim the response as succeeded. */ - if (STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && - (STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == + if (STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && + (STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == BT_OP(BT_OGF_BASEBAND, 0x0063))) { wlwarn("suppress FAILED command STATUS event from mailbox, " "(opcode: 0x%04x, status: %u) \n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); /* Suppress status field error value */ - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; } #endif } @@ -247,29 +247,29 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) bt_netdev_receive(&g_blehci_driver, BT_EVT, &evt->evt_hdr, len); break; - case STM32WB_MBOX_HCIACL: + case STM32_MBOX_HCIACL: len = sizeof(evt->acl_hdr) + evt->acl_hdr.len; wlinfo("received HCI ACL from mailbox (handle: 0x%04x, len: %u)\n", evt->acl_hdr.handle, evt->acl_hdr.len); bt_netdev_receive(&g_blehci_driver, BT_ACL_IN, &evt->acl_hdr, len); break; - case STM32WB_MBOX_SYSEVT: + case STM32_MBOX_SYSEVT: wlinfo("received SYS EVT 0x%02x from mailbox\n", evt->evt_hdr.evt); - if (evt->evt_hdr.evt == STM32WB_SHCI_ASYNC_EVT && - *(uint16_t *)(&evt->evt_hdr + 1) == STM32WB_SHCI_ASYNC_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ASYNC_EVT && + *(uint16_t *)(&evt->evt_hdr + 1) == STM32_SHCI_ASYNC_EVT_C2RDY) { stm32wb_blehci_bleinit(); } break; - case STM32WB_MBOX_SYSACK: + case STM32_MBOX_SYSACK: /* CPU2 Ready is the only expected response */ - DEBUGASSERT(evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY); + DEBUGASSERT(evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY); - if (evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY) { wlinfo("system command ACK response"); @@ -304,8 +304,8 @@ static void stm32wb_blehci_bleinit(void) .gatt_attr_buf_size = CONFIG_STM32WB_BLE_GATT_ATTR_BUF_SIZE, .max_conn = CONFIG_STM32WB_BLE_MAX_CONN, .dle_enable = CONFIG_STM32WB_BLE_DLE, - .prep_write_op_num = STM32WB_BLE_PREP_WRITE_NUM, - .mem_block_num = STM32WB_C2_MEM_BLOCK_NUM, + .prep_write_op_num = STM32_BLE_PREP_WRITE_NUM, + .mem_block_num = STM32_C2_MEM_BLOCK_NUM, .att_max_mtu_size = CONFIG_STM32WB_BLE_MAX_ATT_MTU, .slave_sca = CONFIG_STM32WB_BLE_SLAVE_SCA, .master_sca_range = CONFIG_STM32WB_BLE_MASTER_SCA, @@ -313,12 +313,12 @@ static void stm32wb_blehci_bleinit(void) .conn_event_length = CONFIG_STM32WB_BLE_MAX_CONN_EVT_LENGTH, .hse_startup = CONFIG_STM32WB_BLE_HSE_STARTUP, .viterbi_enable = CONFIG_STM32WB_BLE_VITERBI, - .options = STM32WB_BLE_INIT_OPTIONS, + .options = STM32_BLE_INIT_OPTIONS, .hw_version = 0, .max_initor_coc_num = CONFIG_STM32WB_BLE_MAX_INITOR_COC_NUM, .tx_power_min = CONFIG_STM32WB_BLE_MIN_TX_POWER, .tx_power_max = CONFIG_STM32WB_BLE_MAX_TX_POWER, - .rx_model_config = STM32WB_BLE_RXMOD_AGC_RSSI + .rx_model_config = STM32_BLE_RXMOD_AGC_RSSI }; /* Initialise BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c index ae37c4e53e096..9789c80b45c33 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.c +++ b/arch/arm/src/stm32wb/stm32wb_dma.c @@ -253,7 +253,7 @@ static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = { .id = 1, .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ - .base = STM32WB_DMAMUX1_BASE + .base = STM32_DMAMUX1_BASE } }; @@ -264,7 +264,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* 0 - DMA1 */ { - .base = STM32WB_DMA1_BASE, + .base = STM32_DMA1_BASE, .first = DMA1_FIRST, .nchan = DMA1_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ @@ -274,7 +274,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* 1 - DMA2 */ { - .base = STM32WB_DMA2_BASE, + .base = STM32_DMA2_BASE, .first = DMA2_FIRST, .nchan = DMA2_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ @@ -292,57 +292,57 @@ static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] = { .ctrl = DMA1, .chan = 0, - .irq = STM32WB_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA1, .chan = 1, - .irq = STM32WB_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA1, .chan = 2, - .irq = STM32WB_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA1, .chan = 3, - .irq = STM32WB_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA1, .chan = 4, - .irq = STM32WB_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA1, .chan = 5, - .irq = STM32WB_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA1, .chan = 6, - .irq = STM32WB_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #endif @@ -352,57 +352,57 @@ static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] = { .ctrl = DMA2, .chan = 0, - .irq = STM32WB_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA2, .chan = 1, - .irq = STM32WB_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA2, .chan = 2, - .irq = STM32WB_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA2, .chan = 3, - .irq = STM32WB_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA2, .chan = 4, - .irq = STM32WB_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA2, .chan = 5, - .irq = STM32WB_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA2, .chan = 6, - .irq = STM32WB_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -582,17 +582,17 @@ static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET, + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmachan->chan)); } @@ -617,21 +617,21 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) { } #ifdef CONFIG_STM32WB_DMA1 - else if (irq >= STM32WB_IRQ_DMA1CH1 && irq <= STM32WB_IRQ_DMA1CH7) + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - channel = irq - STM32WB_IRQ_DMA1CH1; + channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif #ifdef CONFIG_STM32WB_DMA2 - else if (irq >= STM32WB_IRQ_DMA2CH1 && irq <= STM32WB_IRQ_DMA2CH5) + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - channel = irq - STM32WB_IRQ_DMA2CH1; + channel = irq - STM32_IRQ_DMA2CH1; controller = DMA2; } - else if (irq >= STM32WB_IRQ_DMA2CH6 && irq <= STM32WB_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - channel = irq - STM32WB_IRQ_DMA2CH6 + (6 - 1); + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); controller = DMA2; } #endif @@ -647,7 +647,7 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmachan->chan); /* Invoke the callback */ @@ -660,7 +660,7 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -697,28 +697,28 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * disabled. */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -726,7 +726,7 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -734,7 +734,7 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); } /**************************************************************************** @@ -762,7 +762,7 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -796,7 +796,7 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** @@ -809,7 +809,7 @@ static size_t stm32wb_dma12_residual(DMA_HANDLE handle) DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - return dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** @@ -824,11 +824,11 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); stm32wb_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, @@ -857,19 +857,19 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, dmachan->ctrl + 1, msg); dmainfo(" ISR[%08x]: %08x\n", - dmabase + STM32WB_DMA_ISR_OFFSET, + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CCR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CCR_OFFSET, + dmachan->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CNDTR_OFFSET, + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CPAR_OFFSET, + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CMAR_OFFSET, + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); stm32wb_dmamux_dump(g_dma[dmachan->ctrl].dmamux, @@ -888,13 +888,13 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, struct stm32wb_dmaregs_s *regs) { - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RGSR_OFFSET); + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); } #endif @@ -908,20 +908,20 @@ static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_CXCR_OFFSET(channel), + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), regs->dmamux.ccr); dmainfo(" CSR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); dmainfo(" RG0CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); dmainfo(" RG1CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); dmainfo(" RG2CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); dmainfo(" RG3CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); dmainfo(" RGSR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); }; #endif @@ -1179,7 +1179,7 @@ void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, /* DMAMUX Set DMA channel source */ regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); /* Enable DMA channel */ @@ -1224,7 +1224,7 @@ void stm32wb_dmastop(DMA_HANDLE handle) /* DMAMUX Clear DMA channel source */ - dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); } /**************************************************************************** @@ -1315,23 +1315,23 @@ bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) mend = maddr + (count << msize_shift) - 1; - if ((maddr & STM32WB_REGION_MASK) != (mend & STM32WB_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32WB_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32WB_PERIPH_BASE: - case STM32WB_FSMC_BASE: - case STM32WB_FSMC_BANK1: - case STM32WB_FSMC_BANK2: - case STM32WB_FSMC_BANK3: - case STM32WB_QSPI_BANK: - case STM32WB_SRAM_BASE: - case STM32WB_SRAM2_BASE: - case STM32WB_SRAM3_BASE: - case STM32WB_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_QSPI_BANK: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_SRAM3_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ diff --git a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c index a0e29b306f188..3a45d0e54c7cf 100644 --- a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c +++ b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c @@ -49,7 +49,7 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32WB_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { 'A', 'B', 'C', #if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) @@ -88,31 +88,31 @@ int stm32wb_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32WB_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32WB_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32WB_GPIO_MODER_OFFSET), - getreg32(base + STM32WB_GPIO_OTYPER_OFFSET), - getreg32(base + STM32WB_GPIO_OSPEED_OFFSET), - getreg32(base + STM32WB_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", - getreg32(base + STM32WB_GPIO_IDR_OFFSET), - getreg32(base + STM32WB_GPIO_ODR_OFFSET), - getreg32(base + STM32WB_GPIO_BSRR_OFFSET), - getreg32(base + STM32WB_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08x AFRL: %08x\n", - getreg32(base + STM32WB_GPIO_AFRH_OFFSET), - getreg32(base + STM32WB_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08x\n", - g_portchar[port], getreg32(STM32WB_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c index a0076663dba61..8a4b9cf1538fc 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c @@ -71,7 +71,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32_EXTI_PR1); return ret; } @@ -107,29 +107,29 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); - up_enable_irq(STM32WB_IRQ_RTCALRM); + irq_attach(STM32_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); + up_enable_irq(STM32_IRQ_RTCALRM); } else { - up_disable_irq(STM32WB_IRQ_RTCALRM); + up_disable_irq(STM32_IRQ_RTCALRM); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_RTCALARM), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_RTCALARM) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_RTCALARM), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_RTCALARM) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_RTCALARM), event ? EXTI_C1EMR1_EM(EXTI_EVT_RTCALARM) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_RTCALARM), func ? EXTI_C1IMR1_IM(EXTI_EVT_RTCALARM) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c index 8ef567ccd1dc7..6d5afe56e694e 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c @@ -71,7 +71,7 @@ static int stm32wb_exti0_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(0), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(0), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -92,7 +92,7 @@ static int stm32wb_exti1_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(1), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(1), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -113,7 +113,7 @@ static int stm32wb_exti2_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(2), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(2), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -134,7 +134,7 @@ static int stm32wb_exti3_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(3), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(3), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -155,7 +155,7 @@ static int stm32wb_exti4_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(4), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(4), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -179,7 +179,7 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32WB_EXTI_PR1); + pr = getreg32(STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -192,7 +192,7 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32WB_EXTI_PR1); + putreg32(mask, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -265,7 +265,7 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32WB_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) @@ -293,14 +293,14 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, } else if (pin < 10) { - irq = STM32WB_IRQ_EXTI95; + irq = STM32_IRQ_EXTI95; handler = stm32wb_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32WB_IRQ_EXTI1510; + irq = STM32_IRQ_EXTI1510; handler = stm32wb_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; @@ -351,19 +351,19 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(pin), risingedge ? EXTI_RTSR1_RT(pin) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(pin), fallingedge ? EXTI_FTSR1_FT(pin) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(pin), event ? EXTI_C1EMR1_EM(pin) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(pin), func ? EXTI_C1IMR1_IM(pin) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c index d470837ff4d00..8caaed920191f 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c @@ -69,7 +69,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_PVD), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_PVD), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -114,29 +114,29 @@ int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); - up_enable_irq(STM32WB_IRQ_PVD); + irq_attach(STM32_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); + up_enable_irq(STM32_IRQ_PVD); } else { - up_disable_irq(STM32WB_IRQ_PVD); + up_disable_irq(STM32_IRQ_PVD); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_PVD), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_PVD) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_PVD), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_PVD) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_PVD), event ? EXTI_C1EMR1_EM(EXTI_EVT_PVD) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_PVD), func ? EXTI_C1IMR1_IM(EXTI_EVT_PVD) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c index eae587fda8e1b..0e44b3f4dcc2d 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c @@ -71,7 +71,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_RTC_WAKEUP, STM32WB_EXTI_PR1); + putreg32(EXTI_RTC_WAKEUP, STM32_EXTI_PR1); return ret; } @@ -107,29 +107,29 @@ int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); - up_enable_irq(STM32WB_IRQ_RTC_WKUP); + irq_attach(STM32_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); + up_enable_irq(STM32_IRQ_RTC_WKUP); } else { - up_disable_irq(STM32WB_IRQ_RTC_WKUP); + up_disable_irq(STM32_IRQ_RTC_WKUP); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_RTCWAKEUP), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_RTCWAKEUP) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_RTCWAKEUP), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_RTCWAKEUP) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_RTCWAKEUP), event ? EXTI_C1EMR1_EM(EXTI_EVT_RTCWAKEUP) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_RTCWAKEUP), func ? EXTI_C1IMR1_IM(EXTI_EVT_RTCWAKEUP) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 5d151d37c75dc..346a135594041 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -63,7 +63,7 @@ #define OPTBYTES_KEY1 0x08192a3b #define OPTBYTES_KEY2 0x4c5d6e7f -#define FLASH_PAGE_SIZE STM32WB_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */ @@ -91,35 +91,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } - if (getreg32(STM32WB_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32WB_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32WB_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32WB_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32WB_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32WB_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -136,17 +136,17 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_STRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** @@ -225,20 +225,20 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32WB_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32WB_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } @@ -251,42 +251,42 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32WB_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32WB_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32WB_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32WB_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32WB_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32WB_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32WB_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32WB_FLASH_PAGESIZE + STM32WB_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32WB_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -298,7 +298,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32WB_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -336,7 +336,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32WB_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -369,12 +369,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32WB_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32WB_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32WB_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -444,23 +444,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); for (i = 0; i < FLASH_PAGE_WORDS; i += 2) { *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } /* Verify */ - if (getreg32(STM32WB_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); ret = -EROFS; goto out; } @@ -468,13 +468,13 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (getreg32(dest - 1) != *(src - 1) || getreg32(dest - 2) != *(src - 2)) { - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); ret = -EIO; goto out; } } - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); /* Adjust pointers and counts for the next time through the loop */ @@ -494,9 +494,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32WB_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32WB_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c index a4168046aa411..bd56695e12142 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ b/arch/arm/src/stm32wb/stm32wb_freerun.c @@ -69,7 +69,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); return OK; } #endif /* CONFIG_CLOCK_TIMEKEEPING */ @@ -117,14 +117,14 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, return -EBUSY; } - STM32WB_TIM_SETCLOCK(freerun->tch, frequency); + STM32_TIM_SETCLOCK(freerun->tch, frequency); /* Initialize the remaining fields in the state structure and return * success. */ freerun->chan = chan; - freerun->width = STM32WB_TIM_GETWIDTH(freerun->tch); + freerun->width = STM32_TIM_GETWIDTH(freerun->tch); #ifdef CONFIG_CLOCK_TIMEKEEPING freerun->counter_mask = 0xffffffff; @@ -135,21 +135,21 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, /* Set up to receive the callback when the counter overflow occurs */ - STM32WB_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); #endif /* Set timer period */ - STM32WB_TIM_SETPERIOD(freerun->tch, + STM32_TIM_SETPERIOD(freerun->tch, (uint32_t)((1ull << freerun->width) - 1)); /* Start the counter */ - STM32WB_TIM_SETMODE(freerun->tch, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); #ifndef CONFIG_CLOCK_TIMEKEEPING - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - STM32WB_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); #endif return OK; @@ -198,9 +198,9 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, flags = enter_critical_section(); overflow = freerun->overflow; - counter = STM32WB_TIM_GETCOUNTER(freerun->tch); - pending = STM32WB_TIM_CHECKINT(freerun->tch, 0); - verify = STM32WB_TIM_GETCOUNTER(freerun->tch); + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -208,7 +208,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, if (pending) { - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -256,7 +256,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, uint64_t *counter) { - *counter = STM32WB_TIM_GETCOUNTER(freerun->tch); + *counter = STM32_TIM_GETCOUNTER(freerun->tch); return OK; } @@ -285,9 +285,9 @@ int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) /* Now we can disable the timer interrupt and disable the timer. */ - STM32WB_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETMODE(freerun->tch, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_SETISR(freerun->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); /* Free the timer */ diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.c b/arch/arm/src/stm32wb/stm32wb_gpio.c index d857d472a502c..433df3cea150c 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_gpio.c @@ -52,14 +52,14 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32WB_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { - STM32WB_GPIOA_BASE, - STM32WB_GPIOB_BASE, - STM32WB_GPIOC_BASE, - STM32WB_GPIOD_BASE, - STM32WB_GPIOE_BASE, - STM32WB_GPIOH_BASE + STM32_GPIOA_BASE, + STM32_GPIOB_BASE, + STM32_GPIOC_BASE, + STM32_GPIOD_BASE, + STM32_GPIOE_BASE, + STM32_GPIOH_BASE }; /**************************************************************************** @@ -119,7 +119,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32WB_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -168,10 +168,10 @@ int stm32wb_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32WB_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -194,10 +194,10 @@ int stm32wb_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32WB_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -212,17 +212,17 @@ int stm32wb_configgpio(uint32_t cfgset) if (pin < 8) { - regval = getreg32(base + STM32WB_GPIO_AFRL_OFFSET); + regval = getreg32(base + STM32_GPIO_AFRL_OFFSET); regval &= ~GPIO_AFRL_AFSEL_MASK(pin); regval |= (setting << GPIO_AFRL_AFSEL_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_AFRL_OFFSET); + putreg32(regval, base + STM32_GPIO_AFRL_OFFSET); } else { - regval = getreg32(base + STM32WB_GPIO_AFRH_OFFSET); + regval = getreg32(base + STM32_GPIO_AFRH_OFFSET); regval &= ~GPIO_AFRH_AFSEL_MASK(pin); regval |= (setting << GPIO_AFRH_AFSEL_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_AFRH_OFFSET); + putreg32(regval, base + STM32_GPIO_AFRH_OFFSET); } /* Set speed (Only outputs and alternate function pins) */ @@ -254,14 +254,14 @@ int stm32wb_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32WB_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32WB_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -274,7 +274,7 @@ int stm32wb_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32WB_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -291,7 +291,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32WB_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -353,7 +353,7 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WB_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -374,7 +374,7 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32WB_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -393,7 +393,7 @@ bool stm32wb_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WB_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -402,7 +402,7 @@ bool stm32wb_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32WB_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.h b/arch/arm/src/stm32wb/stm32wb_gpio.h index befb722c0eeb6..e407a28a56403 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/stm32wb_gpio.h @@ -45,11 +45,11 @@ ****************************************************************************/ #if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_NPORTS 6 +# define STM32_NPORTS 6 #elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_NPORTS 5 +# define STM32_NPORTS 5 #else -# define STM32WB_NPORTS 4 +# define STM32_NPORTS 4 #endif /* Bit-encoded input to stm32wb_configgpio() */ @@ -250,7 +250,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32WB_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index 3d7d6b8db1911..182d588027adf 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -32,7 +32,7 @@ * Standard-mode (up to 100 kHz) * Fast-mode (up to 400 kHz) * Fast-mode+ (up to 1 MHz) - * Clock source selection is based on STM32WB_RCC_CCIPR register + * Clock source selection is based on STM32_RCC_CCIPR register * * - Multiple instances (shared bus) * - Interrupt based operation @@ -432,14 +432,14 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef CONFIG_STM32WB_I2C1 static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = { - .base = STM32WB_I2C1_BASE, + .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, .reset_bit = RCC_APB1RSTR1_I2C1RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32WB_IRQ_I2C1EV, - .er_irq = STM32WB_IRQ_I2C1ER + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER #endif }; @@ -468,14 +468,14 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = #ifdef CONFIG_STM32WB_I2C3 static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = { - .base = STM32WB_I2C3_BASE, + .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32WB_IRQ_I2C3EV, - .er_irq = STM32WB_IRQ_I2C3ER + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER #endif }; @@ -631,7 +631,7 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) static inline void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif @@ -663,7 +663,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) * error-related, are enabled here. */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -701,7 +701,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; @@ -769,7 +769,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_set_7bit_address(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, (priv->msgv->addr << I2C_CR2_SADD7_SHIFT) & I2C_CR2_SADD7_MASK); } @@ -785,7 +785,7 @@ static inline void stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, uint8_t n_bytes) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } @@ -799,7 +799,7 @@ stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, static inline void stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** @@ -812,7 +812,7 @@ stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } @@ -826,7 +826,7 @@ stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } @@ -840,7 +840,7 @@ stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } @@ -880,7 +880,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR2_OFFSET); + cr = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -888,7 +888,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + sr = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { i2cerr("ERROR: waiting for a STOP isr timeout, elapsed: %lu\n", @@ -1076,14 +1076,14 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR1_OFFSET) & I2C_CR1_PE; + pe = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } -#if defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) switch (frequency) { case 100000ul: @@ -1104,7 +1104,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #else -#if STM32WB_PCLK1_FREQUENCY != 64000000ul +#if STM32_PCLK1_FREQUENCY != 64000000ul # error Unsupported I2C configuration. #endif @@ -1128,11 +1128,11 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #endif - stm32wb_i2c_putreg32(priv, STM32WB_I2C_TIMINGR_OFFSET, timingr); + stm32wb_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1279,7 +1279,7 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** @@ -1300,7 +1300,7 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending STOP\n"); stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } @@ -1315,7 +1315,7 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) static inline uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32WB_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** @@ -1329,7 +1329,7 @@ uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_ICR_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } @@ -1357,7 +1357,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Get state of the I2C controller */ - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1526,7 +1526,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Transmit current byte */ - stm32wb_i2c_putreg(priv, STM32WB_I2C_TXDR_OFFSET, *priv->ptr); + stm32wb_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1601,7 +1601,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32wb_i2c_getreg(priv, STM32WB_I2C_RXDR_OFFSET); + *priv->ptr = stm32wb_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1622,7 +1622,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Unsupported state */ stm32wb_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -1866,7 +1866,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); @@ -1889,7 +1889,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #else /* Read rest of the state */ - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -1927,7 +1927,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -1941,7 +1941,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Clear all interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_ICR_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -1954,7 +1954,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif } - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; @@ -1992,9 +1992,9 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Enable power and reset the peripheral */ - modifyreg32(STM32WB_RCC_APB1ENR1, 0, priv->config->clk_bit); - modifyreg32(STM32WB_RCC_APB1RSTR1, 0, priv->config->reset_bit); - modifyreg32(STM32WB_RCC_APB1RSTR1, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR1, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR1, priv->config->reset_bit, 0); /* Configure pins */ @@ -2030,7 +2030,7 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Enable I2C peripheral */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } @@ -2047,7 +2047,7 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) { /* Disable I2C */ - stm32wb_i2c_putreg32(priv, STM32WB_I2C_CR1_OFFSET, 0); + stm32wb_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ @@ -2066,7 +2066,7 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) /* Disable clocking */ - modifyreg32(STM32WB_RCC_APB1ENR1, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, priv->config->clk_bit, 0); return OK; } @@ -2146,8 +2146,8 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, waitrc = stm32wb_i2c_sem_waitdone(priv); - cr1 = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR1_OFFSET); - cr2 = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR2_OFFSET); + cr1 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.c b/arch/arm/src/stm32wb/stm32wb_ipcc.c index a9999bdcd12c2..795ec398c46a6 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.c +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.c @@ -53,27 +53,27 @@ void stm32wb_ipccreset(void) /* Disable CPU1 IPCC interrupts */ - putreg32(0x00000000, STM32WB_IPCC_C1CR); + putreg32(0x00000000, STM32_IPCC_C1CR); /* Clear CPU1 IPCC receive channel status */ - putreg32(IPCC_C1SCR_CLR_MASK, STM32WB_IPCC_C1SCR); + putreg32(IPCC_C1SCR_CLR_MASK, STM32_IPCC_C1SCR); /* Clear CPU2 IPCC receive channel status */ - putreg32(IPCC_C2SCR_CLR_MASK, STM32WB_IPCC_C2SCR); + putreg32(IPCC_C2SCR_CLR_MASK, STM32_IPCC_C2SCR); /* Disable CPU1 transmit/receive channels */ - regval = getreg32(STM32WB_IPCC_C1MR); + regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_MASK | IPCC_C1MR_FM_MASK; - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); /* Disable CPU2 transmit/receive channels */ - regval = getreg32(STM32WB_IPCC_C2MR); + regval = getreg32(STM32_IPCC_C2MR); regval |= IPCC_C2MR_OM_MASK | IPCC_C2MR_FM_MASK; - putreg32(regval, STM32WB_IPCC_C2MR); + putreg32(regval, STM32_IPCC_C2MR); } /**************************************************************************** @@ -90,21 +90,21 @@ void stm32wb_ipccenable(void) /* CPU2 IPCC clock enable */ - regval = getreg32(STM32WB_RCC_C2AHB3ENR); + regval = getreg32(STM32_RCC_C2AHB3ENR); regval |= RCC_C2AHB3ENR_IPCCEN; - putreg32(regval, STM32WB_RCC_C2AHB3ENR); + putreg32(regval, STM32_RCC_C2AHB3ENR); /* Enable EXTI event request for C1SEV interrupt to CPU2 */ - regval = getreg32(STM32WB_EXTI_C2EMR2); + regval = getreg32(STM32_EXTI_C2EMR2); regval |= EXTI_C2EMR2_EM(EXTI_EVT_C1SEV); - putreg32(regval, STM32WB_EXTI_C2EMR2); + putreg32(regval, STM32_EXTI_C2EMR2); /* Enable EXTI rising edge trigger for C1SEV interrupt to CPU2 */ - regval = getreg32(STM32WB_EXTI_RTSR2); + regval = getreg32(STM32_EXTI_RTSR2); regval |= EXTI_RTSR2_RT(EXTI_EVT_C1SEV); - putreg32(regval, STM32WB_EXTI_RTSR2); + putreg32(regval, STM32_EXTI_RTSR2); /* Set the internal event flag and send an event to CPU2 */ @@ -116,7 +116,7 @@ void stm32wb_ipccenable(void) /* Boot CPU2 after reset or wakeup from stop or standby modes */ - regval = getreg32(STM32WB_PWR_CR4); + regval = getreg32(STM32_PWR_CR4); regval |= PWR_CR4_C2BOOT; - putreg32(regval, STM32WB_PWR_CR4); + putreg32(regval, STM32_PWR_CR4); } diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.h b/arch/arm/src/stm32wb/stm32wb_ipcc.h index 1d8ae70afa55b..b130c89966245 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.h @@ -88,7 +88,7 @@ void stm32wb_ipccenable(void); static inline bool stm32wb_ipcc_rxactive(uint8_t chan) { - return (getreg32(STM32WB_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; + return (getreg32(STM32_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; } /**************************************************************************** @@ -101,7 +101,7 @@ static inline bool stm32wb_ipcc_rxactive(uint8_t chan) static inline bool stm32wb_ipcc_txactive(uint8_t chan) { - return (getreg32(STM32WB_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; + return (getreg32(STM32_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; } /**************************************************************************** @@ -114,7 +114,7 @@ static inline bool stm32wb_ipcc_txactive(uint8_t chan) static inline void stm32wb_ipcc_settxactive(uint8_t chan) { - putreg32(IPCC_C1SCR_SET_BIT(chan), STM32WB_IPCC_C1SCR); + putreg32(IPCC_C1SCR_SET_BIT(chan), STM32_IPCC_C1SCR); } /**************************************************************************** @@ -127,9 +127,9 @@ static inline void stm32wb_ipcc_settxactive(uint8_t chan) static inline void stm32wb_ipcc_masktxf(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_FM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** @@ -142,9 +142,9 @@ static inline void stm32wb_ipcc_masktxf(uint8_t chan) static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_FM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** @@ -157,9 +157,9 @@ static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) static inline void stm32wb_ipcc_maskrxo(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** @@ -172,9 +172,9 @@ static inline void stm32wb_ipcc_maskrxo(uint8_t chan) static inline void stm32wb_ipcc_unmaskrxo(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_OM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_irq.c b/arch/arm/src/stm32wb/stm32wb_irq.c index 9b06b2bd709a4..f87503a7802f5 100644 --- a/arch/arm/src/stm32wb/stm32wb_irq.c +++ b/arch/arm/src/stm32wb/stm32wb_irq.c @@ -203,13 +203,13 @@ static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32WB_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32WB_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -219,19 +219,19 @@ static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32WB_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32WB_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32WB_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32WB_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -261,7 +261,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32WB_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -319,13 +319,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32WB_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32WB_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32WB_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif stm32wb_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); @@ -335,23 +335,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32WB_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32WB_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32WB_IRQ_NMI, stm32wb_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32wb_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32WB_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32WB_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32WB_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32WB_IRQ_PENDSV, stm32wb_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32wb_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32WB_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32WB_IRQ_RESERVED, stm32wb_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32wb_reserved, NULL); #endif stm32wb_dumpnvic("initial", NR_IRQS); @@ -387,7 +387,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -422,7 +422,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -465,10 +465,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32WB_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32WB_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -481,7 +481,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32WB_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.c b/arch/arm/src/stm32wb/stm32wb_lowputc.c index 7d73b1afd13c3..c8807a1f5bfb5 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.c +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.c @@ -45,51 +45,51 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32WB_CONSOLE_BASE STM32WB_LPUART1_BASE -# define STM32WB_APBCLOCK STM32WB_PCLK1_FREQUENCY -# define STM32WB_CONSOLE_APBREG STM32WB_RCC_APB1ENR2 -# define STM32WB_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32WB_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32WB_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32WB_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32WB_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32WB_CONSOLE_TX GPIO_LPUART1_TX -# define STM32WB_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32WB_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32WB_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WB_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32WB_CONSOLE_BASE STM32WB_USART1_BASE -# define STM32WB_APBCLOCK STM32WB_PCLK2_FREQUENCY -# define STM32WB_CONSOLE_APBREG STM32WB_RCC_APB2ENR -# define STM32WB_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32WB_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32WB_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32WB_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32WB_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32WB_CONSOLE_TX GPIO_USART1_TX -# define STM32WB_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32WB_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32WB_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WB_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32WB_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32WB_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -97,9 +97,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32WB_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32WB_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -115,7 +115,7 @@ /* CR2 settings */ -# if STM32WB_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -157,19 +157,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32WB_USARTDIV8 \ - (((STM32WB_APBCLOCK << 1) + (STM32WB_CONSOLE_BAUD >> 1)) / STM32WB_CONSOLE_BAUD) -# define STM32WB_USARTDIV16 \ - ((STM32WB_APBCLOCK + (STM32WB_CONSOLE_BAUD >> 1)) / STM32WB_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32WB_USARTDIV8 > 100 -# define STM32WB_BRR_VALUE STM32WB_USARTDIV16 +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32WB_BRR_VALUE \ - ((STM32WB_USARTDIV8 & 0xfff0) | ((STM32WB_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif #endif /* HAVE_CONSOLE */ @@ -211,22 +211,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32WB_CONSOLE_RS485_DIR - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - STM32WB_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32WB_CONSOLE_BASE + STM32WB_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32WB_CONSOLE_RS485_DIR - while ((getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - !STM32WB_CONSOLE_RS485_DIR_POLARITY); + stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -252,7 +252,7 @@ void stm32wb_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32WB_CONSOLE_APBREG, 0, STM32WB_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -261,17 +261,17 @@ void stm32wb_lowsetup(void) * stm32wb_rcc.c */ -#ifdef STM32WB_CONSOLE_TX - stm32wb_configgpio(STM32WB_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32wb_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32WB_CONSOLE_RX - stm32wb_configgpio(STM32WB_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32wb_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32WB_CONSOLE_RS485_DIR - stm32wb_configgpio(STM32WB_CONSOLE_RS485_DIR); - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - !STM32WB_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wb_configgpio(STM32_CONSOLE_RS485_DIR); + stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -279,42 +279,42 @@ void stm32wb_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32WB_BRR_VALUE, - STM32WB_CONSOLE_BASE + STM32WB_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index 86c2e298c686b..232e03af6f77e 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -44,12 +44,12 @@ * the beginning of SRAM2a. */ -#define STM32WB_MBOX_SHARED_BASE STM32WB_SRAM2A_BASE +#define STM32_MBOX_SHARED_BASE STM32_SRAM2A_BASE /* Mailbox shared buffer fields */ #define stm32wb_mbox_shared \ - (*(struct stm32wb_mbox_shared_buffer_s *)STM32WB_MBOX_SHARED_BASE) + (*(struct stm32wb_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) #define stm32wb_mbox_ref_table (stm32wb_mbox_shared.ref_table) #define stm32wb_mbox_di_table (stm32wb_mbox_shared.dev_info_table) @@ -59,12 +59,12 @@ /* Mailbox buffer sizes */ -#define STM32WB_MBOX_CS_BUF_SIZE 16 -#define STM32WB_MBOX_CMDPKT_BUF_SIZE 268 -#define STM32WB_MBOX_ACLPKT_BUF_SIZE 264 +#define STM32_MBOX_CS_BUF_SIZE 16 +#define STM32_MBOX_CMDPKT_BUF_SIZE 268 +#define STM32_MBOX_ACLPKT_BUF_SIZE 264 -#define STM32WB_MBOX_RX_BUF_SIZE \ - (CONFIG_STM32WB_MBOX_RX_EVT_QUEUE_LEN * STM32WB_MBOX_CMDPKT_BUF_SIZE) +#define STM32_MBOX_RX_BUF_SIZE \ + (CONFIG_STM32WB_MBOX_RX_EVT_QUEUE_LEN * STM32_MBOX_CMDPKT_BUF_SIZE) /**************************************************************************** * Private Types @@ -156,15 +156,15 @@ struct stm32wb_mbox_shared_buffer_s aligned_data(4) stm32wb_mbox_list_t sys_evt_queue; #ifdef CONFIG_STM32WB_BLE - aligned_data(4) uint8_t ble_cs_buffer[STM32WB_MBOX_CS_BUF_SIZE]; + aligned_data(4) uint8_t ble_cs_buffer[STM32_MBOX_CS_BUF_SIZE]; #endif - aligned_data(4) uint8_t evtpool_buffer[STM32WB_MBOX_RX_BUF_SIZE]; - aligned_data(4) uint8_t sys_cmd_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t sys_spare_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t evtpool_buffer[STM32_MBOX_RX_BUF_SIZE]; + aligned_data(4) uint8_t sys_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t sys_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; #ifdef CONFIG_STM32WB_BLE - aligned_data(4) uint8_t ble_spare_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t ble_cmd_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t ble_acl_buffer[STM32WB_MBOX_ACLPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_acl_buffer[STM32_MBOX_ACLPKT_BUF_SIZE]; #endif }; @@ -205,7 +205,7 @@ static struct work_s g_tx_cmd_work; static stm32wb_mbox_list_t g_rx_evt_queue; static stm32wb_mbox_list_t g_tx_evtfree_queue; static uint8_t g_free_buffers[CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN] - [STM32WB_MBOX_CMDPKT_BUF_SIZE]; + [STM32_MBOX_CMDPKT_BUF_SIZE]; static stm32wb_mbox_list_t g_free_buffers_pool; static struct stm32wb_mbox_channel_s g_syscmd_channel; @@ -235,24 +235,24 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) /* Pull events from system channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32WB_MBOX_SYSEVT_CHANNEL)) + if (stm32wb_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) { stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.sys_evt_queue, &g_rx_evt_queue); - clrmask |= IPCC_C1SCR_CLR_BIT(STM32WB_MBOX_SYSEVT_CHANNEL); + clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_SYSEVT_CHANNEL); } #ifdef CONFIG_STM32WB_BLE /* Pull events from BLE channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32WB_MBOX_BLEEVT_CHANNEL)) + if (stm32wb_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) { stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.ble_evt_queue, &g_rx_evt_queue); - clrmask |= IPCC_C1SCR_CLR_BIT(STM32WB_MBOX_BLEEVT_CHANNEL); + clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_BLEEVT_CHANNEL); } #endif @@ -265,7 +265,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) /* Clear active statuses */ - putreg32(clrmask, STM32WB_IPCC_C1SCR); + putreg32(clrmask, STM32_IPCC_C1SCR); } /**************************************************************************** @@ -279,7 +279,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { - uint32_t c1mr = getreg32(STM32WB_IPCC_C1MR); + uint32_t c1mr = getreg32(STM32_IPCC_C1MR); uint32_t txfsrc; /* TXF interrupt can be triggered by not masked channels and active status @@ -287,12 +287,12 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) * channels and rise other C1MR bits to highlight needed channels. */ - txfsrc = ~(c1mr | (getreg32(STM32WB_IPCC_C1TOC2SR) << IPCC_C1MR_FM_SHIFT)) + txfsrc = ~(c1mr | (getreg32(STM32_IPCC_C1TOC2SR) << IPCC_C1MR_FM_SHIFT)) & IPCC_C1MR_FM_MASK; /* Check if the release channel triggered the interrupt */ - if (txfsrc & IPCC_C1MR_FM_BIT(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (txfsrc & IPCC_C1MR_FM_BIT(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all released events (if any) into transmission mailbox */ @@ -303,17 +303,17 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) /* Start release channel transmission */ - stm32wb_ipcc_settxactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } } /* Check other channels, except the release channel */ - if (txfsrc & ~IPCC_C1MR_FM_BIT(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (txfsrc & ~IPCC_C1MR_FM_BIT(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Check if the system channel triggered the interrupt */ - if (txfsrc & IPCC_C1MR_FM_BIT(STM32WB_MBOX_SYSCMD_CHANNEL)) + if (txfsrc & IPCC_C1MR_FM_BIT(STM32_MBOX_SYSCMD_CHANNEL)) { /* System channel works in 'half-duplex' mode and acks * immediately on each command before TXF, so it needs @@ -333,7 +333,7 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) /* Mask triggered channels */ - putreg32(c1mr | txfsrc, STM32WB_IPCC_C1MR); + putreg32(c1mr | txfsrc, STM32_IPCC_C1MR); } /**************************************************************************** @@ -350,7 +350,7 @@ static void stm32wb_mbox_txworker(void *arg) { handled = false; - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_SYSCMD_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) { /* Process ack response before send new command */ @@ -364,12 +364,12 @@ static void stm32wb_mbox_txworker(void *arg) } #ifdef CONFIG_STM32WB_BLE - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_BLECMD_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) { handled |= stm32wb_mbox_txnext(&g_blecmd_channel); } - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_BLEACL_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) { handled |= stm32wb_mbox_txnext(&g_bleacl_channel); } @@ -467,7 +467,7 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, stm32wb_ipcc_settxactive(chan->ch_num); if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) || - chan->ch_num == STM32WB_MBOX_SYSCMD_CHANNEL) + chan->ch_num == STM32_MBOX_SYSCMD_CHANNEL) { /* There are more commands awaiting, so unmask interrupt to get * notified when channel gets ready to process a next one. @@ -512,7 +512,7 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) { chan->cmd_buf->type = pkt_buf->type; - if (chan->ch_num == STM32WB_MBOX_BLEACL_CHANNEL) + if (chan->ch_num == STM32_MBOX_BLEACL_CHANNEL) { memcpy(&chan->cmd_buf->acl_hdr, &pkt_buf->acl_hdr, sizeof(pkt_buf->acl_hdr) + pkt_buf->acl_hdr.len); @@ -562,7 +562,7 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Check if release channel is ready to process now */ - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all collected events into transmission queue */ @@ -571,13 +571,13 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Start transmission */ - stm32wb_ipcc_settxactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } else { /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32wb_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); } leave_critical_section(flags); @@ -600,7 +600,7 @@ static void stm32wb_mbox_acksyscmd(void) */ evt = (struct stm32wb_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); - evt->type = STM32WB_MBOX_SYSACK; + evt->type = STM32_MBOX_SYSACK; receive_evt_handler(evt); } @@ -662,7 +662,7 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) /* Init system channel data */ - g_syscmd_channel.ch_num = STM32WB_MBOX_SYSCMD_CHANNEL; + g_syscmd_channel.ch_num = STM32_MBOX_SYSCMD_CHANNEL; g_syscmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) stm32wb_mbox_shared.sys_cmd_buffer; stm32wb_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); @@ -670,14 +670,14 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) #ifdef CONFIG_STM32WB_BLE /* Init BLE command channel data */ - g_blecmd_channel.ch_num = STM32WB_MBOX_BLECMD_CHANNEL; + g_blecmd_channel.ch_num = STM32_MBOX_BLECMD_CHANNEL; g_blecmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) stm32wb_mbox_shared.ble_cmd_buffer; stm32wb_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); /* Init BLE ACL channel data */ - g_bleacl_channel.ch_num = STM32WB_MBOX_BLEACL_CHANNEL; + g_bleacl_channel.ch_num = STM32_MBOX_BLEACL_CHANNEL; g_bleacl_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) stm32wb_mbox_shared.ble_acl_buffer; stm32wb_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); @@ -715,21 +715,21 @@ void stm32wb_mboxenable(void) /* Setup RXO and TXF interrupts */ - irq_attach(STM32WB_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); - up_enable_irq(STM32WB_IRQ_IPCCRX); + irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); + up_enable_irq(STM32_IRQ_IPCCRX); - irq_attach(STM32WB_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); - up_enable_irq(STM32WB_IRQ_IPCCTX); + irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); + up_enable_irq(STM32_IRQ_IPCCTX); - regval = getreg32(STM32WB_IPCC_C1CR); + regval = getreg32(STM32_IPCC_C1CR); regval |= IPCC_C1CR_RXOIE | IPCC_C1CR_TXFIE; - putreg32(regval, STM32WB_IPCC_C1CR); + putreg32(regval, STM32_IPCC_C1CR); /* Unmask system channel RXO interrupt. Once CPU2 started we expect * to receive C2READY event via system channel. */ - stm32wb_ipcc_unmaskrxo(STM32WB_MBOX_SYSEVT_CHANNEL); + stm32wb_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); /* Enable IPCC hardware and boot up CPU2 */ @@ -747,7 +747,7 @@ void stm32wb_mboxenable(void) int stm32wb_mbox_syscmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_syscmd_channel, STM32WB_MBOX_SYSCMD, + return stm32wb_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, data, len); } @@ -763,7 +763,7 @@ int stm32wb_mbox_syscmd(void *data, size_t len) int stm32wb_mbox_blecmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_blecmd_channel, STM32WB_MBOX_HCICMD, + return stm32wb_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, data, len); } @@ -778,7 +778,7 @@ int stm32wb_mbox_blecmd(void *data, size_t len) int stm32wb_mbox_bleacl(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_bleacl_channel, STM32WB_MBOX_HCIACL, + return stm32wb_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, data, len); } @@ -800,7 +800,7 @@ void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) /* Prepare command data */ - cmd->opcode = STM32WB_SHCI_BLE_INIT; + cmd->opcode = STM32_SHCI_BLE_INIT; cmd->param_len = sizeof(*cmd); memcpy(cmd + 1, params, sizeof(*params)); @@ -810,6 +810,6 @@ void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) /* Unmask BLE event channel RXO interrupt */ - stm32wb_ipcc_unmaskrxo(STM32WB_MBOX_BLEEVT_CHANNEL); + stm32wb_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); } #endif /* CONFIG_STM32WB_BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.h b/arch/arm/src/stm32wb/stm32wb_mbox.h index f67821fa5c566..6d5f9cc7932e9 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox.h @@ -42,34 +42,34 @@ /* Mailbox channels */ -#define STM32WB_MBOX_BLEEVT_CHANNEL 1 -#define STM32WB_MBOX_BLECMD_CHANNEL 1 -#define STM32WB_MBOX_SYSEVT_CHANNEL 2 -#define STM32WB_MBOX_SYSCMD_CHANNEL 2 -#define STM32WB_MBOX_EVT_RELEASE_CHANNEL 4 -#define STM32WB_MBOX_BLEACL_CHANNEL 6 +#define STM32_MBOX_BLEEVT_CHANNEL 1 +#define STM32_MBOX_BLECMD_CHANNEL 1 +#define STM32_MBOX_SYSEVT_CHANNEL 2 +#define STM32_MBOX_SYSCMD_CHANNEL 2 +#define STM32_MBOX_EVT_RELEASE_CHANNEL 4 +#define STM32_MBOX_BLEACL_CHANNEL 6 /* Mailbox packet types */ -#define STM32WB_MBOX_HCICMD 0x01 -#define STM32WB_MBOX_HCIACL 0x02 -#define STM32WB_MBOX_HCIEVT 0x04 -#define STM32WB_MBOX_SYSCMD 0x10 -#define STM32WB_MBOX_SYSEVT 0x12 -#define STM32WB_MBOX_SYSACK 0xe0 +#define STM32_MBOX_HCICMD 0x01 +#define STM32_MBOX_HCIACL 0x02 +#define STM32_MBOX_HCIEVT 0x04 +#define STM32_MBOX_SYSCMD 0x10 +#define STM32_MBOX_SYSEVT 0x12 +#define STM32_MBOX_SYSACK 0xe0 /* Mailbox configuration helpers */ -#define STM32WB_MBOX_BLE_ATT_DEFAULT_MTU 23 -#define STM32WB_MBOX_C2_MEM_BLOCK_SZ 32 +#define STM32_MBOX_BLE_ATT_DEFAULT_MTU 23 +#define STM32_MBOX_C2_MEM_BLOCK_SZ 32 #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) -#define STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(max_mtu) \ - (DIV_UP((max_mtu), STM32WB_MBOX_BLE_ATT_DEFAULT_MTU - 5) * 2) +#define STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(max_mtu) \ + (DIV_UP((max_mtu), STM32_MBOX_BLE_ATT_DEFAULT_MTU - 5) * 2) -#define STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(max_mtu, max_conn, pw) \ - ((pw) + ((max_conn) + 1) * (DIV_UP((max_mtu) + 4, STM32WB_MBOX_C2_MEM_BLOCK_SZ) + 2)) +#define STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(max_mtu, max_conn, pw) \ + ((pw) + ((max_conn) + 1) * (DIV_UP((max_mtu) + 4, STM32_MBOX_C2_MEM_BLOCK_SZ) + 2)) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h index 68536c3cfcb96..442dee86f15a0 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h @@ -37,87 +37,87 @@ /* SHCI event types *********************************************************/ -#define STM32WB_SHCI_ASYNC_EVT 0xff +#define STM32_SHCI_ASYNC_EVT 0xff /* SHCI async event subtypes */ -#define STM32WB_SHCI_ASYNC_EVT_C2RDY 0x9200 +#define STM32_SHCI_ASYNC_EVT_C2RDY 0x9200 /* SHCI system command acknowledgement events */ -#define STM32WB_SHCI_ACK_EVT_C2RDY 0x05 +#define STM32_SHCI_ACK_EVT_C2RDY 0x05 /* SHCI command opcodes *****************************************************/ -#define STM32WB_SHCI_OGF 0x3f -#define STM32WB_SHCI_OP(ogf, ocf) (((ogf) << 10) | (ocf)) - -#define STM32WB_SHCI_FUS_GET_STATE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x52) -#define STM32WB_SHCI_FUS_FW_UPGRADE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x54) -#define STM32WB_SHCI_FUS_FW_DELETE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x55) -#define STM32WB_SHCI_FUS_UPDATE_AUTH_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x56) -#define STM32WB_SHCI_FUS_LOCK_AUTH_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x57) -#define STM32WB_SHCI_FUS_STORE_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x58) -#define STM32WB_SHCI_FUS_LOAD_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x59) -#define STM32WB_SHCI_FUS_START_WS STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5a) -#define STM32WB_SHCI_FUS_LOCK_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5d) -#define STM32WB_SHCI_FUS_UNLOAD_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5e) -#define STM32WB_SHCI_FUS_ANTIROLLBACK STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5f) -#define STM32WB_SHCI_BLE_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x66) -#define STM32WB_SHCI_THREAD_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x67) -#define STM32WB_SHCI_DEBUG_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x68) -#define STM32WB_SHCI_FLASH_ERASE_ACTIVITY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x69) -#define STM32WB_SHCI_CONCURRENT_SET_MODE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6a) -#define STM32WB_SHCI_FLASH_STORE_DATA STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6b) -#define STM32WB_SHCI_FLASH_ERASE_DATA STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6c) -#define STM32WB_SHCI_RADIO_ALLOW_LOW_POWER STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6d) -#define STM32WB_SHCI_MAC_802154_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6e) -#define STM32WB_SHCI_REINIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6f) -#define STM32WB_SHCI_ZIGBEE_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x70) -#define STM32WB_SHCI_LLD_TESTS_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x71) -#define STM32WB_SHCI_EXTPA_CONFIG STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x72) -#define STM32WB_SHCI_SET_FLASH_CONTROL STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x73) -#define STM32WB_SHCI_BLE_LLD_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x74) -#define STM32WB_SHCI_CONFIG STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x75) -#define STM32WB_SHCI_GET_NEXT_BLE_EVT_TIME STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x76) -#define STM32WB_SHCI_ENABLE_NEXT_802154_NF STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x77) -#define STM32WB_SHCI_802_15_4_DEINIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x78) +#define STM32_SHCI_OGF 0x3f +#define STM32_SHCI_OP(ogf, ocf) (((ogf) << 10) | (ocf)) + +#define STM32_SHCI_FUS_GET_STATE STM32_SHCI_OP(STM32_SHCI_OGF, 0x52) +#define STM32_SHCI_FUS_FW_UPGRADE STM32_SHCI_OP(STM32_SHCI_OGF, 0x54) +#define STM32_SHCI_FUS_FW_DELETE STM32_SHCI_OP(STM32_SHCI_OGF, 0x55) +#define STM32_SHCI_FUS_UPDATE_AUTH_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x56) +#define STM32_SHCI_FUS_LOCK_AUTH_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x57) +#define STM32_SHCI_FUS_STORE_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x58) +#define STM32_SHCI_FUS_LOAD_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x59) +#define STM32_SHCI_FUS_START_WS STM32_SHCI_OP(STM32_SHCI_OGF, 0x5a) +#define STM32_SHCI_FUS_LOCK_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x5d) +#define STM32_SHCI_FUS_UNLOAD_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x5e) +#define STM32_SHCI_FUS_ANTIROLLBACK STM32_SHCI_OP(STM32_SHCI_OGF, 0x5f) +#define STM32_SHCI_BLE_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x66) +#define STM32_SHCI_THREAD_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x67) +#define STM32_SHCI_DEBUG_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x68) +#define STM32_SHCI_FLASH_ERASE_ACTIVITY STM32_SHCI_OP(STM32_SHCI_OGF, 0x69) +#define STM32_SHCI_CONCURRENT_SET_MODE STM32_SHCI_OP(STM32_SHCI_OGF, 0x6a) +#define STM32_SHCI_FLASH_STORE_DATA STM32_SHCI_OP(STM32_SHCI_OGF, 0x6b) +#define STM32_SHCI_FLASH_ERASE_DATA STM32_SHCI_OP(STM32_SHCI_OGF, 0x6c) +#define STM32_SHCI_RADIO_ALLOW_LOW_POWER STM32_SHCI_OP(STM32_SHCI_OGF, 0x6d) +#define STM32_SHCI_MAC_802154_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x6e) +#define STM32_SHCI_REINIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x6f) +#define STM32_SHCI_ZIGBEE_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x70) +#define STM32_SHCI_LLD_TESTS_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x71) +#define STM32_SHCI_EXTPA_CONFIG STM32_SHCI_OP(STM32_SHCI_OGF, 0x72) +#define STM32_SHCI_SET_FLASH_CONTROL STM32_SHCI_OP(STM32_SHCI_OGF, 0x73) +#define STM32_SHCI_BLE_LLD_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x74) +#define STM32_SHCI_CONFIG STM32_SHCI_OP(STM32_SHCI_OGF, 0x75) +#define STM32_SHCI_GET_NEXT_BLE_EVT_TIME STM32_SHCI_OP(STM32_SHCI_OGF, 0x76) +#define STM32_SHCI_ENABLE_NEXT_802154_NF STM32_SHCI_OP(STM32_SHCI_OGF, 0x77) +#define STM32_SHCI_802_15_4_DEINIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x78) /* Command params bitfield definitions **************************************/ /* BLE init command option flags */ -#define STM32WB_SHCI_BLE_INIT_OPT_STACK_MASK (1 << 0) /* Bit 0: BLE stack select */ -# define STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST (0 << 0) /* 0x0: Link Layer and Host */ -# define STM32WB_SHCI_BLE_INIT_OPT_STACK_LL (1 << 0) /* 0x1: Link Layer only */ +#define STM32_SHCI_BLE_INIT_OPT_STACK_MASK (1 << 0) /* Bit 0: BLE stack select */ +# define STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST (0 << 0) /* 0x0: Link Layer and Host */ +# define STM32_SHCI_BLE_INIT_OPT_STACK_LL (1 << 0) /* 0x1: Link Layer only */ -#define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_MASK (1 << 1) /* Bit 1: Service Changed characteristic */ -# define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED (0 << 1) /* 0x0: Characteristic enabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED (1 << 1) /* 0x1: Characteristic disabled */ +#define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_MASK (1 << 1) /* Bit 1: Service Changed characteristic */ +# define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED (0 << 1) /* 0x0: Characteristic enabled */ +# define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED (1 << 1) /* 0x1: Characteristic disabled */ -#define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_MASK (1 << 2) /* Bit 2: Device Name mode */ -# define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW (0 << 2) /* 0x0: Read-Write mode */ -# define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO (1 << 2) /* 0x1: Read-Only mode */ +#define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_MASK (1 << 2) /* Bit 2: Device Name mode */ +# define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW (0 << 2) /* 0x0: Read-Write mode */ +# define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO (1 << 2) /* 0x1: Read-Only mode */ -#define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_MASK (1 << 4) /* Bit 4: Channel selection algorithm 2 enabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED (0 << 4) /* 0x0: Algorithm 2 disabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED (1 << 4) /* 0x1: Algorithm 2 enabled */ +#define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_MASK (1 << 4) /* Bit 4: Channel selection algorithm 2 enabled */ +# define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED (0 << 4) /* 0x0: Algorithm 2 disabled */ +# define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED (1 << 4) /* 0x1: Algorithm 2 enabled */ -#define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_MASK (1 << 7) /* Bit 7: Power class */ -# define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 (0 << 7) /* 0x0: Power Class 2-3 */ -# define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 (1 << 7) /* 0x1: Power Class 1 */ +#define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_MASK (1 << 7) /* Bit 7: Power class */ +# define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 (0 << 7) /* 0x0: Power Class 2-3 */ +# define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 (1 << 7) /* 0x1: Power Class 1 */ /* BLE init command rx_model_config flags */ -#define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_MASK (1 << 0) /* Bit 0: AGC RSSI model */ -# define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY (0 << 0) /* 0x0: AGC RSSI Legacy */ -# define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED (1 << 0) /* 0x1: AGC RSSI Improved */ +#define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_MASK (1 << 0) /* Bit 0: AGC RSSI model */ +# define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY (0 << 0) /* 0x0: AGC RSSI Legacy */ +# define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED (1 << 0) /* 0x1: AGC RSSI Improved */ /**************************************************************************** * Public Types ****************************************************************************/ -/* STM32WB_SHCI_BLE_INIT command params */ +/* STM32_SHCI_BLE_INIT command params */ begin_packed_struct struct stm32wb_shci_ble_init_cfg_s { diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c index ed0d899531cf0..bd8ffa00d19b5 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.c @@ -86,10 +86,10 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) * Disable the TC now and disable any further interrupts. */ - STM32WB_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32WB_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); /* The timer is no longer running */ @@ -200,7 +200,7 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, return -EBUSY; } - STM32WB_TIM_SETCLOCK(oneshot->tch, frequency); + STM32_TIM_SETCLOCK(oneshot->tch, frequency); /* Initialize the remaining fields in the state structure. */ @@ -301,19 +301,19 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32WB_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); /* Set timer period */ oneshot->period = (uint32_t)period; - STM32WB_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); /* Start the counter */ - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_PULSE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - STM32WB_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - STM32WB_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); /* Enable interrupts. We should get the callback when the interrupt * occurs. @@ -388,14 +388,14 @@ int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, tmrinfo("Cancelling...\n"); - count = STM32WB_TIM_GETCOUNTER(oneshot->tch); + count = STM32_TIM_GETCOUNTER(oneshot->tch); period = oneshot->period; /* Now we can disable the interrupt and stop the timer. */ - STM32WB_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); oneshot->running = false; oneshot->handler = NULL; diff --git a/arch/arm/src/stm32wb/stm32wb_pmlpr.c b/arch/arm/src/stm32wb/stm32wb_pmlpr.c index c81179f8c62b8..fa601b27961bb 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmlpr.c +++ b/arch/arm/src/stm32wb/stm32wb_pmlpr.c @@ -60,34 +60,34 @@ int stm32wb_pmlpr(void) /* Enable MSI clock */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; /* Set MSI clock to 2 MHz */ regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Select MSI clock as system clock source */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_MSI; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the MSI source is used as the system clock source */ - while ((getreg32(STM32WB_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI) { } /* Enable Low-Power Run */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval |= PWR_CR1_LPR; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_pmstandby.c b/arch/arm/src/stm32wb/stm32wb_pmstandby.c index d1fd88ac03c50..657f4bf677926 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstandby.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstandby.c @@ -63,15 +63,15 @@ int stm32wb_pmstandby(void) regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5; - putreg32(regval, STM32WB_PWR_SCR); + putreg32(regval, STM32_PWR_SCR); /* Select Standby mode */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STANDBY; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set SLEEPDEEP bit of Cortex System Control Register */ diff --git a/arch/arm/src/stm32wb/stm32wb_pmstop.c b/arch/arm/src/stm32wb/stm32wb_pmstop.c index 683af0cd07a24..1cbd80f0e23b4 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstop.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstop.c @@ -98,7 +98,7 @@ int stm32wb_pmstop(bool lpds) * register CR1. */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; /* Select Stop 1 mode with low-power regulator if so requested */ @@ -108,7 +108,7 @@ int stm32wb_pmstop(bool lpds) regval |= PWR_CR1_LPMS_STOP1; } - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } @@ -135,10 +135,10 @@ int stm32wb_pmstop2(void) /* Select Stop 2 mode in power control register 1. */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STOP2; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.c b/arch/arm/src/stm32wb/stm32wb_pwr.c index c13ca0b14803a..62fe1b7be840b 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_pwr.c @@ -41,18 +41,18 @@ static inline uint16_t stm32wb_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32WB_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wb_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32WB_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg32(STM32WB_PWR_BASE + (uint32_t)offset, + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); } @@ -82,7 +82,7 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Get the current state of the STM32WB PWR control register 1 */ - regval = stm32wb_pwr_getreg(STM32WB_PWR_CR1_OFFSET); + regval = stm32wb_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -92,14 +92,14 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32WB_PWR_CR1_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32WB_PWR_CR1_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -132,7 +132,7 @@ bool stm32wb_pwr_enableusv(bool set) /* Get the current state of the STM32WB PWR control register 2 */ - regval = stm32wb_pwr_getreg(STM32WB_PWR_CR2_OFFSET); + regval = stm32wb_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -142,14 +142,14 @@ bool stm32wb_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32wb_pwr_putreg(STM32WB_PWR_CR2_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32wb_pwr_putreg(STM32WB_PWR_CR2_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } return was_set; @@ -183,7 +183,7 @@ void stm32_pwr_setvos(int vos) return; } - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; if (vos == 1) @@ -195,5 +195,5 @@ void stm32_pwr_setvos(int vos) regval |= PWR_CR1_VOS_RANGE2; } - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index 9fd6f17b2a4b2..e731a9448e505 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -61,9 +61,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32WB_HAVE_HSI48) && defined(STM32WB_USE_CLK48) -# if STM32WB_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32WB_USE_HSI48 +#if defined(CONFIG_STM32WB_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -89,47 +89,47 @@ static inline void rcc_reset(void) /* Enable the Multi-Speed Internal clock (MSI) @ 4MHz */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_4M | RCC_CR_MSION; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= RCC_CFGR_RESET_MASK; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_MSIPLLEN); - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset LSI1 and LSI2 bits */ - regval = getreg32(STM32WB_RCC_CSR); + regval = getreg32(STM32_RCC_CSR); regval &= ~(RCC_CSR_LSI1ON | RCC_CSR_LSI2ON); - putreg32(regval, STM32WB_RCC_CSR); + putreg32(regval, STM32_RCC_CSR); /* Reset HSI48ON bit */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~(RCC_CRRCR_HSI48ON); - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Reset PLLCFGR register */ - putreg32(RCC_PLLCFG_RESET, STM32WB_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset PLLSAI1CFG register */ - putreg32(RCC_PLLSAI1CFG_RESET, STM32WB_RCC_PLLSAI1CFG); + putreg32(RCC_PLLSAI1CFG_RESET, STM32_RCC_PLLSAI1CFG); /* Disable all interrupts */ - putreg32(0x00000000, STM32WB_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -148,7 +148,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32WB_DMA1 /* DMA 1 clock enable */ @@ -180,7 +180,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32WB_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -199,7 +199,7 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIO ports A-E, H */ @@ -224,7 +224,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_AES1EN; #endif - putreg32(regval, STM32WB_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -243,7 +243,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32WB_QSPI /* QuadSPI module clock enable */ @@ -287,7 +287,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FLASHEN; #endif - putreg32(regval, STM32WB_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -306,7 +306,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32WB_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32WB_TIM2 /* TIM2 clock enable */ @@ -350,8 +350,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef STM32WB_USE_HSI48 - if (STM32WB_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -371,11 +371,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32WB_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32WB_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32WB_LPUART1 /* Low power uart clock enable */ @@ -389,7 +389,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32WB_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -408,7 +408,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32WB_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #ifdef CONFIG_STM32WB_TIM1 /* TIM1 clock enable */ @@ -446,7 +446,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SAI1EN; #endif - putreg32(regval, STM32WB_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -466,9 +466,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32WB_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32WB_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -481,11 +481,11 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI16; #endif -#endif /* STM32WB_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32WB_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32WB_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ @@ -500,7 +500,7 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif - putreg32(regval, STM32WB_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); } /**************************************************************************** @@ -519,12 +519,12 @@ static void stm32wb_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32WB_BOARD_USEHSI) || defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -532,7 +532,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -541,17 +541,17 @@ static void stm32wb_stdclockconfig(void) } #endif -#if defined(STM32WB_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32WB_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { @@ -563,10 +563,10 @@ static void stm32wb_stdclockconfig(void) /* Setting MSIRANGE */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32WB_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32WB_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -574,7 +574,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -582,12 +582,12 @@ static void stm32wb_stdclockconfig(void) } } -#elif defined(STM32WB_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -595,7 +595,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -604,7 +604,7 @@ static void stm32wb_stdclockconfig(void) } #else -# error stm32wb_stdclockconfig(), must have one of STM32WB_BOARD_USEHSI, STM32WB_BOARD_USEMSI, STM32WB_BOARD_USEHSE defined +# error stm32wb_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -617,144 +617,144 @@ static void stm32wb_stdclockconfig(void) { /* Setup regulator voltage according to clock frequency */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; -#if STM32WB_SYSCLK_FREQUENCY > 16000000 || \ +#if STM32_SYSCLK_FREQUENCY > 16000000 || \ (defined(BOARD_MAX_PLL_FREQUENCY) && BOARD_MAX_PLL_FREQUENCY > 16000000) regval |= PWR_CR1_VOS_RANGE1; #else regval |= PWR_CR1_VOS_RANGE2; #endif - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set the HCLK source/divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32WB_RCC_CFGR_HPRE; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the CPU2 HCLK2 source/divider */ - regval = getreg32(STM32WB_RCC_EXTCFGR); + regval = getreg32(STM32_RCC_EXTCFGR); regval &= ~RCC_EXTCFGR_C2HPRE_MASK; - regval |= STM32WB_RCC_EXTCFGR_C2HPRE; - putreg32(regval, STM32WB_RCC_EXTCFGR); + regval |= STM32_RCC_EXTCFGR_C2HPRE; + putreg32(regval, STM32_RCC_EXTCFGR); /* Set the HCLK4 source/divider */ - regval = getreg32(STM32WB_RCC_EXTCFGR); + regval = getreg32(STM32_RCC_EXTCFGR); regval &= ~RCC_EXTCFGR_SHDHPRE_MASK; - regval |= STM32WB_RCC_EXTCFGR_SHDHPRE; - putreg32(regval, STM32WB_RCC_EXTCFGR); + regval |= STM32_RCC_EXTCFGR_SHDHPRE; + putreg32(regval, STM32_RCC_EXTCFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32WB_RCC_CFGR_PPRE1; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32WB_RCC_CFGR_PPRE2; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Configure Main PLL */ - regval = getreg32(STM32WB_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); regval &= ~(RCC_PLLCFG_PLLM_MASK | RCC_PLLCFG_PLLN_MASK); - regval |= (STM32WB_PLLCFG_PLLM | STM32WB_PLLCFG_PLLN); + regval |= (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN); /* Set the PLL dividers and multipliers to configure the main PLL */ regval &= ~(RCC_PLLCFG_PLLPEN | RCC_PLLCFG_PLLQEN | RCC_PLLCFG_PLLREN); -#ifdef STM32WB_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval &= ~RCC_PLLCFG_PLLP_MASK; - regval |= (RCC_PLLCFG_PLLPEN | STM32WB_PLLCFG_PLLP); + regval |= (RCC_PLLCFG_PLLPEN | STM32_PLLCFG_PLLP); #endif -#ifdef STM32WB_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval &= ~RCC_PLLCFG_PLLQ_MASK; - regval |= (RCC_PLLCFG_PLLQEN | STM32WB_PLLCFG_PLLQ); + regval |= (RCC_PLLCFG_PLLQEN | STM32_PLLCFG_PLLQ); #endif -#ifdef STM32WB_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval &= ~RCC_PLLCFG_PLLR_MASK; - regval |= (RCC_PLLCFG_PLLREN | STM32WB_PLLCFG_PLLR); + regval |= (RCC_PLLCFG_PLLREN | STM32_PLLCFG_PLLR); #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32WB_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval &= ~RCC_PLLCFG_PLLSRC_MASK; -#ifdef STM32WB_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32WB_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32WB_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32WB_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WB_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32WB_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32WB_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); regval &= ~RCC_PLLSAI1CFG_PLLN_MASK; - regval |= STM32WB_PLLSAI1CFG_PLLN; + regval |= STM32_PLLSAI1CFG_PLLN; /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ regval &= ~(RCC_PLLSAI1CFG_PLLPEN | RCC_PLLSAI1CFG_PLLQEN | RCC_PLLSAI1CFG_PLLREN); -#ifdef STM32WB_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLP_MASK; - regval |= (RCC_PLLSAI1CFG_PLLPEN | STM32WB_PLLSAI1CFG_PLLP); + regval |= (RCC_PLLSAI1CFG_PLLPEN | STM32_PLLSAI1CFG_PLLP); #endif -#ifdef STM32WB_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLQ_MASK; - regval |= (RCC_PLLSAI1CFG_PLLQEN | STM32WB_PLLSAI1CFG_PLLQ); + regval |= (RCC_PLLSAI1CFG_PLLQEN | STM32_PLLSAI1CFG_PLLQ); #endif -#ifdef STM32WB_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLR_MASK; - regval |= (RCC_PLLSAI1CFG_PLLREN | STM32WB_PLLSAI1CFG_PLLR); + regval |= (RCC_PLLSAI1CFG_PLLREN | STM32_PLLSAI1CFG_PLLR); #endif - putreg32(regval, STM32WB_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WB_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif /* Configure FLASH wait states */ - regval = getreg32(STM32WB_FLASH_ACR); + regval = getreg32(STM32_FLASH_ACR); regval &= ~FLASH_ACR_LATENCY_MASK; #ifdef BOARD_FLASH_WAITSTATES regval |= FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); @@ -770,18 +770,18 @@ static void stm32wb_stdclockconfig(void) regval &= ~FLASH_ACR_PRFTEN; #endif regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); - putreg32(regval, STM32WB_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32WB_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -792,7 +792,7 @@ static void stm32wb_stdclockconfig(void) stm32wb_rcc_enable_lsi(); #endif -#if defined(STM32WB_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -807,25 +807,25 @@ static void stm32wb_stdclockconfig(void) stm32wb_rcc_enable_lse(); -# if defined(STM32WB_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32WB_USE_LSE */ +#endif /* STM32_USE_LSE */ /* Select CPU2 RF wakeup clock source, no clock if not set */ - regval = getreg32(STM32WB_RCC_CSR); + regval = getreg32(STM32_RCC_CSR); regval &= ~RCC_CSR_RFWKPSEL_MASK; -#if defined(STM32WB_BOARD_RFWKP_USELSE) +#if defined(STM32_BOARD_RFWKP_USELSE) regval |= RCC_CSR_RFWKPSEL_LSE; -#elif defined(STM32WB_BOARD_RFWKP_USEHSE) +#elif defined(STM32_BOARD_RFWKP_USEHSE) regval |= RCC_CSR_RFWKPSEL_HSE; #endif - putreg32(regval, STM32WB_RCC_CSR); + putreg32(regval, STM32_RCC_CSR); } } #endif @@ -843,10 +843,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32WB_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32wb_enable_hsi48(STM32WB_HSI48_SYNCSRC); + stm32wb_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -881,14 +881,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32wb_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32WB_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32WB_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32WB_RTC_BKPR(i)); + bkregs[i] = getreg32(STM32_RTC_BKPR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -901,16 +901,16 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32WB_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32WB_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG != STM32WB_RTC_BKPR(i)) + if (RTC_MAGIC_REG != STM32_RTC_BKPR(i)) { - putreg32(bkregs[i], STM32WB_RTC_BKPR(i)); + putreg32(bkregs[i], STM32_RTC_BKPR(i)); } } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index c770e462bd143..e6e675a3534b3 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -88,7 +88,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) { uint32_t regval; - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); /* Set MCO source */ @@ -99,7 +99,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) regval &= ~(RCC_CFGR_MCOPRE_MASK); regval |= (divider & RCC_CFGR_MCOPRE_MASK); - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c index e8d12b2d35282..abdb78b4b4430 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c @@ -77,13 +77,13 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * enabled. */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval |= RCC_CRRCR_HSI48ON; - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Wait for the HSI48 clock to stabilize */ - while ((getreg32(STM32WB_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); + while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); /* Return if no synchronization */ @@ -97,7 +97,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * clock or the USB SOF signal. */ - regval = getreg32(STM32WB_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; switch (syncsrc) @@ -116,7 +116,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) break; } - putreg32(regval, STM32WB_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic * hardware adjustment of TRIM bits according to the measured frequency @@ -124,9 +124,9 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * frequency error counter and SYNC events. */ - regval = getreg32(STM32WB_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; - putreg32(regval, STM32WB_CRS_CR); + putreg32(regval, STM32_CRS_CR); } /**************************************************************************** @@ -149,18 +149,18 @@ void stm32wb_rcc_disable_hsi48(void) /* Disable the HSI48 clock */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~RCC_CRRCR_HSI48ON; - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Set other registers to the default settings. */ - regval = getreg32(STM32WB_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; regval |= CRS_CFGR_SYNCSRC_USBSOF; - putreg32(regval, STM32WB_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); - regval = getreg32(STM32WB_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32WB_CRS_CR); + putreg32(regval, STM32_CRS_CR); } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index 4927de6dec4cd..e032a1a1c6dee 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -68,7 +68,7 @@ void stm32wb_rcc_enable_lse(void) /* Check if the External Low-Speed (LSE) oscillator is already running. */ - regval = getreg32(STM32WB_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) != (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) @@ -94,11 +94,11 @@ void stm32wb_rcc_enable_lse(void) RCC_BDCR_LSEDRV_SHIFT; #endif - putreg32(regval, STM32WB_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready */ - while (((regval = getreg32(STM32WB_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) + while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { stm32wb_waste(); } @@ -116,7 +116,7 @@ void stm32wb_rcc_enable_lse(void) regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WB_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c index 32597118fbfd8..9fa23cfc73a8e 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c @@ -47,11 +47,11 @@ void stm32wb_rcc_enable_lsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WB_RCC_CSR, 0, RCC_CSR_LSI1ON); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSI1ON); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32WB_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); } /**************************************************************************** @@ -68,7 +68,7 @@ void stm32wb_rcc_disable_lsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WB_RCC_CSR, RCC_CSR_LSI1ON, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSI1ON, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.c b/arch/arm/src/stm32wb/stm32wb_rtc.c index f33974fdb4e94..78c793ef0388f 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc.c @@ -139,23 +139,23 @@ static inline void rtc_enable_alarm(void); static void rtc_dumpregs(const char *msg) { rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32WB_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_WUTR)); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_CALR)); - rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TAMPCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBSSR)); - rtcinfo(" OR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_OR)); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAMPCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo(" OR: %08" PRIx32 "\n", getreg32(STM32_RTC_OR)); rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); } #else @@ -211,8 +211,8 @@ static void rtc_wprunlock(void) * Writing a wrong key re-activates the write protection. */ - putreg32(RTC_WPR_KEY1, STM32WB_RTC_WPR); - putreg32(RTC_WPR_KEY2, STM32WB_RTC_WPR); + putreg32(RTC_WPR_KEY1, STM32_RTC_WPR); + putreg32(RTC_WPR_KEY2, STM32_RTC_WPR); } /**************************************************************************** @@ -233,7 +233,7 @@ static inline void rtc_wprlock(void) { /* Writing any wrong key re-activates the write protection. */ - putreg32(0xff, STM32WB_RTC_WPR); + putreg32(0xff, STM32_RTC_WPR); /* Disable write access to the backup domain. */ @@ -263,16 +263,16 @@ static int rtc_synchwait(void) /* Clear Registers synchronization flag (RSF) */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Now wait the registers to become synchronised */ ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_RSF) != 0) { /* Synchronized */ @@ -307,21 +307,21 @@ static int rtc_enterinit(void) /* Check if the Initialization mode is already set */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); ret = OK; if ((regval & RTC_ISR_INITF) == 0) { /* Set the Initialization mode */ - putreg32(RTC_ISR_INIT, STM32WB_RTC_ISR); + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); /* Wait until the RTC is in the INIT state (or a timeout occurs) */ ret = -ETIMEDOUT; for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_INITF) != 0) { ret = OK; @@ -351,9 +351,9 @@ static void rtc_exitinit(void) { uint32_t regval; - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); } /**************************************************************************** @@ -425,13 +425,13 @@ static void rtc_resume(void) /* Clear the RTC alarm flags */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32_EXTI_PR1); #endif } @@ -469,10 +469,10 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* Check for EXTI from Alarm A or B and handle according */ - cr = getreg32(STM32WB_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRAIE) != 0) { - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRAF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMA]; @@ -491,17 +491,17 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRAF; - putreg32(isr, STM32WB_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #if CONFIG_RTC_NALARMS > 1 - cr = getreg32(STM32WB_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRBIE) != 0) { - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRBF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMB]; @@ -520,9 +520,9 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRBF; - putreg32(isr, STM32WB_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #endif @@ -565,7 +565,7 @@ static int rtchw_check_alrawf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRAWF) != 0) { ret = OK; @@ -591,7 +591,7 @@ static int rtchw_check_alrbwf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRBWF) != 0) { ret = OK; @@ -630,12 +630,12 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Disable RTC alarm A & Interrupt A */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); /* Ensure Alarm A flag reset; this is edge triggered */ - isr = getreg32(STM32WB_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm A to be writable */ @@ -647,13 +647,13 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm A register */ - putreg32(alarmreg, STM32WB_RTC_ALRMAR); - putreg32(0, STM32WB_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMAR)); + putreg32(alarmreg, STM32_RTC_ALRMAR); + putreg32(0, STM32_RTC_ALRMASSR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ - modifyreg32(STM32WB_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); errout_with_wprunlock: rtc_wprlock(); @@ -673,12 +673,12 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Disable RTC alarm B & Interrupt B */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); /* Ensure Alarm B flag reset; this is edge triggered */ - isr = getreg32(STM32WB_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm B to be writable */ @@ -690,13 +690,13 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm B register */ - putreg32(alarmreg, STM32WB_RTC_ALRMBR); - putreg32(0, STM32WB_RTC_ALRMBSSR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBR)); + putreg32(alarmreg, STM32_RTC_ALRMBR); + putreg32(0, STM32_RTC_ALRMBSSR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); /* Enable RTC alarm B */ - modifyreg32(STM32WB_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); rtchw_set_alrmbr_exit: rtc_wprlock(); @@ -861,13 +861,13 @@ int up_rtc_initialize(void) stm32wb_pwr_enablebkp(true); #if defined(CONFIG_STM32WB_RTC_HSECLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); #elif defined(CONFIG_STM32WB_RTC_LSICLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); #elif defined(CONFIG_STM32WB_RTC_LSECLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else # error "No clock for RTC!" @@ -875,7 +875,7 @@ int up_rtc_initialize(void) /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - modifyreg32(STM32WB_RCC_BDCR, 0, RCC_BDCR_RTCEN); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* Disable the write protection for RTC registers */ @@ -903,9 +903,9 @@ int up_rtc_initialize(void) { /* Clear RTC_CR FMT, OSEL and POL Bits */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Configure RTC pre-scaler with the required values */ @@ -921,7 +921,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); + STM32_RTC_PRER); #elif defined(CONFIG_STM32WB_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) @@ -929,13 +929,13 @@ int up_rtc_initialize(void) putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); + STM32_RTC_PRER); #else /* defined(CONFIG_STM32WB_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); + STM32_RTC_PRER); #endif /* Exit Initialization mode */ @@ -1029,18 +1029,18 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, do { - dr = getreg32(STM32WB_RTC_DR); - tr = getreg32(STM32WB_RTC_TR); + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); #ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32WB_RTC_SSR); - tmp = getreg32(STM32WB_RTC_TR); + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); if (tmp != tr) { continue; } #endif - tmp = getreg32(STM32WB_RTC_DR); + tmp = getreg32(STM32_RTC_DR); } while (tmp != dr); @@ -1095,7 +1095,7 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, uint32_t prediv_s; uint32_t usecs; - prediv_s = getreg32(STM32WB_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; ssr &= RTC_SSR_MASK; @@ -1242,8 +1242,8 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) { /* Set the RTC TR and DR registers */ - putreg32(tr, STM32WB_RTC_TR); - putreg32(dr, STM32WB_RTC_DR); + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); /* Exit Initialization mode and wait for the RTC Time and Date * registers to be synchronized with RTC APB clock. @@ -1439,7 +1439,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); ret = rtchw_check_alrawf(); if (ret < 0) @@ -1449,8 +1449,8 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(0xffffffff, STM32WB_RTC_ALRMAR); - modifyreg32(STM32WB_RTC_ISR, RTC_ISR_ALRAF, 0); + putreg32(0xffffffff, STM32_RTC_ALRMAR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); rtc_wprlock(); ret = OK; } @@ -1470,7 +1470,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); ret = rtchw_check_alrbwf(); if (ret < 0) @@ -1480,8 +1480,8 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(0xffffffff, STM32WB_RTC_ALRMBR); - modifyreg32(STM32WB_RTC_ISR, RTC_ISR_ALRBF, 0); + putreg32(0xffffffff, STM32_RTC_ALRMBR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); rtc_wprlock(); ret = OK; } @@ -1528,7 +1528,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { case RTC_ALARMA: { - alarmreg = STM32WB_RTC_ALRMAR; + alarmreg = STM32_RTC_ALRMAR; ret = stm32wb_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1537,7 +1537,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #if CONFIG_RTC_NALARMS > 1 case RTC_ALARMB: { - alarmreg = STM32WB_RTC_ALRMBR; + alarmreg = STM32_RTC_ALRMBR; ret = stm32wb_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1574,9 +1574,9 @@ static int stm32wb_rtc_wakeup_handler(int irq, void *context, void *arg) stm32wb_pwr_enablebkp(true); - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); stm32wb_pwr_enablebkp(false); @@ -1622,10 +1622,10 @@ static inline void rtc_set_wcksel(unsigned int wucksel) { uint32_t regval = 0; - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUCKSEL_MASK; regval |= wucksel; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); } #endif @@ -1661,7 +1661,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" #elif defined(CONFIG_STM32WB_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / - STM32WB_LSE_FREQUENCY; + STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1699,9 +1699,9 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, /* Clear WUTE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUTE; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1710,7 +1710,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1734,7 +1734,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, /* Get number of ticks. */ - ticks = millisecs * STM32WB_LSE_FREQUENCY / (16 * 1000); + ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); /* Wake-up is after WUT+1 ticks. */ @@ -1755,17 +1755,17 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, * selection. */ - putreg32(wutr_val, STM32WB_RTC_WUTR); + putreg32(wutr_val, STM32_RTC_WUTR); - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval |= RTC_CR_WUTIE | RTC_CR_WUTE; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Just in case resets the WUTF flag in RTC_ISR */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); rtc_wprlock(); @@ -1797,9 +1797,9 @@ int stm32wb_rtc_cancelperiodic(void) /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1808,7 +1808,7 @@ int stm32wb_rtc_cancelperiodic(void) ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1820,9 +1820,9 @@ int stm32wb_rtc_cancelperiodic(void) /* Clears RTC_WUTR register */ - regval = getreg32(STM32WB_RTC_WUTR); + regval = getreg32(STM32_RTC_WUTR); regval &= ~RTC_WUTR_MASK; - putreg32(regval, STM32WB_RTC_WUTR); + putreg32(regval, STM32_RTC_WUTR); rtc_wprlock(); diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index 6868b14ddcf15..b83811499da0f 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -38,9 +38,9 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_RTC_PRESCALER_SECOND 32767 /* Default prescaler +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler * to get a second base */ -#define STM32WB_RTC_PRESCALER_MIN 1 /* Maximum speed +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed * of 16384 Hz */ #if !defined(CONFIG_STM32WB_RTC_MAGIC) @@ -57,7 +57,7 @@ #define RTC_MAGIC CONFIG_STM32WB_RTC_MAGIC #define RTC_MAGIC_TIME_SET CONFIG_STM32WB_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32WB_RTC_BKPR(CONFIG_STM32WB_RTC_MAGIC_REG) +#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32WB_RTC_MAGIC_REG) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c index 009ead5cea0c2..16fc6ea85587c 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_NALARMS 2 +#define STM32_NALARMS 2 /**************************************************************************** * Private Types @@ -81,7 +81,7 @@ struct stm32wb_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32wb_cbinfo_s cbinfo[STM32WB_NALARMS]; + struct stm32wb_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index e657d7435de58..5289b289fa77f 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -379,13 +379,13 @@ static struct stm32wb_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32WB_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32WB_PCLK1_FREQUENCY, - .usartbase = STM32WB_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -441,13 +441,13 @@ static struct stm32wb_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32WB_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32WB_PCLK2_FREQUENCY, - .usartbase = STM32WB_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -478,7 +478,7 @@ static struct stm32wb_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ static struct stm32wb_serial_s * -const g_uart_devs[STM32WB_NLPUART + STM32WB_NUSART] = +const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -542,15 +542,15 @@ void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) * enable/usage table above) */ - cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -610,8 +610,8 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - cr3 = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -686,8 +686,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - brr = stm32wb_serial_getreg(priv, STM32WB_USART_BRR_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32wb_serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -713,8 +713,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); - stm32wb_serial_putreg(priv, STM32WB_USART_BRR_OFFSET, brr); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif @@ -750,7 +750,7 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32wb_serial_putreg(priv, STM32WB_USART_BRR_OFFSET, brr); + stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif @@ -772,7 +772,7 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) /* Set baud rate */ #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32WB_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { stm32wb_serial_setbaud_lpuart(priv); } @@ -784,7 +784,7 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) /* Configure parity mode */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -822,11 +822,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -834,11 +834,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) @@ -855,7 +855,7 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) } #endif - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -900,7 +900,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + while ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -1008,7 +1008,7 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32WB_NLPUART + STM32WB_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wb_serial_s *priv = g_uart_devs[n]; @@ -1045,15 +1045,15 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) default: return; #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER - case STM32WB_LPUART1_BASE: + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32WB_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif #ifdef CONFIG_STM32WB_USART1_SERIALDRIVER - case STM32WB_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32WB_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif } @@ -1139,7 +1139,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1150,26 +1150,26 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1177,9 +1177,9 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1231,7 +1231,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1242,7 +1242,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1256,9 +1256,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1315,9 +1315,9 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1478,7 +1478,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET); + priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1550,7 +1550,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32wb_serial_putreg(priv, STM32WB_USART_ICR_OFFSET, + stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1619,19 +1619,19 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1667,11 +1667,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1688,17 +1688,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1718,11 +1718,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1739,17 +1739,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1760,11 +1760,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1921,8 +1921,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -1934,8 +1934,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -1970,7 +1970,7 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32wb_serial_getreg(priv, STM32WB_USART_RDR_OFFSET); + rdr = stm32wb_serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2058,7 +2058,7 @@ static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) { struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2219,7 +2219,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2230,7 +2230,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2396,7 +2396,7 @@ static void stm32wb_serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32wb_serial_putreg(priv, STM32WB_USART_TDR_OFFSET, (uint32_t)ch); + stm32wb_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2482,7 +2482,7 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32wb_serial_txready(struct uart_dev_s *dev) { struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2525,11 +2525,11 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET); + priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0) { - stm32wb_serial_putreg(priv, STM32WB_USART_ICR_OFFSET, + stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2655,7 +2655,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32WB_NLPUART + STM32WB_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wb_serial_s *priv = g_uart_devs[n]; @@ -2723,7 +2723,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32WB_NLPUART + STM32WB_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -2787,7 +2787,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32WB_NLPUART + STM32WB_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 7666a72f780c0..67e1cf36b01e9 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -281,10 +281,10 @@ static struct stm32wb_spidev_s g_spi1dev = { .ops = &g_spi1ops, }, - .spibase = STM32WB_SPI1_BASE, - .spiclock = STM32WB_PCLK2_FREQUENCY, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, #ifdef CONFIG_STM32WB_SPI_INTERRUPTS - .spiirq = STM32WB_IRQ_SPI1, + .spiirq = STM32_IRQ_SPI1, #endif #ifdef CONFIG_STM32WB_SPI_DMA /* lines must be configured in board.h */ @@ -339,10 +339,10 @@ static struct stm32wb_spidev_s g_spi2dev = { .ops = &g_spi2ops, }, - .spibase = STM32WB_SPI2_BASE, - .spiclock = STM32WB_PCLK1_FREQUENCY, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32WB_SPI_INTERRUPTS - .spiirq = STM32WB_IRQ_SPI2, + .spiirq = STM32_IRQ_SPI2, #endif #ifdef CONFIG_STM32WB_SPI_DMA .rxch = DMACHAN_SPI2_RX, @@ -462,11 +462,11 @@ static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32WB_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -487,11 +487,11 @@ static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32WB_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -514,11 +514,11 @@ static inline void spi_writeword(struct stm32wb_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32WB_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -541,11 +541,11 @@ static inline void spi_writebyte(struct stm32wb_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32WB_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -748,7 +748,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, /* Configure the RX DMA */ - stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32WB_SPI_DR_OFFSET, + stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -799,7 +799,7 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, /* Setup the TX DMA */ - stm32wb_dmasetup(priv->txdma, priv->spibase + STM32WB_SPI_DR_OFFSET, + stm32wb_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -922,11 +922,11 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32WB_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32WB_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32WB_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -992,9 +992,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) actual = priv->spiclock >> 8; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1064,9 +1064,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster. @@ -1130,9 +1130,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so that subsequent re-configurations will be * faster. @@ -1184,9 +1184,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1252,7 +1252,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32WB_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1670,11 +1670,11 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1686,7 +1686,7 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32WB_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32WB_SPI_DMA /* Get DMA channels. NOTE: stm32wb_dmachannel() will always assign the DMA @@ -1701,13 +1701,13 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) priv->txdma = stm32wb_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ diff --git a/arch/arm/src/stm32wb/stm32wb_start.c b/arch/arm/src/stm32wb/stm32wb_start.c index 7ecd128a5c9d0..660cd4db3a6d6 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.c +++ b/arch/arm/src/stm32wb/stm32wb_start.c @@ -64,12 +64,12 @@ #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) #ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32WB_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) # define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) #endif #ifdef CONFIG_STM32WB_SRAM2B_HEAP -# define SRAM2B_START STM32WB_SRAM2B_BASE +# define SRAM2B_START STM32_SRAM2B_BASE # define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) #endif diff --git a/arch/arm/src/stm32wb/stm32wb_tickless.c b/arch/arm/src/stm32wb/stm32wb_tickless.c index ef5e64b5f60da..acefc6af5ab0b 100644 --- a/arch/arm/src/stm32wb/stm32wb_tickless.c +++ b/arch/arm/src/stm32wb/stm32wb_tickless.c @@ -89,7 +89,7 @@ # define HAVE_32BIT_TICKLESS 1 # endif #else -# error "STM32WB_TICKLESS_TIMER must be defined for tickless configuration" +# error "STM32_TICKLESS_TIMER must be defined for tickless configuration" #endif /**************************************************************************** @@ -166,7 +166,7 @@ static inline void stm32wb_modifyreg16(uint8_t offset, uint16_t clearbits, static inline void stm32wb_tickless_enableint(int channel) { - stm32wb_modifyreg16(STM32WB_TIM_DIER_OFFSET, 0, 1 << channel); + stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); } /**************************************************************************** @@ -175,7 +175,7 @@ static inline void stm32wb_tickless_enableint(int channel) static inline void stm32wb_tickless_disableint(int channel) { - stm32wb_modifyreg16(STM32WB_TIM_DIER_OFFSET, 1 << channel, 0); + stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); } /**************************************************************************** @@ -184,7 +184,7 @@ static inline void stm32wb_tickless_disableint(int channel) static inline void stm32wb_tickless_ackint(int channel) { - stm32wb_putreg16(STM32WB_TIM_SR_OFFSET, ~(1 << channel)); + stm32wb_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); } /**************************************************************************** @@ -193,7 +193,7 @@ static inline void stm32wb_tickless_ackint(int channel) static inline uint16_t stm32wb_tickless_getint(void) { - return stm32wb_getreg16(STM32WB_TIM_SR_OFFSET); + return stm32wb_getreg16(STM32_TIM_SR_OFFSET); } /**************************************************************************** @@ -205,7 +205,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WB_TIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; /* Further we use range as 0..3; if channel=0 it will also overflow here */ @@ -216,7 +216,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(STM32WB_TIM_CCER_OFFSET); + ccer_val = stm32wb_getreg16(STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Frozen mode because we don't want to change the GPIO, preload register @@ -231,14 +231,14 @@ static int stm32wb_tickless_setchannel(uint8_t channel) if (channel > 1) { - ccmr_offset = STM32WB_TIM_CCMR2_OFFSET; + ccmr_offset = STM32_TIM_CCMR2_OFFSET; } ccmr_orig = stm32wb_getreg16(ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; stm32wb_putreg16(ccmr_offset, ccmr_orig); - stm32wb_putreg16(STM32WB_TIM_CCER_OFFSET, ccer_val); + stm32wb_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); return OK; } @@ -294,7 +294,7 @@ static void stm32wb_timing_handler(void) { g_tickless.overflow++; - STM32WB_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); } /**************************************************************************** @@ -364,25 +364,25 @@ void up_timer_initialize(void) { #ifdef CONFIG_STM32WB_TIM1 case 1: - g_tickless.base = STM32WB_TIM1_BASE; + g_tickless.base = STM32_TIM1_BASE; break; #endif #ifdef CONFIG_STM32WB_TIM2 case 2: - g_tickless.base = STM32WB_TIM2_BASE; + g_tickless.base = STM32_TIM2_BASE; break; #endif #ifdef CONFIG_STM32WB_TIM16 case 16: - g_tickless.base = STM32WB_TIM16_BASE; + g_tickless.base = STM32_TIM16_BASE; break; #endif #ifdef CONFIG_STM32WB_TIM17 case 17: - g_tickless.base = STM32WB_TIM17_BASE; + g_tickless.base = STM32_TIM17_BASE; break; #endif @@ -409,15 +409,15 @@ void up_timer_initialize(void) DEBUGPANIC(); } - STM32WB_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); + STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); /* Set up to receive the callback when the counter overflow occurs */ - STM32WB_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); + STM32_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); /* Initialize interval to zero */ - STM32WB_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); /* Setup compare channel for the interval timing */ @@ -426,12 +426,12 @@ void up_timer_initialize(void) /* Set timer period */ #ifdef HAVE_32BIT_TICKLESS - STM32WB_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); + STM32_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP g_oneshot_maxticks = UINT32_MAX; #endif #else - STM32WB_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); + STM32_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP g_oneshot_maxticks = UINT16_MAX; #endif @@ -439,12 +439,12 @@ void up_timer_initialize(void) /* Initialize the counter */ - STM32WB_TIM_SETMODE(g_tickless.tch, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(g_tickless.tch, STM32_TIM_MODE_UP); /* Start the timer */ - STM32WB_TIM_ACKINT(g_tickless.tch, ~0); - STM32WB_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(g_tickless.tch, ~0); + STM32_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); } /**************************************************************************** @@ -501,9 +501,9 @@ int up_timer_gettime(struct timespec *ts) flags = enter_critical_section(); overflow = g_tickless.overflow; - counter = STM32WB_TIM_GETCOUNTER(g_tickless.tch); - pending = STM32WB_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); - verify = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + counter = STM32_TIM_GETCOUNTER(g_tickless.tch); + pending = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); + verify = STM32_TIM_GETCOUNTER(g_tickless.tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -511,7 +511,7 @@ int up_timer_gettime(struct timespec *ts) if (pending) { - STM32WB_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -576,7 +576,7 @@ int up_timer_gettime(struct timespec *ts) int up_timer_gettick(clock_t *ticks) { - *ticks = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + *ticks = STM32_TIM_GETCOUNTER(g_tickless.tch); return OK; } @@ -681,7 +681,7 @@ int up_timer_cancel(struct timespec *ts) stm32wb_tickless_disableint(g_tickless.channel); - count = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + count = STM32_TIM_GETCOUNTER(g_tickless.tch); period = g_tickless.period; g_tickless.pending = false; @@ -807,7 +807,7 @@ int up_timer_start(const struct timespec *ts) */ period = (usec * (uint64_t)g_tickless.frequency) / USEC_PER_SEC; - count = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + count = STM32_TIM_GETCOUNTER(g_tickless.tch); tmrinfo("usec=%llu period=%08llx\n", usec, period); @@ -822,7 +822,7 @@ int up_timer_start(const struct timespec *ts) g_tickless.period = (uint16_t)(period + count); #endif - STM32WB_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, g_tickless.period); /* Enable interrupts. We should get the callback when the interrupt diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c index 9bc6340317bf0..d784f103c2aa9 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ b/arch/arm/src/stm32wb/stm32wb_tim.c @@ -225,16 +225,16 @@ static const struct stm32wb_tim_ops_s stm32wb_tim_ops = struct stm32wb_tim_priv_s stm32wb_tim1_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32WB_TIM2 struct stm32wb_tim_priv_s stm32wb_tim2_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -242,8 +242,8 @@ struct stm32wb_tim_priv_s stm32wb_tim2_priv = struct stm32wb_tim_priv_s stm32wb_tim16_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -251,8 +251,8 @@ struct stm32wb_tim_priv_s stm32wb_tim16_priv = struct stm32wb_tim_priv_s stm32wb_tim17_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -340,9 +340,9 @@ static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_EGR_OFFSET); + uint16_t val = stm32wb_getreg16(dev, STM32_TIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wb_putreg16(dev, STM32WB_TIM_EGR_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_EGR_OFFSET, val); } /**************************************************************************** @@ -351,11 +351,11 @@ static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET); + uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** @@ -364,9 +364,9 @@ static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET); + uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** @@ -380,7 +380,7 @@ static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) { - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32WB_TIM_MODE_DISABLED; + ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32wb_tim_disable(dev); } @@ -393,7 +393,7 @@ static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_gpioconfig(uint32_t cfg, enum stm32wb_tim_channel_e mode) { - if (mode & STM32WB_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32wb_configgpio(cfg); } @@ -413,42 +413,42 @@ static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev) struct stm32wb_tim_priv_s *priv = (struct stm32wb_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CR2_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_SMCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DIER_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CR2_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_SMCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_SR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCMR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCMR2_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCMR1_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CCER_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CNT_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_PSC_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_ARR_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CNT_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CCR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR2_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR3_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR4_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_CCR1_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCR2_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCR3_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCR4_OFFSET) ); - if (priv->base == STM32WB_TIM1_BASE) + if (priv->base == STM32_TIM1_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_RCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_BDTR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DMAR_OFFSET)); + stm32wb_getreg16(dev, STM32_TIM_RCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_BDTR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DMAR_OFFSET)); + stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } } @@ -466,17 +466,17 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, /* The modes DOWN and UPDOWN are not supported on TIM16 and TIM17. */ #if defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) - if ((mode == STM32WB_TIM_MODE_DOWN || mode == STM32WB_TIM_MODE_UPDOWN)) + if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) { #if defined(CONFIG_STM32WB_TIM16) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM16_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM16_BASE) { return -EINVAL; } #endif #if defined(CONFIG_STM32WB_TIM17) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM17_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM17_BASE) { return -EINVAL; } @@ -486,22 +486,22 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32WB_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32WB_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32WB_TIM_MODE_UP: + case STM32_TIM_MODE_UP: val = GTIM_CR1_CEN | GTIM_CR1_ARPE; break; #if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) - case STM32WB_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_DIR; break; - case STM32WB_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_CMS_CNTR1; /* Our default: @@ -511,7 +511,7 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, break; #endif - case STM32WB_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | GTIM_CR1_OPM; break; @@ -520,14 +520,14 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, } stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); #ifdef CONFIG_STM32WB_TIM1 /* Advanced registers require Main Output Enable */ - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM1_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM1_BASE) { - stm32wb_modifyreg16(dev, STM32WB_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); + stm32wb_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); } #endif @@ -564,25 +564,25 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -647,8 +647,8 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) /* Set the reload and prescaler values */ - stm32wb_putreg16(dev, STM32WB_TIM_PSC_OFFSET, prescaler - 1); - stm32wb_putreg16(dev, STM32WB_TIM_ARR_OFFSET, reload); + stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); + stm32wb_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); return (timclk / reload); } @@ -681,25 +681,25 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -730,7 +730,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32wb_putreg16(dev, STM32WB_TIM_PSC_OFFSET, prescaler); + stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); return prescaler; } @@ -754,25 +754,25 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -782,7 +782,7 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wb_getreg16(dev, STM32WB_TIM_PSC_OFFSET) + 1); + clock = freqin / (stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); return clock; } @@ -794,7 +794,7 @@ static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wb_putreg32(dev, STM32WB_TIM_ARR_OFFSET, period); + stm32wb_putreg32(dev, STM32_TIM_ARR_OFFSET, period); } /**************************************************************************** @@ -804,7 +804,7 @@ static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wb_getreg32 (dev, STM32WB_TIM_ARR_OFFSET); + return stm32wb_getreg32 (dev, STM32_TIM_ARR_OFFSET); } /**************************************************************************** @@ -814,12 +814,12 @@ static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wb_getreg32(dev, STM32WB_TIM_CNT_OFFSET); + uint32_t counter = stm32wb_getreg32(dev, STM32_TIM_CNT_OFFSET); /* TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM2_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return counter; } @@ -837,7 +837,7 @@ static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) /* Only TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM2_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return 32; } @@ -859,7 +859,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WB_TIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -872,17 +872,17 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(dev, STM32WB_TIM_CCER_OFFSET); + ccer_val = stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Decode configuration */ - switch (mode & STM32WB_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32WB_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32WB_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = GTIM_CCMR_OCXM_PWM1(channel) | GTIM_CCMR_OCXPE(channel); ccer_val |= GTIM_CCER_CCXE(channel); break; @@ -893,28 +893,28 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32WB_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CCXP(channel); } if (channel > 1) { - ccmr_offset = STM32WB_TIM_CCMR2_OFFSET; + ccmr_offset = STM32_TIM_CCMR2_OFFSET; } ccmr_orig = stm32wb_getreg16(dev, ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; stm32wb_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wb_putreg16(dev, STM32WB_TIM_CCER_OFFSET, ccer_val); + stm32wb_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -947,7 +947,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -980,7 +980,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -995,7 +995,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1029,19 +1029,19 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - stm32wb_putreg32(dev, STM32WB_TIM_CCR1_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); break; case 2: - stm32wb_putreg32(dev, STM32WB_TIM_CCR2_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); break; case 3: - stm32wb_putreg32(dev, STM32WB_TIM_CCR3_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); break; case 4: - stm32wb_putreg32(dev, STM32WB_TIM_CCR4_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); break; default: @@ -1063,16 +1063,16 @@ static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR1_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR1_OFFSET); case 2: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR2_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR2_OFFSET); case 3: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR3_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR3_OFFSET); case 4: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR4_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR4_OFFSET); } return -EINVAL; @@ -1093,26 +1093,26 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: - vectorno = STM32WB_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: - vectorno = STM32WB_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: - vectorno = STM32WB_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: - vectorno = STM32WB_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1144,7 +1144,7 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32WB_TIM_DIER_OFFSET, 0, source); + stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); } /**************************************************************************** @@ -1154,7 +1154,7 @@ static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32WB_TIM_DIER_OFFSET, source, 0); + stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); } /**************************************************************************** @@ -1163,7 +1163,7 @@ static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) { - stm32wb_putreg16(dev, STM32WB_TIM_SR_OFFSET, ~source); + stm32wb_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); } /**************************************************************************** @@ -1172,7 +1172,7 @@ static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) { - uint16_t regval = stm32wb_getreg16(dev, STM32WB_TIM_SR_OFFSET); + uint16_t regval = stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET); return (regval & source) ? 1 : 0; } @@ -1195,28 +1195,28 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) #ifdef CONFIG_STM32WB_TIM1 case 1: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim1_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32WB_TIM2 case 2: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim2_priv; - modifyreg32(STM32WB_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32WB_TIM16 case 16: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim16_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32WB_TIM17 case 17: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim17_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1226,7 +1226,7 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32WB_TIM_MODE_UNUSED) + if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1252,26 +1252,26 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: - modifyreg32(STM32WB_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1281,7 +1281,7 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32WB_TIM_MODE_UNUSED; + ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_tim.h b/arch/arm/src/stm32wb/stm32wb_tim.h index a1257fbee512b..ead07f601957d 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/stm32wb_tim.h @@ -64,25 +64,25 @@ /* Helpers ******************************************************************/ -#define STM32WB_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32WB_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32WB_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32WB_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32WB_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32WB_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32WB_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32WB_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32WB_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32WB_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32WB_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32WB_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32WB_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32WB_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32WB_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32WB_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32WB_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32WB_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32WB_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) /**************************************************************************** * Public Types @@ -110,34 +110,34 @@ struct stm32wb_tim_dev_s enum stm32wb_tim_mode_e { - STM32WB_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32WB_TIM_MODE_MASK = 0x0310, - STM32WB_TIM_MODE_DISABLED = 0x0000, - STM32WB_TIM_MODE_UP = 0x0100, - STM32WB_TIM_MODE_DOWN = 0x0110, - STM32WB_TIM_MODE_UPDOWN = 0x0200, - STM32WB_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32WB_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32WB_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32WB_TIM_MODE_CK_EXT = 0x0800, - STM32WB_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32WB_TIM_MODE_CK_CHINVALID = 0x0000, - STM32WB_TIM_MODE_CK_CH1 = 0x0001, - STM32WB_TIM_MODE_CK_CH2 = 0x0002, - STM32WB_TIM_MODE_CK_CH3 = 0x0003, - STM32WB_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -147,32 +147,32 @@ enum stm32wb_tim_mode_e enum stm32wb_tim_channel_e { - STM32WB_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32WB_TIM_CH_POLARITY_POS = 0x00, - STM32WB_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32WB_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32WB_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active * high when counter < compare */ #if 0 - STM32WB_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32WB_TIM_CH_INCAPTURE = 0x10, - STM32WB_TIM_CH_INPWM = 0x20 - STM32WB_TIM_CH_DRIVE_OC /* Open collector mode */ + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC /* Open collector mode */ #endif }; diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c index ef7af07926eb1..ced3f62d5f9c9 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c @@ -44,10 +44,10 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_TIM1_RES 16 -#define STM32WB_TIM2_RES 32 -#define STM32WB_TIM16_RES 16 -#define STM32WB_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -107,7 +107,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -115,7 +115,7 @@ static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -123,7 +123,7 @@ static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -131,7 +131,7 @@ static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -156,13 +156,13 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) struct stm32wb_lowerhalf_s *lower = (struct stm32wb_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32WB_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); + STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32WB_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -194,12 +194,12 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32WB_TIM_SETMODE(priv->tim, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32WB_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); - STM32WB_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } priv->started = true; @@ -232,9 +232,9 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32WB_TIM_SETMODE(priv->tim, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -288,8 +288,8 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32WB_TIM_GETCLOCK(priv->tim); - period = STM32WB_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -305,7 +305,7 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = clock / 1000000; - status->timeleft = (timeout - STM32WB_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -341,13 +341,13 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32WB_TIM_SETCLOCK(priv->tim, freq); - STM32WB_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32WB_TIM_SETCLOCK(priv->tim, 1000000); - STM32WB_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -386,13 +386,13 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32WB_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); - STM32WB_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } else { - STM32WB_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index c9dc2cc473866..a01219c737b76 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -59,9 +59,9 @@ #undef CONFIG_STM32WB_SYSTICK_HCLKd8 #ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -135,7 +135,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32WB_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); /* Enable SysTick interrupts */ @@ -144,5 +144,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32WB_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32wb/stm32wb_uid.c b/arch/arm/src/stm32wb/stm32wb_uid.c index 22e781f8c6f77..17a3808d3633d 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.c +++ b/arch/arm/src/stm32wb/stm32wb_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32wb_memorymap.h" #include "stm32wb_uid.h" -#ifdef STM32WB_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32wb_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32WB_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32WB_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32wl5/chip.h b/arch/arm/src/stm32wl5/chip.h index b9f0208954f43..cfb6d0903edd9 100644 --- a/arch/arm/src/stm32wl5/chip.h +++ b/arch/arm/src/stm32wl5/chip.h @@ -49,7 +49,7 @@ * arch/stm32wl5/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WL5_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32WL5 */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h index 3a3b11d974c51..85a6160b91767 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h @@ -34,48 +34,48 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_NEXTI1 31 -#define STM32WL5_EXTI1_MASK 0xffffffff -#define STM32WL5_NEXTI2 9 -#define STM32WL5_EXTI2_MASK 0x000001ff +#define STM32_NEXTI1 31 +#define STM32_EXTI1_MASK 0xffffffff +#define STM32_NEXTI2 9 +#define STM32_EXTI2_MASK 0x000001ff /* Register Offsets *********************************************************/ -#define STM32WL5_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */ -#define STM32WL5_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */ -#define STM32WL5_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */ -#define STM32WL5_EXTI_PR1_OFFSET 0x000c /* Pending 1 */ -#define STM32WL5_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */ -#define STM32WL5_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */ -#define STM32WL5_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */ -#define STM32WL5_EXTI_PR2_OFFSET 0x002c /* Pending 2 */ -#define STM32WL5_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */ -#define STM32WL5_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */ -#define STM32WL5_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */ -#define STM32WL5_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */ -#define STM32WL5_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */ -#define STM32WL5_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */ -#define STM32WL5_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */ -#define STM32WL5_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */ +#define STM32_EXTI_PR1_OFFSET 0x000c /* Pending 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */ +#define STM32_EXTI_PR2_OFFSET 0x002c /* Pending 2 */ +#define STM32_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */ +#define STM32_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */ +#define STM32_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */ +#define STM32_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */ +#define STM32_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */ +#define STM32_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */ +#define STM32_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */ +#define STM32_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */ /* Register Addresses *******************************************************/ -#define STM32WL5_EXTI_RTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR1_OFFSET) -#define STM32WL5_EXTI_FTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR1_OFFSET) -#define STM32WL5_EXTI_SWIER1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER1_OFFSET) -#define STM32WL5_EXTI_PR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR1_OFFSET) -#define STM32WL5_EXTI_RTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR2_OFFSET) -#define STM32WL5_EXTI_FTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR2_OFFSET) -#define STM32WL5_EXTI_SWIER2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER2_OFFSET) -#define STM32WL5_EXTI_PR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR2_OFFSET) -#define STM32WL5_EXTI_C1IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR1_OFFSET) -#define STM32WL5_EXTI_C1EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR1_OFFSET) -#define STM32WL5_EXTI_C1IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR2_OFFSET) -#define STM32WL5_EXTI_C1EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR2_OFFSET) -#define STM32WL5_EXTI_C2IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR1_OFFSET) -#define STM32WL5_EXTI_C2EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR1_OFFSET) -#define STM32WL5_EXTI_C2IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR2_OFFSET) -#define STM32WL5_EXTI_C2EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE+STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE+STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE+STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_PR1 (STM32_EXTI_BASE+STM32_EXTI_PR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE+STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE+STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE+STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_PR2 (STM32_EXTI_BASE+STM32_EXTI_PR2_OFFSET) +#define STM32_EXTI_C1IMR1 (STM32_EXTI_BASE+STM32_EXTI_C1IMR1_OFFSET) +#define STM32_EXTI_C1EMR1 (STM32_EXTI_BASE+STM32_EXTI_C1EMR1_OFFSET) +#define STM32_EXTI_C1IMR2 (STM32_EXTI_BASE+STM32_EXTI_C1IMR2_OFFSET) +#define STM32_EXTI_C1EMR2 (STM32_EXTI_BASE+STM32_EXTI_C1EMR2_OFFSET) +#define STM32_EXTI_C2IMR1 (STM32_EXTI_BASE+STM32_EXTI_C2IMR1_OFFSET) +#define STM32_EXTI_C2EMR1 (STM32_EXTI_BASE+STM32_EXTI_C2EMR1_OFFSET) +#define STM32_EXTI_C2IMR2 (STM32_EXTI_BASE+STM32_EXTI_C2IMR2_OFFSET) +#define STM32_EXTI_C2EMR2 (STM32_EXTI_BASE+STM32_EXTI_C2EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h index 0f14d1b02ae4f..e7d57753c2bdd 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h @@ -86,71 +86,71 @@ /* Define the valid configuration */ #if defined(CONFIG_STM32WL5_FLASH_CONFIG_8) /* 64 kB */ -# define STM32WL5_FLASH_NPAGES 32 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32WL5_FLASH_CONFIG_B) /* 128 kB */ -# define STM32WL5_FLASH_NPAGES 64 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32WL5_FLASH_CONFIG_C) /* 256 kB */ -# define STM32WL5_FLASH_NPAGES 128 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32WL5_FLASH_CONFIG_E) /* 512 kB */ -# define STM32WL5_FLASH_NPAGES 256 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32WL5_FLASH_CONFIG_G) /* 1 MB */ -# define STM32WL5_FLASH_NPAGES 512 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 2048 #else # error "unknown flash configuration!" #endif -#define STM32WL5_FLASH_SIZE (STM32WL5_FLASH_NPAGES * STM32WL5_FLASH_PAGESIZE) +#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) /* Register Offsets *********************************************************/ -#define STM32WL5_FLASH_ACR_OFFSET 0x0000 -#define STM32WL5_FLASH_ACR2_OFFSET 0x0004 -#define STM32WL5_FLASH_KEYR_OFFSET 0x0008 -#define STM32WL5_FLASH_OPTKEYR_OFFSET 0x000c -#define STM32WL5_FLASH_SR_OFFSET 0x0010 -#define STM32WL5_FLASH_CR_OFFSET 0x0014 -#define STM32WL5_FLASH_ECCR_OFFSET 0x0018 -#define STM32WL5_FLASH_OPTR_OFFSET 0x0020 -#define STM32WL5_FLASH_PCROP1ASR_OFFSET 0x0024 -#define STM32WL5_FLASH_PCROP1AER_OFFSET 0x0028 -#define STM32WL5_FLASH_WRP1AR_OFFSET 0x002c -#define STM32WL5_FLASH_WRP1BR_OFFSET 0x0030 -#define STM32WL5_FLASH_PCROP1BSR_OFFSET 0x0034 -#define STM32WL5_FLASH_PCROP1BER_OFFSET 0x0038 -#define STM32WL5_FLASH_IPCCBR_OFFSET 0x003c -#define STM32WL5_FLASH_C2ACR_OFFSET 0x005c -#define STM32WL5_FLASH_C2SR_OFFSET 0x0060 -#define STM32WL5_FLASH_C2CR_OFFSET 0x0064 -#define STM32WL5_FLASH_SFR_OFFSET 0x0080 -#define STM32WL5_FLASH_SRRVR_OFFSET 0x0084 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_ACR2_OFFSET 0x0004 +#define STM32_FLASH_KEYR_OFFSET 0x0008 +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c +#define STM32_FLASH_SR_OFFSET 0x0010 +#define STM32_FLASH_CR_OFFSET 0x0014 +#define STM32_FLASH_ECCR_OFFSET 0x0018 +#define STM32_FLASH_OPTR_OFFSET 0x0020 +#define STM32_FLASH_PCROP1ASR_OFFSET 0x0024 +#define STM32_FLASH_PCROP1AER_OFFSET 0x0028 +#define STM32_FLASH_WRP1AR_OFFSET 0x002c +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 +#define STM32_FLASH_PCROP1BSR_OFFSET 0x0034 +#define STM32_FLASH_PCROP1BER_OFFSET 0x0038 +#define STM32_FLASH_IPCCBR_OFFSET 0x003c +#define STM32_FLASH_C2ACR_OFFSET 0x005c +#define STM32_FLASH_C2SR_OFFSET 0x0060 +#define STM32_FLASH_C2CR_OFFSET 0x0064 +#define STM32_FLASH_SFR_OFFSET 0x0080 +#define STM32_FLASH_SRRVR_OFFSET 0x0084 /* Register Addresses *******************************************************/ -#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) -#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) -#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) -#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) -#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) -#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) -#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) -#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) -#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) -#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) -#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) -#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) -#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) -#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) -#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) -#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) -#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) -#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) -#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) -#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_ACR2 (STM32_FLASHIF_BASE+STM32_FLASH_ACR2_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1ASR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ASR_OFFSET) +#define STM32_FLASH_PCROP1AER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1AER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_PCROP1BSR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BSR_OFFSET) +#define STM32_FLASH_PCROP1BER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BER_OFFSET) +#define STM32_FLASH_IPCCBR (STM32_FLASHIF_BASE+STM32_FLASH_IPCCBR_OFFSET) +#define STM32_FLASH_C2ACR (STM32_FLASHIF_BASE+STM32_FLASH_C2ACR_OFFSET) +#define STM32_FLASH_C2SR (STM32_FLASHIF_BASE+STM32_FLASH_C2SR_OFFSET) +#define STM32_FLASH_C2CR (STM32_FLASHIF_BASE+STM32_FLASH_C2CR_OFFSET) +#define STM32_FLASH_SFR (STM32_FLASHIF_BASE+STM32_FLASH_SFR_OFFSET) +#define STM32_FLASH_SRRVR (STM32_FLASHIF_BASE+STM32_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h index 9f76cb4efa0fc..3bd6a33c9fd0a 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h @@ -36,71 +36,71 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32WL5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32WL5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32WL5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32WL5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32WL5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32WL5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32WL5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32WL5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32WL5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32WL5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32WL5_GPIOA_MODER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOA_OTYPER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOA_OSPEED (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOA_PUPDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOA_IDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOA_ODR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOA_BSRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOA_LCKR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOA_AFRL (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOA_AFRH (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOA_BRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOA_ASCR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ASCR_OFFSET) - -#define STM32WL5_GPIOB_MODER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOB_OTYPER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOB_OSPEED (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOB_PUPDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOB_IDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOB_ODR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOB_BSRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOB_LCKR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOB_AFRL (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOB_AFRH (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOB_BRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOB_ASCR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ASCR_OFFSET) - -#define STM32WL5_GPIOC_MODER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOC_OTYPER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOC_OSPEED (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOC_PUPDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOC_IDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOC_ODR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOC_BSRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOC_LCKR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOC_AFRL (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOC_AFRH (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOC_BRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOC_ASCR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ASCR_OFFSET) - -#define STM32WL5_GPIOH_MODER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOH_OTYPER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOH_OSPEED (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOH_PUPDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOH_IDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOH_ODR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOH_BSRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOH_LCKR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOH_AFRL (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOH_AFRH (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOH_BRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOH_ASCR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ASCR_OFFSET) +#define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET) + +#define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET) + +#define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET) + +#define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h index 56632c5a9360a..35acf09fc6e1d 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h @@ -34,48 +34,48 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_IPCC_CPU1_OFFSET 0x00 -#define STM32WL5_IPCC_CPU2_OFFSET 0x10 +#define STM32_IPCC_CPU1_OFFSET 0x00 +#define STM32_IPCC_CPU2_OFFSET 0x10 /* Register Offsets *********************************************************/ -#define STM32WL5_IPCC_CR_OFFSET 0x00 /* IPCC control register */ -#define STM32WL5_IPCC_MR_OFFSET 0x04 /* IPCC mask register */ -#define STM32WL5_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */ -#define STM32WL5_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */ +#define STM32_IPCC_CR_OFFSET 0x00 /* IPCC control register */ +#define STM32_IPCC_MR_OFFSET 0x04 /* IPCC mask register */ +#define STM32_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */ +#define STM32_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */ /* Register Addresses *******************************************************/ -#define STM32WL5_IPCC_C1CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1TOC2SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C2CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2TOC1SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C1CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1TOC2SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C2CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2TOC1SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU2_OFFSET) /* Register Bitfield Definitions ********************************************/ -#define STM32WL5_IPCC_TX_SHIFT (16) /* TX shift for all registers */ +#define STM32_IPCC_TX_SHIFT (16) /* TX shift for all registers */ /* IPCC control register */ -#define STM32WL5_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */ -#define STM32WL5_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */ +#define STM32_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */ +#define STM32_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */ /* IPCC mask register */ -#define STM32WL5_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */ -#define STM32WL5_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */ +#define STM32_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */ +#define STM32_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */ /* IPCC status set clear register */ -#define STM32WL5_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */ -#define STM32WL5_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */ +#define STM32_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */ +#define STM32_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */ /* IPCC processor to processor status register */ -#define STM32WL5_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */ +#define STM32_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */ #endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_IPCC_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h index 89df326775bf3..a51e36241420b 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h @@ -29,40 +29,40 @@ /* STM32WL5XXX Address Blocks ***********************************************/ -#define STM32WL5_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */ -#define STM32WL5_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */ -#define STM32WL5_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */ - /* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */ -#define STM32WL5_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */ + /* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */ -#define STM32WL5_REGION_MASK 0xf0000000 -#define STM32WL5_IS_SRAM(a) ((((uint32_t)(a)) & STM32WL5_REGION_MASK) == STM32WL5_SRAM_BASE) +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) /* Code Base Addresses ******************************************************/ -#define STM32WL5_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */ - /* 0x0004 0000-0x07ff ffff: Reserved */ -#define STM32WL5_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */ - /* 0x0804 0000-0x0fff ffff: Reserved */ -#define STM32WL5_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ - /* 0x1000 0000-0x1ffe 6fff: Reserved */ -#define STM32WL5_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */ -#define STM32WL5_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */ -#define STM32WL5_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */ -#define STM32WL5_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */ - /* 0x1fff 8000-0x1fff ffff: reserved */ -#define STM32WL5_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */ +#define STM32_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */ + /* 0x0004 0000-0x07ff ffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */ + /* 0x0804 0000-0x0fff ffff: Reserved */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ + /* 0x1000 0000-0x1ffe 6fff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */ +#define STM32_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */ +#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */ + /* 0x1fff 8000-0x1fff ffff: reserved */ +#define STM32_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */ /* System Memory Addresses **************************************************/ -#define STM32WL5_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. * 0: UFBGA73 * 2: WLCSP59 * 10: UFQFPN48 */ -#define STM32WL5_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32WL5_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. @@ -70,92 +70,92 @@ /* SRAM Base Addresses ******************************************************/ -#define STM32WL5_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32WL5_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */ - /* 0x4000 B400-0x4000 ffff: Reserved */ -#define STM32WL5_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */ - /* 0x4001 4c00-0x4001 ffff: Reserved */ -#define STM32WL5_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */ - /* 0x4260 0000-0x47ff ffff: Reserved */ -#define STM32WL5_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */ - /* 0x4800 2000-0x57ff ffff: Reserved */ -#define STM32WL5_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */ - /* 0x5800 40c0-0x5800 ffff: Reserved */ +#define STM32_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */ + /* 0x4000 B400-0x4000 ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */ + /* 0x4001 4c00-0x4001 ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */ + /* 0x4260 0000-0x47ff ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */ + /* 0x4800 2000-0x57ff ffff: Reserved */ +#define STM32_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */ + /* 0x5800 40c0-0x5800 ffff: Reserved */ /* Radio Base Addresses *****************************************************/ -#define STM32WL5_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */ - /* 0x5801 0400-0x5801 ffff: Reserved */ +#define STM32_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */ + /* 0x5801 0400-0x5801 ffff: Reserved */ /* in datasheet order */ /* APB1 Base Addresses ******************************************************/ -#define STM32WL5_TAMP_BASE 0x4000B000 -#define STM32WL5_LPTIM3_BASE 0x40009800 -#define STM32WL5_LPTIM2_BASE 0x40009400 -#define STM32WL5_LPUART1_BASE 0x40008000 -#define STM32WL5_LPTIM1_BASE 0x40007C00 -#define STM32WL5_DAC_BASE 0x40007400 -#define STM32WL5_I2C3_BASE 0x40005C00 -#define STM32WL5_I2C2_BASE 0x40005800 -#define STM32WL5_I2C1_BASE 0x40005400 -#define STM32WL5_USART2_BASE 0x40004400 -#define STM32WL5_SPI2S2_BASE 0x40003800 -#define STM32WL5_IWDG_BASE 0x40003000 -#define STM32WL5_WWDG_BASE 0x40002C00 -#define STM32WL5_RTC_BASE 0x40002800 -#define STM32WL5_TIM2_BASE 0x40000000 +#define STM32_TAMP_BASE 0x4000B000 +#define STM32_LPTIM3_BASE 0x40009800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007C00 +#define STM32_DAC_BASE 0x40007400 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI2S2_BASE 0x40003800 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002C00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32WL5_TIM17_BASE 0x40014800 -#define STM32WL5_TIM16_BASE 0x40014400 -#define STM32WL5_USART1_BASE 0x40013800 -#define STM32WL5_SPI1_BASE 0x40013000 -#define STM32WL5_TIM1_BASE 0x40012C00 -#define STM32WL5_ADC_BASE 0x40012400 -#define STM32WL5_COMP_BASE 0x40010200 -#define STM32WL5_SYSCFG2_BASE 0x40010100 -#define STM32WL5_VREFBUF_BASE 0x40010030 -#define STM32WL5_SYSCFG_BASE 0x40010000 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_USART1_BASE 0x40013800 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012C00 +#define STM32_ADC_BASE 0x40012400 +#define STM32_COMP_BASE 0x40010200 +#define STM32_SYSCFG2_BASE 0x40010100 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32WL5_CRC_BASE 0x40023000 -#define STM32WL5_DMAMUX1_BASE 0x40200800 -#define STM32WL5_DMA2_BASE 0x40200400 -#define STM32WL5_DMA1_BASE 0x40020000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_DMAMUX1_BASE 0x40200800 +#define STM32_DMA2_BASE 0x40200400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32WL5_GPIOH_BASE 0x48001C00 -#define STM32WL5_GPIOC_BASE 0x48000800 -#define STM32WL5_GPIOB_BASE 0x48000400 -#define STM32WL5_GPIOA_BASE 0x48000000 +#define STM32_GPIOH_BASE 0x48001C00 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOA_BASE 0x48000000 /* AHB3 Base Addresses ******************************************************/ -#define STM32WL5_GTZC_TZIC_BASE 0x58004800 -#define STM32WL5_GTZC_TZSC_BASE 0x58004400 -#define STM32WL5_FLASHIF_BASE 0x58004000 -#define STM32WL5_PKA2_BASE 0x58003400 -#define STM32WL5_PKARAM_BASE 0x58002400 -#define STM32WL5_PKA_BASE 0x58002000 -#define STM32WL5_AES_BASE 0x58001800 -#define STM32WL5_HSEM_BASE 0x58001400 -#define STM32WL5_RNG_BASE 0x58001000 -#define STM32WL5_IPCC_BASE 0x58000C00 -#define STM32WL5_EXTI_BASE 0x58000800 -#define STM32WL5_PWR_BASE 0x58000400 -#define STM32WL5_RCC_BASE 0x58000000 +#define STM32_GTZC_TZIC_BASE 0x58004800 +#define STM32_GTZC_TZSC_BASE 0x58004400 +#define STM32_FLASHIF_BASE 0x58004000 +#define STM32_PKA2_BASE 0x58003400 +#define STM32_PKARAM_BASE 0x58002400 +#define STM32_PKA_BASE 0x58002000 +#define STM32_AES_BASE 0x58001800 +#define STM32_HSEM_BASE 0x58001400 +#define STM32_RNG_BASE 0x58001000 +#define STM32_IPCC_BASE 0x58000C00 +#define STM32_EXTI_BASE 0x58000800 +#define STM32_PWR_BASE 0x58000400 +#define STM32_RCC_BASE 0x58000000 /* APB3 Base Addresses ******************************************************/ -#define STM32WL5_SUBGHZSPI_BASE 0x58010000 +#define STM32_SUBGHZSPI_BASE 0x58010000 /* Cortex-M4 Base Addresses *************************************************/ @@ -163,7 +163,7 @@ * this address range */ -#define STM32WL5_SCS_BASE 0xe000e000 -#define STM32WL5_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 #endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h index 978e931a4d588..2d6e28db6280b 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h @@ -36,53 +36,53 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32WL5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32WL5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32WL5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32WL5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32WL5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32WL5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32WL5_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ -#define STM32WL5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32WL5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32WL5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32WL5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32WL5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32WL5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32WL5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32WL5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32WL5_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */ -#define STM32WL5_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */ -#define STM32WL5_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */ -#define STM32WL5_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */ -#define STM32WL5_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */ -#define STM32WL5_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */ +#define STM32_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */ +#define STM32_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */ +#define STM32_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */ +#define STM32_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */ +#define STM32_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */ /* Register Addresses *******************************************************/ -#define STM32WL5_PWR_CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR1_OFFSET) -#define STM32WL5_PWR_CR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR2_OFFSET) -#define STM32WL5_PWR_CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR3_OFFSET) -#define STM32WL5_PWR_CR4 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR4_OFFSET) -#define STM32WL5_PWR_SR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR1_OFFSET) -#define STM32WL5_PWR_SR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR2_OFFSET) -#define STM32WL5_PWR_SCR (STM32WL5_PWR_BASE+STM32WL5_PWR_SCR_OFFSET) -#define STM32WL5_PWR_CR5 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR5_OFFSET) -#define STM32WL5_PWR_PUCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRA_OFFSET) -#define STM32WL5_PWR_PDCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRA_OFFSET) -#define STM32WL5_PWR_PUCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRB_OFFSET) -#define STM32WL5_PWR_PDCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRB_OFFSET) -#define STM32WL5_PWR_PUCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRC_OFFSET) -#define STM32WL5_PWR_PDCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRC_OFFSET) -#define STM32WL5_PWR_PUCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRH_OFFSET) -#define STM32WL5_PWR_PDCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRH_OFFSET) -#define STM32WL5_PWR_C2CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR1_OFFSET) -#define STM32WL5_PWR_C2CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR3_OFFSET) -#define STM32WL5_PWR_EXTSCR (STM32WL5_PWR_BASE+STM32WL5_PWR_EXTSCR_OFFSET) -#define STM32WL5_PWR_SECCFGR (STM32WL5_PWR_BASE+STM32WL5_PWR_SECCFGR_OFFSET) -#define STM32WL5_PWR_SUBGHZSPICR (STM32WL5_PWR_BASE+STM32WL5_PWR_SUBGHZSPICR_OFFSET) -#define STM32WL5_PWR_RSSCMDR (STM32WL5_PWR_BASE+STM32WL5_PWR_RSSCMDR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET) +#define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_C2CR1 (STM32_PWR_BASE+STM32_PWR_C2CR1_OFFSET) +#define STM32_PWR_C2CR3 (STM32_PWR_BASE+STM32_PWR_C2CR3_OFFSET) +#define STM32_PWR_EXTSCR (STM32_PWR_BASE+STM32_PWR_EXTSCR_OFFSET) +#define STM32_PWR_SECCFGR (STM32_PWR_BASE+STM32_PWR_SECCFGR_OFFSET) +#define STM32_PWR_SUBGHZSPICR (STM32_PWR_BASE+STM32_PWR_SUBGHZSPICR_OFFSET) +#define STM32_PWR_RSSCMDR (STM32_PWR_BASE+STM32_PWR_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h index 3f7309342f300..987fed3348f18 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h @@ -35,95 +35,95 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32WL5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32WL5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32WL5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32WL5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32WL5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32WL5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32WL5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32WL5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32WL5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32WL5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32WL5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32WL5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32WL5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32WL5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32WL5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32WL5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32WL5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32WL5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32WL5_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32WL5_RCC_EXTCFGR_OFFSET 0x0108 -#define STM32WL5_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ -#define STM32WL5_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ -#define STM32WL5_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32WL5_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32WL5_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_EXTCFGR_OFFSET 0x0108 +#define STM32_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ +#define STM32_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ +#define STM32_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */ /* Register Addresses *******************************************************/ -#define STM32WL5_RCC_CR (STM32WL5_RCC_BASE + STM32WL5_RCC_CR_OFFSET) -#define STM32WL5_RCC_ICSCR (STM32WL5_RCC_BASE + STM32WL5_RCC_ICSCR_OFFSET) -#define STM32WL5_RCC_CFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_CFGR_OFFSET) -#define STM32WL5_RCC_PLLCFG (STM32WL5_RCC_BASE + STM32WL5_RCC_PLLCFG_OFFSET) -#define STM32WL5_RCC_CIER (STM32WL5_RCC_BASE + STM32WL5_RCC_CIER_OFFSET) -#define STM32WL5_RCC_CIFR (STM32WL5_RCC_BASE + STM32WL5_RCC_CIFR_OFFSET) -#define STM32WL5_RCC_CICR (STM32WL5_RCC_BASE + STM32WL5_RCC_CICR_OFFSET) -#define STM32WL5_RCC_AHB1RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1RSTR_OFFSET) -#define STM32WL5_RCC_AHB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2RSTR_OFFSET) -#define STM32WL5_RCC_AHB3RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3RSTR_OFFSET) -#define STM32WL5_RCC_APB1RSTR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR1_OFFSET) -#define STM32WL5_RCC_APB1RSTR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR2_OFFSET) -#define STM32WL5_RCC_APB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2RSTR_OFFSET) -#define STM32WL5_RCC_AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1ENR_OFFSET) -#define STM32WL5_RCC_AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2ENR_OFFSET) -#define STM32WL5_RCC_AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3ENR_OFFSET) -#define STM32WL5_RCC_APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR1_OFFSET) -#define STM32WL5_RCC_APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR2_OFFSET) -#define STM32WL5_RCC_APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2ENR_OFFSET) -#define STM32WL5_RCC_AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1SMENR_OFFSET) -#define STM32WL5_RCC_AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2SMENR_OFFSET) -#define STM32WL5_RCC_AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3SMENR_OFFSET) -#define STM32WL5_RCC_APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR1_OFFSET) -#define STM32WL5_RCC_APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR2_OFFSET) -#define STM32WL5_RCC_APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2SMENR_OFFSET) -#define STM32WL5_RCC_CCIPR (STM32WL5_RCC_BASE + STM32WL5_RCC_CCIPR_OFFSET) -#define STM32WL5_RCC_BDCR (STM32WL5_RCC_BASE + STM32WL5_RCC_BDCR_OFFSET) -#define STM32WL5_RCC_CSR (STM32WL5_RCC_BASE + STM32WL5_RCC_CSR_OFFSET) -#define STM32WL5_RCC_EXTCFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_EXTCFGR_OFFSET) -#define STM32WL5_RCC_C2AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1ENR_OFFSET) -#define STM32WL5_RCC_C2AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2ENR_OFFSET) -#define STM32WL5_RCC_C2AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3ENR_OFFSET) -#define STM32WL5_RCC_C2APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR1_OFFSET) -#define STM32WL5_RCC_C2APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR2_OFFSET) -#define STM32WL5_RCC_C2APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2ENR_OFFSET) -#define STM32WL5_RCC_C2APB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3ENR_OFFSET) -#define STM32WL5_RCC_C2AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1SMENR_OFFSET) -#define STM32WL5_RCC_C2AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2SMENR_OFFSET) -#define STM32WL5_RCC_C2AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3SMENR_OFFSET) -#define STM32WL5_RCC_C2APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR1_OFFSET) -#define STM32WL5_RCC_C2APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR2_OFFSET) -#define STM32WL5_RCC_C2APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2SMENR_OFFSET) -#define STM32WL5_RCC_C2APB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3SMENR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_EXTCFGR (STM32_RCC_BASE + STM32_RCC_EXTCFGR_OFFSET) +#define STM32_RCC_C2AHB1ENR (STM32_RCC_BASE + STM32_RCC_C2AHB1ENR_OFFSET) +#define STM32_RCC_C2AHB2ENR (STM32_RCC_BASE + STM32_RCC_C2AHB2ENR_OFFSET) +#define STM32_RCC_C2AHB3ENR (STM32_RCC_BASE + STM32_RCC_C2AHB3ENR_OFFSET) +#define STM32_RCC_C2APB1ENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR1_OFFSET) +#define STM32_RCC_C2APB1ENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR2_OFFSET) +#define STM32_RCC_C2APB2ENR (STM32_RCC_BASE + STM32_RCC_C2APB2ENR_OFFSET) +#define STM32_RCC_C2APB3ENR (STM32_RCC_BASE + STM32_RCC_C2APB3ENR_OFFSET) +#define STM32_RCC_C2AHB1SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB1SMENR_OFFSET) +#define STM32_RCC_C2AHB2SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB2SMENR_OFFSET) +#define STM32_RCC_C2AHB3SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB3SMENR_OFFSET) +#define STM32_RCC_C2APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR1_OFFSET) +#define STM32_RCC_C2APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR2_OFFSET) +#define STM32_RCC_C2APB2SMENR (STM32_RCC_BASE + STM32_RCC_C2APB2SMENR_OFFSET) +#define STM32_RCC_C2APB3SMENR (STM32_RCC_BASE + STM32_RCC_C2APB3SMENR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h index 22c61af23aedb..aaeac35731539 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h @@ -45,7 +45,7 @@ #undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ #undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ -#if defined(STM32WL5_HAVE_IP_SPI_V2) +#if defined(STM32_HAVE_IP_SPI_V2) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -54,7 +54,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32WL5_HAVE_IP_SPI_V3) +#if defined(STM32_HAVE_IP_SPI_V3) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -63,7 +63,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32WL5_HAVE_IP_SPI_V4) +#if defined(STM32_HAVE_IP_SPI_V4) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -75,65 +75,65 @@ /* Maximum allowed speed as per specifications for all SPIs */ #if defined(CONFIG_STM32WL5_STM32F4XXX) -# define STM32WL5_SPI_CLK_MAX 37500000UL +# define STM32_SPI_CLK_MAX 37500000UL #else -# define STM32WL5_SPI_CLK_MAX 18000000UL +# define STM32_SPI_CLK_MAX 18000000UL #endif /* Register Offsets *********************************************************/ -#define STM32WL5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32WL5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32WL5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32WL5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32WL5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32WL5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32WL5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ #if defined(HAVE_SPI_I2S) -# define STM32WL5_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ -# define STM32WL5_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ +# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ #endif /* Register Addresses *******************************************************/ -#if STM32WL5_NSPI > 0 -# define STM32WL5_SPI1_CR1 \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CR1_OFFSET) -# define STM32WL5_SPI1_CR2 \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CR2_OFFSET) -# define STM32WL5_SPI1_SR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_SR_OFFSET) -# define STM32WL5_SPI1_DR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_DR_OFFSET) -# define STM32WL5_SPI1_CRCPR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CRCPR_OFFSET) -# define STM32WL5_SPI1_RXCRCR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_RXCRCR_OFFSET) -# define STM32WL5_SPI1_TXCRCR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 \ + (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 \ + (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR \ + (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR \ + (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR \ + (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR \ + (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR \ + (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32WL5_NSPI > 1 -# define STM32WL5_SPI2S2_CR1 \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR1_OFFSET) -# define STM32WL5_SPI2S2_CR2 \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR2_OFFSET) -# define STM32WL5_SPI2S2_SR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_SR_OFFSET) -# define STM32WL5_SPI2S2_DR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_DR_OFFSET) -# define STM32WL5_SPI2S2_CRCPR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CRCPR_OFFSET) -# define STM32WL5_SPI2S2_RXCRCR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_RXCRCR_OFFSET) -# define STM32WL5_SPI2S2_TXCRCR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2S2_CR1 \ + (STM32_SPI2S2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2S2_CR2 \ + (STM32_SPI2S2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2S2_SR \ + (STM32_SPI2S2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2S2_DR \ + (STM32_SPI2S2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2S2_CRCPR \ + (STM32_SPI2S2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2S2_RXCRCR \ + (STM32_SPI2S2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2S2_TXCRCR \ + (STM32_SPI2S2_BASE + STM32_SPI_TXCRCR_OFFSET) # if defined(HAVE_SPI_I2S) -# define STM32WL5_SPI2S2_I2SCFGR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SCFGR_OFFSET) -# define STM32WL5_SPI2S2_I2SPR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SPR_OFFSET) +# define STM32_SPI2S2_I2SCFGR \ + (STM32_SPI2S2_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2S2_I2SPR \ + (STM32_SPI2S2_BASE + STM32_SPI_I2SPR_OFFSET) # endif #endif diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h index eaf17d3ad0d82..34874962a4b6e 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h @@ -36,43 +36,43 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32WL5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ - -#define STM32WL5_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ - -#define STM32WL5_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32WL5_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32WL5_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32WL5_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32WL5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32WL5_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32WL5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32WL5_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32WL5_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */ -#define STM32WL5_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */ -#define STM32WL5_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */ -#define STM32WL5_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */ -#define STM32WL5_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ + +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ + +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */ +#define STM32_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */ +#define STM32_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */ +#define STM32_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */ +#define STM32_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */ /* Register Addresses *******************************************************/ -#define STM32WL5_SYSCFG_MEMRMP (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_MEMRMP_OFFSET) -#define STM32WL5_SYSCFG_CFGR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR1_OFFSET) -#define STM32WL5_SYSCFG_EXTICR(p) (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR_OFFSET(p)) -#define STM32WL5_SYSCFG_EXTICR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR1) -#define STM32WL5_SYSCFG_EXTICR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR2) -#define STM32WL5_SYSCFG_EXTICR3 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR3) -#define STM32WL5_SYSCFG_EXTICR4 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR4) -#define STM32WL5_SYSCFG_SCSR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SCSR) -#define STM32WL5_SYSCFG_CFGR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR2) -#define STM32WL5_SYSCFG_SWPR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SWPR) -#define STM32WL5_SYSCFG_SKR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SKR) -#define STM32WL5_SYSCFG_IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR1) -#define STM32WL5_SYSCFG_IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR2) -#define STM32WL5_SYSCFG_C2IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR1) -#define STM32WL5_SYSCFG_C2IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR2) -#define STM32WL5_SYSCFG_RFDCR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_RFDCR) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR) +#define STM32_SYSCFG_IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR1) +#define STM32_SYSCFG_IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR2) +#define STM32_SYSCFG_C2IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR1) +#define STM32_SYSCFG_C2IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR2) +#define STM32_SYSCFG_RFDCR (STM32_SYSCFG_BASE+STM32_SYSCFG_RFDCR) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h index 1ffe5b780381b..f3bc9aa64c12a 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h @@ -31,166 +31,166 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32WL5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32WL5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32WL5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */ -#define STM32WL5_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32WL5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32WL5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */ +#define STM32_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 32-bit General Timers - TIM2 * TIM2 and 5 are 32-bit. * TIM15, 16 and 17 are 16-bit. */ -#define STM32WL5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32WL5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32WL5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32WL5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32WL5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32WL5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32WL5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32WL5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32WL5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32WL5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32WL5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32WL5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 */ -#define STM32WL5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32WL5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32WL5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32WL5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32WL5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32WL5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32WL5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32WL5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32WL5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32WL5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32WL5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32WL5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32WL5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32WL5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32WL5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32WL5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32WL5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32WL5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32WL5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32WL5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32WL5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32WL5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32WL5_TIM1_CR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR1_OFFSET) -#define STM32WL5_TIM1_CR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR2_OFFSET) -#define STM32WL5_TIM1_SMCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SMCR_OFFSET) -#define STM32WL5_TIM1_DIER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DIER_OFFSET) -#define STM32WL5_TIM1_SR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SR_OFFSET) -#define STM32WL5_TIM1_EGR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_EGR_OFFSET) -#define STM32WL5_TIM1_CCMR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR1_OFFSET) -#define STM32WL5_TIM1_CCMR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR2_OFFSET) -#define STM32WL5_TIM1_CCER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCER_OFFSET) -#define STM32WL5_TIM1_CNT (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CNT_OFFSET) -#define STM32WL5_TIM1_PSC (STM32WL5_TIM1_BASE+STM32WL5_ATIM_PSC_OFFSET) -#define STM32WL5_TIM1_ARR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_ARR_OFFSET) -#define STM32WL5_TIM1_RCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_RCR_OFFSET) -#define STM32WL5_TIM1_CCR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR1_OFFSET) -#define STM32WL5_TIM1_CCR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR2_OFFSET) -#define STM32WL5_TIM1_CCR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR3_OFFSET) -#define STM32WL5_TIM1_CCR4 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR4_OFFSET) -#define STM32WL5_TIM1_BDTR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_BDTR_OFFSET) -#define STM32WL5_TIM1_DCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DCR_OFFSET) -#define STM32WL5_TIM1_DMAR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DMAR_OFFSET) -#define STM32WL5_TIM1_OR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR1_OFFSET) -#define STM32WL5_TIM1_CCMR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR3_OFFSET) -#define STM32WL5_TIM1_CCR5 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR5_OFFSET) -#define STM32WL5_TIM1_CCR6 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR6_OFFSET) -#define STM32WL5_TIM1_OR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR2_OFFSET) -#define STM32WL5_TIM1_OR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM16-17. * TIM2 is 32-bit. * TIM16 and 17 are 16-bit. */ -#define STM32WL5_TIM2_CR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM2_CR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM2_SMCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SMCR_OFFSET) -#define STM32WL5_TIM2_DIER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM2_SR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM2_EGR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM2_CCMR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM2_CCMR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR2_OFFSET) -#define STM32WL5_TIM2_CCER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM2_CNT (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM2_PSC (STM32WL5_TIM2_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM2_ARR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM2_CCR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM2_CCR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR2_OFFSET) -#define STM32WL5_TIM2_CCR3 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR3_OFFSET) -#define STM32WL5_TIM2_CCR4 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR4_OFFSET) -#define STM32WL5_TIM2_DCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM2_DMAR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DMAR_OFFSET) -#define STM32WL5_TIM2_OR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_OR_OFFSET) - -#define STM32WL5_TIM16_CR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM16_CR2 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM16_DIER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM16_SR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM16_EGR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM16_CCMR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM16_CCER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM16_CNT (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM16_PSC (STM32WL5_TIM16_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM16_ARR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM16_RCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_RCR_OFFSET) -#define STM32WL5_TIM16_CCR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM16_BDTR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_BDTR_OFFSET) -#define STM32WL5_TIM16_DCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM16_DMAR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DMAR_OFFSET) -#define STM32WL5_TIM16_OR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_OR_OFFSET) - -#define STM32WL5_TIM17_CR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM17_CR2 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM17_DIER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM17_SR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM17_EGR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM17_CCMR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM17_CCER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM17_CNT (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM17_PSC (STM32WL5_TIM17_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM17_ARR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM17_RCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_RCR_OFFSET) -#define STM32WL5_TIM17_CCR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM17_BDTR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_BDTR_OFFSET) -#define STM32WL5_TIM17_DCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM17_DMAR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h index 5eb2450e7a34f..921ee283b4d32 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h @@ -37,57 +37,57 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32WL5_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32WL5_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32WL5_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32WL5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32WL5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32WL5_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32WL5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32WL5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32WL5_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32WL5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ -#define STM32WL5_USART_PRESC_OFFSET 0x002c /* Prescaler */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler */ /* Register Addresses *******************************************************/ -#define STM32WL5_USART1_CR1 (STM32WL5_USART1_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_USART1_CR2 (STM32WL5_USART1_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_USART1_CR3 (STM32WL5_USART1_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_USART1_BRR (STM32WL5_USART1_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_USART1_GTPR (STM32WL5_USART1_BASE+STM32WL5_USART_GTPR_OFFSET) -#define STM32WL5_USART1_RTOR (STM32WL5_USART1_BASE+STM32WL5_USART_RTOR_OFFSET) -#define STM32WL5_USART1_RQR (STM32WL5_USART1_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_USART1_ISR (STM32WL5_USART1_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_USART1_ICR (STM32WL5_USART1_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_USART1_RDR (STM32WL5_USART1_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_USART1_TDR (STM32WL5_USART1_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_USART1_PRESC (STM32WL5_USART1_BASE+STM32WL5_USART_PRESC_OFFSET) - -#define STM32WL5_USART2_CR1 (STM32WL5_USART2_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_USART2_CR2 (STM32WL5_USART2_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_USART2_CR3 (STM32WL5_USART2_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_USART2_BRR (STM32WL5_USART2_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_USART2_GTPR (STM32WL5_USART2_BASE+STM32WL5_USART_GTPR_OFFSET) -#define STM32WL5_USART2_RTOR (STM32WL5_USART2_BASE+STM32WL5_USART_RTOR_OFFSET) -#define STM32WL5_USART2_RQR (STM32WL5_USART2_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_USART2_ISR (STM32WL5_USART2_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_USART2_ICR (STM32WL5_USART2_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_USART2_RDR (STM32WL5_USART2_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_USART2_TDR (STM32WL5_USART2_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_USART2_PRESC (STM32WL5_USART2_BASE+STM32WL5_USART_PRESC_OFFSET) - -#define STM32WL5_LPUART1_CR1 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_LPUART1_CR2 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_LPUART1_CR3 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_LPUART1_BRR (STM32WL5_LPUART1_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_LPUART1_RQR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_LPUART1_ISR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_LPUART1_ICR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_LPUART1_RDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_LPUART1_TDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_LPUART1_PRESC (STM32WL5_LPUART1_BASE+STM32WL5_USART_PRESC_OFFSET) +#define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +#define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +#define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +#define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +#define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) +#define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) +#define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) +#define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) +#define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) +#define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) +#define STM32_USART1_PRESC (STM32_USART1_BASE+STM32_USART_PRESC_OFFSET) + +#define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +#define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +#define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +#define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +#define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) +#define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) +#define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) +#define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) +#define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) +#define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) +#define STM32_USART2_PRESC (STM32_USART2_BASE+STM32_USART_PRESC_OFFSET) + +#define STM32_LPUART1_CR1 (STM32_LPUART1_BASE+STM32_USART_CR1_OFFSET) +#define STM32_LPUART1_CR2 (STM32_LPUART1_BASE+STM32_USART_CR2_OFFSET) +#define STM32_LPUART1_CR3 (STM32_LPUART1_BASE+STM32_USART_CR3_OFFSET) +#define STM32_LPUART1_BRR (STM32_LPUART1_BASE+STM32_USART_BRR_OFFSET) +#define STM32_LPUART1_RQR (STM32_LPUART1_BASE+STM32_USART_RQR_OFFSET) +#define STM32_LPUART1_ISR (STM32_LPUART1_BASE+STM32_USART_ISR_OFFSET) +#define STM32_LPUART1_ICR (STM32_LPUART1_BASE+STM32_USART_ICR_OFFSET) +#define STM32_LPUART1_RDR (STM32_LPUART1_BASE+STM32_USART_RDR_OFFSET) +#define STM32_LPUART1_TDR (STM32_LPUART1_BASE+STM32_USART_TDR_OFFSET) +#define STM32_LPUART1_PRESC (STM32_LPUART1_BASE+STM32_USART_PRESC_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c index 61e9a51df81f7..7b8dc6081ba72 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c +++ b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c @@ -66,17 +66,17 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32WL5_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32WL5_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ #ifdef CONFIG_IPCC # define SRAM2_START IPCC_END #else -# define SRAM2_START STM32WL5_SRAM2_BASE +# define SRAM2_START STM32_SRAM2_BASE #endif -#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Some sanity checking. If multiple memory regions are defined, verify * that CONFIG_MM_REGIONS is set to match the number of memory regions diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c index 6d6318f023832..f94f6f9bbdabf 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c @@ -72,7 +72,7 @@ static int stm32wl5_exti0_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0001, STM32WL5_EXTI_PR1); + putreg32(0x0001, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -93,7 +93,7 @@ static int stm32wl5_exti1_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0002, STM32WL5_EXTI_PR1); + putreg32(0x0002, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -114,7 +114,7 @@ static int stm32wl5_exti2_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0004, STM32WL5_EXTI_PR1); + putreg32(0x0004, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -135,7 +135,7 @@ static int stm32wl5_exti3_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0008, STM32WL5_EXTI_PR1); + putreg32(0x0008, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -156,7 +156,7 @@ static int stm32wl5_exti4_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0010, STM32WL5_EXTI_PR1); + putreg32(0x0010, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -180,7 +180,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32WL5_EXTI_PR1); + pr = getreg32(STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -193,7 +193,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32WL5_EXTI_PR1); + putreg32(mask, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -267,7 +267,7 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32WL5_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) @@ -295,14 +295,14 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, } else if (pin < 10) { - irq = STM32WL5_IRQ_EXTI95; + irq = STM32_IRQ_EXTI95; handler = stm32wl5_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32WL5_IRQ_EXTI1510; + irq = STM32_IRQ_EXTI1510; handler = stm32wl5_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; @@ -353,19 +353,19 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32WL5_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32WL5_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WL5_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32WL5_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.c b/arch/arm/src/stm32wl5/stm32wl5_flash.c index 054ca10b3ae1d..bb83f736a46a0 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.c +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.c @@ -65,7 +65,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */ @@ -93,35 +93,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } - if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32WL5_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32WL5_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32WL5_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32WL5_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -138,17 +138,17 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", (unsigned int)page); - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** @@ -227,20 +227,20 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32WL5_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32WL5_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } @@ -253,42 +253,42 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32WL5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32WL5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32WL5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32WL5_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32WL5_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32WL5_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32WL5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32WL5_FLASH_PAGESIZE + STM32WL5_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32WL5_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -300,7 +300,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32WL5_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -338,7 +338,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32WL5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -372,12 +372,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32WL5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32WL5_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32WL5_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -447,7 +447,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); set_pg_bit = true; for (i = 0; i < FLASH_PAGE_WORDS; i += 2) @@ -455,14 +455,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } /* Verify */ - if (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { ret = -EROFS; goto out; @@ -476,7 +476,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) } } - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); set_pg_bit = false; /* Adjust pointers and counts for the next time through the loop */ @@ -492,7 +492,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) out: if (set_pg_bit) { - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); } /* If there was an error, clear all error flags in status register (rc_w1 @@ -502,9 +502,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32WL5_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32WL5_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_gpio.c index 3b22db6f904e2..b3ec90cac4cb1 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.c @@ -55,19 +55,19 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32WL5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32WL5_NPORTS > 0 - STM32WL5_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32WL5_NPORTS > 1 - STM32WL5_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32WL5_NPORTS > 2 - STM32WL5_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32WL5_NPORTS > 3 - STM32WL5_GPIOH_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOH_BASE, #endif }; @@ -130,7 +130,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32WL5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -179,10 +179,10 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32WL5_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -205,10 +205,10 @@ int stm32wl5_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32WL5_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -223,12 +223,12 @@ int stm32wl5_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32WL5_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32WL5_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -266,14 +266,14 @@ int stm32wl5_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32WL5_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32WL5_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -286,7 +286,7 @@ int stm32wl5_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32WL5_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -303,7 +303,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32WL5_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -365,7 +365,7 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WL5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -386,7 +386,7 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32WL5_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -405,7 +405,7 @@ bool stm32wl5_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WL5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -414,7 +414,7 @@ bool stm32wl5_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32WL5_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/stm32wl5_gpio.h index 86480eb193a55..9e583c880e8ba 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.h @@ -237,7 +237,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32WL5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c index 38a41c718032e..d625e58f1e683 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c @@ -225,8 +225,8 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) UNUSED(arg); UNUSED(irq); - mr = getreg32(STM32WL5_IPCC_C1MR) >> STM32WL5_IPCC_TX_SHIFT; - sr = getreg32(STM32WL5_IPCC_C1TOC2SR); + mr = getreg32(STM32_IPCC_C1MR) >> STM32_IPCC_TX_SHIFT; + sr = getreg32(STM32_IPCC_C1TOC2SR); /* Consider only channels that have tx memory free and are unmasked */ @@ -266,7 +266,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) /* Yes, tell another CPU that data is available to read */ txmem->len = nwritten; - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(chan)); } if (circbuf_used(&priv->ipcc->txbuf) == 0) @@ -276,7 +276,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * will be constantly interrupted by tx free irq. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan)); } #else /* CONFIG_IPCC_BUFFERED */ /* In unbuffered operations we never write anything to IPCC @@ -284,7 +284,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * or else we will constantly get TX interrupts */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan)); #endif /* CONFIG_IPCC_BUFFERED */ /* Wake up all blocked writers that there is free space available * in IPCC memory (or txbuffer) to write. @@ -324,7 +324,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, struct stm32wl5_ipcc_chan_mem_s *txmem; uint32_t sr; - sr = getreg32(STM32WL5_IPCC_C1TOC2SR); + sr = getreg32(STM32_IPCC_C1TOC2SR); if ((sr & (1 << ipcc->chan))) { @@ -334,7 +334,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, * so we are notified when we can write to memory. */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; } @@ -343,7 +343,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, /* Disable TX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_TX_IT); /* Copy as much as we can into IPCC memory */ @@ -353,12 +353,12 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, /* Tell another CPU that data is available to read */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(ipcc->chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(ipcc->chan)); /* Re-enable interrupts */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); + up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT); /* Return number of successfully copied bytes to IPCC memory */ @@ -404,8 +404,8 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) UNUSED(arg); UNUSED(irq); - mr = getreg32(STM32WL5_IPCC_C1MR); - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + mr = getreg32(STM32_IPCC_C1MR); + sr = getreg32(STM32_IPCC_C2TOC1SR); /* Consider only channels that have data in rx memory and are unmasked */ @@ -446,7 +446,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) * we have to mask rxirq so we don't get that irq again. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan)); #endif } @@ -485,7 +485,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, struct stm32wl5_ipcc_s *priv; struct stm32wl5_ipcc_chan_mem_s *rxmem; - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + sr = getreg32(STM32_IPCC_C2TOC1SR); if (!(sr & (1 << ipcc->chan))) { @@ -502,7 +502,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, /* Disable RX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* This function may be called multiple times to get only part * of data from IPCC memory, ie. There are 8 bytes of data in @@ -525,17 +525,17 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, /* Tell another CPU that IPCC rx buffer is free to be populated */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, - STM32WL5_IPCC_SCR_CHNC(ipcc->chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, + STM32_IPCC_SCR_CHNC(ipcc->chan)); /* Unmask RX interrupt to know when second CPU sends us a message */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(ipcc->chan), 0); } /* Re-enable interrupt */ - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); return to_copy; } @@ -569,7 +569,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, struct stm32wl5_ipcc_chan_mem_s *rxmem; uint32_t sr; - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + sr = getreg32(STM32_IPCC_C2TOC1SR); if (!(sr & (1 << chan))) { @@ -609,7 +609,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, * this one. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan)); } /* Buffer data. This function cannot really fail us if we @@ -629,11 +629,11 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, /* Tell another CPU that IPCC rx buffer is free to be populated */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNC(chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNC(chan)); /* Unmask RX interrupt to know when second CPU sends us a message */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0); } return to_copy; @@ -665,7 +665,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, /* Disable RX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* Copy data to buffer */ @@ -673,7 +673,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, /* Re-enable interrupt */ - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* Return number of bytes that were successfully buffered */ @@ -701,7 +701,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, #ifdef CONFIG_IPCC_BUFFERED static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) { - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; } #endif @@ -728,8 +728,8 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) /* Mask interrupts for given channel */ - modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNFM(ipcc->chan)); - modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNOM(ipcc->chan)); + modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNFM(ipcc->chan)); + modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNOM(ipcc->chan)); /* Free allocated ipcc memory */ @@ -798,8 +798,8 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) /* Unmask channel interrupt */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(chan), 0); - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0); if (ipcc_fti) { @@ -810,14 +810,14 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * interrupt functions */ - ret = irq_attach(STM32WL5_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL); if (ret) { kmm_free(ipcc); return NULL; } - ret = irq_attach(STM32WL5_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL); if (ret) { kmm_free(ipcc); @@ -829,11 +829,11 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * - CPU2 has read message from us and TX memory is free to be used again */ - putreg32(STM32WL5_IPCC_CR_RXOIE | STM32WL5_IPCC_CR_TXFIE, - STM32WL5_IPCC_C1CR); + putreg32(STM32_IPCC_CR_RXOIE | STM32_IPCC_CR_TXFIE, + STM32_IPCC_C1CR); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT); ipcc_fti = 1; diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h index 14b68fdb151f3..1e632661c0511 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h @@ -135,7 +135,7 @@ * of SRAM2. SRAM2 region will be right after IPCC reserved memory */ -#define IPCC_START STM32WL5_SRAM2_BASE +#define IPCC_START STM32_SRAM2_BASE #define IPCC_NCHAN (IPCC_CHAN1 + IPCC_CHAN2 + IPCC_CHAN3 + \ IPCC_CHAN4 + IPCC_CHAN5 + IPCC_CHAN6) #define IPCC_END (IPCC_START + IPCC_CHAN1_SIZE + IPCC_CHAN2_SIZE + \ diff --git a/arch/arm/src/stm32wl5/stm32wl5_irq.c b/arch/arm/src/stm32wl5/stm32wl5_irq.c index 8e953adb2500f..b0b25e844bce9 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_irq.c +++ b/arch/arm/src/stm32wl5/stm32wl5_irq.c @@ -202,13 +202,13 @@ static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32WL5_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32WL5_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -218,19 +218,19 @@ static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32WL5_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32WL5_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32WL5_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32WL5_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -260,7 +260,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32WL5_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -314,13 +314,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32WL5_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32WL5_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32WL5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif stm32wl5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); @@ -330,23 +330,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32WL5_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32WL5_IRQ_NMI, stm32wl5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32wl5_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32WL5_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32WL5_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32WL5_IRQ_PENDSV, stm32wl5_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32wl5_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32WL5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32WL5_IRQ_RESERVED, stm32wl5_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32wl5_reserved, NULL); #endif stm32wl5_dumpnvic("initial", NR_IRQS); @@ -382,7 +382,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -417,7 +417,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -460,10 +460,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32WL5_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32WL5_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -476,7 +476,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32WL5_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c index 06a47209fc635..474315559282d 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c @@ -47,70 +47,70 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_LPUART1_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR2 -# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32WL5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32WL5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32WL5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_USART1_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK2_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB2ENR -# define STM32WL5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32WL5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32WL5_CONSOLE_TX GPIO_USART1_TX -# define STM32WL5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_USART2_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR1 -# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32WL5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32WL5_CONSOLE_TX GPIO_USART2_TX -# define STM32WL5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32WL5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32WL5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -118,9 +118,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32WL5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32WL5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -136,7 +136,7 @@ /* CR2 settings */ -# if STM32WL5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -178,24 +178,24 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32WL5_USARTDIV8 \ - (((STM32WL5_APBCLOCK << 1) + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD) -# define STM32WL5_USARTDIV16 \ - ((STM32WL5_APBCLOCK + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) /* lpuart has different formula for baud rate than normal uart */ -# define STM32WL5_BRR_VALUE \ - (((256ull * STM32WL5_APBCLOCK) / STM32WL5_CONSOLE_BAUD) & LPUART_BRR_MASK) +# define STM32_BRR_VALUE \ + (((256ull * STM32_APBCLOCK) / STM32_CONSOLE_BAUD) & LPUART_BRR_MASK) # else /* CONFIG_LPUART1_SERIAL_CONSOLE */ -# if STM32WL5_USARTDIV8 > 2000 -# define STM32WL5_BRR_VALUE STM32WL5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32WL5_BRR_VALUE \ - ((STM32WL5_USARTDIV8 & 0xfff0) | ((STM32WL5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif /* CONFIG_LPUART1_SERIAL_CONSOLE */ @@ -238,22 +238,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32WL5_CONSOLE_RS485_DIR - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - STM32WL5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32WL5_CONSOLE_BASE + STM32WL5_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32WL5_CONSOLE_RS485_DIR - while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - !STM32WL5_CONSOLE_RS485_DIR_POLARITY); + stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -279,7 +279,7 @@ void stm32wl5_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32WL5_CONSOLE_APBREG, 0, STM32WL5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -288,17 +288,17 @@ void stm32wl5_lowsetup(void) * stm32wl5_rcc.c */ -#ifdef STM32WL5_CONSOLE_TX - stm32wl5_configgpio(STM32WL5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32wl5_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32WL5_CONSOLE_RX - stm32wl5_configgpio(STM32WL5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32wl5_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32WL5_CONSOLE_RS485_DIR - stm32wl5_configgpio(STM32WL5_CONSOLE_RS485_DIR); - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - !STM32WL5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wl5_configgpio(STM32_CONSOLE_RS485_DIR); + stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -306,42 +306,42 @@ void stm32wl5_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32WL5_BRR_VALUE, - STM32WL5_CONSOLE_BASE + STM32WL5_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lse.c b/arch/arm/src/stm32wl5/stm32wl5_lse.c index 5abad5f93ab6c..fe1bcb5ff4d9a 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lse.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lse.c @@ -89,7 +89,7 @@ void stm32wl5_rcc_enablelse(void) * clock are already running. */ - regval = getreg32(STM32WL5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY | RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) != @@ -117,7 +117,7 @@ void stm32wl5_rcc_enablelse(void) regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif @@ -126,11 +126,11 @@ void stm32wl5_rcc_enablelse(void) { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= drives[drive++]; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready (or until a timeout elapsed) */ @@ -139,7 +139,7 @@ void stm32wl5_rcc_enablelse(void) { /* Check if the LSERDY flag is the set in the BDCR */ - regval = getreg32(STM32WL5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if (regval & RCC_BDCR_LSERDY) { @@ -167,11 +167,11 @@ void stm32wl5_rcc_enablelse(void) regval |= RCC_BDCR_LSESYSEN; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE system clock to be ready */ - while (!((regval = getreg32(STM32WL5_RCC_BDCR)) & + while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { stm32wl5_waste(); @@ -184,7 +184,7 @@ void stm32wl5_rcc_enablelse(void) regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lsi.c b/arch/arm/src/stm32wl5/stm32wl5_lsi.c index ea4495ddbd664..5b5b36395dfd6 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lsi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lsi.c @@ -46,11 +46,11 @@ void stm32wl5_rcc_enablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WL5_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32WL5_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** @@ -67,7 +67,7 @@ void stm32wl5_rcc_disablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WL5_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.c b/arch/arm/src/stm32wl5/stm32wl5_pwr.c index e1a1644ed5631..1e0fa17138968 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.c @@ -42,18 +42,18 @@ static inline uint16_t stm32wl5_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32WL5_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wl5_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32WL5_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg32(STM32WL5_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); } @@ -83,7 +83,7 @@ bool stm32wl5_pwr_enablebkp(bool writable) /* Get the current state of the STM32WL5 PWR control register 1 */ - regval = stm32wl5_pwr_getreg(STM32WL5_PWR_CR1_OFFSET); + regval = stm32wl5_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -93,14 +93,14 @@ bool stm32wl5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval); + stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval); + stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -121,5 +121,5 @@ bool stm32wl5_pwr_enablebkp(bool writable) void stm32wl5_pwr_boot_c2(void) { - modifyreg32(STM32WL5_PWR_CR4, 0, PWR_CR4_C2BOOT); + modifyreg32(STM32_PWR_CR4, 0, PWR_CR4_C2BOOT); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.c b/arch/arm/src/stm32wl5/stm32wl5_rcc.c index 571ea43fc7fd7..cbc5c60afc827 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.c @@ -84,14 +84,14 @@ static inline void stm32wl5_rcc_resetbkp(void) init_stat = stm32wl5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32WL5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32WL5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -104,19 +104,19 @@ static inline void stm32wl5_rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32WL5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32WL5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32WL5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32WL5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } (void)stm32wl5_pwr_enablebkp(false); @@ -199,7 +199,7 @@ static void stm32wl5_rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32WL5_DMA1 /* DMA 1 clock enable */ @@ -219,7 +219,7 @@ static void stm32wl5_rcc_enableahb1(void) regval |= RCC_AHB1ENR_CRCEN; #endif - putreg32(regval, STM32WL5_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -238,25 +238,25 @@ static inline void stm32wl5_rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32WL5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32WL5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32WL5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32WL5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIOHEN #endif ); -#endif /* STM32WL5_NPORTS */ +#endif /* STM32_NPORTS */ - putreg32(regval, STM32WL5_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -275,7 +275,7 @@ static inline void stm32wl5_rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32WL5_AES /* Cryptographic modules clock enable */ @@ -301,7 +301,7 @@ static inline void stm32wl5_rcc_enableahb3(void) regval |= RCC_AHB3ENR_IPCCEN; #endif - putreg32(regval, STM32WL5_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -320,7 +320,7 @@ static inline void stm32wl5_rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32WL5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32WL5_TIM2 /* TIM2 clock enable */ @@ -370,11 +370,11 @@ static inline void stm32wl5_rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32WL5_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32WL5_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32WL5_LPUART1 /* Low power uart clock enable */ @@ -394,7 +394,7 @@ static inline void stm32wl5_rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM3EN; #endif - putreg32(regval, STM32WL5_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -413,7 +413,7 @@ static inline void stm32wl5_rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32WL5_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32WL5_ADC1) /* ADC clock enable */ @@ -451,7 +451,7 @@ static inline void stm32wl5_rcc_enableapb2(void) regval |= RCC_APB2ENR_TIM17EN; #endif - putreg32(regval, STM32WL5_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -471,9 +471,9 @@ static inline void stm32wl5_rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32WL5_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32WL5_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32WL5_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -489,15 +489,15 @@ static inline void stm32wl5_rcc_enableccip(void) regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32WL5_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32WL5_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32WL5_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ - regval |= STM32WL5_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32WL5_ADC1) @@ -518,19 +518,19 @@ static inline void stm32wl5_rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32WL5_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32WL5_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32WL5_I2C4 - regval = getreg32(STM32WL5_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval |= RCC_CCIPR_I2C4SEL_HSI; - putreg32(regval, STM32WL5_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -610,12 +610,12 @@ void stm32wl5_stdclockconfig(void) { uint32_t regval; -#if defined(STM32WL5_BOARD_USEHSI) || defined(STM32WL5_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ @@ -623,7 +623,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out */ @@ -632,17 +632,17 @@ void stm32wl5_stdclockconfig(void) } #endif -#if defined(STM32WL5_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32WL5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready */ for (; ; ) { - if ((regval = getreg32(STM32WL5_RCC_CR)), + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out */ @@ -653,9 +653,9 @@ void stm32wl5_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32WL5_RCC_CR); - regval |= (STM32WL5_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready */ @@ -663,7 +663,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out */ @@ -671,23 +671,23 @@ void stm32wl5_stdclockconfig(void) } } -#elif defined(STM32WL5_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ -#if defined(STM32WL5_BOARD_USETCXO) +#if defined(STM32_BOARD_USETCXO) /* nucleo-wl55jc uses TCXO crystal, which needs to be first * powered up with PB0 pin - or more conveniently by setting * HSEBYPPWR register. This has to be done before HSE is enabled */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEBYPPWR; - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); #endif - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready */ @@ -695,7 +695,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out */ @@ -704,7 +704,7 @@ void stm32wl5_stdclockconfig(void) } #else -# error stm32wl5_stdclockconfig(), must have one of STM32WL5_BOARD_USEHSI, STM32WL5_BOARD_USEMSI, STM32WL5_BOARD_USEHSE defined +# error stm32wl5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -714,10 +714,10 @@ void stm32wl5_stdclockconfig(void) /* Select correct main regulator range */ - regval = getreg32(STM32WL5_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - if (STM32WL5_SYSCLK_FREQUENCY <= 16000000) + if (STM32_SYSCLK_FREQUENCY <= 16000000) { /* set low power range for frequencies <= 16MHz */ @@ -730,121 +730,121 @@ void stm32wl5_stdclockconfig(void) regval |= PWR_CR1_VOS_RANGE1; } - putreg32(regval, STM32WL5_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Wait for voltage regulator to stabilize */ - while (getreg32(STM32WL5_PWR_SR2) & PWR_SR2_VOSF) + while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32WL5_RCC_CFGR_HPRE; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32WL5_RCC_CFGR_PPRE2; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32WL5_RCC_CFGR_PPRE1; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); #ifdef CONFIG_STM32WL5_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif /* Set the PLL source and main divider */ - regval = getreg32(STM32WL5_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32WL5_PLLCFG_PLLM | STM32WL5_PLLCFG_PLLN | - STM32WL5_PLLCFG_PLLP | STM32WL5_PLLCFG_PLLQ | - STM32WL5_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32WL5_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32WL5_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32WL5_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32WL5_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32WL5_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32WL5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32WL5_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32WL5_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WL5_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure flash wait states according to manual */ - if (STM32WL5_HCLK3_FREQUENCY <= 18000000 /* 18MHz */) + if (STM32_HCLK3_FREQUENCY <= 18000000 /* 18MHz */) { regval = FLASH_ACR_LATENCY_0; } - else if (STM32WL5_HCLK3_FREQUENCY <= 36000000 /* 36MHz */) + else if (STM32_HCLK3_FREQUENCY <= 36000000 /* 36MHz */) { regval = FLASH_ACR_LATENCY_1; } - else /* STM32WL5_HCLK3_FREQUENCY <= 48MHz */ + else /* STM32_HCLK3_FREQUENCY <= 48MHz */ { regval = FLASH_ACR_LATENCY_2; } - putreg32(regval, STM32WL5_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32WL5_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/stm32wl5_rcc.h index 1989f237afd61..3d563c431c4be 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.h @@ -77,10 +77,10 @@ static inline void stm32wl5_mcoconfig(uint32_t source) /* Set MCO source */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCOSEL_MASK); regval |= (source & RCC_CFGR_MCOSEL_MASK); - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 524483ef5cbe1..462d9170324a2 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -418,13 +418,13 @@ static struct stm32wl5_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32WL5_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32WL5_PCLK2_FREQUENCY, - .usartbase = STM32WL5_LPUART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -478,13 +478,13 @@ static struct stm32wl5_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32WL5_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32WL5_PCLK2_FREQUENCY, - .usartbase = STM32WL5_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -540,13 +540,13 @@ static struct stm32wl5_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32WL5_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32WL5_PCLK1_FREQUENCY, - .usartbase = STM32WL5_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -577,7 +577,7 @@ static struct stm32wl5_serial_s g_usart2priv = /* This table lets us iterate over the configured USARTs */ static struct stm32wl5_serial_s * const - g_uart_devs[STM32WL5_NLPUART + STM32WL5_NUSART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART] = { #ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -647,15 +647,15 @@ void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie) * above) */ - cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -710,8 +710,8 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - cr3 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -772,7 +772,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) uint32_t cr1; uint32_t brr; - if (priv->usartbase == STM32WL5_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { /* lpuart has different calculations baudrate, and there is not * oversampling: @@ -804,7 +804,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) * But what is small? */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 2000) { /* Use usartdiv16 */ @@ -828,14 +828,14 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) cr1 |= USART_CR1_OVER8; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); } - stm32wl5serial_putreg(priv, STM32WL5_USART_BRR_OFFSET, brr); + stm32wl5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); /* Configure parity mode */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -873,11 +873,11 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -885,11 +885,11 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN) @@ -906,7 +906,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) } #endif - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -951,7 +951,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + while ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_DMA @@ -1057,7 +1057,7 @@ static void stm32wl5serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wl5_serial_s *priv = g_uart_devs[n]; @@ -1097,21 +1097,21 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) default: return; #ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER - case STM32WL5_LPUART1_BASE: + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32WL5_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif #ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER - case STM32WL5_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32WL5_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif #ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER - case STM32WL5_USART2_BASE: + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32WL5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1198,7 +1198,7 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1209,26 +1209,26 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1236,9 +1236,9 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1291,7 +1291,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1302,7 +1302,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1316,9 +1316,9 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1376,9 +1376,9 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1544,7 +1544,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, /* Get the masked USART status word. */ - priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET); + priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1612,7 +1612,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, * interrupt clear register (ICR). */ - stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET, + stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1685,19 +1685,19 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1742,11 +1742,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1763,17 +1763,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1793,11 +1793,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1814,17 +1814,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1835,11 +1835,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1996,8 +1996,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2009,8 +2009,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2046,7 +2046,7 @@ static int stm32wl5serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32wl5serial_getreg(priv, STM32WL5_USART_RDR_OFFSET); + rdr = stm32wl5serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2133,7 +2133,7 @@ static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev) struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv; - return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2296,7 +2296,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2307,7 +2307,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2476,7 +2476,7 @@ static void stm32wl5serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32wl5serial_putreg(priv, STM32WL5_USART_TDR_OFFSET, (uint32_t)ch); + stm32wl5serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2561,7 +2561,7 @@ static bool stm32wl5serial_txready(struct uart_dev_s *dev) struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv; - return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2603,11 +2603,11 @@ static void stm32wl5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET); + priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET, + stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2743,7 +2743,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wl5_serial_s *priv = g_uart_devs[n]; @@ -2813,7 +2813,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -2882,7 +2882,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.c b/arch/arm/src/stm32wl5/stm32wl5_spi.c index 3aa45fe20c4f2..55229b624349c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.c @@ -316,10 +316,10 @@ static struct stm32wl5_spidev_s g_spi1dev = { .ops = &g_sp1iops, }, - .spibase = STM32WL5_SPI1_BASE, - .spiclock = STM32WL5_PCLK2_FREQUENCY, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, #ifdef CONFIG_STM32WL5_SPI_INTERRUPTS - .spiirq = STM32WL5_IRQ_SPI1, + .spiirq = STM32_IRQ_SPI1, #endif #ifdef CONFIG_STM32WL5_SPI_DMA # ifdef CONFIG_STM32WL5_SPI1_DMA @@ -386,10 +386,10 @@ static struct stm32wl5_spidev_s g_spi2s2dev = { &g_sp2iops }, - .spibase = STM32WL5_SPI2S2_BASE, - .spiclock = STM32WL5_PCLK1_FREQUENCY, + .spibase = STM32_SPI2S2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32WL5_SPI_INTERRUPTS - .spiirq = STM32WL5_IRQ_SPI2S2, + .spiirq = STM32_IRQ_SPI2S2, #endif #ifdef CONFIG_STM32WL5_SPI_DMA # ifdef CONFIG_STM32WL5_SPI2S2_DMA @@ -518,7 +518,7 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) { } @@ -539,11 +539,11 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) if (priv->nbits < 9) { - return (uint16_t)spi_getreg8(priv, STM32WL5_SPI_DR_OFFSET); + return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET); } else { - return spi_getreg(priv, STM32WL5_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } } @@ -568,7 +568,7 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) { } @@ -576,11 +576,11 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, if (priv->nbits < 9) { - spi_putreg8(priv, STM32WL5_SPI_DR_OFFSET, (uint8_t)word); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word); } else { - spi_putreg(priv, STM32WL5_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } } @@ -766,7 +766,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, /* Configure the RX DMA */ - stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32WL5_SPI_DR_OFFSET, + stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -817,7 +817,7 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, /* Setup the TX DMA */ - stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32WL5_SPI_DR_OFFSET, + stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -875,12 +875,12 @@ static void spi_modifycr1(struct stm32wl5_spidev_s *priv, uint16_t clrbits) { uint16_t cr1; - cr1 = spi_getreg(priv, STM32WL5_SPI_CR1_OFFSET); + cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET); cr1 &= ~clrbits; cr1 |= setbits; - spi_putreg(priv, STM32WL5_SPI_CR1_OFFSET, cr1); + spi_putreg(priv, STM32_SPI_CR1_OFFSET, cr1); - spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR1_OFFSET, + spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR1_OFFSET, cr1); } @@ -904,11 +904,11 @@ static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr2; - cr2 = spi_getreg(priv, STM32WL5_SPI_CR2_OFFSET); + cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET); cr2 &= ~clrbits; cr2 |= setbits; - spi_putreg(priv, STM32WL5_SPI_CR2_OFFSET, cr2); - spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR2_OFFSET, + spi_putreg(priv, STM32_SPI_CR2_OFFSET, cr2); + spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR2_OFFSET, cr2); } @@ -1314,7 +1314,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * (Reading from the SR clears the error flags) */ - regval = spi_getreg(priv, STM32WL5_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32 "\n", wd, ret, regval); @@ -1731,7 +1731,7 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32WL5_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32WL5_SPI_DMA if (priv->rxch && priv->txch) diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.c b/arch/arm/src/stm32wl5/stm32wl5_start.c index e828fca974eda..aedd8b76cbf09 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.c +++ b/arch/arm/src/stm32wl5/stm32wl5_start.c @@ -60,8 +60,8 @@ * 0x2000:8000 - Start of internal SRAM2 */ -#define SRAM2_START STM32WL5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.c b/arch/arm/src/stm32wl5/stm32wl5_tim.c index 7be699ed8f7fb..9ecd2811a6e77 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.c @@ -306,16 +306,16 @@ static const struct stm32wl5_tim_ops_s stm32wl5_tim_ops = struct stm32wl5_tim_priv_s stm32wl5_tim1_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM2 struct stm32wl5_tim_priv_s stm32wl5_tim2_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -323,8 +323,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim2_priv = struct stm32wl5_tim_priv_s stm32wl5_tim3_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -332,8 +332,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim3_priv = struct stm32wl5_tim_priv_s stm32wl5_tim4_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -341,8 +341,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim4_priv = struct stm32wl5_tim_priv_s stm32wl5_tim5_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -350,8 +350,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim5_priv = struct stm32wl5_tim_priv_s stm32wl5_tim6_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -359,8 +359,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim6_priv = struct stm32wl5_tim_priv_s stm32wl5_tim7_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -368,8 +368,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim7_priv = struct stm32wl5_tim_priv_s stm32wl5_tim8_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -377,8 +377,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim8_priv = struct stm32wl5_tim_priv_s stm32wl5_tim15_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -386,8 +386,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim15_priv = struct stm32wl5_tim_priv_s stm32wl5_tim16_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -395,8 +395,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim16_priv = struct stm32wl5_tim_priv_s stm32wl5_tim17_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -484,9 +484,9 @@ static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev, static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_EGR_OFFSET); + uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wl5_putreg16(dev, STM32WL5_GTIM_EGR_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -495,10 +495,10 @@ static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev) static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET); + uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -507,9 +507,9 @@ static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev) static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET); + uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -523,7 +523,7 @@ static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev) { - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_DISABLED; + ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32wl5_tim_disable(dev); } @@ -541,7 +541,7 @@ static void stm32wl5_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32WL5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32wl5_configgpio(cfg); } @@ -567,13 +567,13 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32WL5_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32WL5_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32WL5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -582,19 +582,19 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32WL5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32WL5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32WL5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32WL5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32WL5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -603,7 +603,7 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, break; - case STM32WL5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -612,15 +612,15 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, } stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32WL5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM1_BASE || - ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM8_BASE) + if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32wl5_modifyreg16(dev, STM32WL5_ATIM_BDTR_OFFSET, + stm32wl5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -657,66 +657,66 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -747,7 +747,7 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, prescaler = 0xffff; } - stm32wl5_putreg16(dev, STM32WL5_GTIM_PSC_OFFSET, prescaler); + stm32wl5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32wl5_tim_enable(dev); return prescaler; @@ -772,64 +772,64 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -839,7 +839,7 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wl5_getreg16(dev, STM32WL5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32wl5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -851,7 +851,7 @@ static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wl5_putreg32(dev, STM32WL5_GTIM_ARR_OFFSET, period); + stm32wl5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -861,7 +861,7 @@ static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wl5_getreg32 (dev, STM32WL5_GTIM_ARR_OFFSET); + return stm32wl5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -871,7 +871,7 @@ static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev) static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wl5_getreg32(dev, STM32WL5_GTIM_CNT_OFFSET); + uint32_t counter = stm32wl5_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -881,10 +881,10 @@ static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -908,7 +908,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WL5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -921,7 +921,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CCER_OFFSET); + ccer_val = stm32wl5_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -929,13 +929,13 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32WL5_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32WL5_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32WL5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -944,12 +944,12 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32WL5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32WL5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32WL5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -961,7 +961,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32WL5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -976,21 +976,21 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32WL5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32wl5_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32wl5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CCER_OFFSET, ccer_val); + stm32wl5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1023,7 +1023,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1056,7 +1056,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1089,7 +1089,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1121,7 +1121,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1154,7 +1154,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1187,7 +1187,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1220,7 +1220,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1253,7 +1253,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1305,19 +1305,19 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR1_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR2_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR3_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR4_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1339,16 +1339,16 @@ static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR1_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR2_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR3_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR4_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1369,66 +1369,66 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: - vectorno = STM32WL5_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: - vectorno = STM32WL5_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: - vectorno = STM32WL5_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: - vectorno = STM32WL5_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: - vectorno = STM32WL5_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: - vectorno = STM32WL5_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: - vectorno = STM32WL5_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: - vectorno = STM32WL5_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: - vectorno = STM32WL5_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: - vectorno = STM32WL5_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: - vectorno = STM32WL5_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1461,7 +1461,7 @@ static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1472,7 +1472,7 @@ static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1481,7 +1481,7 @@ static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source) { - stm32wl5_putreg16(dev, STM32WL5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32wl5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1491,7 +1491,7 @@ static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source) static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, int source) { - uint16_t regval = stm32wl5_getreg16(dev, STM32WL5_GTIM_SR_OFFSET); + uint16_t regval = stm32wl5_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1514,76 +1514,76 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) #ifdef CONFIG_STM32WL5_TIM1 case 1: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim1_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32WL5_TIM2 case 2: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim2_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32WL5_TIM3 case 3: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim3_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32WL5_TIM4 case 4: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim4_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32WL5_TIM5 case 5: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim5_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32WL5_TIM6 case 6: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim6_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32WL5_TIM7 case 7: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim7_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32WL5_TIM8 case 8: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim8_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32WL5_TIM15 case 15: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim15_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32WL5_TIM16 case 16: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim16_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32WL5_TIM17 case 17: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim17_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1593,7 +1593,7 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32WL5_TIM_MODE_UNUSED) + if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1619,67 +1619,67 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1689,7 +1689,7 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_UNUSED; + ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.h b/arch/arm/src/stm32wl5/stm32wl5_tim.h index 9826600b87ab0..5329205535571 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.h @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32WL5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32WL5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32WL5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32WL5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32WL5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32WL5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32WL5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32WL5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32WL5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32WL5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32WL5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32WL5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32WL5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32WL5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32wl5_tim_dev_s enum stm32wl5_tim_mode_e { - STM32WL5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32WL5_TIM_MODE_MASK = 0x0310, - STM32WL5_TIM_MODE_DISABLED = 0x0000, - STM32WL5_TIM_MODE_UP = 0x0100, - STM32WL5_TIM_MODE_DOWN = 0x0110, - STM32WL5_TIM_MODE_UPDOWN = 0x0200, - STM32WL5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32WL5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32WL5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32WL5_TIM_MODE_CK_EXT = 0x0800, - STM32WL5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32WL5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32WL5_TIM_MODE_CK_CH1 = 0x0001, - STM32WL5_TIM_MODE_CK_CH2 = 0x0002, - STM32WL5_TIM_MODE_CK_CH3 = 0x0003, - STM32WL5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,22 +118,22 @@ enum stm32wl5_tim_mode_e enum stm32wl5_tim_channel_e { - STM32WL5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32WL5_TIM_CH_POLARITY_POS = 0x00, - STM32WL5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32WL5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32WL5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32WL5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif }; diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c index 572c4c95c218c..10c2a3c324334 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c @@ -52,17 +52,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_TIM1_RES 16 -#define STM32WL5_TIM2_RES 32 -#define STM32WL5_TIM3_RES 16 -#define STM32WL5_TIM4_RES 16 -#define STM32WL5_TIM5_RES 32 -#define STM32WL5_TIM6_RES 16 -#define STM32WL5_TIM7_RES 16 -#define STM32WL5_TIM8_RES 16 -#define STM32WL5_TIM15_RES 16 -#define STM32WL5_TIM16_RES 16 -#define STM32WL5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -122,7 +122,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -130,7 +130,7 @@ static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -138,7 +138,7 @@ static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif @@ -146,7 +146,7 @@ static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif @@ -154,7 +154,7 @@ static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif @@ -162,7 +162,7 @@ static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif @@ -170,7 +170,7 @@ static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif @@ -178,7 +178,7 @@ static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif @@ -186,7 +186,7 @@ static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif @@ -194,7 +194,7 @@ static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -202,7 +202,7 @@ static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg) (struct stm32wl5_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32WL5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32WL5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); - STM32WL5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_DISABLED); - STM32WL5_TIM_DISABLEINT(priv->tim, 0); - STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32WL5_TIM_GETCLOCK(priv->tim); - period = STM32WL5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000)? 1: (clock / 1000000); - status->timeleft = (timeout - STM32WL5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32WL5_TIM_SETCLOCK(priv->tim, freq); - STM32WL5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32WL5_TIM_SETCLOCK(priv->tim, 1000000); - STM32WL5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); - STM32WL5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32WL5_TIM_DISABLEINT(priv->tim, 0); - STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c index c4238fbf26827..070fbc8b74506 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c @@ -62,9 +62,9 @@ #undef CONFIG_STM32WL5_SYSTICK_HCLKd8 #ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -138,7 +138,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32WL5_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL); + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL); /* Enable SysTick interrupts */ @@ -147,5 +147,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32WL5_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.c b/arch/arm/src/stm32wl5/stm32wl5_uid.c index b8fa93730bf10..311458d7adb11 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.c +++ b/arch/arm/src/stm32wl5/stm32wl5_uid.c @@ -44,7 +44,7 @@ #include "hardware/stm32wl5_memorymap.h" #include "stm32wl5_uid.h" -#ifdef STM32WL5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -56,8 +56,8 @@ void stm32wl5_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32WL5_SYSMEM_UID)+i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID)+i); } } -#endif /* STM32WL5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/boards/arm/stm32f7/common/src/stm32_spitest.c b/boards/arm/stm32f7/common/src/stm32_spitest.c index f82b9b8fe645e..51bf2d63ca679 100644 --- a/boards/arm/stm32f7/common/src/stm32_spitest.c +++ b/boards/arm/stm32f7/common/src/stm32_spitest.c @@ -127,7 +127,7 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI1 to STM32F7_SPI1_FREQ and mode */ + /* Default SPI1 to STM32_SPI1_FREQ and mode */ SPI_SETFREQUENCY(g_spi1, CONFIG_STM32F7_SPI1_TEST_FREQ); SPI_SETBITS(g_spi1, CONFIG_STM32F7_SPI1_TEST_BITS); @@ -145,7 +145,7 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI2 to STM32F7_SPI2_FREQ and mode */ + /* Default SPI2 to STM32_SPI2_FREQ and mode */ SPI_SETFREQUENCY(g_spi2, CONFIG_STM32F7_SPI2_TEST_FREQ); SPI_SETBITS(g_spi2, CONFIG_STM32F7_SPI2_TEST_BITS); @@ -163,7 +163,7 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI3 to STM32F7_SPI3_FREQ and mode */ + /* Default SPI3 to STM32_SPI3_FREQ and mode */ SPI_SETFREQUENCY(g_spi3, CONFIG_STM32F7_SPI3_TEST_FREQ); SPI_SETBITS(g_spi3, CONFIG_STM32F7_SPI3_TEST_BITS); diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c index 11dab91d01c85..96deea3ee989f 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32F7_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32F7_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c index b9a578268f703..04b76397fdf01 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c index 76e270d40d32d..7f79bebc84d67 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32F7_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32F7_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c index e575a7f653d4b..7834ac832df6b 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c index d8c2ca1239b66..bf7d56c0c6b98 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32F7_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32F7_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c index d1c7ab99d2d11..31431f9d53df7 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index b390498974974..0cd3f2c56243b 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -152,8 +152,8 @@ /* SAIx input frequency = 25 / M * N / Q / P * 25000000 / 25 * 192 / 2 / 1 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c index 774f9204fb621..666181b3eb88e 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c @@ -61,7 +61,7 @@ # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 7 +#if STM32_NGPIO < 7 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c index 26ee7b72fd32f..f0c45df93e30a 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c @@ -47,7 +47,7 @@ # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 8 +#if STM32_NGPIO < 8 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index 9f5fb71fe13a2..2b1cfc1a9f922 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -158,8 +158,8 @@ * 25000000 / 25 * 384 / 2 / 8 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c index a73495f2e0c29..25d4604116ba3 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c @@ -47,7 +47,7 @@ # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 6 +#if STM32_NGPIO < 6 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h index 11ff18fb03729..d68741a262085 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/include/board.h +++ b/boards/arm/stm32h5/nucleo-h563zi/include/board.h @@ -132,7 +132,7 @@ #define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FRQ / 10) /* 48 MHz */ /* Use PLL3Q (48 MHz) for USB - more stable than HSI48 */ -#define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK +#define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK #endif /* CONFIG_STM32H5_USBFS_HOST */ @@ -186,18 +186,18 @@ /* Enable CLK48; get it from HSI48 */ #if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG) -# define STM32H5_USE_CLK48 1 +# define STM32_USE_CLK48 1 #endif #if defined(CONFIG_STM32H5_USBFS) -# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK -# define STM32H5_HSI48_SYNCSRC SYNCSRC_USB +# define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK +# define STM32_HSI48_SYNCSRC SYNCSRC_USB #else -# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif #if defined(CONFIG_STM32H5_RNG) -# define STM32H5_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK +# define STM32_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK #endif /* Enable LSE (for the RTC) */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h index 3782cd800783c..47a7f317e0d2f 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h @@ -56,20 +56,20 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) * (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -85,13 +85,13 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -130,7 +130,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -225,7 +225,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -235,13 +235,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -255,72 +255,72 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1, when - * NOT define STM32L4_RCC_CFGR_PPRE1 as RCC_CFGR_PPRE1_HCLK. + * NOT define STM32_RCC_CFGR_PPRE1 as RCC_CFGR_PPRE1_HCLK. */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM3_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM4_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM5_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM6_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM7_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_LPTIM1_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_LPTIM2_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_LPTIM1_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_LPTIM2_CLKIN STM32_PCLK1_FREQUENCY /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM8_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM15_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM16_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM17_CLKIN STM32L4_PCLK2_FREQUENCY +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM8_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -335,7 +335,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -343,78 +343,78 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -422,71 +422,71 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -495,19 +495,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32L4_APB1_TIM2_CLKIN -#define BOARD_TIM3_FREQUENCY STM32L4_APB1_TIM3_CLKIN -#define BOARD_TIM4_FREQUENCY STM32L4_APB1_TIM4_CLKIN -#define BOARD_TIM5_FREQUENCY STM32L4_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY STM32L4_APB1_TIM6_CLKIN -#define BOARD_TIM7_FREQUENCY STM32L4_APB1_TIM7_CLKIN -#define BOARD_TIM8_FREQUENCY STM32L4_APB2_TIM8_CLKIN -#define BOARD_TIM15_FREQUENCY STM32L4_APB2_TIM15_CLKIN -#define BOARD_TIM16_FREQUENCY STM32L4_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32L4_APB2_TIM17_CLKIN -#define BOARD_LPTIM1_FREQUENCY STM32L4_APB1_LPTIM1_CLKIN -#define BOARD_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN +#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN +#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN +#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN +#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN +#define BOARD_TIM15_FREQUENCY STM32_APB2_TIM15_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN +#define BOARD_LPTIM1_FREQUENCY STM32_APB1_LPTIM1_CLKIN +#define BOARD_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN /**************************************************************************** * Public Data @@ -534,4 +534,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARMSTM32L4__B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK */ +#endif /* __BOARDS_ARMSTM32__B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/board.h b/boards/arm/stm32l4/nucleo-l432kc/include/board.h index cc2f750933f9c..8b8519497ca87 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/board.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/board.h @@ -265,7 +265,7 @@ */ #if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) -# define STM32L4_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN +# define STM32_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN #endif #if 1 diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h index bc2cd77d6dde7..cacbf3ea929cd 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h @@ -57,20 +57,20 @@ * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL * configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) * (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -86,11 +86,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -127,7 +127,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -216,7 +216,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -226,13 +226,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -246,45 +246,45 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -293,16 +293,16 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -311,9 +311,9 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -321,7 +321,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -329,59 +329,59 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -390,14 +390,14 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -406,16 +406,16 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -423,74 +423,74 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -500,14 +500,14 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index 63bcbcb47b980..ad672643696a8 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -336,7 +336,7 @@ static void tim6_handler(void) /* TODO: Software update */ - STM32L4_TIM_ACKINT(tim, ATIM_SR_UIF); + STM32_TIM_ACKINT(tim, ATIM_SR_UIF); } /**************************************************************************** @@ -368,12 +368,12 @@ static int spwm_tim6_setup(struct spwm_s *spwm) freq = spwm->samples * spwm->waveform_freq; - STM32L4_TIM_SETFREQ(tim, freq); - STM32L4_TIM_ENABLE(tim); + STM32_TIM_SETFREQ(tim, freq); + STM32_TIM_ENABLE(tim); /* Attach TIM6 ram vector */ - ret = arm_ramvec_attach(STM32L4_IRQ_TIM6, tim6_handler); + ret = arm_ramvec_attach(STM32_IRQ_TIM6, tim6_handler); if (ret < 0) { printf("ERROR: arm_ramvec_attach failed: %d\n", ret); @@ -383,7 +383,7 @@ static int spwm_tim6_setup(struct spwm_s *spwm) /* Set the priority of the TIM6 interrupt vector */ - ret = up_prioritize_irq(STM32L4_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); + ret = up_prioritize_irq(STM32_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); if (ret < 0) { printf("ERROR: up_prioritize_irq failed: %d\n", ret); @@ -407,8 +407,8 @@ static int spwm_tim6_start(struct spwm_s *spwm) /* Enable the timer interrupt at the NVIC and at TIM6 */ - up_enable_irq(STM32L4_IRQ_TIM6); - STM32L4_TIM_ENABLEINT(tim, BTIM_DIER_UIE); + up_enable_irq(STM32_IRQ_TIM6); + STM32_TIM_ENABLEINT(tim, BTIM_DIER_UIE); return OK; } @@ -423,8 +423,8 @@ static int spwm_tim6_stop(struct spwm_s *spwm) /* Disable the timer interrupt at the NVIC and at TIM6 */ - up_disable_irq(STM32L4_IRQ_TIM6); - STM32L4_TIM_DISABLEINT(tim, BTIM_DIER_UIE); + up_disable_irq(STM32_IRQ_TIM6); + STM32_TIM_DISABLEINT(tim, BTIM_DIER_UIE); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h index 0dd3430e3bda1..55c553e492796 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h @@ -44,16 +44,16 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -69,9 +69,9 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #if 1 # define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */ @@ -85,7 +85,7 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -125,7 +125,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -221,7 +221,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -232,55 +232,55 @@ * want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ 0 -#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from HSI48 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -289,17 +289,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -308,9 +308,9 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -318,7 +318,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -326,82 +326,82 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -409,75 +409,75 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ 0 -#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from HSI48 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -487,17 +487,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h index 4ab69149c5d59..08cecef41509b 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h @@ -65,14 +65,14 @@ /* How many SPI modules does this chip support? */ -#if STM32L4_NSPI < 1 +#if STM32_NSPI < 1 # undef CONFIG_STM32L4_SPI1 # undef CONFIG_STM32L4_SPI2 # undef CONFIG_STM32L4_SPI3 -#elif STM32L4_NSPI < 2 +#elif STM32_NSPI < 2 # undef CONFIG_STM32L4_SPI2 # undef CONFIG_STM32L4_SPI3 -#elif STM32L4_NSPI < 3 +#elif STM32_NSPI < 3 # undef CONFIG_STM32L4_SPI3 #endif diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h index 39623ef7e569d..48a4b158b7d79 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h @@ -55,16 +55,16 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -80,11 +80,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -124,7 +124,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -219,7 +219,7 @@ * as per comment above HSI) . */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -230,13 +230,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -250,68 +250,68 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -326,7 +326,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -334,81 +334,81 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -416,74 +416,74 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -492,19 +492,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index 7aa8a010e5acd..30d1bcd22eb31 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -55,20 +55,20 @@ * LSE: 32.768 kHz */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */ -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */ +#define STM32_LSE_FREQUENCY 32768 #define MSI_CLOCK_CONFIG #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI +#define STM32_BOARD_USEHSI /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -79,13 +79,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -99,71 +99,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -174,11 +174,11 @@ #elif defined(HSE_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSE +#define STM32_BOARD_USEHSE /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 8 MHz / 1 * 20 / 2 = 80 MHz @@ -189,13 +189,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -209,71 +209,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -284,12 +284,12 @@ #elif defined(MSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEMSI -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 40 / 2 = 80 MHz @@ -300,13 +300,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -320,71 +320,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -400,19 +400,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /* SDMMC dividers. * Note that slower clocking is required when DMA is disabled diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c index 83b338839af64..0ad0e10887dc2 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32L4_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32L4_ADC3 #endif -#if STM32L4_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32L4_ADC2 #endif -#if STM32L4_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32L4_ADC1 #endif diff --git a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h index 7c5ffc6ddfb78..4ecb2c970fba4 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h @@ -37,16 +37,16 @@ /* System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -62,11 +62,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -106,7 +106,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -165,7 +165,7 @@ * as per comment above HSI) . */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -176,13 +176,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -196,87 +196,87 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h index ce9c293eddccf..d73085956e07c 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h @@ -59,9 +59,9 @@ * LSE - not installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul @@ -79,13 +79,13 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -96,13 +96,13 @@ * may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -116,65 +116,65 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 1 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -185,76 +185,76 @@ /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Disable LSE (for the RTC) */ -#undef STM32L4_USE_LSE +#undef STM32_USE_LSE /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -263,19 +263,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c index 328eb3c834a47..bf16becc8f37e 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c @@ -59,115 +59,115 @@ void stm32l4_board_clockconfig(void) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -181,18 +181,18 @@ void stm32l4_board_clockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -204,7 +204,7 @@ void stm32l4_board_clockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h index d336955276ea1..65da2b2da59cb 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h @@ -51,9 +51,9 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul @@ -75,13 +75,13 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -91,13 +91,13 @@ * may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -111,42 +111,42 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 1 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -155,17 +155,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -174,14 +174,14 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -189,78 +189,78 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -268,71 +268,71 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -343,19 +343,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c index 5257fe5408b0a..b2a93e9b22b98 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c @@ -59,115 +59,115 @@ void stm32l4_board_clockconfig(void) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -181,18 +181,18 @@ void stm32l4_board_clockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -204,7 +204,7 @@ void stm32l4_board_clockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index ddc8d01fb149e..bb33ba52a60d4 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -53,13 +53,13 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 -#define STM32L4_HSE_FREQUENCY 16000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 16000000ul -#define STM32L4_SYSCLK_FREQUENCY 120000000ul -#define BOARD_AHB_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_SYSCLK_FREQUENCY 120000000ul +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY /* Higher SYSCLK requires more flash wait states. */ @@ -81,11 +81,11 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz @@ -96,13 +96,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -116,47 +116,47 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* AHB clock (HCLK) is SYSCLK (120 MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (120 MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -165,17 +165,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (120 MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -184,18 +184,18 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz @@ -206,13 +206,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -226,73 +226,73 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 60 / 2 = 120 MHz @@ -303,13 +303,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -323,62 +323,62 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif /* clock selection */ @@ -388,19 +388,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c index e17b57ba7fddf..cfd2d047792ef 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c @@ -59,115 +59,115 @@ void stm32l4_board_clockconfig(void) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -181,18 +181,18 @@ void stm32l4_board_clockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -204,7 +204,7 @@ void stm32l4_board_clockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 1cea1f1689eea..86a474e5a6448 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -45,16 +45,16 @@ * * System Clock source : PLL (MSI) * SYSCLK(Hz) : 110000000 Determined by PLL configuration - * HCLK(Hz) : 110000000 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz) - * AHB Prescaler : 1 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz) - * APB1 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE1) (Max 110MHz) - * APB2 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE2) (Max 110MHz) + * HCLK(Hz) : 110000000 (STM32_RCC_CFGR_HPRE) (Max 110MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 110MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 110MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 110MHz) * MSI Frequency(Hz) : 4000000 (nominal) - * PLLM : 1 (STM32L5_PLLCFG_PLLM) - * PLLN : 55 (STM32L5_PLLCFG_PLLN) - * PLLP : 0 (STM32L5_PLLCFG_PLLP) - * PLLQ : 0 (STM32L5_PLLCFG_PLLQ) - * PLLR : 2 (STM32L5_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 55 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * Flash Latency(WS) : 5 */ @@ -65,84 +65,84 @@ * LSE - 32.768 kHz installed */ -#define STM32L5_HSI_FREQUENCY 16000000ul -#define STM32L5_LSI_FREQUENCY 32000 -#define STM32L5_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L5_BOARD_USEMSI 1 -#define STM32L5_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* prescaler common to all PLL inputs */ -#define STM32L5_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L5_PLLCFG_PLLN RCC_PLLCFG_PLLN(55) -#define STM32L5_PLLCFG_PLLP 0 -#undef STM32L5_PLLCFG_PLLP_ENABLED -#define STM32L5_PLLCFG_PLLQ 0 -#undef STM32L5_PLLCFG_PLLQ_ENABLED -#define STM32L5_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L5_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(55) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L5_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L5_PLLSAI1CFG_PLLP 0 -#undef STM32L5_PLLSAI1CFG_PLLP_ENABLED -#define STM32L5_PLLSAI1CFG_PLLQ 0 -#undef STM32L5_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L5_PLLSAI1CFG_PLLR 0 -#undef STM32L5_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L5_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L5_PLLSAI2CFG_PLLP 0 -#undef STM32L5_PLLSAI2CFG_PLLP_ENABLED -#define STM32L5_PLLSAI2CFG_PLLR 0 -#undef STM32L5_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L5_SYSCLK_FREQUENCY 110000000ul +#define STM32_SYSCLK_FREQUENCY 110000000ul /* Enable CLK48; get it from HSI48 */ #if defined(CONFIG_STM32L5_USBFS) || defined(CONFIG_STM32L5_RNG) -# define STM32L5_USE_CLK48 1 -# define STM32L5_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L5_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC and for MSI autotrimming) */ -#define STM32L5_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L5_PCLK1_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L5_APB1_TIM2_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM3_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM4_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM5_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM6_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM7_CLKIN (STM32L5_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L5_APB2_TIM1_CLKIN (STM32L5_PCLK2_FREQUENCY) -#define STM32L5_APB2_TIM15_CLKIN (STM32L5_PCLK2_FREQUENCY) -#define STM32L5_APB2_TIM16_CLKIN (STM32L5_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -150,17 +150,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ diff --git a/boards/arm/stm32l5/stm32l562e-dk/include/board.h b/boards/arm/stm32l5/stm32l562e-dk/include/board.h index 395095c7b9c3e..256110d074311 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/include/board.h +++ b/boards/arm/stm32l5/stm32l562e-dk/include/board.h @@ -67,15 +67,15 @@ * LSE - 32.768 kHz installed */ -#define STM32L5_HSI_FREQUENCY 16000000ul -#define STM32L5_LSI_FREQUENCY 32000 -#define STM32L5_MSI_FREQUENCY 4000000ul -#define STM32L5_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_MSI_FREQUENCY 4000000ul +#define STM32_LSE_FREQUENCY 32768 -#define STM32L5_SYSCLK_FREQUENCY 110000000ul -#define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY -#define STM32L5_PCLK1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_SYSCLK_FREQUENCY 110000000ul +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -83,17 +83,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c index 2d246c3377f45..5cde87263ab16 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c @@ -118,7 +118,7 @@ int stm32_bringup(void) return -1; } -#if defined(STM32U5_I2C2) +#if defined(STM32_I2C2) i2c2_m = stm32_i2cbus_initialize(2); if (i2c2_m == NULL) { diff --git a/boards/arm/stm32wb/flipperzero/include/board.h b/boards/arm/stm32wb/flipperzero/include/board.h index e00cf8ce7ae94..bb948a3f3c631 100644 --- a/boards/arm/stm32wb/flipperzero/include/board.h +++ b/boards/arm/stm32wb/flipperzero/include/board.h @@ -84,13 +84,13 @@ /* LCD */ -#define STM32WB_LCD_SPINO 2 /* SPI2 */ +#define STM32_LCD_SPINO 2 /* SPI2 */ -#define STM32WB_LCD_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN11) -#define STM32WB_LCD_RST (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_RST (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0) -#define STM32WB_LCD_A0 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_A0 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1) /**************************************************************************** diff --git a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h index ce6734fd5a602..cff810a1b03b8 100644 --- a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h +++ b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h @@ -51,10 +51,10 @@ * HSI48 - 48 MHz fine-granularity trimmable RC with CRS */ -#define STM32WB_HSI_FREQUENCY 16000000ul -#define STM32WB_LSI_FREQUENCY 32000 -#define STM32WB_LSE_FREQUENCY 32768 -#define STM32WB_HSE_FREQUENCY 32000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 32000000ul /* XXX there needs to be independent selections for the System Clock Mux and * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL @@ -71,145 +71,145 @@ #endif #if 0 -# define STM32WB_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ +# define STM32_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ #elif 1 -# define STM32WB_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ +# define STM32_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ #endif #if defined(HSI_CLOCK_CONFIG) -#define STM32WB_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((16MHz / 1) * 8) / 2) = 64MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from HSI48 */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -#define STM32WB_HSI48_SYNCSRC SYNCSRC_LSE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +#define STM32_HSI48_SYNCSRC SYNCSRC_LSE /* Enable LSE oscillator, used automatically trim the HSI48, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32WB_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 2 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((32MHz / 2) * 12) / 3) = 64MHz * And the Q output is set as (((32MHz / 2) * 12) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable LSE (for the RTC) */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI */ -#define STM32WB_BOARD_USEMSI 1 +#define STM32_BOARD_USEMSI 1 -#define STM32WB_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((4MHz / 1) * 48) / 3) = 64MHz * And the Q output is set as (((4MHz / 1) * 48) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #endif /* AHB clock (HCLK) is SYSCLK (64MHz) */ -#define BOARD_AHB_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32WB_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32WB_HCLK_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* CPU2 clock (HCLK2) is SYSCLK/2 (32MHz) */ -#define STM32WB_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 +#define STM32_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 /* AHB4 clock (HCLK4) is SYSCLK (64MHz) */ -#define STM32WB_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 +#define STM32_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 /* APB1 clock (PCLK1) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 -#define STM32WB_PCLK1_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* APB2 clock (PCLK2) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 -#define STM32WB_PCLK2_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timer Frequencies, if APB prescaler is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -218,18 +218,18 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32WB_APB1_TIM2_CLKIN (1 * STM32WB_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32WB_APB2_TIM1_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM16_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM17_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM1_FREQUENCY STM32WB_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32WB_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN /* Higher SYSCLK requires more flash wait states. */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c index ed22e8917b2cb..4eea343833db8 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c @@ -83,23 +83,23 @@ static struct st7565_lcd_s g_st7565_dev = static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on) { - stm32wb_gpiowrite(STM32WB_LCD_RST, !on); + stm32wb_gpiowrite(STM32_LCD_RST, !on); } static void stm32wb_st7565_select(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32WB_LCD_CS, 0); + stm32wb_gpiowrite(STM32_LCD_CS, 0); } static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32WB_LCD_CS, 1); + stm32wb_gpiowrite(STM32_LCD_CS, 1); } static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd) { - stm32wb_gpiowrite(STM32WB_LCD_A0, !cmd); + stm32wb_gpiowrite(STM32_LCD_A0, !cmd); } static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, @@ -124,14 +124,14 @@ static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) int board_lcd_initialize(void) { - stm32wb_configgpio(STM32WB_LCD_RST); - stm32wb_configgpio(STM32WB_LCD_A0); + stm32wb_configgpio(STM32_LCD_RST); + stm32wb_configgpio(STM32_LCD_A0); - g_spidev = stm32wb_spibus_initialize(STM32WB_LCD_SPINO); + g_spidev = stm32wb_spibus_initialize(STM32_LCD_SPINO); if (!g_spidev) { - lcderr("ERROR: Failed to initialize SPI port %d\n", STM32WB_LCD_SPINO); + lcderr("ERROR: Failed to initialize SPI port %d\n", STM32_LCD_SPINO); return -ENODEV; } @@ -139,9 +139,9 @@ int board_lcd_initialize(void) g_spidev->ops->setbits(g_spidev, 8); g_spidev->ops->setfrequency(g_spidev, 1000000); - stm32wb_gpiowrite(STM32WB_LCD_RST, 0); + stm32wb_gpiowrite(STM32_LCD_RST, 0); up_mdelay(1); - stm32wb_gpiowrite(STM32WB_LCD_RST, 1); + stm32wb_gpiowrite(STM32_LCD_RST, 1); return OK; } @@ -156,12 +156,12 @@ struct lcd_dev_s *board_lcd_getdev(int lcddev) if (!g_lcddev) { lcderr("ERROR: Failed to bind SPI port %d to LCD %d\n", - STM32WB_LCD_SPINO, lcddev); + STM32_LCD_SPINO, lcddev); } else { lcdinfo("SPI port %d bound to LCD %d\n", - STM32WB_LCD_SPINO, lcddev); + STM32_LCD_SPINO, lcddev); /* And turn the LCD on (CONFIG_LCD_MAXPOWER should be 1) */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c index a655b0f4f624c..cfb057dae1e67 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c @@ -55,7 +55,7 @@ void weak_function stm32wb_spidev_initialize(void) */ #ifdef CONFIG_LCD_ST7565 - stm32wb_configgpio(STM32WB_LCD_CS); /* ST7565 chip select */ + stm32wb_configgpio(STM32_LCD_CS); /* ST7565 chip select */ #endif } @@ -91,7 +91,7 @@ void stm32wb_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) #ifdef CONFIG_LCD_ST7565 if (devid == SPIDEV_DISPLAY(0)) { - stm32wb_gpiowrite(STM32WB_LCD_CS, !selected); + stm32wb_gpiowrite(STM32_LCD_CS, !selected); } #endif } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h index d48843b2736c3..a4f9d490a7beb 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h @@ -52,10 +52,10 @@ * HSI48 - 48 MHz fine-granularity trimmable RC with CRS */ -#define STM32WB_HSI_FREQUENCY 16000000ul -#define STM32WB_LSI_FREQUENCY 32000 -#define STM32WB_LSE_FREQUENCY 32768 -#define STM32WB_HSE_FREQUENCY 32000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 32000000ul /* XXX there needs to be independent selections for the System Clock Mux and * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL @@ -72,145 +72,145 @@ #endif #if 0 -# define STM32WB_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ +# define STM32_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ #elif 1 -# define STM32WB_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ +# define STM32_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ #endif #if defined(HSI_CLOCK_CONFIG) -#define STM32WB_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((16MHz / 1) * 8) / 2) = 64MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from HSI48 */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -#define STM32WB_HSI48_SYNCSRC SYNCSRC_LSE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +#define STM32_HSI48_SYNCSRC SYNCSRC_LSE /* Enable LSE oscillator, used automatically trim the HSI48, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32WB_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 2 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((32MHz / 2) * 12) / 3) = 64MHz * And the Q output is set as (((32MHz / 2) * 12) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable LSE (for the RTC) */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI */ -#define STM32WB_BOARD_USEMSI 1 +#define STM32_BOARD_USEMSI 1 -#define STM32WB_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((4MHz / 1) * 48) / 3) = 64MHz * And the Q output is set as (((4MHz / 1) * 48) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #endif /* AHB clock (HCLK) is SYSCLK (64MHz) */ -#define BOARD_AHB_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32WB_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32WB_HCLK_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* CPU2 clock (HCLK2) is SYSCLK/2 (32MHz) */ -#define STM32WB_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 +#define STM32_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 /* AHB4 clock (HCLK4) is SYSCLK (64MHz) */ -#define STM32WB_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 +#define STM32_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 /* APB1 clock (PCLK1) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 -#define STM32WB_PCLK1_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* APB2 clock (PCLK2) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 -#define STM32WB_PCLK2_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timer Frequencies, if APB prescaler is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -219,18 +219,18 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32WB_APB1_TIM2_CLKIN (1 * STM32WB_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32WB_APB2_TIM1_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM16_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM17_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM1_FREQUENCY STM32WB_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32WB_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN /* Higher SYSCLK requires more flash wait states. */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h index 673b0232ecb88..b00acf8b0d20c 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h @@ -36,72 +36,72 @@ /* nucleo-wl55jc has installed 32Mhz HSE oscillator */ -#define STM32WL5_XTAL_FREQ 32000000ul +#define STM32_XTAL_FREQ 32000000ul /* Use the HSE */ -#define STM32WL5_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* HSE source is a TCXO crystal which needs to be first powered on */ -#define STM32WL5_BOARD_USETCXO +#define STM32_BOARD_USETCXO /* Prescaler common to all PLL inputs */ -#define STM32WL5_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */ +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */ /* 'main' PLL config; we use this to generate our system clock */ /* disable unused pll clocks */ -#define STM32WL5_PLLCFG_PLLP 0 -#undef STM32WL5_PLLCFG_PLLP_ENABLED -#define STM32WL5_PLLCFG_PLLQ 0 -#undef STM32WL5_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED /* further multiplicate source for system clock */ -#define STM32WL5_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */ -#define STM32WL5_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */ -#define STM32WL5_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */ +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */ +#define STM32_PLLCFG_PLLR_ENABLED /* Resulting system clock is 48MHz */ -#define STM32WL5_SYSCLK_FREQUENCY 48000000ul +#define STM32_SYSCLK_FREQUENCY 48000000ul /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32WL5_HCLK_FREQUENCY STM32WL5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the HCLK3 divisor (for flash and sram2) */ -#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */ -#define STM32WL5_HCLK3_FREQUENCY STM32WL5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */ +#define STM32_HCLK3_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32WL5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32WL5_PCLK1_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32WL5_APB1_TIM2_CLKIN (STM32WL5_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32WL5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32WL5_PCLK2_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32WL5_APB2_TIM1_CLKIN STM32WL5_PCLK2_FREQUENCY -#define STM32WL5_APB2_TIM16_CLKIN STM32WL5_PCLK2_FREQUENCY -#define STM32WL5_APB2_TIM17_CLKIN STM32WL5_PCLK2_FREQUENCY +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -109,13 +109,13 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM3_FREQUENCY STM32WL5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM3_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c index ec04c1555a604..16b1724823082 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c @@ -91,7 +91,7 @@ # warning "There is unused space on flash" #endif -#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE /**************************************************************************** * Private Definitions