t27 gen-verilog MAC contains * operator — R-SI-1 violation for TTSKY26b

[gHashTag]

Bug: t27c gen-verilog MAC output violates TTSKY26b CROWN R-SI-1 and is not synthesizable

Context

Attempting t27 language adoption track for TRI-1-GAMMA (TTSKY26b tapeout).
Generated file: gen/verilog/fpga/mac.v (SHA d96edaefc294ac56dc5ae73dbc81ec41240d02c1).
Source spec: specs/fpga/mac.t27.

Integration target: gHashTag/tt-trinity-gamma — replace one MAC slot with t27-generated Verilog.

---

Blocker 1 — R-SI-1: * operator present in synthesizable code

CROWN rule R-SI-1 mandates zero * operators in synthesizable RTL. The OpenLane autograder fails any run containing * outside comments.

Line	Code	Fix
42	reg [31:0] bit_pos = (index * 2);	→ index << 1
60	reg [31:0] bit_pos = (index * 2);	→ index << 1
155	reg [31:0] mat_idx = ((row * cols) + col);	→ shift-add (requires cols as power-of-2 param)

---

Blocker 2 — Not synthesizable: fails iverilog -g2005 with 30+ errors

The generated Verilog requires SystemVerilog features that are forbidden on this tapeout:

Root cause	Example line(s)
reg variable declarations with initializers inside begin..end blocks (SV only)	42, 60, 78–80, 107–108, 149, 151, 155, 206, 245, 247
Variable declaration in unnamed block (requires SV)	Throughout
Struct field access corruption: mac_unitsstatus instead of valid identifier	75, 76, 104, 130, 153, 198
Unresolved struct/array literals emitted as block comments, leaving dangling assignments	72, 89, 198
|| / && used instead of bitwise | / &	84, 87, 44
Orphan as; and u8; bare statements (cast artifact)	~246

iverilog error summary (truncated):

/tmp/t27_mac.v:42: error: Variable declaration assignments are only allowed at the module level.
/tmp/t27_mac.v:1: error: Variable declaration in unnamed block requires SystemVerilog.
/tmp/t27_mac.v:75: syntax error
/tmp/t27_mac.v:198: error: Malformed statement
... (30+ total errors, file fails to compile)

---

Expected Behaviour

t27c gen-verilog specs/fpga/mac.t27 should emit Verilog-2005 that:

1. Contains zero * operators in synthesizable code (use shifts / LUTs)
2. Compiles cleanly under iverilog -Wall -g2005
3. Uses flat register naming (no struct dot notation)
4. Resolves all struct/array literals to explicit assignments
5. Uses bitwise operators (|, &) not logical (||, &&) where appropriate

---

Impact

This blocks the t27 language adoption track for TTSKY26b production tapeout (deadline ~2026-06-15).
The chip uses SKY130A via TinyTapeout and the OpenLane runner auto-rejects any design with * in RTL.

---

Reproduction

gh api repos/gHashTag/t27/contents/gen/verilog/fpga/mac.v -H 'Accept: application/vnd.github.raw+json' > /tmp/t27_mac.v
grep -n '\*' /tmp/t27_mac.v | grep -v '//'   # shows R-SI-1 violations
iverilog -Wall -g2005 -o /dev/null /tmp/t27_mac.v  # 30+ errors

---

References

• TTSKY26b CROWN rule R-SI-1: no * in synthesizable RTL
• Target repo: gHashTag/tt-trinity-gamma
• Spec: gHashTag/t27/specs/fpga/mac.t27
• Generated SHA: d96edaefc294ac56dc5ae73dbc81ec41240d02c1