[FEATURE]: Added PARITY_ERROR output to RX module, code refactoring.

Author: jakubcabal

rtl/comp/uart_rx.vhd

@@ -16,34 +16,36 @@ entity UART_RX is
         PARITY_BIT  : string := "none" -- type of parity: "none", "even", "odd", "mark", "space"
     );
     Port (
-        CLK         : in  std_logic; -- system clock
-        RST         : in  std_logic; -- high active synchronous reset
+        CLK          : in  std_logic; -- system clock
+        RST          : in  std_logic; -- high active synchronous reset
         -- UART INTERFACE
-        UART_CLK_EN : in  std_logic; -- oversampling (16x) UART clock enable
-        UART_RXD    : in  std_logic; -- serial receive data
+        UART_CLK_EN  : in  std_logic; -- oversampling (16x) UART clock enable
+        UART_RXD     : in  std_logic; -- serial receive data
         -- USER DATA OUTPUT INTERFACE
-        DOUT        : out std_logic_vector(7 downto 0); -- output data received via UART
-        DOUT_VLD    : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid (is assert only for one clock cycle)
-        FRAME_ERROR : out std_logic  -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
+        DOUT         : out std_logic_vector(7 downto 0); -- output data received via UART
+        DOUT_VLD     : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid without errors (is assert only for one clock cycle)
+        FRAME_ERROR  : out std_logic; -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
+        PARITY_ERROR : out std_logic  -- when PARITY_ERROR = 1, parity bit was invalid (is assert only for one clock cycle)
     );
-end UART_RX;
+end entity;
 
-architecture FULL of UART_RX is
+architecture RTL of UART_RX is
 
     signal rx_clk_en          : std_logic;
     signal rx_ticks           : unsigned(3 downto 0);
-    signal rx_clk_divider_en  : std_logic;
     signal rx_data            : std_logic_vector(7 downto 0);
     signal rx_bit_count       : unsigned(2 downto 0);
-    signal rx_receiving_data  : std_logic;
     signal rx_parity_bit      : std_logic;
     signal rx_parity_error    : std_logic;
     signal rx_parity_check_en : std_logic;
-    signal rx_output_reg_en   : std_logic;
+    signal rx_done            : std_logic;
+    signal fsm_receiving      : std_logic;
+    signal fsm_databits       : std_logic;
+    signal fsm_stopbit        : std_logic;
 
     type state is (idle, startbit, databits, paritybit, stopbit);
-    signal rx_pstate : state;
-    signal rx_nstate : state;
+    signal fsm_pstate : state;
+    signal fsm_nstate : state;
 
 begin
 
@@ -54,7 +56,7 @@ begin
     uart_rx_clk_divider_p : process (CLK)
     begin
         if (rising_edge(CLK)) then
-            if (rx_clk_divider_en = '1') then
+            if (fsm_receiving = '1') then
                 if (UART_CLK_EN = '1') then
                     if (rx_ticks = "1111") then
                         rx_ticks <= (others => '0');
@@ -92,7 +94,7 @@ begin
         if (rising_edge(CLK)) then
             if (RST = '1') then
                 rx_bit_count <= (others => '0');
-            elsif (rx_clk_en = '1' AND rx_receiving_data = '1') then
+            elsif (rx_clk_en = '1' AND fsm_databits = '1') then
                 if (rx_bit_count = "111") then
                     rx_bit_count <= (others => '0');
                 else
@@ -109,7 +111,7 @@ begin
     uart_rx_data_shift_reg_p : process (CLK)
     begin
         if (rising_edge(CLK)) then
-            if (rx_clk_en = '1' AND rx_receiving_data = '1') then
+            if (rx_clk_en = '1' AND fsm_databits = '1') then
                 rx_data <= UART_RXD & rx_data(7 downto 1);
             end if;
         end if;
@@ -150,20 +152,19 @@ begin
     -- UART RECEIVER OUTPUT REGISTER
     -- -------------------------------------------------------------------------
 
+    rx_done <= rx_clk_en and fsm_stopbit;
+
     uart_rx_output_reg_p : process (CLK)
     begin
         if (rising_edge(CLK)) then
             if (RST = '1') then
-                DOUT_VLD <= '0';
-                FRAME_ERROR <= '0';
+                DOUT_VLD     <= '0';
+                FRAME_ERROR  <= '0';
+                PARITY_ERROR <= '0';
             else
-                if (rx_clk_en = '1' AND rx_output_reg_en = '1') then
-                    DOUT_VLD <= NOT rx_parity_error AND UART_RXD;
-                    FRAME_ERROR <= NOT UART_RXD;
-                else
-                    DOUT_VLD <= '0';
-                    FRAME_ERROR <= '0';
-                end if;
+                DOUT_VLD     <= rx_done and not rx_parity_error and UART_RXD;
+                FRAME_ERROR  <= rx_done and not UART_RXD;
+                PARITY_ERROR <= rx_done and rx_parity_error;
             end if;
         end if;
     end process;
@@ -177,84 +178,84 @@ begin
     begin
         if (rising_edge(CLK)) then
             if (RST = '1') then
-                rx_pstate <= idle;
+                fsm_pstate <= idle;
             else
-                rx_pstate <= rx_nstate;
+                fsm_pstate <= fsm_nstate;
             end if;
         end if;
     end process;
 
     -- NEXT STATE AND OUTPUTS LOGIC
-    process (rx_pstate, UART_RXD, rx_clk_en, rx_bit_count)
+    process (fsm_pstate, UART_RXD, rx_clk_en, rx_bit_count)
     begin
-        case rx_pstate is
+        case fsm_pstate is
 
             when idle =>
-                rx_output_reg_en  <= '0';
-                rx_receiving_data <= '0';
-                rx_clk_divider_en <= '0';
+                fsm_stopbit   <= '0';
+                fsm_databits  <= '0';
+                fsm_receiving <= '0';
 
                 if (UART_RXD = '0') then
-                    rx_nstate <= startbit;
+                    fsm_nstate <= startbit;
                 else
-                    rx_nstate <= idle;
+                    fsm_nstate <= idle;
                 end if;
 
             when startbit =>
-                rx_output_reg_en  <= '0';
-                rx_receiving_data <= '0';
-                rx_clk_divider_en <= '1';
+                fsm_stopbit   <= '0';
+                fsm_databits  <= '0';
+                fsm_receiving <= '1';
 
                 if (rx_clk_en = '1') then
-                    rx_nstate <= databits;
+                    fsm_nstate <= databits;
                 else
-                    rx_nstate <= startbit;
+                    fsm_nstate <= startbit;
                 end if;
 
             when databits =>
-                rx_output_reg_en  <= '0';
-                rx_receiving_data <= '1';
-                rx_clk_divider_en <= '1';
+                fsm_stopbit   <= '0';
+                fsm_databits  <= '1';
+                fsm_receiving <= '1';
 
                 if ((rx_clk_en = '1') AND (rx_bit_count = "111")) then
                     if (PARITY_BIT = "none") then
-                        rx_nstate <= stopbit;
+                        fsm_nstate <= stopbit;
                     else
-                        rx_nstate <= paritybit;
+                        fsm_nstate <= paritybit;
                     end if ;
                 else
-                    rx_nstate <= databits;
+                    fsm_nstate <= databits;
                 end if;
 
             when paritybit =>
-                rx_output_reg_en  <= '0';
-                rx_receiving_data <= '0';
-                rx_clk_divider_en <= '1';
+                fsm_stopbit   <= '0';
+                fsm_databits  <= '0';
+                fsm_receiving <= '1';
 
                 if (rx_clk_en = '1') then
-                    rx_nstate <= stopbit;
+                    fsm_nstate <= stopbit;
                 else
-                    rx_nstate <= paritybit;
+                    fsm_nstate <= paritybit;
                 end if;
 
             when stopbit =>
-                rx_output_reg_en  <= '1';
-                rx_receiving_data <= '0';
-                rx_clk_divider_en <= '1';
+                fsm_stopbit   <= '1';
+                fsm_databits  <= '0';
+                fsm_receiving <= '1';
 
                 if (rx_clk_en = '1') then
-                    rx_nstate <= idle;
+                    fsm_nstate <= idle;
                 else
-                    rx_nstate <= stopbit;
+                    fsm_nstate <= stopbit;
                 end if;
 
             when others =>
-                rx_output_reg_en  <= '0';
-                rx_receiving_data <= '0';
-                rx_clk_divider_en <= '0';
-                rx_nstate         <= idle;
+                fsm_stopbit   <= '0';
+                fsm_databits  <= '0';
+                fsm_receiving <= '0';
+                fsm_nstate    <= idle;
 
         end case;
     end process;
 
-end FULL;
+end architecture;

rtl/uart.vhd

@@ -55,40 +55,40 @@ entity UART is
     );
 end entity;
 
-architecture FULL of UART is
+architecture RTL of UART is
 
-    constant DIVIDER_VALUE    : integer  := CLK_FREQ/(16*BAUD_RATE);
-    constant CLK_CNT_WIDTH    : integer  := integer(ceil(log2(real(DIVIDER_VALUE))));
-    constant CLK_CNT_MAX      : unsigned := to_unsigned(DIVIDER_VALUE-1, CLK_CNT_WIDTH);
+    constant DIVIDER_VALUE : integer  := CLK_FREQ/(16*BAUD_RATE);
+    constant CLK_CNT_WIDTH : integer  := integer(ceil(log2(real(DIVIDER_VALUE))));
+    constant CLK_CNT_MAX   : unsigned := to_unsigned(DIVIDER_VALUE-1, CLK_CNT_WIDTH);
 
-    signal uart_clk_cnt       : unsigned(CLK_CNT_WIDTH-1 downto 0);
-    signal uart_clk_en        : std_logic;
-    signal uart_rxd_meta      : std_logic;
-    signal uart_rxd_synced    : std_logic;
-    signal uart_rxd_debounced : std_logic;
+    signal oversampling_clk_cnt : unsigned(CLK_CNT_WIDTH-1 downto 0);
+    signal oversampling_clk_en  : std_logic;
+    signal uart_rxd_meta        : std_logic;
+    signal uart_rxd_synced      : std_logic;
+    signal uart_rxd_debounced   : std_logic;
 
 begin
 
     -- -------------------------------------------------------------------------
-    --  UART CLOCK COUNTER AND CLOCK ENABLE FLAG
+    --  UART OVERSAMPLING (16X) CLOCK COUNTER AND CLOCK ENABLE FLAG
     -- -------------------------------------------------------------------------
 
-    uart_clk_cnt_p : process (CLK)
+    oversampling_clk_cnt_p : process (CLK)
     begin
         if (rising_edge(CLK)) then
             if (RST = '1') then
-                uart_clk_cnt <= (others => '0');
+                oversampling_clk_cnt <= (others => '0');
             else
-                if (uart_clk_en = '1') then
-                    uart_clk_cnt <= (others => '0');
+                if (oversampling_clk_en = '1') then
+                    oversampling_clk_cnt <= (others => '0');
                 else
-                    uart_clk_cnt <= uart_clk_cnt + 1;
+                    oversampling_clk_cnt <= oversampling_clk_cnt + 1;
                 end if;
             end if;
         end if;
     end process;
 
-    uart_clk_en <= '1' when (uart_clk_cnt = CLK_CNT_MAX) else '0';
+    oversampling_clk_en <= '1' when (oversampling_clk_cnt = CLK_CNT_MAX) else '0';
 
     -- -------------------------------------------------------------------------
     --  UART RXD CROSS DOMAIN CROSSING
@@ -131,15 +131,16 @@ begin
         PARITY_BIT  => PARITY_BIT
     )
     port map (
-        CLK         => CLK,
-        RST         => RST,
+        CLK          => CLK,
+        RST          => RST,
         -- UART INTERFACE
-        UART_CLK_EN => uart_clk_en,
-        UART_RXD    => uart_rxd_debounced,
+        UART_CLK_EN  => oversampling_clk_en,
+        UART_RXD     => uart_rxd_debounced,
         -- USER DATA OUTPUT INTERFACE
-        DOUT        => DOUT,
-        DOUT_VLD    => DOUT_VLD,
-        FRAME_ERROR => FRAME_ERROR
+        DOUT         => DOUT,
+        DOUT_VLD     => DOUT_VLD,
+        FRAME_ERROR  => FRAME_ERROR,
+        PARITY_ERROR => open
     );
 
     -- -------------------------------------------------------------------------
@@ -154,7 +155,7 @@ begin
         CLK         => CLK,
         RST         => RST,
         -- UART INTERFACE
-        UART_CLK_EN => uart_clk_en,
+        UART_CLK_EN => oversampling_clk_en,
         UART_TXD    => UART_TXD,
         -- USER DATA INPUT INTERFACE
         DIN         => DIN,