Added Quartus projct file for example design, removed some resets, BUSY changed to DIN_RDY.

Author: jakubcabal

README.md

@@ -12,19 +12,16 @@ The UART controller was simulated and tested in hardware.
 -- CLOCK AND RESET
 CLK         : in  std_logic; -- system clock
 RST         : in  std_logic; -- high active synchronous reset
-
 -- UART INTERFACE
 UART_TXD    : out std_logic; -- serial transmit data
 UART_RXD    : in  std_logic; -- serial receive data
-
 -- USER DATA INPUT INTERFACE
-DIN         : in  std_logic_vector(7 downto 0); -- data to be transmitted over UART
-DIN_VLD     : in  std_logic; -- when DIN_VLD = 1, DIN is valid and will be accepted for transmiting
-BUSY        : out std_logic; -- when BUSY = 1, transmitter is busy and DIN can not be accepted
-
+DIN         : in  std_logic_vector(7 downto 0); -- input data to be transmitted over UART
+DIN_VLD     : in  std_logic; -- when DIN_VLD = 1, input data (DIN) are valid
+DIN_RDY     : out std_logic  -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting
 -- USER DATA OUTPUT INTERFACE
-DOUT        : out std_logic_vector(7 downto 0); -- data received via UART
-DOUT_VLD    : out std_logic; -- when DOUT_VLD = 1, DOUT is valid (is assert only for one clock cycle)
+DOUT        : out std_logic_vector(7 downto 0); -- output data received via UART
+DOUT_VLD    : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid (is assert only for one clock cycle)
 FRAME_ERROR : out std_logic  -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
 ```
 
@@ -41,14 +38,14 @@ USE_DEBOUNCER : boolean := True    -- enable/disable debouncer
 
 Use debouncer | Parity type | LE (LUT+FF) | LUT | FF | BRAM | Fmax
 :---:|:---:|:---:|:---:|:---:|:---:|:---:
-True | none | 77 | 64 | 55 | 0 | 202.2 MHz
-True | even/odd | 82 | 75 | 58 | 0 | 162.5 MHz
-True | mark/space | 80 | 68 | 58 | 0 | 184.5 MHz
-False | none | 72 | 59 | 50 | 0 | 182.7 MHz
-False | even/odd | 77 | 70 | 53 | 0 | 155.6 MHz
-False | mark/space | 75 | 62 | 53 | 0 | 200.8 MHz
-
-*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 for FPGA Altera Cyclone II with enable force use of synchronous clear. Setting of some generics: BAUD_RATE = 115200, CLK_FREQ = 50e6.*
+True | none | 74 | 59 | 53 | 0 | 220.0 MHz
+True | even/odd | 81 | 70 | 56 | 0 | 193.3 MHz
+True | mark/space | 78 | 63 | 56 | 0 | 210.2 MHz
+False | none | 70 | 57 | 49 | 0 | 182.3 MHz
+False | even/odd | 78 | 68 | 52 | 0 | 183.5 MHz
+False | mark/space | 74 | 61 | 52 | 0 | 186.2 MHz
+
+*Implementation was performed using Quartus Prime Lite Edition 17.0.0 for FPGA Altera Cyclone IV E EP4CE6E22C8. Setting of some generics: BAUD_RATE = 115200, CLK_FREQ = 50e6.*
 
 # Simulation:
 

example/ep4ce6_starter_board_assignments.qsf

@@ -0,0 +1,10 @@
+#-------------------------------------------------------------------------------
+# PROJECT: SIMPLE UART FOR FPGA
+#-------------------------------------------------------------------------------
+# NAME:    QUARTUS PROJECT FILE
+# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
+# LICENSE: The MIT License (MIT), please read LICENSE file
+# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
+#-------------------------------------------------------------------------------
+
+PROJECT_REVISION = "uart_loopback"

example/quartus/uart_loopback.qpf

@@ -0,0 +1,29 @@
+#-------------------------------------------------------------------------------
+# PROJECT: SIMPLE UART FOR FPGA
+#-------------------------------------------------------------------------------
+# NAME:    QUARTUS SETTINGS FILE FOR EP4CE6 STARTER BOARD
+# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
+# LICENSE: The MIT License (MIT), please read LICENSE file
+# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
+#-------------------------------------------------------------------------------
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE6E22C8
+set_global_assignment -name TOP_LEVEL_ENTITY UART_LOOPBACK
+
+# PROJECT VHDL FILES
+set_global_assignment -name VHDL_FILE ../uart_loopback.vhd
+set_global_assignment -name VHDL_FILE ../../rtl/uart.vhd
+set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_tx.vhd
+set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_rx.vhd
+set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_parity.vhd
+set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_debouncer.vhd
+
+# TIMING CONSTRAINTS
+set_global_assignment -name SDC_FILE ../timing_constraints.sdc
+
+# FPGA PINS ASSIGNMENT FOR EP4CE6 STARTER BOARD
+set_location_assignment PIN_91  -to CLK
+set_location_assignment PIN_25  -to RST
+set_location_assignment PIN_85  -to UART_TXD
+set_location_assignment PIN_86  -to UART_RXD

example/quartus/uart_loopback.qsf

@@ -57,7 +57,7 @@ begin
         -- USER DATA INPUT INTERFACE
         DIN         => data,
         DIN_VLD     => valid,
-        BUSY        => open
+        DIN_RDY     => open
     );
 
 end FULL;

example/uart_loopback.vhd

@@ -17,10 +17,10 @@ end UART_LOOPBACK_TB;
 architecture FULL of UART_LOOPBACK_TB is
 
 	signal CLK           : std_logic := '0';
-	signal RST_N         : std_logic := '0';
+	signal RST           : std_logic := '1';
 	signal tx_uart       : std_logic;
 	signal rx_uart       : std_logic := '1';
-    signal busy          : std_logic;
+    signal din_rdy       : std_logic;
     signal frame_error   : std_logic;
 
   	constant clk_period  : time := 20 ns;
@@ -38,12 +38,12 @@ begin
     )
     port map (
         CLK         => CLK,
-        RST_N       => RST_N,
+        RST         => RST,
         -- UART INTERFACE
         UART_TXD    => tx_uart,
         UART_RXD    => rx_uart,
         -- DEBUG INTERFACE
-        BUSY        => busy,
+        DIN_RDY     => din_rdy,
         FRAME_ERR   => frame_error
     );
 
@@ -58,9 +58,9 @@ begin
 	test_rx_uart : process
 	begin
 		rx_uart <= '1';
-		RST_N <= '0';
+		RST <= '1';
 		wait for 100 ns;
-    	RST_N <= '1';
+    	RST <= '0';
 
 		wait for uart_period;
 

example/uart_loopback_tb.vhd

@@ -1,7 +1,7 @@
 --------------------------------------------------------------------------------
 -- PROJECT: SIMPLE UART FOR FPGA
 --------------------------------------------------------------------------------
--- MODULE:  DEBOUNCER
+-- MODULE:  UART DEBOUNCER
 -- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
 -- LICENSE: The MIT License (MIT), please read LICENSE file
 -- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
@@ -11,7 +11,7 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
-entity DEBOUNCER is
+entity UART_DEBOUNCER is
     Generic (
         -- latency of debouncer in clock cycles, minimum value is 2,
         -- value also corresponds to the number of bits compared
@@ -22,9 +22,9 @@ entity DEBOUNCER is
         DEB_IN  : in  std_logic; -- input of signal from outside FPGA
         DEB_OUT : out std_logic  -- output of debounced (filtered) signal
     );
-end DEBOUNCER;
+end UART_DEBOUNCER;
 
-architecture RTL of DEBOUNCER is
+architecture RTL of UART_DEBOUNCER is
 
     constant SHREG_DEPTH : natural := LATENCY-1;
 

rtl/comp/debouncer.vhd rtl/comp/uart_debouncer.vhdrtl/comp/debouncer.vhd renamed to rtl/comp/uart_debouncer.vhd

@@ -22,8 +22,8 @@ entity UART_RX is
         UART_CLK_EN : in  std_logic; -- oversampling (16x) UART clock enable
         UART_RXD    : in  std_logic; -- serial receive data
         -- USER DATA OUTPUT INTERFACE
-        DOUT        : out std_logic_vector(7 downto 0); -- data received via UART
-        DOUT_VLD    : out std_logic; -- when DOUT_VLD = 1, DOUT is valid (is assert only for one clock cycle)
+        DOUT        : out std_logic_vector(7 downto 0); -- output data received via UART
+        DOUT_VLD    : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid (is assert only for one clock cycle)
         FRAME_ERROR : out std_logic  -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
     );
 end UART_RX;
@@ -55,7 +55,7 @@ begin
     begin
         if (rising_edge(CLK)) then
             if (rx_clk_divider_en = '1') then
-                if (uart_clk_en = '1') then
+                if (UART_CLK_EN = '1') then
                     if (rx_ticks = "1111") then
                         rx_ticks <= (others => '0');
                     else
@@ -75,7 +75,7 @@ begin
         if (rising_edge(CLK)) then
             if (RST = '1') then
                 rx_clk_en <= '0';
-            elsif (uart_clk_en = '1' AND rx_ticks = "0111") then
+            elsif (UART_CLK_EN = '1' AND rx_ticks = "0111") then
                 rx_clk_en <= '1';
             else
                 rx_clk_en <= '0';
@@ -109,9 +109,7 @@ begin
     uart_rx_data_shift_reg_p : process (CLK)
     begin
         if (rising_edge(CLK)) then
-            if (RST = '1') then
-                rx_data <= (others => '0');
-            elsif (rx_clk_en = '1' AND rx_receiving_data = '1') then
+            if (rx_clk_en = '1' AND rx_receiving_data = '1') then
                 rx_data <= UART_RXD & rx_data(7 downto 1);
             end if;
         end if;
@@ -137,9 +135,7 @@ begin
         uart_rx_parity_check_reg_p : process (CLK)
         begin
             if (rising_edge(CLK)) then
-                if (RST = '1') then
-                    rx_parity_error <= '0';
-                elsif (rx_parity_check_en = '1') then
+                if (rx_clk_en = '1') then
                     rx_parity_error <= rx_parity_bit XOR UART_RXD;
                 end if;
             end if;
@@ -194,10 +190,9 @@ begin
         case rx_pstate is
 
             when idle =>
-                rx_output_reg_en   <= '0';
-                rx_receiving_data  <= '0';
-                rx_clk_divider_en  <= '0';
-                rx_parity_check_en <= '0';
+                rx_output_reg_en  <= '0';
+                rx_receiving_data <= '0';
+                rx_clk_divider_en <= '0';
 
                 if (UART_RXD = '0') then
                     rx_nstate <= startbit;
@@ -206,10 +201,9 @@ begin
                 end if;
 
             when startbit =>
-                rx_output_reg_en   <= '0';
-                rx_receiving_data  <= '0';
-                rx_clk_divider_en  <= '1';
-                rx_parity_check_en <= '0';
+                rx_output_reg_en  <= '0';
+                rx_receiving_data <= '0';
+                rx_clk_divider_en <= '1';
 
                 if (rx_clk_en = '1') then
                     rx_nstate <= databits;
@@ -218,10 +212,9 @@ begin
                 end if;
 
             when databits =>
-                rx_output_reg_en   <= '0';
-                rx_receiving_data  <= '1';
-                rx_clk_divider_en  <= '1';
-                rx_parity_check_en <= '0';
+                rx_output_reg_en  <= '0';
+                rx_receiving_data <= '1';
+                rx_clk_divider_en <= '1';
 
                 if ((rx_clk_en = '1') AND (rx_bit_count = "111")) then
                     if (PARITY_BIT = "none") then
@@ -234,10 +227,9 @@ begin
                 end if;
 
             when paritybit =>
-                rx_output_reg_en   <= '0';
-                rx_receiving_data  <= '0';
-                rx_clk_divider_en  <= '1';
-                rx_parity_check_en <= '1';
+                rx_output_reg_en  <= '0';
+                rx_receiving_data <= '0';
+                rx_clk_divider_en <= '1';
 
                 if (rx_clk_en = '1') then
                     rx_nstate <= stopbit;
@@ -246,10 +238,9 @@ begin
                 end if;
 
             when stopbit =>
-                rx_receiving_data  <= '0';
-                rx_clk_divider_en  <= '1';
-                rx_parity_check_en <= '0';
-                rx_output_reg_en   <= '1';
+                rx_output_reg_en  <= '1';
+                rx_receiving_data <= '0';
+                rx_clk_divider_en <= '1';
 
                 if (rx_clk_en = '1') then
                     rx_nstate <= idle;
@@ -258,11 +249,10 @@ begin
                 end if;
 
             when others =>
-                rx_output_reg_en   <= '0';
-                rx_receiving_data  <= '0';
-                rx_clk_divider_en  <= '0';
-                rx_parity_check_en <= '0';
-                rx_nstate <= idle;
+                rx_output_reg_en  <= '0';
+                rx_receiving_data <= '0';
+                rx_clk_divider_en <= '0';
+                rx_nstate         <= idle;
 
         end case;
     end process;