fix peripheral register read/write for larger ULP addresses

When register addresses less than or equal to 0x3ff are given to the
reg_rd and reg_wr opcodes, these addresses should be used unmodified
as the address in the machine instruction.

In our implementation we split the 10 bit address field of the machine
instruction into two fields, namely "addr" for the lower 8 bits and
"periph_sel" for the upper 2 bits.

We already had a mechanism for determining the periph_sel part for
"full" addresses (e.g. 0x3ff48000), but for direct (ULP) addresses, we
always set periph_sel to 0 instead of using the upper 2 bits from the
given address. This commit fixes that.

Note 1: In binutils-esp32ulp, they don't split the address into these 2
fields but simply put the direct ULP address into a single combined
field of 10 bits, which has the same effect. See: https://github.com/espressif/binutils-esp32ulp/blob/249ec34/gas/config/tc-esp32ulp_esp32.c#L145

Note 2: In the "macro approach" in esp-idf for creating ULP code, they
also use the split field approach (I assume our implementation is
modelled after that) and they also don't handle direct (ULP) addresses
correctly (or seemingly at all). See: https://github.com/espressif/esp-idf/blob/9d34a1c/components/ulp/include/esp32/ulp.h#L349

This commit contributes to being able to eventually assemble the
esp32ulp_ranges.s test from binutils-esp32ulp. It addresses this line:
https://github.com/espressif/binutils-esp32ulp/blob/249ec34/gas/testsuite/gas/esp32ulp/esp32/esp32ulp_ranges.s#L136

Author: wnienhaus

esp32_ulp/opcodes.py

@@ -379,9 +379,10 @@ def i_reg_wr(reg, high_bit, low_bit, val):
     reg = get_imm(reg)
     if reg <= DR_REG_MAX_DIRECT:  # see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
         _wr_reg.addr = reg
+        _wr_reg.periph_sel = reg >> 8
     else:
         _wr_reg.addr = (reg & 0xff) >> 2
-    _wr_reg.periph_sel = _soc_reg_to_ulp_periph_sel(reg)
+        _wr_reg.periph_sel = _soc_reg_to_ulp_periph_sel(reg)
     _wr_reg.data = get_imm(val)
     _wr_reg.low = get_imm(low_bit)
     _wr_reg.high = get_imm(high_bit)
@@ -393,9 +394,10 @@ def i_reg_rd(reg, high_bit, low_bit):
     reg = get_imm(reg)
     if reg <= DR_REG_MAX_DIRECT:  # see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
         _rd_reg.addr = reg
+        _rd_reg.periph_sel = reg >> 8
     else:
         _rd_reg.addr = (reg & 0xff) >> 2
-    _rd_reg.periph_sel = _soc_reg_to_ulp_periph_sel(reg)
+        _rd_reg.periph_sel = _soc_reg_to_ulp_periph_sel(reg)
     _rd_reg.unused = 0
     _rd_reg.low = get_imm(low_bit)
     _rd_reg.high = get_imm(high_bit)

tests/opcodes.py

@@ -108,10 +108,78 @@ def assert_raises(exception, func, *args):
     assert raised
 
 
+def test_reg_direct_ulp_addressing():
+    """
+    Test direct ULP addressing of peripheral registers
+    input must be <= 0x3ff (10 bits)
+    periph_sel == high 2 bits from input
+    addr == low 8 bits from input
+    """
+
+    ins = make_ins("""
+    addr : 8        # Address within either RTC_CNTL, RTC_IO, or SARADC
+    periph_sel : 2  # Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2)
+    unused : 8      # Unused
+    low : 5         # Low bit
+    high : 5        # High bit
+    opcode : 4      # Opcode (OPCODE_RD_REG)
+    """)
+
+    ins.all = opcodes.i_reg_rd("0x0", "0", "0")
+    assert ins.periph_sel == 0
+    assert ins.addr == 0x0
+
+    ins.all = opcodes.i_reg_rd("0x012", "0", "0")
+    assert ins.periph_sel == 0
+    assert ins.addr == 0x12
+
+    ins.all = opcodes.i_reg_rd("0x123", "0", "0")
+    assert ins.periph_sel == 1
+    assert ins.addr == 0x23
+
+    ins.all = opcodes.i_reg_rd("0x2ee", "0", "0")
+    assert ins.periph_sel == 2
+    assert ins.addr == 0xee
+
+    ins.all = opcodes.i_reg_rd("0x3ff", "0", "0")
+    assert ins.periph_sel == 3
+    assert ins.addr == 0xff
+
+    # anything bigger than 0x3ff must be a valid full address
+    assert_raises(ValueError, opcodes.i_reg_rd, "0x400", "0", "0")
+
+
+def test_reg_address_translations():
+    """
+    Test addressing of peripheral registers using full DPORT bus addresses
+    """
+
+    ins = make_ins("""
+    addr : 8        # Address within either RTC_CNTL, RTC_IO, or SARADC
+    periph_sel : 2  # Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2)
+    unused : 8      # Unused
+    low : 5         # Low bit
+    high : 5        # High bit
+    opcode : 4      # Opcode (OPCODE_RD_REG)
+    """)
+
+    # direct ULP address is derived from full address as follows:
+    # full:0x3ff484a8 == ulp:(0x3ff484a8-DR_REG_RTCCNTL_BASE) / 4
+    # full:0x3ff484a8 == ulp:(0x3ff484a8-0x3ff48000) / 4
+    # full:0x3ff484a8 == ulp:0x4a8 / 4
+    # full:0x3ff484a8 == ulp:0x12a
+    # see: https://github.com/espressif/binutils-esp32ulp/blob/249ec34/gas/config/tc-esp32ulp_esp32.c#L149
+    ins.all = opcodes.i_reg_rd("0x3ff484a8", "0", "0")
+    assert ins.periph_sel == 1  # high 2 bits of 0x12a
+    assert ins.addr == 0x2a  # low 8 bits of 0x12a
+
+
 test_make_ins_struct_def()
 test_make_ins()
 test_arg_qualify()
 test_get_reg()
 test_get_imm()
 test_get_cond()
-test_eval_arg()
+test_eval_arg()
+test_reg_direct_ulp_addressing()
+test_reg_address_translations()