In addition to an ISA doc there should probably be complete documentation of the microarchitecture for some official agreement between the rtl and the simulation. Details should include the pipeline structure, the cache specification, and main memory access. Schematics and block diagrams nice but optional.
Lower priority than the ISA documentation.
In addition to an ISA doc there should probably be complete documentation of the microarchitecture for some official agreement between the rtl and the simulation. Details should include the pipeline structure, the cache specification, and main memory access. Schematics and block diagrams nice but optional.
Lower priority than the ISA documentation.