Error with v3.0, RTL simulation, Questasim,SIGILL

[Zexu-Tan]

Greeting,

I was trying to upgrade the local version of ara from v2.2.0 to v3.0.

Meanwhile, when doing RTL simulation, the questasim terminates simulation with the following statements.

I am working with gcc/g++ 13, clang/clang++ 18.

# ** Warning: (vsim-3015) [PCDPC] - Port size (2) does not match connection size (1) for port 'idx_o'. The port definition is at: /home/zexu/Documents/RVV/v3.0_ud/ara/hardware/deps/cva6/src/common_cells/src/rr_arb_tree.sv(56).
#    Time: 0 ps  Iteration: 0  Instance: /ara_tb/dut/i_ara_soc/i_axi_slave_uart_dwc/gen_dw_downsize/i_axi_dw_downsizer/i_mst_ar_arb File: /home/zexu/Documents/RVV/v3.0_ud/ara/hardware/deps/axi/src/axi_dw_downsizer.sv Line: 167
# Compiling /tmp/zexu@Zexu-Personal-01_dpi_589755/linux_x86_64_gcc-13/exportwrapper.c
# Loading /tmp/zexu@Zexu-Personal-01_dpi_589755/linux_x86_64_gcc-13/vsim_auto_compile.so
# Loading ./work-dpi/ara_dpi.so
# do ../scripts/run.tcl
# Dump results on ../gold_results.txt
# Loading ELF file /home/zexu/Documents/RVV/v3.0_ud/ara/apps/bin/hello_world
# Loading section 0000000080000000 of length 0000000000000fbe
# ** Fatal: (SIGILL) Illegal Instruction.
#    Time: 2 ns  Iteration: 0  Process: /ara_tb/#INITIAL#98(dram_init) File: /home/zexu/Documents/RVV/v3.0_ud/ara/hardware/tb/ara_tb.sv
# Fatal error in Module ara_tb_sv_unit at /home/zexu/Documents/RVV/v3.0_ud/ara/hardware/tb/ara_tb.sv line 11

BR,
Tan