From 20a5059a1a71ddb31f975b946d65bd0da4a0f048 Mon Sep 17 00:00:00 2001 From: Wren Turkal Date: Tue, 10 Mar 2026 13:48:35 -0700 Subject: [PATCH 1/6] Update the MSRV to 1.85 on all crates. The lifetime change is due to a lint error from clippy that did not find this problem in prior versions. The change itself shouldn't effect code depending on the cortex-m crate. --- .github/workflows/ci.yml | 9 +-------- .github/workflows/clippy.yml | 2 +- .github/workflows/rt-ci.yml | 2 +- cortex-m-rt/CHANGELOG.md | 2 +- cortex-m-rt/Cargo.toml | 2 +- cortex-m-rt/README.md | 2 +- cortex-m-semihosting/CHANGELOG.md | 2 +- cortex-m-semihosting/Cargo.toml | 2 +- cortex-m-semihosting/README.md | 2 +- cortex-m-types/CHANGELOG.md | 1 + cortex-m-types/Cargo.toml | 2 +- cortex-m-types/README.md | 2 +- cortex-m/CHANGELOG.md | 2 +- cortex-m/Cargo.toml | 2 +- cortex-m/README.md | 2 +- cortex-m/src/itm.rs | 2 +- panic-itm/CHANGELOG.md | 1 + panic-itm/Cargo.toml | 1 + panic-itm/README.md | 2 +- panic-semihosting/CHANGELOG.md | 1 + panic-semihosting/Cargo.toml | 2 +- panic-semihosting/README.md | 2 +- testsuite/Cargo.toml | 1 + xtask/Cargo.toml | 1 + 24 files changed, 24 insertions(+), 25 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 77bfdb04a..b1530b066 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -17,13 +17,10 @@ jobs: include: # Test MSRV - - rust: 1.71.0 - # Should be set to true for >= 1.81.0 - test_cortex_m_types: false + - rust: 1.85.0 # Test nightly but don't fail - rust: nightly - test_cortex_m_types: true experimental: true steps: - uses: actions/checkout@v4 @@ -31,8 +28,4 @@ jobs: with: toolchain: ${{ matrix.rust }} - name: Run tests - if: ${{ matrix.test_cortex_m_types }} run: cargo test --all --exclude cortex-m-rt --exclude testsuite --features cortex-m/critical-section-single-core - - name: Run tests for < 1.81.0 (need to exclude cortex-m-types) - if: ${{ matrix.test_cortex_m_types == false }} - run: cargo test --all --exclude cortex-m-rt --exclude testsuite --exclude cortex-m-types --features cortex-m/critical-section-single-core diff --git a/.github/workflows/clippy.yml b/.github/workflows/clippy.yml index 6367f7413..d40ee3183 100644 --- a/.github/workflows/clippy.yml +++ b/.github/workflows/clippy.yml @@ -9,7 +9,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - - uses: dtolnay/rust-toolchain@1.81 + - uses: dtolnay/rust-toolchain@1.85 with: components: clippy - run: cargo clippy --all --features cortex-m/critical-section-single-core -- --deny warnings diff --git a/.github/workflows/rt-ci.yml b/.github/workflows/rt-ci.yml index 831dc5301..cd01ffc0a 100644 --- a/.github/workflows/rt-ci.yml +++ b/.github/workflows/rt-ci.yml @@ -11,7 +11,7 @@ jobs: continue-on-error: ${{ matrix.experimental || false }} strategy: matrix: - rust: [nightly, stable, 1.71.0] + rust: [nightly, stable, 1.85.0] include: # Nightly is only for reference and allowed to fail diff --git a/cortex-m-rt/CHANGELOG.md b/cortex-m-rt/CHANGELOG.md index bba99cab5..2679bcf8e 100644 --- a/cortex-m-rt/CHANGELOG.md +++ b/cortex-m-rt/CHANGELOG.md @@ -16,7 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). from an external device. Note that this relies on the bootloader to have already copied `.data` to the VMA before relinquishing control. - Updated references from 'Cortex-M Team' to 'Arm Team' -- Bump MSRV to 1.71 +- Bump MSRV to 1.85 ## [v0.7.5] diff --git a/cortex-m-rt/Cargo.toml b/cortex-m-rt/Cargo.toml index 941c45ba0..608788749 100644 --- a/cortex-m-rt/Cargo.toml +++ b/cortex-m-rt/Cargo.toml @@ -16,7 +16,7 @@ version = "0.7.5" autoexamples = true links = "cortex-m-rt" # Prevent multiple versions of cortex-m-rt being linked edition = "2021" -rust-version = "1.71" +rust-version = "1.85" [dependencies] cortex-m-rt-macros = { path = "macros", version = "=0.7.5" } diff --git a/cortex-m-rt/README.md b/cortex-m-rt/README.md index 3be60989d..fc7ec4cc6 100644 --- a/cortex-m-rt/README.md +++ b/cortex-m-rt/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [Embedded Devices Working Group' ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.61.0 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It *might* compile with older versions but that may change in any new patch release. ## License diff --git a/cortex-m-semihosting/CHANGELOG.md b/cortex-m-semihosting/CHANGELOG.md index e1b532cc6..2c2d509be 100644 --- a/cortex-m-semihosting/CHANGELOG.md +++ b/cortex-m-semihosting/CHANGELOG.md @@ -5,7 +5,7 @@ This project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] -- MSRV bumped to 1.60 to align with `embedded-hal` version 1. +- MSRV bumped to 1.85 - Updated references from 'Cortex-M Team' to 'Arm Team' ## [v0.5.0] - 2022-03-01 diff --git a/cortex-m-semihosting/Cargo.toml b/cortex-m-semihosting/Cargo.toml index 29875e268..8d87e7305 100644 --- a/cortex-m-semihosting/Cargo.toml +++ b/cortex-m-semihosting/Cargo.toml @@ -13,7 +13,7 @@ readme = "README.md" repository = "https://github.com/rust-embedded/cortex-m" version = "0.5.0" edition = "2021" -rust-version = "1.71" +rust-version = "1.85" [features] jlink-quirks = [] diff --git a/cortex-m-semihosting/README.md b/cortex-m-semihosting/README.md index ca4559b00..fdaefb259 100644 --- a/cortex-m-semihosting/README.md +++ b/cortex-m-semihosting/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [Embedded Devices Working Group' # Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.61.0 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It *might* compile with older versions but that may change in any new patch release. ## License diff --git a/cortex-m-types/CHANGELOG.md b/cortex-m-types/CHANGELOG.md index 9d73d99cc..1663330b1 100644 --- a/cortex-m-types/CHANGELOG.md +++ b/cortex-m-types/CHANGELOG.md @@ -7,4 +7,5 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +- MSRV bumped to 1.85 - Updated references from 'Cortex-M Team' to 'Arm Team' diff --git a/cortex-m-types/Cargo.toml b/cortex-m-types/Cargo.toml index 0b9027f6b..1245de0b2 100644 --- a/cortex-m-types/Cargo.toml +++ b/cortex-m-types/Cargo.toml @@ -2,7 +2,6 @@ name = "cortex-m-types" version = "0.1.0" edition = "2021" -rust-version = "1.81" repository = "https://github.com/rust-embedded/cortex-m" authors = ["The Embedded Devices Working Group's Arm Team ",] categories = ["embedded", "hardware-support", "no-std"] @@ -11,6 +10,7 @@ documentation = "https://docs.rs/cortex-m-types" keywords = ["arm", "cortex-m", "register", "peripheral"] license = "MIT OR Apache-2.0" readme = "README.md" +rust-version = "1.85" [package.metadata.docs.rs] targets = [ diff --git a/cortex-m-types/README.md b/cortex-m-types/README.md index ba2aa68de..4ff5e664c 100644 --- a/cortex-m-types/README.md +++ b/cortex-m-types/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [Arm team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.81 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It *might* compile with older versions but that may change in any new patch release. ## License diff --git a/cortex-m/CHANGELOG.md b/cortex-m/CHANGELOG.md index 758ad2f45..d87d00dcb 100644 --- a/cortex-m/CHANGELOG.md +++ b/cortex-m/CHANGELOG.md @@ -7,7 +7,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] -- MSRV is 1.71 to match cortex-m-rt crate +- MSRV is 1.85 to match cortex-m-rt crate - Add `enter_unprivileged` function to switch to unprivileged mode (on the Process Stack, or `PSP`) - Updated references from 'Cortex-M Team' to 'Arm Team' diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml index da65e72c7..8bf22ef43 100644 --- a/cortex-m/Cargo.toml +++ b/cortex-m/Cargo.toml @@ -14,7 +14,7 @@ repository = "https://github.com/rust-embedded/cortex-m" edition = "2021" version = "0.7.7" links = "cortex-m" # prevent multiple versions of this crate to be linked together -rust-version = "1.71" +rust-version = "1.85" [dependencies] bare-metal = { version = "0.2.4", features = ["const-fn"] } diff --git a/cortex-m/README.md b/cortex-m/README.md index 44ab13eb8..26a5b93e7 100644 --- a/cortex-m/README.md +++ b/cortex-m/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [Embedded Devices Working Group' ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.61 and up. It might compile with older versions but that may change in any new patch release. +This crate is guaranteed to compile on stable Rust 1.85 and up. It might compile with older versions but that may change in any new patch release. ## License diff --git a/cortex-m/src/itm.rs b/cortex-m/src/itm.rs index 72cb0d9a8..905aefb83 100644 --- a/cortex-m/src/itm.rs +++ b/cortex-m/src/itm.rs @@ -57,7 +57,7 @@ unsafe fn write_aligned_impl(port: &mut Stim, buffer: &[u8]) { struct Port<'p>(&'p mut Stim); -impl<'p> fmt::Write for Port<'p> { +impl fmt::Write for Port<'_> { #[inline] fn write_str(&mut self, s: &str) -> fmt::Result { write_all(self.0, s.as_bytes()); diff --git a/panic-itm/CHANGELOG.md b/panic-itm/CHANGELOG.md index c7534cd98..090422211 100644 --- a/panic-itm/CHANGELOG.md +++ b/panic-itm/CHANGELOG.md @@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- MSRV bumped to 1.85 - switched from `ITM::ptr()` to `ITM::PTR` as `ptr()` has been deprecated/removed (#385). - Updated references from 'Cortex-M Team' to 'Arm Team' diff --git a/panic-itm/Cargo.toml b/panic-itm/Cargo.toml index 5325243e2..feb6d9afc 100644 --- a/panic-itm/Cargo.toml +++ b/panic-itm/Cargo.toml @@ -12,6 +12,7 @@ name = "panic-itm" repository = "https://github.com/rust-embedded/cortex-m" edition = "2021" version = "0.4.2" +rust-version = "1.85" [dependencies] cortex-m = { path = "../cortex-m", version = ">= 0.5.8, < 0.8" } diff --git a/panic-itm/README.md b/panic-itm/README.md index bff93efc0..1d50b09d4 100644 --- a/panic-itm/README.md +++ b/panic-itm/README.md @@ -8,7 +8,7 @@ This project is developed and maintained by the [Embedded Devices Working Group' ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.31.0 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It *might* compile with older versions but that may change in any new patch release. ## License diff --git a/panic-semihosting/CHANGELOG.md b/panic-semihosting/CHANGELOG.md index b70947f42..5a8a2966c 100644 --- a/panic-semihosting/CHANGELOG.md +++ b/panic-semihosting/CHANGELOG.md @@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +- MSRV bumped to 1.85 - Updated references from 'Cortex-M Team' to 'Arm Team' ## [v0.6.0] - 2022-03-01 diff --git a/panic-semihosting/Cargo.toml b/panic-semihosting/Cargo.toml index 2d5b683be..a292c466f 100644 --- a/panic-semihosting/Cargo.toml +++ b/panic-semihosting/Cargo.toml @@ -11,8 +11,8 @@ license = "MIT OR Apache-2.0" name = "panic-semihosting" repository = "https://github.com/rust-embedded/cortex-m" version = "0.6.0" -rust-version = "1.71" edition = "2021" +rust-version = "1.85" [dependencies] cortex-m = { path = "../cortex-m", version = ">= 0.5.6, < 0.8" } diff --git a/panic-semihosting/README.md b/panic-semihosting/README.md index f22632437..1a97bb5cb 100644 --- a/panic-semihosting/README.md +++ b/panic-semihosting/README.md @@ -8,7 +8,7 @@ This project is developed and maintained by the [Embedded Devices Working Group' ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.61.0 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It *might* compile with older versions but that may change in any new patch release. ## License diff --git a/testsuite/Cargo.toml b/testsuite/Cargo.toml index 75fb05df8..185ea2d56 100644 --- a/testsuite/Cargo.toml +++ b/testsuite/Cargo.toml @@ -4,6 +4,7 @@ name = "testsuite" publish = false edition = "2021" version = "0.1.0" +rust-version = "1.85" [features] rtt = ["rtt-target", "minitest/rtt"] diff --git a/xtask/Cargo.toml b/xtask/Cargo.toml index 1f48803f5..f2da7fb18 100644 --- a/xtask/Cargo.toml +++ b/xtask/Cargo.toml @@ -4,6 +4,7 @@ version = "0.0.0" authors = ["The Embedded Devices Working Group's Arm Team"] edition = "2021" publish = false +rust-version = "1.85" [[test]] name = "ci" From 51620b3fd48d24b0db1849d742e6789673a5b1a6 Mon Sep 17 00:00:00 2001 From: Wren Turkal Date: Tue, 10 Mar 2026 13:53:33 -0700 Subject: [PATCH 2/6] Remove deprecated authors in Cargo.tomls. --- cortex-m-rt/Cargo.toml | 5 ----- cortex-m-semihosting/Cargo.toml | 4 ---- cortex-m-types/Cargo.toml | 1 - cortex-m/Cargo.toml | 4 ---- panic-itm/Cargo.toml | 4 ---- panic-semihosting/Cargo.toml | 4 ---- testsuite/Cargo.toml | 1 - xtask/Cargo.toml | 1 - 8 files changed, 24 deletions(-) diff --git a/cortex-m-rt/Cargo.toml b/cortex-m-rt/Cargo.toml index 608788749..fb16592d9 100644 --- a/cortex-m-rt/Cargo.toml +++ b/cortex-m-rt/Cargo.toml @@ -1,9 +1,4 @@ [package] -authors = [ - "The Embedded Devices Working Group's Arm Team ", - "Jorge Aparicio ", - "Hideki Sekine ", -] categories = ["embedded", "no-std"] description = "Minimal runtime / startup for Cortex-M microcontrollers" documentation = "https://docs.rs/cortex-m-rt/" diff --git a/cortex-m-semihosting/Cargo.toml b/cortex-m-semihosting/Cargo.toml index 8d87e7305..dc35d716d 100644 --- a/cortex-m-semihosting/Cargo.toml +++ b/cortex-m-semihosting/Cargo.toml @@ -1,8 +1,4 @@ [package] -authors = [ - "The Embedded Devices Working Group's Arm Team ", - "Jorge Aparicio ", -] description = "Semihosting for ARM Cortex-M processors" documentation = "https://docs.rs/cortex-m-semihosting" keywords = ["semihosting", "arm", "cortex-m"] diff --git a/cortex-m-types/Cargo.toml b/cortex-m-types/Cargo.toml index 1245de0b2..e40f47899 100644 --- a/cortex-m-types/Cargo.toml +++ b/cortex-m-types/Cargo.toml @@ -3,7 +3,6 @@ name = "cortex-m-types" version = "0.1.0" edition = "2021" repository = "https://github.com/rust-embedded/cortex-m" -authors = ["The Embedded Devices Working Group's Arm Team ",] categories = ["embedded", "hardware-support", "no-std"] description = "Low level access to Cortex-M processors" documentation = "https://docs.rs/cortex-m-types" diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml index 8bf22ef43..c449ac59c 100644 --- a/cortex-m/Cargo.toml +++ b/cortex-m/Cargo.toml @@ -1,8 +1,4 @@ [package] -authors = [ - "The Embedded Devices Working Group's Arm Team ", - "Jorge Aparicio ", -] categories = ["embedded", "hardware-support", "no-std"] description = "Low level access to Cortex-M processors" documentation = "https://docs.rs/cortex-m" diff --git a/panic-itm/Cargo.toml b/panic-itm/Cargo.toml index feb6d9afc..b1a11647d 100644 --- a/panic-itm/Cargo.toml +++ b/panic-itm/Cargo.toml @@ -1,8 +1,4 @@ [package] -authors = [ - "The Embedded Devices Working Group's Arm Team ", - "Jorge Aparicio ", -] categories = ["no-std", "embedded"] description = "Log panic messages using the ITM (Instrumentation Trace Macrocell)" documentation = "https://docs.rs/panic-itm" diff --git a/panic-semihosting/Cargo.toml b/panic-semihosting/Cargo.toml index a292c466f..6b8a32cc4 100644 --- a/panic-semihosting/Cargo.toml +++ b/panic-semihosting/Cargo.toml @@ -1,8 +1,4 @@ [package] -authors = [ - "The Embedded Devices Working Group's Arm Team", - "Jorge Aparicio ", -] categories = ["no-std", "embedded"] description = "Report panic messages to the host stderr using semihosting" documentation = "https://docs.rs/panic-semihosting" diff --git a/testsuite/Cargo.toml b/testsuite/Cargo.toml index 185ea2d56..cb619649e 100644 --- a/testsuite/Cargo.toml +++ b/testsuite/Cargo.toml @@ -1,5 +1,4 @@ [package] -authors = ["The Embedded Devices Working Group's Arm Team"] name = "testsuite" publish = false edition = "2021" diff --git a/xtask/Cargo.toml b/xtask/Cargo.toml index f2da7fb18..88f58a410 100644 --- a/xtask/Cargo.toml +++ b/xtask/Cargo.toml @@ -1,7 +1,6 @@ [package] name = "xtask" version = "0.0.0" -authors = ["The Embedded Devices Working Group's Arm Team"] edition = "2021" publish = false rust-version = "1.85" From 10b8831655e14461a100cf6d8cf8d297ad198182 Mon Sep 17 00:00:00 2001 From: Wren Turkal Date: Tue, 10 Mar 2026 15:05:30 -0700 Subject: [PATCH 3/6] Update all code to be edition 2024 compatible. --- cortex-m-rt/examples/device.rs | 7 +- cortex-m-rt/examples/main.rs | 2 +- cortex-m-rt/examples/unsafety.rs | 8 +- cortex-m-rt/src/lib.rs | 54 ++++++------- cortex-m-semihosting/src/lib.rs | 6 +- cortex-m/src/asm.rs | 8 +- cortex-m/src/call_asm.rs | 2 +- cortex-m/src/critical_section.rs | 2 +- cortex-m/src/interrupt.rs | 2 +- cortex-m/src/itm.rs | 64 ++++++++------- cortex-m/src/macros.rs | 4 +- cortex-m/src/peripheral/cbp.rs | 32 ++++---- cortex-m/src/peripheral/mod.rs | 102 ++++++++++++------------ cortex-m/src/peripheral/nvic.rs | 38 +++++---- cortex-m/src/peripheral/scb.rs | 131 +++++++++++++++++-------------- 15 files changed, 246 insertions(+), 216 deletions(-) diff --git a/cortex-m-rt/examples/device.rs b/cortex-m-rt/examples/device.rs index 02a60c8a8..364bd0a21 100644 --- a/cortex-m-rt/examples/device.rs +++ b/cortex-m-rt/examples/device.rs @@ -1,6 +1,5 @@ //! Manually create the interrupts portion of the vector table -#![deny(unsafe_code)] #![deny(warnings)] #![no_main] #![no_std] @@ -22,14 +21,14 @@ pub union Vector { reserved: usize, } -extern "C" { +unsafe extern "C" { fn WWDG(); fn PVD(); } #[allow(unsafe_code)] -#[link_section = ".vector_table.interrupts"] -#[no_mangle] +#[unsafe(link_section = ".vector_table.interrupts")] +#[unsafe(no_mangle)] pub static __INTERRUPTS: [Vector; 3] = [ Vector { handler: WWDG }, Vector { reserved: 0 }, diff --git a/cortex-m-rt/examples/main.rs b/cortex-m-rt/examples/main.rs index 58e3cb485..321ac79ea 100644 --- a/cortex-m-rt/examples/main.rs +++ b/cortex-m-rt/examples/main.rs @@ -7,7 +7,7 @@ extern crate cortex_m_rt as rt; extern crate panic_halt; -#[no_mangle] +#[unsafe(no_mangle)] pub unsafe extern "C" fn main() -> ! { loop {} } diff --git a/cortex-m-rt/examples/unsafety.rs b/cortex-m-rt/examples/unsafety.rs index cdb5acaf9..444de6c96 100644 --- a/cortex-m-rt/examples/unsafety.rs +++ b/cortex-m-rt/examples/unsafety.rs @@ -11,26 +11,26 @@ use cortex_m_rt::{entry, exception, ExceptionFrame}; #[entry] unsafe fn main() -> ! { - foo(); + unsafe { foo() }; loop {} } #[exception] unsafe fn DefaultHandler(_irqn: i16) { - foo(); + unsafe { foo() }; } #[exception] unsafe fn HardFault(_ef: &ExceptionFrame) -> ! { - foo(); + unsafe { foo() }; loop {} } #[exception] unsafe fn SysTick() { - foo(); + unsafe { foo() }; } unsafe fn foo() {} diff --git a/cortex-m-rt/src/lib.rs b/cortex-m-rt/src/lib.rs index cb90b43c2..b04fd57e1 100644 --- a/cortex-m-rt/src/lib.rs +++ b/cortex-m-rt/src/lib.rs @@ -361,13 +361,13 @@ //! reserved: usize, //! } //! -//! extern "C" { +//! unsafe extern "C" { //! fn Foo(); //! fn Bar(); //! } //! -//! #[link_section = ".vector_table.interrupts"] -//! #[no_mangle] +//! #[unsafe(link_section = ".vector_table.interrupts")] +//! #[unsafe(no_mangle)] //! pub static __INTERRUPTS: [Vector; 5] = [ //! // 0-1: Reserved //! Vector { reserved: 0 }, @@ -440,14 +440,14 @@ //! //! [`MaybeUninit`]: https://doc.rust-lang.org/core/mem/union.MaybeUninit.html //! -//! ```no_run,edition2018 +//! ```no_run //! # extern crate core; //! use core::mem::MaybeUninit; //! //! const STACK_SIZE: usize = 8 * 1024; //! const NTHREADS: usize = 4; //! -//! #[link_section = ".uninit.STACKS"] +//! #[unsafe(link_section = ".uninit.STACKS")] //! static mut STACKS: MaybeUninit<[[u8; STACK_SIZE]; NTHREADS]> = MaybeUninit::uninit(); //! ``` //! @@ -483,10 +483,10 @@ //! //! You can then use something like this to place a variable into this specific section of memory: //! -//! ```no_run,edition2018 +//! ```no_run //! # extern crate core; //! # use core::mem::MaybeUninit; -//! #[link_section=".ccmram.BUFFERS"] +//! #[unsafe(link_section=".ccmram.BUFFERS")] //! static mut BUF: MaybeUninit<[u8; 1024]> = MaybeUninit::uninit(); //! ``` //! @@ -937,7 +937,7 @@ pub use macros::pre_init; // two copies of cortex-m-rt together, linking will fail. We also declare a links key in // Cargo.toml which is the more modern way to solve the same problem, but we have to keep // __ONCE__ around to prevent linking with versions before the links key was added. -#[export_name = "error: cortex-m-rt appears more than once in the dependency graph"] +#[unsafe(export_name = "error: cortex-m-rt appears more than once in the dependency graph")] #[doc(hidden)] pub static __ONCE__: () = (); @@ -1120,7 +1120,7 @@ impl fmt::Debug for ExceptionFrame { /// The returned pointer is guaranteed to be 4-byte aligned. #[inline] pub fn heap_start() -> *mut u32 { - extern "C" { + unsafe extern "C" { static mut __sheap: u32; } @@ -1132,27 +1132,27 @@ pub fn heap_start() -> *mut u32 { // Entry point is Reset. #[doc(hidden)] -#[cfg_attr(cortex_m, link_section = ".vector_table.reset_vector")] -#[no_mangle] +#[cfg_attr(cortex_m, unsafe(link_section = ".vector_table.reset_vector"))] +#[unsafe(no_mangle)] pub static __RESET_VECTOR: unsafe extern "C" fn() -> ! = Reset; #[doc(hidden)] -#[cfg_attr(cortex_m, link_section = ".HardFault.default")] -#[no_mangle] +#[cfg_attr(cortex_m, unsafe(link_section = ".HardFault.default"))] +#[unsafe(no_mangle)] pub unsafe extern "C" fn HardFault_() -> ! { #[allow(clippy::empty_loop)] loop {} } #[doc(hidden)] -#[no_mangle] +#[unsafe(no_mangle)] pub unsafe extern "C" fn DefaultHandler_() -> ! { #[allow(clippy::empty_loop)] loop {} } #[doc(hidden)] -#[no_mangle] +#[unsafe(no_mangle)] pub unsafe extern "C" fn DefaultPreInit() {} /* Exceptions */ @@ -1187,7 +1187,7 @@ pub enum Exception { #[doc(hidden)] pub use self::Exception as exception; -extern "C" { +unsafe extern "C" { fn Reset() -> !; fn NonMaskableInt(); @@ -1224,8 +1224,8 @@ pub union Vector { } #[doc(hidden)] -#[cfg_attr(cortex_m, link_section = ".vector_table.exceptions")] -#[no_mangle] +#[cfg_attr(cortex_m, unsafe(link_section = ".vector_table.exceptions"))] +#[unsafe(no_mangle)] pub static __EXCEPTIONS: [Vector; 14] = [ // Exception 2: Non Maskable Interrupt. Vector { @@ -1284,10 +1284,10 @@ pub static __EXCEPTIONS: [Vector; 14] = [ // to the default handler #[cfg(all(any(not(feature = "device"), test), not(armv6m), not(armv8m_main)))] #[doc(hidden)] -#[cfg_attr(cortex_m, link_section = ".vector_table.interrupts")] -#[no_mangle] +#[cfg_attr(cortex_m, unsafe(link_section = ".vector_table.interrupts"))] +#[unsafe(no_mangle)] pub static __INTERRUPTS: [unsafe extern "C" fn(); 240] = [{ - extern "C" { + unsafe extern "C" { fn DefaultHandler(); } @@ -1297,10 +1297,10 @@ pub static __INTERRUPTS: [unsafe extern "C" fn(); 240] = [{ // ARMv8-M Mainline can have up to 480 device specific interrupts #[cfg(all(not(feature = "device"), armv8m_main))] #[doc(hidden)] -#[cfg_attr(cortex_m, link_section = ".vector_table.interrupts")] -#[no_mangle] +#[cfg_attr(cortex_m, unsafe(link_section = ".vector_table.interrupts"))] +#[unsafe(no_mangle)] pub static __INTERRUPTS: [unsafe extern "C" fn(); 480] = [{ - extern "C" { + unsafe extern "C" { fn DefaultHandler(); } @@ -1310,10 +1310,10 @@ pub static __INTERRUPTS: [unsafe extern "C" fn(); 480] = [{ // ARMv6-M can only have a maximum of 32 device specific interrupts #[cfg(all(not(feature = "device"), armv6m))] #[doc(hidden)] -#[link_section = ".vector_table.interrupts"] -#[no_mangle] +#[unsafe(link_section = ".vector_table.interrupts")] +#[unsafe(no_mangle)] pub static __INTERRUPTS: [unsafe extern "C" fn(); 32] = [{ - extern "C" { + unsafe extern "C" { fn DefaultHandler(); } diff --git a/cortex-m-semihosting/src/lib.rs b/cortex-m-semihosting/src/lib.rs index 6a6e9da50..b3be6abaa 100644 --- a/cortex-m-semihosting/src/lib.rs +++ b/cortex-m-semihosting/src/lib.rs @@ -193,7 +193,7 @@ pub mod nr; /// [semihosting operation]: https://developer.arm.com/documentation/dui0471/i/semihosting/semihosting-operations?lang=en #[inline(always)] pub unsafe fn syscall(nr: usize, arg: &T) -> usize { - syscall1(nr, arg as *const T as usize) + unsafe { syscall1(nr, arg as *const T as usize) } } /// Performs a semihosting operation, takes one integer as an argument @@ -209,7 +209,9 @@ pub unsafe fn syscall1(_nr: usize, _arg: usize) -> usize { use core::arch::asm; let mut nr = _nr as u32; let arg = _arg as u32; - asm!("bkpt #0xab", inout("r0") nr, in("r1") arg, options(nostack, preserves_flags)); + unsafe { + asm!("bkpt #0xab", inout("r0") nr, in("r1") arg, options(nostack, preserves_flags)); + } nr as usize } #[cfg(all(thumb, feature = "no-semihosting"))] diff --git a/cortex-m/src/asm.rs b/cortex-m/src/asm.rs index 3a5695b06..3f8fd0e84 100644 --- a/cortex-m/src/asm.rs +++ b/cortex-m/src/asm.rs @@ -293,7 +293,9 @@ pub unsafe fn bootstrap(msp: *const u32, rv: *const u32) -> ! { /// a valid reset vector as the second word. #[inline] pub unsafe fn bootload(vector_table: *const u32) -> ! { - let msp = core::ptr::read_volatile(vector_table); - let rv = core::ptr::read_volatile(vector_table.offset(1)); - bootstrap(msp as *const u32, rv as *const u32); + unsafe { + let msp = core::ptr::read_volatile(vector_table); + let rv = core::ptr::read_volatile(vector_table.offset(1)); + bootstrap(msp as *const u32, rv as *const u32); + } } diff --git a/cortex-m/src/call_asm.rs b/cortex-m/src/call_asm.rs index 295277f38..be5699945 100644 --- a/cortex-m/src/call_asm.rs +++ b/cortex-m/src/call_asm.rs @@ -12,7 +12,7 @@ macro_rules! call_asm { #[cfg(not(feature = "inline-asm"))] () => { - extern "C" { + unsafe extern "C" { fn $func($($args: $tys),*) $(-> $ret)?; } diff --git a/cortex-m/src/critical_section.rs b/cortex-m/src/critical_section.rs index 6bedfffaa..c4fcf147d 100644 --- a/cortex-m/src/critical_section.rs +++ b/cortex-m/src/critical_section.rs @@ -19,6 +19,6 @@ unsafe impl Impl for SingleCoreCriticalSection { unsafe fn release(restore_state: RawRestoreState) { // NOTE: Fence guarantees are provided by primask::write_raw(), which performs a `compiler_fence(SeqCst)`. - primask::write_raw(restore_state); + unsafe { primask::write_raw(restore_state) }; } } diff --git a/cortex-m/src/interrupt.rs b/cortex-m/src/interrupt.rs index 48efd3659..a5c4b414c 100644 --- a/cortex-m/src/interrupt.rs +++ b/cortex-m/src/interrupt.rs @@ -65,7 +65,7 @@ where // disable interrupts disable(); - let r = f(unsafe { &CriticalSection::new() }); + let r = f(&unsafe { CriticalSection::new() }); unsafe { crate::register::primask::write_raw(primask); diff --git a/cortex-m/src/itm.rs b/cortex-m/src/itm.rs index 905aefb83..77bdc8ae1 100644 --- a/cortex-m/src/itm.rs +++ b/cortex-m/src/itm.rs @@ -8,11 +8,13 @@ use crate::peripheral::itm::Stim; // NOTE assumes that `bytes` is 32-bit aligned unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) { - let mut p = bytes.as_ptr(); - for _ in 0..bytes.len() { - while !stim.is_fifo_ready() {} - stim.write_u32(ptr::read(p)); - p = p.offset(1); + unsafe { + let mut p = bytes.as_ptr(); + for _ in 0..bytes.len() { + while !stim.is_fifo_ready() {} + stim.write_u32(ptr::read(p)); + p = p.offset(1); + } } } @@ -20,38 +22,40 @@ unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) { /// /// `buffer` must be 4-byte aligned. unsafe fn write_aligned_impl(port: &mut Stim, buffer: &[u8]) { - let len = buffer.len(); + unsafe { + let len = buffer.len(); - if len == 0 { - return; - } + if len == 0 { + return; + } - let split = len & !0b11; - #[allow(clippy::cast_ptr_alignment)] - write_words( - port, - slice::from_raw_parts(buffer.as_ptr() as *const u32, split >> 2), - ); + let split = len & !0b11; + #[allow(clippy::cast_ptr_alignment)] + write_words( + port, + slice::from_raw_parts(buffer.as_ptr() as *const u32, split >> 2), + ); - // 3 bytes or less left - let mut left = len & 0b11; - let mut ptr = buffer.as_ptr().add(split); + // 3 bytes or less left + let mut left = len & 0b11; + let mut ptr = buffer.as_ptr().add(split); - // at least 2 bytes left - if left > 1 { - while !port.is_fifo_ready() {} + // at least 2 bytes left + if left > 1 { + while !port.is_fifo_ready() {} - #[allow(clippy::cast_ptr_alignment)] - port.write_u16(ptr::read(ptr as *const u16)); + #[allow(clippy::cast_ptr_alignment)] + port.write_u16(ptr::read(ptr as *const u16)); - ptr = ptr.offset(2); - left -= 2; - } + ptr = ptr.offset(2); + left -= 2; + } - // final byte - if left == 1 { - while !port.is_fifo_ready() {} - port.write_u8(*ptr); + // final byte + if left == 1 { + while !port.is_fifo_ready() {} + port.write_u8(*ptr); + } } } diff --git a/cortex-m/src/macros.rs b/cortex-m/src/macros.rs index c4483b872..f89b339cd 100644 --- a/cortex-m/src/macros.rs +++ b/cortex-m/src/macros.rs @@ -121,8 +121,8 @@ const CPASS: () = (); /// /// fn foo() { /// // check that attributes are forwarded -/// singleton!(#[link_section = ".bss"] FOO: u8 = 0); -/// singleton!(#[link_section = ".bss"]: u8 = 1); +/// singleton!(#[unsafe(link_section = ".bss")] FOO: u8 = 0); +/// singleton!(#[unsafe(link_section = ".bss")]: u8 = 1); /// } /// ``` #[allow(dead_code)] diff --git a/cortex-m/src/peripheral/cbp.rs b/cortex-m/src/peripheral/cbp.rs index 5aee5444b..9121412aa 100644 --- a/cortex-m/src/peripheral/cbp.rs +++ b/cortex-m/src/peripheral/cbp.rs @@ -53,7 +53,9 @@ impl CBP { /// D-cache invalidate by MVA to PoC #[inline(always)] pub unsafe fn dcimvac(&mut self, mva: u32) { - self.dcimvac.write(mva); + unsafe { + self.dcimvac.write(mva); + } } /// D-cache invalidate by set-way @@ -61,19 +63,21 @@ impl CBP { /// `set` is masked to be between 0 and 3, and `way` between 0 and 511. #[inline(always)] pub unsafe fn dcisw(&mut self, set: u16, way: u16) { - // The ARMv7-M Architecture Reference Manual, as of Revision E.b, says these set/way - // operations have a register data format which depends on the implementation's - // associativity and number of sets. Specifically the 'way' and 'set' fields have - // offsets 32-log2(ASSOCIATIVITY) and log2(LINELEN) respectively. - // - // However, in Cortex-M7 devices, these offsets are fixed at 30 and 5, as per the Cortex-M7 - // Generic User Guide section 4.8.3. Since no other ARMv7-M implementations except the - // Cortex-M7 have a DCACHE or ICACHE at all, it seems safe to do the same thing as the - // CMSIS-Core implementation and use fixed values. - self.dcisw.write( - ((u32::from(way) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS) - | ((u32::from(set) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS), - ); + unsafe { + // The ARMv7-M Architecture Reference Manual, as of Revision E.b, says these set/way + // operations have a register data format which depends on the implementation's + // associativity and number of sets. Specifically the 'way' and 'set' fields have + // offsets 32-log2(ASSOCIATIVITY) and log2(LINELEN) respectively. + // + // However, in Cortex-M7 devices, these offsets are fixed at 30 and 5, as per the Cortex-M7 + // Generic User Guide section 4.8.3. Since no other ARMv7-M implementations except the + // Cortex-M7 have a DCACHE or ICACHE at all, it seems safe to do the same thing as the + // CMSIS-Core implementation and use fixed values. + self.dcisw.write( + ((u32::from(way) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS) + | ((u32::from(set) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS), + ); + } } /// D-cache clean by MVA to PoU diff --git a/cortex-m/src/peripheral/mod.rs b/cortex-m/src/peripheral/mod.rs index 93e8dc879..d65707c14 100644 --- a/cortex-m/src/peripheral/mod.rs +++ b/cortex-m/src/peripheral/mod.rs @@ -149,7 +149,7 @@ pub struct Peripherals { // NOTE `no_mangle` is used here to prevent linking different minor versions of this crate as that // would let you `take` the core peripherals more than once (one per minor version) -#[no_mangle] +#[unsafe(no_mangle)] static CORE_PERIPHERALS: () = (); /// Set to `true` when `take` or `steal` was called to make `Peripherals` a singleton. @@ -171,55 +171,57 @@ impl Peripherals { /// Unchecked version of `Peripherals::take` #[inline] pub unsafe fn steal() -> Self { - TAKEN = true; - - Peripherals { - #[cfg(feature = "cm7")] - AC: AC { - _marker: PhantomData, - }, - CBP: CBP { - _marker: PhantomData, - }, - CPUID: CPUID { - _marker: PhantomData, - }, - DCB: DCB { - _marker: PhantomData, - }, - DWT: DWT { - _marker: PhantomData, - }, - FPB: FPB { - _marker: PhantomData, - }, - FPU: FPU { - _marker: PhantomData, - }, - ICB: ICB { - _marker: PhantomData, - }, - ITM: ITM { - _marker: PhantomData, - }, - MPU: MPU { - _marker: PhantomData, - }, - NVIC: NVIC { - _marker: PhantomData, - }, - SAU: SAU { - _marker: PhantomData, - }, - SCB: SCB { - _marker: PhantomData, - }, - SYST: SYST { - _marker: PhantomData, - }, - TPIU: TPIU { - _marker: PhantomData, - }, + unsafe { + TAKEN = true; + + Peripherals { + #[cfg(feature = "cm7")] + AC: AC { + _marker: PhantomData, + }, + CBP: CBP { + _marker: PhantomData, + }, + CPUID: CPUID { + _marker: PhantomData, + }, + DCB: DCB { + _marker: PhantomData, + }, + DWT: DWT { + _marker: PhantomData, + }, + FPB: FPB { + _marker: PhantomData, + }, + FPU: FPU { + _marker: PhantomData, + }, + ICB: ICB { + _marker: PhantomData, + }, + ITM: ITM { + _marker: PhantomData, + }, + MPU: MPU { + _marker: PhantomData, + }, + NVIC: NVIC { + _marker: PhantomData, + }, + SAU: SAU { + _marker: PhantomData, + }, + SCB: SCB { + _marker: PhantomData, + }, + SYST: SYST { + _marker: PhantomData, + }, + TPIU: TPIU { + _marker: PhantomData, + }, + } } } } diff --git a/cortex-m/src/peripheral/nvic.rs b/cortex-m/src/peripheral/nvic.rs index 067c1d951..60411f0e7 100644 --- a/cortex-m/src/peripheral/nvic.rs +++ b/cortex-m/src/peripheral/nvic.rs @@ -124,9 +124,11 @@ impl NVIC { where I: InterruptNumber, { - let nr = interrupt.number(); - // NOTE(ptr) this is a write to a stateless register - (*Self::PTR).iser[usize::from(nr / 32)].write(1 << (nr % 32)) + unsafe { + let nr = interrupt.number(); + // NOTE(ptr) this is a write to a stateless register + (*Self::PTR).iser[usize::from(nr / 32)].write(1 << (nr % 32)) + } } /// Returns the NVIC priority of `interrupt` @@ -224,20 +226,22 @@ impl NVIC { where I: InterruptNumber, { - #[cfg(not(armv6m))] - { - let nr = interrupt.number(); - self.ipr[usize::from(nr)].write(prio) - } - - #[cfg(armv6m)] - { - self.ipr[Self::ipr_index(interrupt)].modify(|value| { - let mask = 0x0000_00ff << Self::ipr_shift(interrupt); - let prio = u32::from(prio) << Self::ipr_shift(interrupt); - - (value & !mask) | prio - }) + unsafe { + #[cfg(not(armv6m))] + { + let nr = interrupt.number(); + self.ipr[usize::from(nr)].write(prio) + } + + #[cfg(armv6m)] + { + self.ipr[Self::ipr_index(interrupt)].modify(|value| { + let mask = 0x0000_00ff << Self::ipr_shift(interrupt); + let prio = u32::from(prio) << Self::ipr_shift(interrupt); + + (value & !mask) | prio + }) + } } } diff --git a/cortex-m/src/peripheral/scb.rs b/cortex-m/src/peripheral/scb.rs index 4cd4742cb..30b9e7402 100644 --- a/cortex-m/src/peripheral/scb.rs +++ b/cortex-m/src/peripheral/scb.rs @@ -317,7 +317,7 @@ impl SCB { cbp.iciallu(); // Enable I-cache - extern "C" { + unsafe extern "C" { // see asm-v7m.s fn __enable_icache(); } @@ -392,7 +392,7 @@ impl SCB { unsafe { self.invalidate_dcache(cpuid) }; // Now turn on the D-cache - extern "C" { + unsafe extern "C" { // see asm-v7m.s fn __enable_dcache(); } @@ -442,21 +442,23 @@ impl SCB { /// It's used immediately before enabling the dcache, but not exported publicly. #[inline] unsafe fn invalidate_dcache(&mut self, cpuid: &mut CPUID) { - // NOTE(unsafe): No races as all CBP registers are write-only and stateless - let mut cbp = CBP::new(); + unsafe { + // NOTE(unsafe): No races as all CBP registers are write-only and stateless + let mut cbp = CBP::new(); - // Read number of sets and ways - let (sets, ways) = cpuid.cache_num_sets_ways(0, CsselrCacheType::DataOrUnified); + // Read number of sets and ways + let (sets, ways) = cpuid.cache_num_sets_ways(0, CsselrCacheType::DataOrUnified); - // Invalidate entire D-cache - for set in 0..sets { - for way in 0..ways { - cbp.dcisw(set, way); + // Invalidate entire D-cache + for set in 0..sets { + for way in 0..ways { + cbp.dcisw(set, way); + } } - } - crate::asm::dsb(); - crate::asm::isb(); + crate::asm::dsb(); + crate::asm::isb(); + } } /// Cleans the entire D-cache. @@ -540,37 +542,39 @@ impl SCB { /// a runtime-dependent `panic!()` call. #[inline] pub unsafe fn invalidate_dcache_by_address(&mut self, addr: usize, size: usize) { - // No-op zero sized operations - if size == 0 { - return; - } + unsafe { + // No-op zero sized operations + if size == 0 { + return; + } - // NOTE(unsafe): No races as all CBP registers are write-only and stateless - let mut cbp = CBP::new(); + // NOTE(unsafe): No races as all CBP registers are write-only and stateless + let mut cbp = CBP::new(); - // dminline is log2(num words), so 2**dminline * 4 gives size in bytes - let dminline = CPUID::cache_dminline(); - let line_size = (1 << dminline) * 4; + // dminline is log2(num words), so 2**dminline * 4 gives size in bytes + let dminline = CPUID::cache_dminline(); + let line_size = (1 << dminline) * 4; - debug_assert!((addr & (line_size - 1)) == 0); - debug_assert!((size & (line_size - 1)) == 0); + debug_assert!((addr & (line_size - 1)) == 0); + debug_assert!((size & (line_size - 1)) == 0); - crate::asm::dsb(); + crate::asm::dsb(); - // Find number of cache lines to invalidate - let num_lines = ((size - 1) / line_size) + 1; + // Find number of cache lines to invalidate + let num_lines = ((size - 1) / line_size) + 1; - // Compute address of first cache line - let mask = 0xFFFF_FFFF - (line_size - 1); - let mut addr = addr & mask; + // Compute address of first cache line + let mask = 0xFFFF_FFFF - (line_size - 1); + let mut addr = addr & mask; - for _ in 0..num_lines { - cbp.dcimvac(addr as u32); - addr += line_size; - } + for _ in 0..num_lines { + cbp.dcimvac(addr as u32); + addr += line_size; + } - crate::asm::dsb(); - crate::asm::isb(); + crate::asm::dsb(); + crate::asm::isb(); + } } /// Invalidates an object from the D-cache. @@ -608,7 +612,9 @@ impl SCB { /// a runtime-dependent `panic!()` call. #[inline] pub unsafe fn invalidate_dcache_by_ref(&mut self, obj: &mut T) { - self.invalidate_dcache_by_address(obj as *const T as usize, core::mem::size_of::()); + unsafe { + self.invalidate_dcache_by_address(obj as *const T as usize, core::mem::size_of::()); + } } /// Invalidates a slice from the D-cache. @@ -646,7 +652,12 @@ impl SCB { /// a runtime-dependent `panic!()` call. #[inline] pub unsafe fn invalidate_dcache_by_slice(&mut self, slice: &mut [T]) { - self.invalidate_dcache_by_address(slice.as_ptr() as usize, core::mem::size_of_val(slice)); + unsafe { + self.invalidate_dcache_by_address( + slice.as_ptr() as usize, + core::mem::size_of_val(slice), + ); + } } /// Cleans D-cache by address. @@ -1000,32 +1011,34 @@ impl SCB { /// [`register::basepri`](crate::register::basepri)) and compromise memory safety. #[inline] pub unsafe fn set_priority(&mut self, system_handler: SystemHandler, prio: u8) { - let index = system_handler as u8; + unsafe { + let index = system_handler as u8; - #[cfg(not(armv6m))] - { - // NOTE(unsafe): Index is bounded to [4,15] by SystemHandler design. - // TODO: Review it after rust-lang/rust/issues/13926 will be fixed. - let priority_ref = (*Self::PTR).shpr.get_unchecked(usize::from(index - 4)); + #[cfg(not(armv6m))] + { + // NOTE(unsafe): Index is bounded to [4,15] by SystemHandler design. + // TODO: Review it after rust-lang/rust/issues/13926 will be fixed. + let priority_ref = (*Self::PTR).shpr.get_unchecked(usize::from(index - 4)); - priority_ref.write(prio) - } + priority_ref.write(prio) + } - #[cfg(armv6m)] - { - // NOTE(unsafe): Index is bounded to [11,15] by SystemHandler design. - // TODO: Review it after rust-lang/rust/issues/13926 will be fixed. - let priority_ref = (*Self::PTR) - .shpr - .get_unchecked(usize::from((index - 8) / 4)); + #[cfg(armv6m)] + { + // NOTE(unsafe): Index is bounded to [11,15] by SystemHandler design. + // TODO: Review it after rust-lang/rust/issues/13926 will be fixed. + let priority_ref = (*Self::PTR) + .shpr + .get_unchecked(usize::from((index - 8) / 4)); - priority_ref.modify(|value| { - let shift = 8 * (index % 4); - let mask = 0x0000_00ff << shift; - let prio = u32::from(prio) << shift; + priority_ref.modify(|value| { + let shift = 8 * (index % 4); + let mask = 0x0000_00ff << shift; + let prio = u32::from(prio) << shift; - (value & !mask) | prio - }); + (value & !mask) | prio + }); + } } } From 88c5106cfcc2174ed2bafc9bc5396b1a191add50 Mon Sep 17 00:00:00 2001 From: Wren Turkal Date: Tue, 10 Mar 2026 17:00:05 -0700 Subject: [PATCH 4/6] Bump all crates to edition 2024. I also explicitly set the rustfmt style to 2021 to prevent formatting churn in this same commit. --- cortex-m-rt/.rustfmt.toml | 1 + cortex-m-rt/Cargo.toml | 2 +- cortex-m-semihosting/Cargo.toml | 2 +- cortex-m-types/Cargo.toml | 2 +- cortex-m/.rustfmt.toml | 1 + cortex-m/Cargo.toml | 2 +- panic-itm/Cargo.toml | 2 +- panic-semihosting/Cargo.toml | 2 +- testsuite/.rustfmt.toml | 1 + testsuite/Cargo.toml | 2 +- xtask/.rustfmt.toml | 1 + xtask/Cargo.toml | 2 +- 12 files changed, 12 insertions(+), 8 deletions(-) create mode 100644 cortex-m-rt/.rustfmt.toml create mode 100644 cortex-m/.rustfmt.toml create mode 100644 testsuite/.rustfmt.toml create mode 100644 xtask/.rustfmt.toml diff --git a/cortex-m-rt/.rustfmt.toml b/cortex-m-rt/.rustfmt.toml new file mode 100644 index 000000000..8153a3d0b --- /dev/null +++ b/cortex-m-rt/.rustfmt.toml @@ -0,0 +1 @@ +style_edition = "2021" diff --git a/cortex-m-rt/Cargo.toml b/cortex-m-rt/Cargo.toml index fb16592d9..1ba4f45b3 100644 --- a/cortex-m-rt/Cargo.toml +++ b/cortex-m-rt/Cargo.toml @@ -10,7 +10,7 @@ repository = "https://github.com/rust-embedded/cortex-m" version = "0.7.5" autoexamples = true links = "cortex-m-rt" # Prevent multiple versions of cortex-m-rt being linked -edition = "2021" +edition = "2024" rust-version = "1.85" [dependencies] diff --git a/cortex-m-semihosting/Cargo.toml b/cortex-m-semihosting/Cargo.toml index dc35d716d..7e1e212c4 100644 --- a/cortex-m-semihosting/Cargo.toml +++ b/cortex-m-semihosting/Cargo.toml @@ -8,7 +8,7 @@ name = "cortex-m-semihosting" readme = "README.md" repository = "https://github.com/rust-embedded/cortex-m" version = "0.5.0" -edition = "2021" +edition = "2024" rust-version = "1.85" [features] diff --git a/cortex-m-types/Cargo.toml b/cortex-m-types/Cargo.toml index e40f47899..e415efab2 100644 --- a/cortex-m-types/Cargo.toml +++ b/cortex-m-types/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "cortex-m-types" version = "0.1.0" -edition = "2021" +edition = "2024" repository = "https://github.com/rust-embedded/cortex-m" categories = ["embedded", "hardware-support", "no-std"] description = "Low level access to Cortex-M processors" diff --git a/cortex-m/.rustfmt.toml b/cortex-m/.rustfmt.toml new file mode 100644 index 000000000..8153a3d0b --- /dev/null +++ b/cortex-m/.rustfmt.toml @@ -0,0 +1 @@ +style_edition = "2021" diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml index c449ac59c..80eadd609 100644 --- a/cortex-m/Cargo.toml +++ b/cortex-m/Cargo.toml @@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0" name = "cortex-m" readme = "README.md" repository = "https://github.com/rust-embedded/cortex-m" -edition = "2021" +edition = "2024" version = "0.7.7" links = "cortex-m" # prevent multiple versions of this crate to be linked together rust-version = "1.85" diff --git a/panic-itm/Cargo.toml b/panic-itm/Cargo.toml index b1a11647d..6996a1d03 100644 --- a/panic-itm/Cargo.toml +++ b/panic-itm/Cargo.toml @@ -6,7 +6,7 @@ keywords = ["panic-impl", "panic-handler", "ITM", "ARM", "Cortex-M"] license = "MIT OR Apache-2.0" name = "panic-itm" repository = "https://github.com/rust-embedded/cortex-m" -edition = "2021" +edition = "2024" version = "0.4.2" rust-version = "1.85" diff --git a/panic-semihosting/Cargo.toml b/panic-semihosting/Cargo.toml index 6b8a32cc4..2e2248f53 100644 --- a/panic-semihosting/Cargo.toml +++ b/panic-semihosting/Cargo.toml @@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0" name = "panic-semihosting" repository = "https://github.com/rust-embedded/cortex-m" version = "0.6.0" -edition = "2021" +edition = "2024" rust-version = "1.85" [dependencies] diff --git a/testsuite/.rustfmt.toml b/testsuite/.rustfmt.toml new file mode 100644 index 000000000..8153a3d0b --- /dev/null +++ b/testsuite/.rustfmt.toml @@ -0,0 +1 @@ +style_edition = "2021" diff --git a/testsuite/Cargo.toml b/testsuite/Cargo.toml index cb619649e..84661f0ea 100644 --- a/testsuite/Cargo.toml +++ b/testsuite/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "testsuite" publish = false -edition = "2021" +edition = "2024" version = "0.1.0" rust-version = "1.85" diff --git a/xtask/.rustfmt.toml b/xtask/.rustfmt.toml new file mode 100644 index 000000000..8153a3d0b --- /dev/null +++ b/xtask/.rustfmt.toml @@ -0,0 +1 @@ +style_edition = "2021" diff --git a/xtask/Cargo.toml b/xtask/Cargo.toml index 88f58a410..25a4a4932 100644 --- a/xtask/Cargo.toml +++ b/xtask/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "xtask" version = "0.0.0" -edition = "2021" +edition = "2024" publish = false rust-version = "1.85" From 4ccdf2ade305941bbb052ac47f0a0762ad8b6d16 Mon Sep 17 00:00:00 2001 From: Wren Turkal Date: Tue, 10 Mar 2026 17:20:42 -0700 Subject: [PATCH 5/6] Bump rustfmt style to 2024. Needed to update the assembled libs because the formatting touched the asm boilerplate. --- cortex-m-rt/.rustfmt.toml | 1 - cortex-m-rt/examples/hard-fault-trampoline.rs | 2 +- cortex-m-rt/examples/override-exception.rs | 2 +- cortex-m-rt/examples/unsafe-hard-fault.rs | 2 +- cortex-m-rt/examples/unsafety.rs | 2 +- cortex-m-rt/examples/warnings.rs | 2 +- cortex-m/.rustfmt.toml | 1 - cortex-m/asm/inline.rs | 4 ++-- cortex-m/bin/thumbv6m-none-eabi-lto.a | Bin 11256 -> 11256 bytes cortex-m/bin/thumbv7em-none-eabi-lto.a | Bin 15340 -> 15340 bytes cortex-m/bin/thumbv7em-none-eabihf-lto.a | Bin 16168 -> 16168 bytes cortex-m/bin/thumbv7m-none-eabi-lto.a | Bin 14196 -> 14192 bytes cortex-m/bin/thumbv8m.base-none-eabi-lto.a | Bin 14340 -> 14340 bytes cortex-m/bin/thumbv8m.main-none-eabi-lto.a | Bin 18732 -> 18728 bytes cortex-m/bin/thumbv8m.main-none-eabihf-lto.a | Bin 19512 -> 19508 bytes cortex-m/src/critical_section.rs | 2 +- cortex-m/src/delay.rs | 2 +- cortex-m/src/peripheral/scb.rs | 4 ++-- cortex-m/src/register/primask.rs | 2 +- testsuite/.rustfmt.toml | 1 - testsuite/src/main.rs | 2 +- xtask/.rustfmt.toml | 1 - xtask/src/main.rs | 8 ++++++-- 23 files changed, 19 insertions(+), 19 deletions(-) delete mode 100644 cortex-m-rt/.rustfmt.toml delete mode 100644 cortex-m/.rustfmt.toml delete mode 100644 testsuite/.rustfmt.toml delete mode 100644 xtask/.rustfmt.toml diff --git a/cortex-m-rt/.rustfmt.toml b/cortex-m-rt/.rustfmt.toml deleted file mode 100644 index 8153a3d0b..000000000 --- a/cortex-m-rt/.rustfmt.toml +++ /dev/null @@ -1 +0,0 @@ -style_edition = "2021" diff --git a/cortex-m-rt/examples/hard-fault-trampoline.rs b/cortex-m-rt/examples/hard-fault-trampoline.rs index 995e7ce29..e2fb56d4f 100644 --- a/cortex-m-rt/examples/hard-fault-trampoline.rs +++ b/cortex-m-rt/examples/hard-fault-trampoline.rs @@ -10,7 +10,7 @@ extern crate cortex_m_rt; extern crate panic_halt; use core::arch::asm; -use cortex_m_rt::{entry, exception, ExceptionFrame}; +use cortex_m_rt::{ExceptionFrame, entry, exception}; // This defines both `HardFault` and `_HardFault`. Both should have // link_section attributes placing them at the end of the .text section, diff --git a/cortex-m-rt/examples/override-exception.rs b/cortex-m-rt/examples/override-exception.rs index 3190b77d5..46783d078 100644 --- a/cortex-m-rt/examples/override-exception.rs +++ b/cortex-m-rt/examples/override-exception.rs @@ -9,7 +9,7 @@ extern crate cortex_m_rt as rt; extern crate panic_halt; use cortex_m::asm; -use rt::{entry, exception, ExceptionFrame}; +use rt::{ExceptionFrame, entry, exception}; #[entry] fn main() -> ! { diff --git a/cortex-m-rt/examples/unsafe-hard-fault.rs b/cortex-m-rt/examples/unsafe-hard-fault.rs index b1d48f340..ee4cad967 100644 --- a/cortex-m-rt/examples/unsafe-hard-fault.rs +++ b/cortex-m-rt/examples/unsafe-hard-fault.rs @@ -5,7 +5,7 @@ extern crate cortex_m_rt; extern crate panic_halt; -use cortex_m_rt::{entry, exception, ExceptionFrame}; +use cortex_m_rt::{ExceptionFrame, entry, exception}; #[entry] fn foo() -> ! { diff --git a/cortex-m-rt/examples/unsafety.rs b/cortex-m-rt/examples/unsafety.rs index 444de6c96..86eaa5f35 100644 --- a/cortex-m-rt/examples/unsafety.rs +++ b/cortex-m-rt/examples/unsafety.rs @@ -7,7 +7,7 @@ extern crate cortex_m_rt; extern crate panic_halt; -use cortex_m_rt::{entry, exception, ExceptionFrame}; +use cortex_m_rt::{ExceptionFrame, entry, exception}; #[entry] unsafe fn main() -> ! { diff --git a/cortex-m-rt/examples/warnings.rs b/cortex-m-rt/examples/warnings.rs index abf4a2f24..3e65041a3 100644 --- a/cortex-m-rt/examples/warnings.rs +++ b/cortex-m-rt/examples/warnings.rs @@ -11,7 +11,7 @@ extern crate cortex_m_rt; extern crate panic_halt; -use cortex_m_rt::{entry, exception, interrupt, pre_init, ExceptionFrame}; +use cortex_m_rt::{ExceptionFrame, entry, exception, interrupt, pre_init}; #[allow(non_camel_case_types)] enum interrupt { diff --git a/cortex-m/.rustfmt.toml b/cortex-m/.rustfmt.toml deleted file mode 100644 index 8153a3d0b..000000000 --- a/cortex-m/.rustfmt.toml +++ /dev/null @@ -1 +0,0 @@ -style_edition = "2021" diff --git a/cortex-m/asm/inline.rs b/cortex-m/asm/inline.rs index 37e2cf463..3444c62d5 100644 --- a/cortex-m/asm/inline.rs +++ b/cortex-m/asm/inline.rs @@ -7,7 +7,7 @@ //! applicable. use core::arch::asm; -use core::sync::atomic::{compiler_fence, Ordering}; +use core::sync::atomic::{Ordering, compiler_fence}; #[inline(always)] pub unsafe fn __bkpt() { @@ -228,7 +228,7 @@ pub use self::v7m::*; #[cfg(any(armv7m, armv8m_main))] mod v7m { use core::arch::asm; - use core::sync::atomic::{compiler_fence, Ordering}; + use core::sync::atomic::{Ordering, compiler_fence}; #[inline(always)] pub unsafe fn __basepri_max(val: u8) { diff --git a/cortex-m/bin/thumbv6m-none-eabi-lto.a b/cortex-m/bin/thumbv6m-none-eabi-lto.a index b07a93295743d6a6745baf82c269fb4800f9363e..529cd646660a0baff58d8a03a2ae6d93122045b2 100644 GIT binary patch delta 76 zcmV-S0JH!2SNK=3w+J9&GcsjmGBIW{Ic7F9G&L|aW@a#BHZ(FfH8(XmF*0Pc*9eOr i8CM_S`wsSbA62C^`BGhly4~X&AKdhW-wm^SD18GbRUOL! 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ZsVlXsiWo0%pH)S

2W?;tLHwI&6;#o4nR00029Ge!Xh)^8x} diff --git a/cortex-m/src/critical_section.rs b/cortex-m/src/critical_section.rs index c4fcf147d..039d12a0b 100644 --- a/cortex-m/src/critical_section.rs +++ b/cortex-m/src/critical_section.rs @@ -1,4 +1,4 @@ -use critical_section::{set_impl, Impl, RawRestoreState}; +use critical_section::{Impl, RawRestoreState, set_impl}; use crate::interrupt; use crate::register::primask; diff --git a/cortex-m/src/delay.rs b/cortex-m/src/delay.rs index 4dcc1345c..969653097 100644 --- a/cortex-m/src/delay.rs +++ b/cortex-m/src/delay.rs @@ -1,6 +1,6 @@ //! A delay driver based on SysTick. -use crate::peripheral::{syst::SystClkSource, SYST}; +use crate::peripheral::{SYST, syst::SystClkSource}; use eh1::delay::DelayNs; /// System timer (SysTick) as a delay provider. diff --git a/cortex-m/src/peripheral/scb.rs b/cortex-m/src/peripheral/scb.rs index 30b9e7402..81e1b8b5d 100644 --- a/cortex-m/src/peripheral/scb.rs +++ b/cortex-m/src/peripheral/scb.rs @@ -4,13 +4,13 @@ use core::ptr; use volatile_register::RW; -#[cfg(not(armv6m))] -use super::cpuid::CsselrCacheType; #[cfg(not(armv6m))] use super::CBP; #[cfg(not(armv6m))] use super::CPUID; use super::SCB; +#[cfg(not(armv6m))] +use super::cpuid::CsselrCacheType; #[cfg(feature = "serde")] use serde::{Deserialize, Serialize}; diff --git a/cortex-m/src/register/primask.rs b/cortex-m/src/register/primask.rs index 0099c69b0..28e31d8c4 100644 --- a/cortex-m/src/register/primask.rs +++ b/cortex-m/src/register/primask.rs @@ -3,7 +3,7 @@ #[cfg(cortex_m)] use core::arch::asm; #[cfg(cortex_m)] -use core::sync::atomic::{compiler_fence, Ordering}; +use core::sync::atomic::{Ordering, compiler_fence}; /// All exceptions with configurable priority are ... #[derive(Clone, Copy, Debug, Eq, PartialEq)] diff --git a/testsuite/.rustfmt.toml b/testsuite/.rustfmt.toml deleted file mode 100644 index 8153a3d0b..000000000 --- a/testsuite/.rustfmt.toml +++ /dev/null @@ -1 +0,0 @@ -style_edition = "2021" diff --git a/testsuite/src/main.rs b/testsuite/src/main.rs index 143706b51..5aa220379 100644 --- a/testsuite/src/main.rs +++ b/testsuite/src/main.rs @@ -25,7 +25,7 @@ fn PendSV() { #[minitest::tests] mod tests { - use crate::{Ordering, EXCEPTION_FLAG}; + use crate::{EXCEPTION_FLAG, Ordering}; use minitest::log; #[init] diff --git a/xtask/.rustfmt.toml b/xtask/.rustfmt.toml deleted file mode 100644 index 8153a3d0b..000000000 --- a/xtask/.rustfmt.toml +++ /dev/null @@ -1 +0,0 @@ -style_edition = "2021" diff --git a/xtask/src/main.rs b/xtask/src/main.rs index 26dce31b4..01da649bd 100644 --- a/xtask/src/main.rs +++ b/xtask/src/main.rs @@ -12,8 +12,12 @@ fn main() { eprintln!(); eprintln!("subcommands:"); eprintln!(" assemble Reassemble the pre-built artifacts"); - eprintln!(" check-blobs Check that the pre-built artifacts are up-to-date and reproducible"); - eprintln!(" check-host-side Build the crate in a non-Cortex-M host application and check host side usage of certain types"); + eprintln!( + " check-blobs Check that the pre-built artifacts are up-to-date and reproducible" + ); + eprintln!( + " check-host-side Build the crate in a non-Cortex-M host application and check host side usage of certain types" + ); process::exit(1); } } From f2ad315d4c3a33b05410e72e82243346f5691aae Mon Sep 17 00:00:00 2001 From: Wren Turkal Date: Tue, 10 Mar 2026 21:47:50 -0700 Subject: [PATCH 6/6] Bump resolver version to the default for 2024 edition. --- Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index 82eba3749..d025be626 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,5 +1,5 @@ [workspace] -resolver = "2" +resolver = "3" members = [ "cortex-m", "cortex-m-types",