[LLVM][CodeGen][AArch64] Prevent invalid extract_elt within combineStoreValueFPToInt.

This reverts a small part of llvm#147707
that triggers an isel failure because we cannot extract an >i32 element
into an i64 result.

Author: paulwalker-arm

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -23988,13 +23988,6 @@ static SDValue combineStoreValueFPToInt(StoreSDNode *ST,
   SDValue VecFP = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecSrcVT, FPSrc);
   SDValue VecConv = DAG.getNode(Value.getOpcode(), DL, VecDstVT, VecFP);
 
-  if (ST->isTruncatingStore()) {
-    EVT NewVecDstVT = EVT::getVectorVT(
-        *DAG.getContext(), ST->getMemoryVT(),
-        VecDstVT.getFixedSizeInBits() / ST->getMemoryVT().getFixedSizeInBits());
-    VecConv = DAG.getNode(AArch64ISD::NVCAST, DL, NewVecDstVT, VecConv);
-  }
-
   SDValue Zero = DAG.getVectorIdxConstant(0, DL);
   SDValue Extracted =
       DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, VecConv, Zero);

llvm/test/CodeGen/AArch64/tbl-loops.ll

@@ -64,7 +64,8 @@ define void @loop1(ptr noalias nocapture noundef writeonly %dst, ptr nocapture n
 ; CHECK-NEXT:    fcsel s2, s0, s3, mi
 ; CHECK-NEXT:    subs w10, w10, #1
 ; CHECK-NEXT:    fcvtzs s2, s2
-; CHECK-NEXT:    st1 { v2.b }[0], [x9], #1
+; CHECK-NEXT:    fmov w11, s2
+; CHECK-NEXT:    strb w11, [x9], #1
 ; CHECK-NEXT:    b.ne .LBB0_7
 ; CHECK-NEXT:  .LBB0_8: // %for.cond.cleanup
 ; CHECK-NEXT:    ret