From 95fb046e50fbb0b02ce047478714427256cb5c0f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Teichgr=C3=A4ber?= Date: Wed, 25 Feb 2026 11:17:32 +0100 Subject: [PATCH 1/5] lib/stm32-svd: update submodule --- lib/stm32-svd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/stm32-svd b/lib/stm32-svd index e6db8e32d5..bfed180b63 160000 --- a/lib/stm32-svd +++ b/lib/stm32-svd @@ -1 +1 @@ -Subproject commit e6db8e32d5d42293a528434ec12e7f88479a8649 +Subproject commit bfed180b639863db414221bdb6aa77e198f464f5 From 4776e4a91b46ffaab7aaa3ce0468289587a27db7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Teichgr=C3=A4ber?= Date: Fri, 28 Nov 2025 21:26:16 +0100 Subject: [PATCH 2/5] targets/nucleo-f722ze.json: add build-tag stm32f722, change stm32f7x2.s to ..722.s In stm32-rs, stm32f7x2.svd got replaced by stm32f722.svd and stm32f732.svd. This change adjusts the target definition where stm32f7x2 is used, --- targets/nucleo-f722ze.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/nucleo-f722ze.json b/targets/nucleo-f722ze.json index f426b332d7..88d7aed3ec 100644 --- a/targets/nucleo-f722ze.json +++ b/targets/nucleo-f722ze.json @@ -1,10 +1,10 @@ { "inherits": ["cortex-m7"], - "build-tags": ["nucleof722ze", "stm32f7x2", "stm32f7", "stm32"], + "build-tags": ["nucleof722ze", "stm32f722", "stm32f7x2", "stm32f7", "stm32"], "serial": "uart", "linkerscript": "targets/stm32f7x2zetx.ld", "extra-files": [ - "src/device/stm32/stm32f7x2.s" + "src/device/stm32/stm32f722.s" ], "flash-method": "openocd", "openocd-interface": "stlink-v2-1", From ea7989dcd6f4048300fdda5091e27a0020596391 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Teichgr=C3=A4ber?= Date: Mon, 23 Feb 2026 16:35:07 +0100 Subject: [PATCH 3/5] targets/swan: rename group build tag stm32l4x5 => stm32l4y5 to avoid clash with stm32 device name Previously, there was no specific stm32f4r5.svd in lib/stm32-svd, just stm32f4x5.svd was used; now, both files are present. This means that the existing build-tag stm32f4r5 will include the device/stm32/stm32f4r5.go file, and the additional build-tag stm32f4x5 would include the device/stm32/stm32f4x5.go file as well, resulting in build conflicts. Renaming just the tag, which is used in src/machine, and src/runtime, into stm32f4y5 solves this issue. --- src/machine/machine_stm32l4x5.go | 2 +- src/runtime/runtime_stm32l4x5.go | 2 +- targets/swan.json | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/machine/machine_stm32l4x5.go b/src/machine/machine_stm32l4x5.go index c8c550c3da..28fb5da334 100644 --- a/src/machine/machine_stm32l4x5.go +++ b/src/machine/machine_stm32l4x5.go @@ -1,4 +1,4 @@ -//go:build stm32l4x5 +//go:build stm32l4y5 package machine diff --git a/src/runtime/runtime_stm32l4x5.go b/src/runtime/runtime_stm32l4x5.go index 273eb726f5..c7c242975f 100644 --- a/src/runtime/runtime_stm32l4x5.go +++ b/src/runtime/runtime_stm32l4x5.go @@ -1,4 +1,4 @@ -//go:build stm32 && stm32l4x5 +//go:build stm32 && stm32l4y5 package runtime diff --git a/targets/swan.json b/targets/swan.json index fbb46a5569..92587690e8 100644 --- a/targets/swan.json +++ b/targets/swan.json @@ -1,6 +1,6 @@ { "inherits": ["cortex-m4"], - "build-tags": ["swan", "stm32l4r5", "stm32l4x5", "stm32l4", "stm32"], + "build-tags": ["swan", "stm32l4r5", "stm32l4y5", "stm32l4", "stm32"], "serial": "uart", "linkerscript": "targets/stm32l4x5.ld", "extra-files": [ From 9326152446b254a179d15fbb1bb575a2a19e8c4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Teichgr=C3=A4ber?= Date: Mon, 23 Feb 2026 16:50:34 +0100 Subject: [PATCH 4/5] machine: sync stm32g0 with updated stm32 device files USART.ISR_FIFO_ENABLED => USART.ISR IRQ_TIM6_DAC => IRQ_TIM6_DAC_LPTIM1 ADC.CHSELR => ADC.CHSELR0 (alternate registers 0/1) --- src/machine/machine_stm32_adc_g0.go | 2 +- src/machine/machine_stm32_uart.go | 2 +- src/machine/machine_stm32g0.go | 6 +- src/machine/machine_stm32g0_uart.go | 86 ----------------------------- 4 files changed, 5 insertions(+), 91 deletions(-) delete mode 100644 src/machine/machine_stm32g0_uart.go diff --git a/src/machine/machine_stm32_adc_g0.go b/src/machine/machine_stm32_adc_g0.go index d8cca3c8df..7d7150ade1 100644 --- a/src/machine/machine_stm32_adc_g0.go +++ b/src/machine/machine_stm32_adc_g0.go @@ -123,7 +123,7 @@ func (a ADC) Get() uint16 { // Select the channel to convert using CHSELR // CHSELR uses a bitfield where bit N = 1 enables channel N - stm32.ADC.CHSELR.Set(1 << ch) + stm32.ADC.CHSELR0.Set(1 << ch) // Wait for channel configuration ready for stm32.ADC.GetISR_CCRDY() == 0 { diff --git a/src/machine/machine_stm32_uart.go b/src/machine/machine_stm32_uart.go index 6d37582448..6beafe4e1c 100644 --- a/src/machine/machine_stm32_uart.go +++ b/src/machine/machine_stm32_uart.go @@ -1,4 +1,4 @@ -//go:build stm32 && !stm32g0 +//go:build stm32 package machine diff --git a/src/machine/machine_stm32g0.go b/src/machine/machine_stm32g0.go index b338faef1a..530c77aade 100644 --- a/src/machine/machine_stm32g0.go +++ b/src/machine/machine_stm32g0.go @@ -230,7 +230,7 @@ func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 { func (uart *UART) setRegisters() { uart.rxReg = &uart.Bus.RDR uart.txReg = &uart.Bus.TDR - uart.statusReg = &uart.Bus.ISR_FIFO_ENABLED + uart.statusReg = &uart.Bus.ISR uart.txEmptyFlag = stm32.USART_ISR_TXE } @@ -508,7 +508,7 @@ func (t *TIM) registerUPInterrupt() interrupt.Interrupt { case &TIM3: return interrupt.New(stm32.IRQ_TIM3_TIM4, TIM3.handleUPInterrupt) case &TIM6: - return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt) + return interrupt.New(stm32.IRQ_TIM6_DAC_LPTIM1, TIM6.handleUPInterrupt) case &TIM7: return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt) case &TIM14: @@ -533,7 +533,7 @@ func (t *TIM) registerOCInterrupt() interrupt.Interrupt { case &TIM3: return interrupt.New(stm32.IRQ_TIM3_TIM4, TIM3.handleOCInterrupt) case &TIM6: - return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt) + return interrupt.New(stm32.IRQ_TIM6_DAC_LPTIM1, TIM6.handleOCInterrupt) case &TIM7: return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt) case &TIM14: diff --git a/src/machine/machine_stm32g0_uart.go b/src/machine/machine_stm32g0_uart.go deleted file mode 100644 index 18544c3ecd..0000000000 --- a/src/machine/machine_stm32g0_uart.go +++ /dev/null @@ -1,86 +0,0 @@ -//go:build stm32g0 - -package machine - -// Peripheral abstraction layer for UARTs on the stm32g0 family. - -import ( - "device/stm32" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -// UART representation -type UART struct { - Buffer *RingBuffer - Bus *stm32.USART_Type - Interrupt interrupt.Interrupt - TxAltFuncSelector uint8 - RxAltFuncSelector uint8 - - // Registers specific to the chip - rxReg *volatile.Register32 - txReg *volatile.Register32 - statusReg *volatile.Register32 - txEmptyFlag uint32 -} - -// Configure the UART. -func (uart *UART) Configure(config UARTConfig) { - // Default baud rate to 115200. - if config.BaudRate == 0 { - config.BaudRate = 115200 - } - - // Set the GPIO pins to defaults if they're not set - if config.TX == 0 && config.RX == 0 { - config.TX = UART_TX_PIN - config.RX = UART_RX_PIN - } - - // STM32 families have different, but compatible, registers for - // basic UART functions. For each family populate the registers - // into `uart`. - uart.setRegisters() - - // Enable USART clock - enableAltFuncClock(unsafe.Pointer(uart.Bus)) - - uart.configurePins(config) - - // Set baud rate - uart.SetBaudRate(config.BaudRate) - - // Enable USART port, tx, rx and rx interrupts - // STM32G0 uses CR1_FIFO_ENABLED register - uart.Bus.CR1_FIFO_ENABLED.Set(stm32.USART_CR1_TE | stm32.USART_CR1_RE | stm32.USART_CR1_RXNEIE | stm32.USART_CR1_UE) - - // Enable RX IRQ - uart.Interrupt.SetPriority(0xc0) - uart.Interrupt.Enable() -} - -// handleInterrupt should be called from the appropriate interrupt handler for -// this UART instance. -func (uart *UART) handleInterrupt(interrupt.Interrupt) { - uart.Receive(byte((uart.rxReg.Get() & 0xFF))) -} - -// SetBaudRate sets the communication speed for the UART. Defer to chip-specific -// routines for calculation -func (uart *UART) SetBaudRate(br uint32) { - divider := uart.getBaudRateDivisor(br) - uart.Bus.BRR.Set(divider) -} - -// WriteByte writes a byte of data to the UART. -func (uart *UART) writeByte(c byte) error { - uart.txReg.Set(uint32(c)) - - for !uart.statusReg.HasBits(uart.txEmptyFlag) { - } - return nil -} - -func (uart *UART) flush() {} From c49d0ba8952564d0c0e6faf9dbd75d5082db8d6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Teichgr=C3=A4ber?= Date: Mon, 23 Feb 2026 17:01:16 +0100 Subject: [PATCH 5/5] machine: stm32l0x1,l0x2: TIM: adapt to 32-bit register access Recent changes in stm32-svd result in a change from previous 16-bit register access to 32-bit access. Both access types are allowed, according to the register manuals. --- src/machine/machine_stm32l0x1.go | 4 ++-- src/machine/machine_stm32l0x2.go | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/machine/machine_stm32l0x1.go b/src/machine/machine_stm32l0x1.go index f0d23ca495..292b81f462 100644 --- a/src/machine/machine_stm32l0x1.go +++ b/src/machine/machine_stm32l0x1.go @@ -188,8 +188,8 @@ func (t *TIM) enableMainOutput() { // nothing to do - no BDTR register } -type arrtype = uint16 -type arrRegType = volatile.Register16 +type arrtype = uint32 +type arrRegType = volatile.Register32 const ( ARR_MAX = 0x10000 diff --git a/src/machine/machine_stm32l0x2.go b/src/machine/machine_stm32l0x2.go index 2a747920be..fe1ba3a229 100644 --- a/src/machine/machine_stm32l0x2.go +++ b/src/machine/machine_stm32l0x2.go @@ -245,8 +245,8 @@ func (t *TIM) enableMainOutput() { // nothing to do - no BDTR register } -type arrtype = uint16 -type arrRegType = volatile.Register16 +type arrtype = uint32 +type arrRegType = volatile.Register32 const ( ARR_MAX = 0x10000