diff --git a/build_model/CMakeLists.txt b/build_model/CMakeLists.txt index 089c959..1994dba 100644 --- a/build_model/CMakeLists.txt +++ b/build_model/CMakeLists.txt @@ -54,6 +54,8 @@ if(${RISCV_ARCH} STREQUAL "rv32im") #Build only scalar core set(RISCV_ZVE32X "" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) elseif(${RISCV_ARCH} STREQUAL "rv32imf") #Build scalar core with FPU on the Xif interface set(XIF_FLAG "-DXIF_ON" ) @@ -62,6 +64,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf") #Build scalar core with FPU on the Xif set(RISCV_ZVE32X "" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_F) @@ -72,6 +76,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh") #Build scalar core with FPU on the set(RISCV_ZVE32X "" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_F) add_definitions(-DRISCV_ZFH) @@ -83,6 +89,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x") #Build scalar core with Vicuna on set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_ZVE32X) @@ -93,6 +101,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zve32f") #Build scalar core with Vicuna a set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) set(RISCV_ZVE32F "-DRISCV_ZVE32F" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_F) add_definitions(-DRISCV_ZVE32X) @@ -105,6 +115,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh_zve32f_zvfh") #Build scalar core with set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) set(RISCV_ZVE32F "-DRISCV_ZVE32F" ) set(RISCV_ZVFH "-DRISCV_ZVFH" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_F) add_definitions(-DRISCV_ZFH) @@ -112,6 +124,42 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh_zve32f_zvfh") #Build scalar core with add_definitions(-DRISCV_ZVE32F) add_definitions(-DRISCV_ZVFH) +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb") #Build CV32E40X with Vicuna (+ crypto Extension) on the Xif interface + set(XIF_FLAG "-DXIF_ON" ) + set(RISCV_F "" ) + set(RISCV_ZFH "" ) + set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) + set(RISCV_ZVE32F "" ) + set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "-DRISCV_ZVBB" ) + set(RISCV_ZVBC "" ) + #C++ Flags + add_definitions(-DRISCV_ZVE32X) + +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbc") #Build CV32E40X with Vicuna (+ crypto Extension) on the Xif interface + set(XIF_FLAG "-DXIF_ON" ) + set(RISCV_F "" ) + set(RISCV_ZFH "" ) + set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) + set(RISCV_ZVE32F "" ) + set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "-DRISCV_ZVBC" ) + #C++ Flags + add_definitions(-DRISCV_ZVE32X) + +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb_zvbc") #Build CV32E40X with Vicuna (+ crypto Extension) on the Xif interface + set(XIF_FLAG "-DXIF_ON" ) + set(RISCV_F "" ) + set(RISCV_ZFH "" ) + set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) + set(RISCV_ZVE32F "" ) + set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "-DRISCV_ZVBB" ) + set(RISCV_ZVBC "-DRISCV_ZVBC" ) + #C++ Flags + add_definitions(-DRISCV_ZVE32X) + else() message(FATAL_ERROR "Unsupported RISCV_ARCH selected") @@ -407,6 +455,8 @@ if ( ${SCALAR_CORE} STREQUAL "cv32e40x" ) ${RISCV_ZVE32X} ${RISCV_ZVE32F} ${RISCV_ZVFH} + ${RISCV_ZVBB} + ${RISCV_ZVBC} -CFLAGS "-std=gnu++14 -O2") elseif( ${SCALAR_CORE} STREQUAL "cv32a60x" ) #TODO: Verify/Test support for floating point vector systems with this core. Currently, only Zve32x tested. @@ -437,6 +487,8 @@ elseif( ${SCALAR_CORE} STREQUAL "cv32a60x" ) #TODO: Verify/Test support for floa ${RISCV_ZVE32X} ${RISCV_ZVE32F} ${RISCV_ZVFH} + ${RISCV_ZVBB} + ${RISCV_ZVBC} ${COMMIT_AND_ISSUE} -CFLAGS "-std=gnu++14 -O2") else() diff --git a/build_model/vector_config.cmake b/build_model/vector_config.cmake index ce1e5c6..6eee540 100644 --- a/build_model/vector_config.cmake +++ b/build_model/vector_config.cmake @@ -2,7 +2,7 @@ # Set configurations of the system here. This is imported into CMAKE ### -#Currently Supported: rv32im, rv32im_zve32x, rv32imf, rv32imf_zhf, rv32imf_zve32x, rv32imf_zve32f +#Currently Supported: rv32im, rv32im_zve32x, rv32imf, rv32imf_zhf, rv32imf_zve32x, rv32imf_zve32f, rv32im_zve32x_zvbb, rv32im_zve32x_zvbc, rv32im_zve32x_zvbb_zvbc set(RISCV_ARCH rv32im_zve32x CACHE STRING "Specify the configuration") #Currently Supported: cv32e40x, cv32a60x @@ -11,5 +11,4 @@ set(SCALAR_CORE "cv32e40x") set(VMEM_W 32) set(VREG_W 128) -set(VPROC_PIPELINES "${VMEM_W}:VLSU 32:VELEM,VSLD,VDIV,VALU,VMUL") - +set(VPROC_PIPELINES "${VMEM_W}:VLSU 64:VELEM,VSLD,VDIV,VALU,VMUL,VZVBB,VZVBC") diff --git a/build_tests/CMakeLists.txt b/build_tests/CMakeLists.txt index cc250ae..5adb305 100644 --- a/build_tests/CMakeLists.txt +++ b/build_tests/CMakeLists.txt @@ -64,6 +64,8 @@ option(RISCV_ZFH "Use the RISC-V ZFH Extension" OFF) option(RISCV_ZVE32X "Use the RISC-V Embedded V Extension" OFF) option(RISCV_ZVE32F "Use the RISC-V Embedded V Float Extension" OFF) option(RISCV_ZVFH "Use the RISC-V V Half Float Extension" OFF) +option(RISCV_ZVBB "Use the RISC-V V Basic Bit-manipulation" OFF) +option(RISCV_ZVBC "Use the RISC-V V Carryless Multiplication" OFF) if(${RISCV_ARCH} STREQUAL "rv32im") set(RISCV_ABI ilp32) @@ -96,6 +98,25 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh_zve32f_zvfh") set(RISCV_ZFH ON) set(RISCV_F ON) set(RISCV_ZVFH ON) + +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb") + set(RISCV_ABI ilp32) + set(RISCV_ZVE32X ON) + set(RISCV_ZVBB ON) + set(INTEGER 1) + +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbc") + set(RISCV_ABI ilp32) + set(RISCV_ZVE32X ON) + set(RISCV_ZVBC ON) + set(INTEGER 1) + +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb_zvbc") + set(RISCV_ABI ilp32) + set(RISCV_ZVE32X ON) + set(RISCV_ZVBB ON) + set(RISCV_ZVBC ON) + set(INTEGER 1) else()