From c0304c51826206513195bfc19bb2e666f81760bc Mon Sep 17 00:00:00 2001 From: Daniel Blattner Date: Tue, 17 Feb 2026 10:44:37 +0100 Subject: [PATCH 1/5] Added zvbb and zvbc to configuration --- README.md | 4 ++++ build_model/CMakeLists.txt | 10 ++++++++++ build_tests/CMakeLists.txt | 9 +++++++++ 3 files changed, 23 insertions(+) diff --git a/README.md b/README.md index 2abf0c9..916f685 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,6 @@ # vicuna2_unit_testing Unit Testing Framework for Vicuna. Includes legacy handwritten unit tests, as well as the official RISC-V Tests and ChipsAlliance Tests for the V extension + + +# Required additional +sudo apt-get install golang srecord \ No newline at end of file diff --git a/build_model/CMakeLists.txt b/build_model/CMakeLists.txt index 51c611b..5e07b76 100644 --- a/build_model/CMakeLists.txt +++ b/build_model/CMakeLists.txt @@ -112,6 +112,16 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh_zve32f_zvfh") #Build CV32E40X with Vi add_definitions(-DRISCV_ZVE32F) add_definitions(-DRISCV_ZVFH) +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb_zvbc") #Build CV32E40X with Vicuna (+ crypto Extension) on the Xif interface + set(XIF_FLAG "-DXIF_ON" ) + set(RISCV_F "" ) + set(RISCV_ZFH "" ) + set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) + set(RISCV_ZVE32F "" ) + set(RISCV_ZVFH "" ) + #C++ Flags + add_definitions(-DRISCV_ZVE32X) + else() message(FATAL_ERROR "Unsupported RISCV_ARCH selected") diff --git a/build_tests/CMakeLists.txt b/build_tests/CMakeLists.txt index cc250ae..d42fc22 100644 --- a/build_tests/CMakeLists.txt +++ b/build_tests/CMakeLists.txt @@ -64,6 +64,8 @@ option(RISCV_ZFH "Use the RISC-V ZFH Extension" OFF) option(RISCV_ZVE32X "Use the RISC-V Embedded V Extension" OFF) option(RISCV_ZVE32F "Use the RISC-V Embedded V Float Extension" OFF) option(RISCV_ZVFH "Use the RISC-V V Half Float Extension" OFF) +option(RISCV_ZVBB "Use the RISC-V V Basic Bit-manipulation" OFF) +option(RISCV_ZVBC "Use the RISC-V V Carryless Multiplication" OFF) if(${RISCV_ARCH} STREQUAL "rv32im") set(RISCV_ABI ilp32) @@ -96,6 +98,13 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh_zve32f_zvfh") set(RISCV_ZFH ON) set(RISCV_F ON) set(RISCV_ZVFH ON) + +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb_zvbc") + set(RISCV_ABI ilp32) + set(RISCV_ZVE32X ON) + set(RISCV_ZVBB ON) + set(RISCV_ZVBC ON) + set(INTEGER 1) else() From 37eea85a286e7b233265404d71684040316ad389 Mon Sep 17 00:00:00 2001 From: Daniel Blattner Date: Fri, 20 Feb 2026 11:37:03 +0100 Subject: [PATCH 2/5] Added Zvbb and Zvbc to build file --- .gitmodules | 2 ++ build_model/vector_config.cmake | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index db641f0..017126f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -11,3 +11,5 @@ path = rtl/cv32e40x url = https://github.com/ParkerJones567/cv32e40x_f_zhf.git branch = f_zhf_fixes +[submodule "rtl/vicuna2_core/"] + branch = main diff --git a/build_model/vector_config.cmake b/build_model/vector_config.cmake index 5f9fcae..593abdf 100644 --- a/build_model/vector_config.cmake +++ b/build_model/vector_config.cmake @@ -3,8 +3,8 @@ ### #Currently Supported: rv32im, rv32im_zve32x, rv32imf, rv32imf_zhf, rv32imf_zve32x, rv32imf_zve32f -set(RISCV_ARCH rv32im_zve32x CACHE STRING "Specify the configuration") +set(RISCV_ARCH rv32im_zve32x_zvbb_zvbc CACHE STRING "Specify the configuration") set(VREG_W 128) set(VMEM_W 32) -set(VPROC_PIPELINES "${VMEM_W}:VLSU 64:VELEM,VSLD,VDIV,VALU,VMUL") +set(VPROC_PIPELINES "${VMEM_W}:VLSU 64:VELEM,VSLD,VDIV,VALU,VMUL,VZVBB,VZVBC") From 94b3b2b873f7a53615fb9bc2852d33f52f7684db Mon Sep 17 00:00:00 2001 From: Daniel Blattner Date: Sat, 28 Feb 2026 14:15:41 +0100 Subject: [PATCH 3/5] Added single Zvbb and Zvbc configuration --- build_model/CMakeLists.txt | 20 ++++++++++++++++++++ build_model/vector_config.cmake | 2 +- build_tests/CMakeLists.txt | 12 ++++++++++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/build_model/CMakeLists.txt b/build_model/CMakeLists.txt index d767b81..e8cb1d6 100644 --- a/build_model/CMakeLists.txt +++ b/build_model/CMakeLists.txt @@ -112,6 +112,26 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh_zve32f_zvfh") #Build scalar core with add_definitions(-DRISCV_ZVE32F) add_definitions(-DRISCV_ZVFH) +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb") #Build CV32E40X with Vicuna (+ crypto Extension) on the Xif interface + set(XIF_FLAG "-DXIF_ON" ) + set(RISCV_F "" ) + set(RISCV_ZFH "" ) + set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) + set(RISCV_ZVE32F "" ) + set(RISCV_ZVFH "" ) + #C++ Flags + add_definitions(-DRISCV_ZVE32X) + +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbc") #Build CV32E40X with Vicuna (+ crypto Extension) on the Xif interface + set(XIF_FLAG "-DXIF_ON" ) + set(RISCV_F "" ) + set(RISCV_ZFH "" ) + set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) + set(RISCV_ZVE32F "" ) + set(RISCV_ZVFH "" ) + #C++ Flags + add_definitions(-DRISCV_ZVE32X) + elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb_zvbc") #Build CV32E40X with Vicuna (+ crypto Extension) on the Xif interface set(XIF_FLAG "-DXIF_ON" ) set(RISCV_F "" ) diff --git a/build_model/vector_config.cmake b/build_model/vector_config.cmake index 68966ae..18b75a6 100644 --- a/build_model/vector_config.cmake +++ b/build_model/vector_config.cmake @@ -3,7 +3,7 @@ ### #Currently Supported: rv32im, rv32im_zve32x, rv32imf, rv32imf_zhf, rv32imf_zve32x, rv32imf_zve32f -set(RISCV_ARCH rv32im_zve32x_zvbb_zvbc CACHE STRING "Specify the configuration") +set(RISCV_ARCH rv32im_zve32x_zvbb CACHE STRING "Specify the configuration") #Currently Supported: cv32e40x, cv32a60x set(SCALAR_CORE "cv32e40x") diff --git a/build_tests/CMakeLists.txt b/build_tests/CMakeLists.txt index d42fc22..5adb305 100644 --- a/build_tests/CMakeLists.txt +++ b/build_tests/CMakeLists.txt @@ -99,6 +99,18 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh_zve32f_zvfh") set(RISCV_F ON) set(RISCV_ZVFH ON) +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb") + set(RISCV_ABI ilp32) + set(RISCV_ZVE32X ON) + set(RISCV_ZVBB ON) + set(INTEGER 1) + +elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbc") + set(RISCV_ABI ilp32) + set(RISCV_ZVE32X ON) + set(RISCV_ZVBC ON) + set(INTEGER 1) + elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb_zvbc") set(RISCV_ABI ilp32) set(RISCV_ZVE32X ON) From 4b21cb1b7b5e184d84b32f059fedeaf9f8377e08 Mon Sep 17 00:00:00 2001 From: Daniel Blattner Date: Sat, 28 Feb 2026 14:58:22 +0100 Subject: [PATCH 4/5] Added flags to disable Zvbb and Zvbc --- build_model/CMakeLists.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/build_model/CMakeLists.txt b/build_model/CMakeLists.txt index e8cb1d6..1994dba 100644 --- a/build_model/CMakeLists.txt +++ b/build_model/CMakeLists.txt @@ -54,6 +54,8 @@ if(${RISCV_ARCH} STREQUAL "rv32im") #Build only scalar core set(RISCV_ZVE32X "" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) elseif(${RISCV_ARCH} STREQUAL "rv32imf") #Build scalar core with FPU on the Xif interface set(XIF_FLAG "-DXIF_ON" ) @@ -62,6 +64,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf") #Build scalar core with FPU on the Xif set(RISCV_ZVE32X "" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_F) @@ -72,6 +76,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh") #Build scalar core with FPU on the set(RISCV_ZVE32X "" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_F) add_definitions(-DRISCV_ZFH) @@ -83,6 +89,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x") #Build scalar core with Vicuna on set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_ZVE32X) @@ -93,6 +101,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zve32f") #Build scalar core with Vicuna a set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) set(RISCV_ZVE32F "-DRISCV_ZVE32F" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_F) add_definitions(-DRISCV_ZVE32X) @@ -105,6 +115,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32imf_zfh_zve32f_zvfh") #Build scalar core with set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) set(RISCV_ZVE32F "-DRISCV_ZVE32F" ) set(RISCV_ZVFH "-DRISCV_ZVFH" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_F) add_definitions(-DRISCV_ZFH) @@ -119,6 +131,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb") #Build CV32E40X with Vicuna set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "-DRISCV_ZVBB" ) + set(RISCV_ZVBC "" ) #C++ Flags add_definitions(-DRISCV_ZVE32X) @@ -129,6 +143,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbc") #Build CV32E40X with Vicuna set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "" ) + set(RISCV_ZVBC "-DRISCV_ZVBC" ) #C++ Flags add_definitions(-DRISCV_ZVE32X) @@ -139,6 +155,8 @@ elseif(${RISCV_ARCH} STREQUAL "rv32im_zve32x_zvbb_zvbc") #Build CV32E40X with Vi set(RISCV_ZVE32X "-DRISCV_ZVE32X" ) set(RISCV_ZVE32F "" ) set(RISCV_ZVFH "" ) + set(RISCV_ZVBB "-DRISCV_ZVBB" ) + set(RISCV_ZVBC "-DRISCV_ZVBC" ) #C++ Flags add_definitions(-DRISCV_ZVE32X) @@ -437,6 +455,8 @@ if ( ${SCALAR_CORE} STREQUAL "cv32e40x" ) ${RISCV_ZVE32X} ${RISCV_ZVE32F} ${RISCV_ZVFH} + ${RISCV_ZVBB} + ${RISCV_ZVBC} -CFLAGS "-std=gnu++14 -O2") elseif( ${SCALAR_CORE} STREQUAL "cv32a60x" ) #TODO: Verify/Test support for floating point vector systems with this core. Currently, only Zve32x tested. @@ -467,6 +487,8 @@ elseif( ${SCALAR_CORE} STREQUAL "cv32a60x" ) #TODO: Verify/Test support for floa ${RISCV_ZVE32X} ${RISCV_ZVE32F} ${RISCV_ZVFH} + ${RISCV_ZVBB} + ${RISCV_ZVBC} ${COMMIT_AND_ISSUE} -CFLAGS "-std=gnu++14 -O2") else() From 66bd05ac60dad7490430002726f7f9a4a35d346d Mon Sep 17 00:00:00 2001 From: Daniel Blattner Date: Sat, 28 Feb 2026 16:43:06 +0100 Subject: [PATCH 5/5] Reset vector_config.cmake to default and added supported extensions --- build_model/vector_config.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/build_model/vector_config.cmake b/build_model/vector_config.cmake index 18b75a6..6eee540 100644 --- a/build_model/vector_config.cmake +++ b/build_model/vector_config.cmake @@ -2,8 +2,8 @@ # Set configurations of the system here. This is imported into CMAKE ### -#Currently Supported: rv32im, rv32im_zve32x, rv32imf, rv32imf_zhf, rv32imf_zve32x, rv32imf_zve32f -set(RISCV_ARCH rv32im_zve32x_zvbb CACHE STRING "Specify the configuration") +#Currently Supported: rv32im, rv32im_zve32x, rv32imf, rv32imf_zhf, rv32imf_zve32x, rv32imf_zve32f, rv32im_zve32x_zvbb, rv32im_zve32x_zvbc, rv32im_zve32x_zvbb_zvbc +set(RISCV_ARCH rv32im_zve32x CACHE STRING "Specify the configuration") #Currently Supported: cv32e40x, cv32a60x set(SCALAR_CORE "cv32e40x")