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Remove redundant preprocessor checks in VAL files#334

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avinaw01-arm wants to merge 16 commits intoARM-software:mainfrom
avinaw01-arm:checks_2
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Remove redundant preprocessor checks in VAL files#334
avinaw01-arm wants to merge 16 commits intoARM-software:mainfrom
avinaw01-arm:checks_2

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Optimized preprocessor include directives in VAL files

shrutig-arm and others added 16 commits March 16, 2026 12:26
- Add val_logger.c and val_logger.h as implementation
- Design patchset(review comments addressed)

Signed-off-by: Shruti Ghadge <shruti.ghadge@arm.com>
Change-Id: I12cc4a2338013cc80060d0c5e8795455f594c085
Signed-off-by: Avi Nawal <Avi.Nawal@arm.com>
Change-Id: I8aa1870cfb9039d6d6b0699976080d9cd2e1ee47
    - Add val_sysreg*.h and val_arch.h to provide macro-based inline accessors for Timer, GIC, MPAM, PE (Reg, Test), PMU and RAS system registers, consolidating register knowledge in C
    - Legacy AArch64 Sysreg/PMU/RAS/timer assembly files are removed to shrink the asm surface
    - These framework changes have been made as a part of Unified VAL

Signed-off-by: Avi Nawal <Avi.Nawal@arm.com>
Change-Id: Ibbf84bbf32dc9be03323c5c7df500174f026b1c1
    - Point existing headers at the new Sysreg helpers and remove numerous old prototypes
    - Modified all function callers to the new inline accessors
    - These changes have been made as a part of Unified VAL

Signed-off-by: Avi Nawal <Avi.Nawal@arm.com>
Change-Id: Id308002dcc1eb4d3f447d2c7e4e8b9df62fbb53d
- Update acs to align with new verbosity levels
- Align val infra to call new logger API

Signed-off-by: Shruti Ghadge <shruti.ghadge@arm.com>
Change-Id: Ia693e814efd239ed46e01dc70cadd38ad9d7be5b
 - As part of Unified VAL, XLAT library is added into VAL directory
 - Validated the changes for BSA, SBSA suites on Baremetal RDV3 environment setup

Signed-off-by: Avi Nawal <Avi.Nawal@arm.com>
Change-Id: I80798a673f140ed40dc5f67ec1934b888d8c3751
- Added val_status.h and val_status.h for status reporting
- Design changes only patchset(review feedback incorporated)

Signed-off-by: Shruti Ghadge <shruti.ghadge@arm.com>
Change-Id: If614cff14863a21c54405380569f854acc3d114b
- Align test pool and infra to updated status report design

Signed-off-by: Shruti Ghadge <shruti.ghadge@arm.com>

Change-Id: I7c880574a04d52270ba6dbbd6202ef05ade9d98d
  - Provide support to BSD-3 license for sysarch-acs
  - These changes have been made as a part of Unified VAL

Signed-off-by: Avi Nawal <Avi.Nawal@arm.com>
Change-Id: Iac2d1bd8a885182a70dc23c9c9e5c1fdd90d464d
  -update RB exection infra files for new status report design
  -align exerciser and SMMU tests
  -align val_prints as per the log parser
  -update SbsaValNistLib.inf as per unified val changes

Signed-off-by: Shruti Ghadge <shruti.ghadge@arm.com>
Change-Id: I8b75be4c7018b96343e485e81bc7484c5ea0cab7
 -avoid inclusion of std C headers in kernel builds
 -Uupdate VAL headers to support cross-platform compilation

Change-Id: I5d8079119cde7c6e8f8d3981f9ec73c799e2c1e4
Signed-off-by: Avi Nawal <Avi.Nawal@arm.com>
Change-Id: I5fb837358584a1da4442bbafb2b352ca0dcafbb8
Change-Id: I26f3b1c0801e3c5e96f11f4e399a169688ed2c5d
…ed-val

Signed-off-by: Avi Nawal <Avi.Nawal@arm.com>
Change-Id: I6004a86b172f865f6442012308fbe1cfffea5150
Signed-off-by: Avi Nawal <Avi.Nawal@arm.com>
Change-Id: Ie6a5437588bc53b262357e342321c083f85b9b90
@avinaw01-arm avinaw01-arm deleted the checks_2 branch April 10, 2026 06:48
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2 participants