Brhd support#915
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Add settings to specify the polarity of PCIe signals. Some board designs invert RX or TX lines on the connectors. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Avoid adding APOB NV or BIOS NV is size is not specified. Otherwise, the PSP BIOS directory may end up with BIOS NV of base 0 and size 0. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Include new PMU firmware file in the PSP BIOS directories that are available on Turin SOC. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
It is not required to build multilevel directories to make the platform boot. If multilevel is disabled, the blob footprint is reduced due to inclusion of a single copy of given blob, at the cost of PSP recovery, which we do not support anyways. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
AMD FCH UARTs can work with 3M baud rates. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The bootblock may be placed in the CBFS as in the old days. The Makefile.mk that prepares parameters for amdfwtool must simply pass the right parameters about BIOS_BIN to be uncompressed and where to look for the bootblock in flash. On AMD platforms it can be the last block of COREBOOT region of C_ENV_BOOTBLOCK_SIZE. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add APCBs from R22_F15 vendor BIOS image. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
On server platforms the maximum number of logical processors is greater than default 64 defined in the DSC file. Use MAX_CPUs Kconfig value to pass the epxected maximum processor count and use the 100ms increments for each processor for the AP init timeout as coreboot does for its own MP init. TEST=Boot Gigbyte MZ33-AR1 with 128 core processor Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Increase MAX_ACPI_TABLE_SIZE_KB to fit all ACPI tables when a higher core count CPU is used. The SSDT gets linearly bigger with higher core count and the default fixed allocation for ACPI tables is not enough. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
We do not cover enough of memory with page tables to reach higher memory than 1TB. When there is more memory than 1TB in the system, RMP is unreachable, resulting in page faults. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add missing memory hole definitions to have human readable information what given hole represents. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
If holes are not continuous, we may end up loosing some RAM, e.g. if Remap1Tb entry is present in the list of holes. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Some bridges were missing the operations and were not marked as hidden. Fix it for consistency. Also the intenal GPP bridges are PCIe bridges and should use PCIe bridge scann method. Otherwise, the devices may end up with mismatched MaxPayload capability. For openSIL, which does not program PCIe capabilities yet on the bridges and devices behind them, let coreboot do it. For external GPP bridges assign hotplug ops if hotplug enabled and port is capable of hotplugging. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Since SDXI devices are not visible by default, turn them off. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add missing ACP device described in the Turin PPR. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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