RISC-V Processor

This project implements a 64-bit RISC-V processor in Verilog.
The processor is developed in two stages:

1. Sequential (Single-Cycle) Processor
2. 5-Stage Pipelined Processor

The design supports a subset of the RISC-V ISA including R-type, I-type, load/store, and branch instructions.

The processor datapath and control logic are based on the architecture described in Computer Organization and Design – RISC-V Edition by Patterson and Hennessy.

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Salient Features

• Designed and implementated of a 64-bit RISC-V processor with both single-cycle and 5-stage pipelined architectures (IF, ID, EX, MEM, WB) supporting R-type, I-type, ld, sd, and beq instructions in verilog.
• Individually implemented the core datapath modules, hazard detection unit, and forwarding logic to resolve data hazards and reduce pipeline stalls.
• Branch resolution moved to the ID stage, reducing branch misprediction penalty to a single pipeline flush cycle using a static always-not-taken predictor.
• Developed Verilog testbenches to verify pipeline execution, hazard handling, and memory operations.

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Architecture Overview

Sequential Processor

In the single-cycle architecture, every instruction completes all stages of execution in a single clock cycle.

Stages executed within the cycle:

1. Instruction Fetch
2. Instruction Decode
3. Execute
4. Memory Access
5. Write Back

Advantages:

• Simple design
• Easier verification

Limitations:

• Long critical path
• Lower performance

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Pipelined Processor

The pipelined processor divides instruction execution into five stages:

Stage	Description
IF	Instruction Fetch
ID	Instruction Decode
EX	Execute
MEM	Memory Access
WB	Write Back

Multiple instructions execute simultaneously across stages, improving overall throughput.

Pipeline Enhancements

The pipeline design includes:

• Hazard Detection Unit
• Forwarding Units
• Branch forwarding logic
• Pipeline registers
• Stall and flush control
• Load-store forwarding unit

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Processor Modules

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Arithmetic Logic Unit (ALU)

The ALU performs arithmetic and logical operations on two 64-bit operands according to the control signals generated by the ALU Control unit.

The ALU result is used for:

• arithmetic operations
• memory address calculation
• branch comparisons

Inputs

Signal	Width	Description
Operand A	64	First operand from register file
Operand B	64	Second operand from register file or immediate
ALU Control	4	Operation selector

Outputs

Signal	Width	Description
ALU Result	64	Result of operation
Zero Flag	1	Indicates if result equals zero

Supported Operations

ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU

Design Optimization

The ALU uses a single shared 64-bit adder instead of multiple adders to reduce hardware complexity.

Zero Flag

The zero_flag is generated using a NOR reduction of the result bus and is used for branch instructions such as BEQ.

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Control Unit

The Control Unit decodes the instruction opcode and generates control signals that guide datapath components such as the ALU, register file, memory, and multiplexers.

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ALU Control

The ALU Control module determines the exact ALU operation based on:

• ALUOp from the main control unit
• instruction fields funct3
• instruction fields funct7

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Register File

The Register File contains 32 general purpose registers (x0 – x31).

Features:

• Two simultaneous reads
• One write per clock cycle
• Register x0 always returns zero

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Immediate Generator (ImmGen)

The Immediate Generator extracts immediate values from instructions and sign-extends them to 64 bits for use in arithmetic operations.

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Program Counter (PC)

The Program Counter stores the address of the next instruction to fetch.

• Normally increments by 4
• Updated with branch target address for branch instructions

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Instruction Memory

Instruction memory stores the program instructions.

Features:

• 4096 byte memory
• Byte-addressable
• Instructions loaded from instructions.txt

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Data Memory

Data memory stores runtime data used by load and store instructions.

Features:

• Byte-addressable memory
• Supports both read and write operations

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Multiplexers (MUX)

Multiplexers select between different datapath inputs such as:

• register values
• immediate values
• ALU outputs
• memory outputs

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Pipeline Registers

Pipeline registers separate the pipeline stages and store intermediate results between clock cycles.

Register	Between Stages
IF/ID	Instruction Fetch → Decode
ID/EX	Decode → Execute
EX/MEM	Execute → Memory
MEM/WB	Memory → Write Back

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Hazard Detection Unit

The Hazard Detection Unit detects situations where an instruction depends on data that has not yet been produced.

When a hazard is detected:

• PC is frozen
• IF/ID pipeline register is frozen
• A NOP bubble is inserted

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Forwarding Unit

The Forwarding Unit resolves Read-After-Write (RAW) hazards by forwarding results from later pipeline stages directly to the ALU inputs.

This reduces pipeline stalls.

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Branch Forwarding Unit

The Branch Forwarding Unit forwards updated register values to the branch comparison logic in the ID stage, allowing branches to be resolved earlier.

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Load-Store Forwarding Unit

The Extra Forwarding Unit handles hazards between load and store instructions by forwarding the loaded value directly to the store operation.

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Stall and Flush Control

Two control signals ensure correct pipeline execution:

Stall

• Freezes early pipeline stages when data is not ready.

Flush

• Removes incorrectly fetched instructions when a branch is taken.

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Testing

To test the processor implementation, follow these steps:

1. Download the repository and ensure the folder structure is preserved (both SEQ and Pipeline folders should remain intact).

2. Write your program in RISC-V assembly.

3. Use the provided assembler to convert the assembly program into big-endian hexadecimal instruction format.

4. Copy the generated instruction bytes and paste them into the file instructions.txt located in the respective implementation folder (SEQ or Pipeline).

5. Run the corresponding testbench file using your Verilog simulator.

Sequential processor: seq_tb.v

Pipelined processor: pipe_tb.v

The simulator will execute the instructions and display the register and pipeline outputs, allowing verification of correct processor behavior.

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Detailed Documentation

For a detailed explanation of the sequential processor design and pipelined processor implementation, please refer to the reports present in the respective folders:

• SEQ/Sequential_Report.pdf
• Pipeline/RISC_V_Processor_Pipeline_Report.pdf