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T8142 (M5) platform bring-up: PCIe, DAPF, DCP carveouts, CTRR, ATC PHY - #12

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GravityLinux:mainfrom
hishamMounir:j704/t8142-bringup
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hishamMounir wants to merge 10 commits into
GravityLinux:mainfrom
hishamMounir:j704/t8142-bringup

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@hishamMounir

@hishamMounir hishamMounir commented Oct 30, 2026 •

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This series brings the bootloader up on T8142 (Apple M5), as seen on the 14"
MacBook Pro (Mac17,2 / J704). With it the tree reaches a usable proxy on that
machine and chainloads Linux from the internal SSD.

What is here

  • pcie: support t8142 — needed for the internal NVMe and WLAN.
  • kboot: raise WLAN_REG_ON (SMC gP13) before PCIe init — without it the
    WLAN device never appears on J704. Includes the small SMC write plumbing.
  • dapf: find the DAPF reg by its ADT instance name — on t8142 the reg
    index used on earlier SoCs lands on a page shared with PMGR and SErrors on
    access. The index path is kept for the SoCs that use it.
  • kboot: reserve the CTRR ranges on t8142 — adds t8142 to the existing
    CTRR reservation, and reserves the second CTRR instance that covers the
    DeviceTree/TrustCache area below the bootloader. See the porting note below.
  • kboot: reserve the DCP carveouts and split DCP mapping runs, reserve unlisted iBoot DCP mappings, skip iommu-addresses without phandle — iBoot
    maps some regions (t8142 dcp_data) in several IOVA runs, and Linux replaces
    a locked DART's tables with exactly what iommu-addresses lists, so each run
    has to be described. A run with no mapping now fails rather than silently
    handing Linux a truncated list, once at least one run has been described.
  • kboot: match DT CPU nodes to running CPUs by MPIDR — index-based
    matching does not hold on this SoC.
  • kboot_atc: copy the atc-phy tunables on t8142 — same tunable layout as
    t8122/t8132.
  • pmgr_adt2dt: resolve no_ps parents to their nearest real ancestors.
  • smp: log once when a call target hasn't taken a call after 1 s — a
    secondary that never takes a cross-CPU call otherwise looks exactly like a
    dead board. Logs once, then waits as before.

Porting notes

These were developed against AsahiLinux/m1n1 and rebased onto this tree, so
three of them were reworked rather than applied:

  • CTRR: this tree already reserves the CTRR range its own way, keyed on
    chip_id, and has no names for the second instance's registers. Rather than
    import Asahi's renamed CTRR_C_*/CTRR_D_* set, I added only the two
    D-instance encodings (3, 0, 11, 0, 2/3) next to the existing pair and
    extended the existing block. The D reservation is gated on t8142 and skipped
    when the instance reads back zero, so the M4 targets are untouched.
  • kboot_atc: only the t8142 compatible is added. Asahi's t8130 entry and
    its CIO-lane tunable block do not exist here and were deliberately not
    imported.
  • smp: include fixup only (iodev.h for the console flush).

Testing

J704 (Mac17,2, T8142, 16 GB) with the bootloader as the custom boot object of a
second macOS install (26.6.2 25G83, later 27.2 26B123; system firmware
mBoot-20457.41.3). Linux boots from the internal SSD and the proxy runs over
USB-C from an M4 Mac mini. AIC3, pmgr (386 devices), framebuffer, dockchannel
UART, USB (3 DARTs, t8110), PCIe and NVMe all come up.

Caveats I would rather state than have you discover: that testing was done with
the AsahiLinux-based build, not with this tree — the three reworked commits
above are compile-tested here but have not been booted. Every C file the series
touches compiles warning-free with aarch64-linux-gnu-gcc; I could not link a
full image because neither machine I have here has a bare-metal Rust target for
librust.a, and clang-format is not installed either, so no formatting pass
was run. The new DCP failure path has not been hit on hardware: it needs a
region iBoot maps in several runs with a gap, which this machine has not
produced.

Provenance

  • Clean room: every commit here is platform bring-up derived from the ADT,
    hypervisor traces and driver experiments. No Apple binary was disassembled for
    any of them. My GPU work on this machine is not clean-room and is staying
    local — none of it is in this series, and I will not send it here.
  • These patches were briefly open as AsahiLinux/m1n1#747, which I closed in
    favour of carrying them in this tree.
  • sh1ftmaker's m5-linux-research was a reference during this bring-up. Their
    T8142 GPU firmware memory handoff patch is not included — it is their work to
    send.
  • The hypervisor side of this machine's bring-up (12 commits: t8142 timer
    trapping via IMASK + ECV, impdef sysreg handling, a watchdog mode,
    run_guest --disable-node) rests on the SPTM/SPRR emulation by Sven Peter and
    Lukas Radermacher. I have it ready but am holding it, since janmarek98's
    M4 Pro/Max SPTM PR is still open here and one of my commits reverts an
    upstream change I cannot yet explain. Happy to send it whenever you want it.
  • I also have t8142 kernel-side DT and an irq-apple-aic fix, which overlap
    Lostosword's open PR HV fixups for macOS 26.6.2 #4 in GravityLinux/linux. I would rather rebase the
    non-overlapping parts onto that branch than open a competing PR — tell me
    which you prefer.

🤖 Generated with Claude Code

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
Instead of assuming the DT lists CPUs in the same order as the ADT, look
up the live CPU with the node's MPIDR. Same result for in-order trees;
lets a bring-up DT reorder CPUs (used to boot one specific E-core early
on t8142).

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
iBoot leaves a CTRR instance enabled on the secondary cores, so Linux crashes
when it hands those pages to a secondary CPU and writes to them. t8142 needs
the same treatment T8132/T8140 already get, so add it to the existing
reservation.

t8142 also has a second CTRR instance, covering the DeviceTree/TrustCache area
below m1n1, which faults the same way. Name its two registers (encodings
3, 0, 11, 0, 2/3, next to the existing pair) and reserve that range too, gated
on t8142 and skipped when the instance reads back zero, so the M4 targets are
untouched.

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
Register layout and PHY init from macOS AppleT8142PCIe: 8 shared reg entries, the PHY-PHY block at reg[2] + 0x20000, the 100 MHz reference clock poll, the Gen4 PHY IP bit (_initializeGen4Phy) and PHY_CTRL bit 27 (_apcieGPInit). No fuse block.

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
Built only with -DJ704_WLAN_PWR. Linux has no SMC driver for t8142 yet, so m1n1 sets SMC GPIO gP13 = 0x01000001 (CMD_OUTPUT | 1, as macsmc-gpio does) before pcie_init so the BCM4388 enumerates. Adds smc_read_u32 to log the old value.

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
On t8142 the DAPF reg index used on earlier SoCs lands on a page shared with
PMGR, and touching it raises an SError. The reg this SoC wants is identified by
the ADT instance name instead, so look it up that way and keep the index path
for the SoCs that use it.

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
Same region ids as t8112, all mapped in dart-dcp stream 23 on the M5.
No disp0/piodma nodes yet; a no-op unless the DT has a "dcp" alias.

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
…ngs, skip iommu-addresses without phandle

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
t8142's atc-phy nodes carry the same tunable layout as t8122/t8132, so list the
compatible in the fuse table (reverse-chronological, ahead of t8132) and select
the t8122 tunable set for it.

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
A secondary that never takes a cross-CPU call leaves smp_call4() spinning with
no output at all, which looks exactly like a dead board. Print the CPU, the
call and the target state once after a second, flush the console, and then keep
waiting as before, so the behaviour is unchanged apart from the message.

This was written to chase a first-secondary wedge on J704 (M5) that shows up
roughly one boot in three.

Assisted-By: LLM
Signed-off-by: Hisham Alkhudrawi <hisham.ma.mohammed@gmail.com>
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