Project period: January 2026 – May 2026
This project brings together custom standard-cell development and a small arithmetic datapath at the 7 nm node. A three-bit Verilog ALU serves as the example circuit for synthesis and physical implementation using the project library.
The ALU computes addition or subtraction from two three-bit operands and registers the result on the rising edge of the clock.
| Port | Purpose |
|---|---|
clk |
Rising-edge clock for the output register |
A[2:0], B[2:0] |
Arithmetic operands |
reset_n |
Synchronous active-low reset; clears the output at a rising clock edge |
select |
0: addition; 1: subtraction using two's-complement addition |
F[2:0] |
Registered three-bit result |
Only the lowest three result bits are retained, so arithmetic wraps modulo eight. The interface has no separate carry, borrow, or overflow output. These interface details follow the checked-in alu.v source.
The documented cell work covers inverters, NAND/NOR gates, XOR, AOI/OAI functions, a multiplexer, and a flip-flop. The workflow includes schematic capture, layout, DRC and LVS checks, parasitic extraction, HSPICE simulation, and Liberty characterization.
The library is then used to map the ALU into a gate-level netlist and support its physical implementation. The original write-up describes a manually placed and routed design with 34 cells and reports passing DRC and LVS checks. These are reported project results, not checks rerun for this portfolio edition.
The original documentation also describes a negative-edge-triggered, active-high-reset flip-flop cell. Its cell-level interface should be distinguished from the positive-edge, active-low-reset behavior specified by the ALU RTL; the mapped netlist and reports are the references for how the design was implemented.
| File | Role |
|---|---|
| alu.v | Arithmetic logic and output-register RTL |
| tb_alu.v | Verilog testbench |
| alu_syn.v | Synthesized gate-level netlist |
| library.lib | Liberty library data |
| library.db | Compiled library database |
| Standard Cell Layout.pdf | Standard-cell layout report |
| Place and route.pdf | Physical implementation report |
Start with the RTL and testbench to understand the interface, inspect the library and mapped netlist to follow synthesis, and then read the PDF reports for the physical-design work.
Full reproduction depends on compatible EDA tools, the appropriate technology setup, and the required device models. The checked-in files provide RTL, library artifacts, a mapped netlist, and reports; they should not be assumed to include a complete standalone physical-design environment.