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GCE
GCE
 
 
.gitignore
.gitignore
 
 
ALU.vhd
ALU.vhd
 
 
ALUDecoder.vhd
ALUDecoder.vhd
 
 
Adder.vhd
Adder.vhd
 
 
ControlUnit.vhd
ControlUnit.vhd
 
 
DataMemory.vhd
DataMemory.vhd
 
 
Datapath.vhd
Datapath.vhd
 
 
Datapth_tb.vhd
Datapth_tb.vhd
 
 
Extend.vhd
Extend.vhd
 
 
InstrMemory.vhd
InstrMemory.vhd
 
 
MainDecoder.vhd
MainDecoder.vhd
 
 
Mux_2_to_1.vhd
Mux_2_to_1.vhd
 
 
README.md
README.md
 
 
RegisterFile.vhd
RegisterFile.vhd
 
 
beq_tb.vhd
beq_tb.vhd
 
 
lw_tb.vhd
lw_tb.vhd
 
 
program.txt
program.txt
 
 
registerfile_tb.vhd
registerfile_tb.vhd
 
 
risc-v.qpf
risc-v.qpf
 
 
risc-v.qsf
risc-v.qsf
 
 
riscv.vhd
riscv.vhd
 
 
riscv_tb.vhd
riscv_tb.vhd
 
 
serv_req_info.txt
serv_req_info.txt
 
 
sw_tb.vhd
sw_tb.vhd
 
 

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RISC-V

A RV32I compliant RISC-V CPU in VHDL, accompanied by a custom made simulation tool that allows interactive program execution on the CPU

The CPU

The Simulation Tool

Design and Architecture

GCE drawio

Screenshots

screen-gce

Thanks

Thanks to JabRef for the awesome CSS stylesheet.

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A (not yet) RV32I compliant RISC-V CPU in VHDL, accompanied by a graphical simulation tool that allows interactive program execution on the CPU

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