Add generic tensor copy and architecture-aware Gated Delta Rule support

[lzhangzz]

Summary

This change introduces a reusable, layout-aware CUDA tensor copy path and replaces the legacy Gated Delta Net implementation with a planned, registered Gated Delta Rule kernel stack.

Key Changes

• Add generic strided tensor copy with vectorized and tiled transpose paths.
• Preserve DLPack byte offsets, strides, and backing-storage capacity.
• Add recurrent and chunked Gated Delta Rule planning and dispatch.
• Add architecture-specific kernels for pre-SM90, SM90, and SM120 GPUs.
• Support mixed decode and prefill batches, grouped recurrent state, multiple state dtypes, and context-parallel planning.
• Integrate the new planner and kernels into GatedDeltaNetLayer.
• Expose native copy and Gated Delta Rule planning/execution through Python bindings.
• Add reference, correctness, and benchmark tooling for TurboMind, FLA, and FlashQLA comparisons.
• Remove the legacy tensor copy source and old GDN benchmark.

Validation

• Completed a Qwen3.5-27B TurboMind smoke test with TP=1 and CP=1.
• Added coverage for recurrent and chunked execution, strided layouts, grouped state, state dtypes, finished sequences, and context-parallel behavior.

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