feat(intrinsics): add KI.vload / KI.vstore! for wide vector memory operations#719
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shreyas-omkar wants to merge 5 commits into
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feat(intrinsics): add KI.vload / KI.vstore! for wide vector memory operations#719shreyas-omkar wants to merge 5 commits into
shreyas-omkar wants to merge 5 commits into
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Implements vectorised load/store for AbstractArray across all KA backends:
- CPU (Ptr path): reinterpret to Ptr{NTuple{N,VecElement{T}}} + unsafe_load/store!
- GPU (LLVMPtr path): reinterpret to LLVMPtr{NTuple{N,VecElement{T}},AS} + unsafe_load/store!
with N*sizeof(T) alignment; lowers to ld.global.v4 (CUDA), global_load_dwordx4
(AMDGPU), or OpLoad <N x T> (SPIR-V/POCL) — avoids pointerref/pointerset which
are unsupported in SPIR-V
- Scalar fallback for N=1 or non-primitive element types
Adds @generated helpers (_vload_ptr, _vload_lptr, _vstore_ptr!, _vstore_lptr!,
_vload_arr, _vstore_arr!) and comprehensive CPU test suite (147 tests, all pass).
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
…ore!
Base vload/vstore! now fall back to scalar indexing for all non-Ptr arrays.
GPU backends inject the vectorized path by registering @device_override for
their concrete device array type, following the KernelIntrinsics.jl pattern:
- src/intrinsics.jl: remove _vload_lptr/_vstore_lptr! and the LLVMPtr branch;
base dispatch is now: Ptr{T} → wide load, everything else → scalar fallback
- src/pocl/backend.jl: add @device_override for KI.vload/KI.vstore! on
CLDeviceArray, using reinterpret(LLVMPtr{NTuple{N,VecElement{T}},AS}, ptr)
+ unsafe_load/unsafe_store! to emit OpLoad <N x T> (SPIR-V/POCL)
CUDA.jl, AMDGPU.jl etc. should add analogous overrides for CuDeviceArray /
ROCDeviceArray to get ld.global.v4.f32 / global_load_dwordx4.
147/147 CPU tests pass.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
…le error
The AbstractArray fallback called pointer(arr, idx) which routes through
unsafe_convert(Ptr{T}, arr) — a path with a runtime string-formatting
error that GPU compilers (CUDA, SPIR-V) reject as an unsupported
dynamic function invocation.
Fix: split into two methods — Array (CPU Ptr path) and AbstractArray
(scalar fallback). GPU @device_overrides catch their device array types
before the AbstractArray fallback, so the Ptr path is never reachable in
GPU IR.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
oneAPI (Intel GPU) throws "Float64 is not supported on this device" when
allocating a oneArray{Float64}, so guard Float64 test cases behind
KernelAbstractions.supports_float64(backend()).
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Codecov Report❌ Patch coverage is
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## main #719 +/- ##
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Adds
KernelIntrinsics.vloadandKernelIntrinsics.vstore!CPU (
Array{T}): castspointer(arr, idx)toPtr{NTuple{N,VecElement{T}}}and callsunsafe_load/unsafe_store!.Julia/LLVM lowers
NTuple{N,VecElement{T}}to<N x T>, emitting one wideop (e.g.
movups/vmovapson x86).GPU: each backend registers a
@device_overridefor its concrete devicearray type that reinterprets the
LLVMPtrwithN*sizeof(T)alignment.POCL/SPIR-V override is included here (
CLDeviceArrayinsrc/pocl/backend.jl); CUDA.jl and AMDGPU.jl can add analogous overridesin their own KA extensions.
Fallback:
N == 1, non-primitiveT, or any array without a registeredoverride falls back to N scalar accesses via a
@generatedfunction (avoidsclosures, which GPU compilers reject).
Benchmark (POCLBackend, Float32, cyclops)
Speedup is visible in L2/L3-resident workloads where instruction throughput is
the bottleneck; DRAM-bound workloads are flat as expected.