TileOP: enforce the ISA capacity-derived TCVT geometry contract (#42)

[VV0003]

Fixes the TileOP side of #42 per the ISA verdict in the earlier comment.

What changed

The ordinary (non-CUBE) TCVT path required bitwise-identical C++ Rows/Cols between source and destination. That is stricter than the ISA:

PTO-TILE-TCVT legality: "Source and destination have equal Row, Col, ValidRow, and ValidCol. Their capacities and packing independently match their own DataTypes."

where Row/Col are the capacity-derived physical dimensions (DerivedTileRows = capacity*8 / (Col * elementBits), asl/tile/model/shape/rows-columns.asl) — not the C++ logical Rows/Cols — and each side's capacity independently matches its own DataType.

Why the old check was wrong for narrowing dtypes

bf16 → e8m0 [64,1]: the e8m0 destination's 64B payload is padded to the 128B minimum TSize, so its derived rows double (128) while the bf16 source stays at 64 — the emulator correctly rejects this per the ISA (that is the crash in #42). The ISA-legal encoding declares a wider physical column on both sides:

0 ""

0 ""

0 ""

1 "/usr/include/stdc-predef.h" 1 3 4

0 "" 2

1 ""

The old bitwise assertion made this legal encoding un-expressible (compounded by the reduce-chain pinning Col=1).

The fix

• Replace Rows==Rows && Cols==Cols with the exact ISA condition: equal capacity-derived rows (computed from each side's StorageBytes — the B.IOT-encoded capacity — physical Col, and element bits), keeping ValidRow/ValidCol equality.
• The old illegal form ([64,1]→[64,1] e8m0) now fails with a static_assert that names the ISA contract and points to the [Rows,2] pattern.
• TCVT usage page documents the narrowing pattern (per the docs-sync convention).

Verification

• issue 窄化 TCVT（bf16→e8m0）目的物理 row 被 128B 最小 tile 档撑大 → TCVT 形状契约断言崩溃 #42 chain (half→fp32→bf16→e8m0, all [64,2] VC=1) compiles; final bundle: lb2=2, e8m0 destination at 128B, derived rows 64 == source 64
• gate 64/74 (11 pre-existing failures identical on baseline); unittest 40/40

Note: the kernel-side fix (dynamic_mx_quant) needs to declare the scale-chain tiles as [TileM, 2] with ValidCol=1 per the documented pattern; the model needs no change (its assertion is the correct ISA behavior).