A compact study of cache latency, energy, leakage, and physical area across capacity, port-count, and technology-node configurations using CACTI 7.0.
This repository contains experiment outputs produced for the analysis. The CACTI source code is intentionally not redistributed; obtain the original tool from its official upstream source.
| Output | Configuration |
|---|---|
output_A_32KB_4way_45nm.txt |
32 KB, 4-way, 45 nm baseline |
output_A_32KB_4way_45nm_2ports.txt |
baseline with two read/write ports |
output_B_1MB_8way_45nm.txt |
1 MB, 8-way, 45 nm |
output_T22_32KB_4way.txt |
32 KB, 4-way, 22 nm |
output_T90_32KB_4way.txt |
32 KB, 4-way, 90 nm |
The outputs support direct comparison of access time, cycle time, dynamic energy, leakage power, and array dimensions.
For the 32 KB, 4-way, 45 nm configuration, CACTI reported:
- Access time:
0.698504 ns - Cycle time:
2.33883 ns - Dynamic read energy:
0.118281 nJ/access - Dynamic write energy:
0.11691 nJ/access - Bank leakage power:
41.6604 mW
Mehrdad Sheikh Abbasi