Provide `CCCL_HOST_COMPILER` macro by fbusato · Pull Request #11195 · NVIDIA/cccl

fbusato · 2026-09-04T00:41:41Z

Description

(Hope not too controversal). The PR provides the public macro CCCL_HOST_COMPILER() to identify gcc, clang, msvc, nvhpc and their specific versions. The macro aliases _CCCL_COMPILER().

The macro is aligned with CCCL_OS and CCCL_HOST_ARCH.

Address #8247

coderabbitai · 2026-09-04T00:46:22Z

No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info

⚙️ Run configuration

Configuration used: Path: .coderabbit.yaml

Review profile: CHILL

Plan: Enterprise

Run ID: 654ad17d-5794-4605-8c17-5c76f4ce4050

📥 Commits

Reviewing files that changed from the base of the PR and between 70f958a and 4e04634.

📒 Files selected for processing (1)

libcudacxx/include/cuda/std/__cccl/host_compiler.h

🚧 Files skipped from review as they are similar to previous changes (1)

libcudacxx/include/cuda/std/__cccl/host_compiler.h

Included review availability: Your plan provides up to 12 included reviews per hour; 11 remain after this review.

📝 Summary

Summary by CodeRabbit

New Features
- Added host compiler detection for NVHPC, Clang, GCC, and MSVC.
- Added compiler version comparisons, including major and major/minor versions.
- Added support for identifying MSVC 2019, 2022, and 2026.
- Added a public macro for checking compiler identity and supported versions.
Documentation
- Documented host compiler detection and version comparisons.
- Added availability information for CCCL 3.6.0 and CUDA 13.6.
Tests
- Added coverage for compiler identification and version comparisons across supported host compilers.

Walkthrough

The PR adds CCCL_HOST_COMPILER(...) and related compiler identifiers for NVHPC, Clang, GCC, and MSVC. It exports and documents the header, updates Doxygen input, and adds compile-time tests for detection and version comparisons.

Changes

Host compiler detection

Layer / File(s)	Summary
Macro contract and implementation `libcudacxx/include/cuda/std/__cccl/host_compiler.h`, `libcudacxx/include/cuda/std/__cccl/compiler.h`	The new header defines host compiler identifiers, version construction, compiler detection, version comparisons, supported forms, and Doxygen behavior. The copyright notice now covers 2024–2026.
Header export and documentation `libcudacxx/include/cuda/__cccl_config`, `docs/libcudacxx/Doxyfile`, `docs/libcudacxx/extended_api/macros.rst`	The configuration include exports `host_compiler.h`. Doxygen includes the header, and the macro reference documents `CCCL_HOST_COMPILER` and its availability.
Compile-time validation `libcudacxx/test/libcudacxx/libcxx/macros/compiler.compile.pass.cpp`	The compile-pass test checks unversioned and versioned detection for NVHPC, Clang, GCC, and MSVC. It also checks macro-expansion resilience, excludes NVRTC, and repeats the checks with `static_assert`.

Merge Risk: ⚪ Minimal · up to 4e046

This change adds and documents host-compiler detection macros with compile-time coverage. No concrete merge-blocking risk is currently identified.

_{Comment @coderabbitai help to get the list of available commands.}

davebayer

I'm fine with the idea of exposing these macros, but I think we shouldn't expose those MSVC20XX macros.

Also, what about clang-cl, do our users care about that one?

miscco · 2026-09-04T05:30:13Z

+#define _CCCL_HOST_COMPILER_MAKE_VERSION(_MAJOR, _MINOR) _CCCL_COMPILER_MAKE_VERSION(_MAJOR, _MINOR)
+#define _CCCL_HOST_COMPILER_NVHPC()                      _CCCL_COMPILER_NVHPC()
+#define _CCCL_HOST_COMPILER_CLANG()                      _CCCL_COMPILER_CLANG()
+#define _CCCL_HOST_COMPILER_GCC()                        _CCCL_COMPILER_GCC()


I find it a bit dangerous because we do not handle known compilers like

Apple-Clang and Intel-LLVM

Supporting compilers outside of what is guaranteed by the CUDA toolkit is not really expected.
(I meant, users should use CCCL outside CUDA supported platforms).
Do you have suggestions? I would add a note that other compilers are UB. (disable them looks bad)

miscco · 2026-09-04T05:31:41Z

I love that of all PRs this is triggering SASS changes ^^

fbusato · 2026-09-04T15:44:52Z

I love that of all PRs this is triggering SASS changes ^^

🤯this makes no sense to me

fbusato · 2026-09-04T22:27:20Z

I love that of all PRs this is triggering SASS changes ^^

This PR explains the problem #11191

github-actions · 2026-09-04T22:43:38Z

🔬 CUB benchmark SASS comparison

⚠️ The SASS changed for 84 of 84 CUB benchmark target(s). A benchmark run may be necessary

How to request a benchmark run

Request a CUB benchmark run for this PR:

1. Replace the `benchmarks:` block of ci/bench.yaml with exactly this:

benchmarks:
  filters:
    cub:
      - '^cub\.bench\.'   # all 84 changed targets
  gpus:
    - "h100"   # pick the GPUs that this change can affect

2. Commit with `[bench-only]` at the end of the commit summary, so that
   the unrelated CI jobs are skipped. Then push.

ci/bench.yaml must match ci/bench.template.yaml before the PR can merge.
Reset it once the measurement is done.

Run	Value
Baseline	`042e17c80e12f0d7c65dd8c6c70e19c4808d2dbd`
Tested	`HEAD`
Architectures	`75-real;80-real;90-real;100-real;110-real;120-real;120-virtual`

Targets with a SASS change

Target	Architectures with a SASS change
`cub.bench.adjacent_difference.subtract_left.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.bitonic_sort.warp_keys.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.bitonic_sort.warp_pairs.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.copy.memcpy.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.find_bound.lower_bound.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.find_bound.lower_bound_sorted_values.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.find_bound.upper_bound.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.find_bound.upper_bound_sorted_values.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.find_if.base.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.for_each.base.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.for_each.copy.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.for_each.extents.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.histogram.even.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.histogram.multi.even.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.histogram.multi.range.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.histogram.range.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.merge.keys.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.merge.pairs.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.merge_sort.keys.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.merge_sort.pairs.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.partition.flagged.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.partition.if.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.partition.three_way.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.radix_sort.keys.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
`cub.bench.radix_sort.pairs.base`	`sm_80`, `sm_100`, `sm_75`, `sm_110`, `sm_90`, `sm_120`
... and 59 more

‼️ Summary of Differences ‼️

Showing 10/84 summaries.

cub.bench.adjacent_difference.subtract_left.base - sm_80

Showing 40/2998 diff lines, 1856 changes. - ⬇️ Full diff

--- base/cub.bench.adjacent_difference.subtract_left.base.sm_80
+++ test/cub.bench.adjacent_difference.subtract_left.base.sm_80
@@ -43449,13 +43449,13 @@
 S2R R0, SR_CTAID.X ;
 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
 ULDC UR4, c[0x0][0x18c] ;
-BSSY B0, <+0x41d0> ;
+BSSY B0, <+0x4490> ;
 USHF.L.U32 UR4, UR4, 0xc, URZ ;
 LOP3.LUT P0, RZ, R2, 0xf, RZ, 0xc0, !PT ;
 ULDC.64 UR6, c[0x0][0x118] ;
 IMAD.SHL.U32 R17, R0, 0x1000, RZ ;
 IADD3 R28, -R17, c[0x0][0x188], RZ ;
-@!P0 BRA <+0x2630> ;
+@!P0 BRA <+0x2790> ;
 ISETP.GE.U32.AND P0, PT, R28, 0x1000, PT ;
 @!P0 BRA <+0x18a0> ;
 S2R R2, SR_TID.X ;
@@ -43842,7 +43842,7 @@
 @!P0 STS [R4.X4+0x8], R3 ;
 BAR.SYNC.DEFER_BLOCKING 0x0 ;
 ISETP.NE.AND P0, PT, R2, RZ, PT ;
-@P0 BRA <+0x2930> ;
+@P0 BRA <+0x2bf0> ;
 LDS R2, [0xc] ;
 LDS.128 R4, [0x10] ;
 LDS.64 R8, [0x20] ;
@@ -43850,7 +43850,7 @@
 IADD3 R2, R6, R5, R2 ;
 IADD3 R2, R8, R7, R2 ;
 IMAD.IADD R3, R2, 0x1, R9 ;
-BRA <+0x28b0> ;
+BRA <+0x2b70> ;
 S2R R15, SR_TID.X ;
 BSSY B1, <+0xb0> ;
 IMAD.MOV.U32 R18, RZ, RZ, RZ ;
@@ -44010,27 +44010,49 @@
 IADD3 R18, R4, R3, R18 ;
 IADD3 R18, R16, R7, R18 ;
 BSYNC B1 ;

cub.bench.bitonic_sort.warp_keys.base - sm_80

Showing 40/125171 diff lines, 122187 changes. - ⬇️ Full diff

--- base/cub.bench.bitonic_sort.warp_keys.base.sm_80
+++ test/cub.bench.bitonic_sort.warp_keys.base.sm_80
@@ -387,155 +387,154 @@
 ISETP.GE.AND P0, PT, R0, 0x1, PT ;
 @!P0 EXIT ;
 S2R R0, SR_TID.X ;
-S2R R8, SR_LANEID ;
-S2R R9, SR_VIRTUALSMID ;
+S2R R9, SR_LANEID ;
+S2R R10, SR_VIRTUALSMID ;
 IADD3 R0, R0, 0x7, RZ ;
-SHF.R.U32.HI R2, RZ, 0x1, R8 ;
+SHF.R.U32.HI R2, RZ, 0x1, R9 ;
 LOP3.LUT R3, R0, 0x1f, RZ, 0xc0, !PT ;
 IMAD.MOV.U32 R0, RZ, RZ, RZ ;
 LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ;
 IADD3 R3, R3, UR4, RZ ;
 ULDC.64 UR4, c[0x0][0x118] ;
 IMAD.MOV.U32 R4, RZ, RZ, 0x19660d ;
-ISETP.NE.AND P5, PT, R9, -0x1, PT ;
+ISETP.NE.AND P5, PT, R10, -0x1, PT ;
 IMAD R3, R3, R4, 0x3c6ef35f ;
-LOP3.LUT R4, R8, 0x1, RZ, 0xc0, !PT ;
-LOP3.LUT R5, R3.reuse, 0xffff, RZ, 0xc0, !PT ;
+LOP3.LUT R4, R9, 0x1, RZ, 0xc0, !PT ;
+SHFL.BFLY PT, R6, R3, 0x1, 0x1f ;
 ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ;
-PRMT R7, R3, 0x9910, RZ ;
-SHFL.BFLY PT, R6, R5, 0x1, 0x1f ;
+PRMT R5, R3, 0x9910, RZ ;
 ISETP.EQ.U32.XOR P1, PT, R2, 0x1, !P0 ;
 PRMT R4, R6, 0x9910, RZ ;
-ISETP.LT.XOR P1, PT, R7, R4, P1 ;
-ISETP.NE.AND P1, PT, R7, R4, !P1 ;
-SHF.R.U32.HI R4, RZ, 0x2, R8 ;
-SEL R6, R6, R3, P1 ;
+ISETP.LT.XOR P1, PT, R5, R4, P1 ;
+ISETP.NE.AND P1, PT, R5, R4, !P1 ;
+SHF.R.U32.HI R4, RZ, 0x2, R9 ;
+SEL R7, R6, R3, P1 ;

cub.bench.bitonic_sort.warp_pairs.base - sm_80

Showing 40/378315 diff lines, 374799 changes. - ⬇️ Full diff

--- base/cub.bench.bitonic_sort.warp_pairs.base.sm_80
+++ test/cub.bench.bitonic_sort.warp_pairs.base.sm_80
@@ -538,125 +538,125 @@
 SEL R11, R8, R7, P4 ;
 SHFL.BFLY PT, R8, R3, 0x1, 0x1f ;
 LOP3.LUT R4, R12, 0x1, RZ, 0xc0, !PT ;
-SEL R16, R6, R5, P3 ;
+SEL R6, R6, R5, P3 ;
 SHFL.BFLY PT, R14, R11, 0x4, 0x1f ;
 ISETP.EQ.U32.XOR P5, PT, R4, 0x1, !P2 ;
-SHFL.BFLY PT, R5, R16, 0x2, 0x1f ;
-SEL R15, R8, R3, P3 ;
+SHFL.BFLY PT, R5, R6, 0x2, 0x1f ;
+SEL R8, R8, R3, P3 ;
 ISETP.EQ.U32.XOR P3, PT, R4, 0x1, !P1 ;
 FSETP.LT.XOR P5, PT, R11.reuse, R14.reuse, P5 ;
-SHFL.BFLY PT, R6, R15, 0x2, 0x1f ;
+SHFL.BFLY PT, R7, R8, 0x2, 0x1f ;
 FSETP.NE.AND P5, PT, R11, R14, !P5 ;
-SEL R12, R5, R16, P6 ;
+SEL R5, R5, R6, P6 ;
 SEL R11, R14, R11, P5 ;
-SHFL.BFLY PT, R5, R12, 0x1, 0x1f ;
-SHFL.BFLY PT, R8, R11, 0x2, 0x1f ;
-SEL R13, R6, R15, P6 ;
-SHFL.BFLY PT, R6, R13, 0x1, 0x1f ;
-SEL R14, R5, R12, P4 ;
-FSETP.LT.XOR P3, PT, R11, R8, P3 ;
-SHFL.BFLY PT, R5, R14, 0x4, 0x1f ;
-FSETP.NE.AND P3, PT, R11, R8, !P3 ;
-SEL R8, R8, R11, P3 ;
+SHFL.BFLY PT, R12, R5, 0x1, 0x1f ;
+SHFL.BFLY PT, R16, R11, 0x2, 0x1f ;
+SEL R7, R7, R8, P6 ;
+SHFL.BFLY PT, R14, R7, 0x1, 0x1f ;
+SEL R12, R12, R5, P4 ;
+SHF.R.U32.HI R5, RZ, 0x4, R9 ;
+FSETP.LT.XOR P3, PT, R11, R16, P3 ;
+FSETP.NE.AND P3, PT, R11, R16, !P3 ;
+SEL R16, R16, R11, P3 ;

cub.bench.copy.memcpy.base - sm_80

Showing 40/2998 diff lines, 1856 changes. - ⬇️ Full diff

--- base/cub.bench.copy.memcpy.base.sm_80
+++ test/cub.bench.copy.memcpy.base.sm_80
@@ -55418,13 +55418,13 @@
 S2R R0, SR_CTAID.X ;
 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
 ULDC UR4, c[0x0][0x18c] ;
-BSSY B0, <+0x41d0> ;
+BSSY B0, <+0x4490> ;
 USHF.L.U32 UR4, UR4, 0xc, URZ ;
 LOP3.LUT P0, RZ, R2, 0xf, RZ, 0xc0, !PT ;
 ULDC.64 UR6, c[0x0][0x118] ;
 IMAD.SHL.U32 R17, R0, 0x1000, RZ ;
 IADD3 R28, -R17, c[0x0][0x188], RZ ;
-@!P0 BRA <+0x2630> ;
+@!P0 BRA <+0x2790> ;
 ISETP.GE.U32.AND P0, PT, R28, 0x1000, PT ;
 @!P0 BRA <+0x18a0> ;
 S2R R2, SR_TID.X ;
@@ -55811,7 +55811,7 @@
 @!P0 STS [R4.X4+0x8], R3 ;
 BAR.SYNC.DEFER_BLOCKING 0x0 ;
 ISETP.NE.AND P0, PT, R2, RZ, PT ;
-@P0 BRA <+0x2930> ;
+@P0 BRA <+0x2bf0> ;
 LDS R2, [0xc] ;
 LDS.128 R4, [0x10] ;
 LDS.64 R8, [0x20] ;
@@ -55819,7 +55819,7 @@
 IADD3 R2, R6, R5, R2 ;
 IADD3 R2, R8, R7, R2 ;
 IMAD.IADD R3, R2, 0x1, R9 ;
-BRA <+0x28b0> ;
+BRA <+0x2b70> ;
 S2R R15, SR_TID.X ;
 BSSY B1, <+0xb0> ;
 IMAD.MOV.U32 R18, RZ, RZ, RZ ;
@@ -55979,27 +55979,49 @@
 IADD3 R18, R4, R3, R18 ;
 IADD3 R18, R16, R7, R18 ;
 BSYNC B1 ;

cub.bench.find_bound.lower_bound.base - sm_80

Showing 40/2998 diff lines, 1856 changes. - ⬇️ Full diff

--- base/cub.bench.find_bound.lower_bound.base.sm_80
+++ test/cub.bench.find_bound.lower_bound.base.sm_80
@@ -78394,13 +78394,13 @@
 S2R R0, SR_CTAID.X ;
 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
 ULDC UR4, c[0x0][0x18c] ;
-BSSY B0, <+0x41d0> ;
+BSSY B0, <+0x4490> ;
 USHF.L.U32 UR4, UR4, 0xc, URZ ;
 LOP3.LUT P0, RZ, R2, 0xf, RZ, 0xc0, !PT ;
 ULDC.64 UR6, c[0x0][0x118] ;
 IMAD.SHL.U32 R17, R0, 0x1000, RZ ;
 IADD3 R28, -R17, c[0x0][0x188], RZ ;
-@!P0 BRA <+0x2630> ;
+@!P0 BRA <+0x2790> ;
 ISETP.GE.U32.AND P0, PT, R28, 0x1000, PT ;
 @!P0 BRA <+0x18a0> ;
 S2R R2, SR_TID.X ;
@@ -78787,7 +78787,7 @@
 @!P0 STS [R4.X4+0x8], R3 ;
 BAR.SYNC.DEFER_BLOCKING 0x0 ;
 ISETP.NE.AND P0, PT, R2, RZ, PT ;
-@P0 BRA <+0x2930> ;
+@P0 BRA <+0x2bf0> ;
 LDS R2, [0xc] ;
 LDS.128 R4, [0x10] ;
 LDS.64 R8, [0x20] ;
@@ -78795,7 +78795,7 @@
 IADD3 R2, R6, R5, R2 ;
 IADD3 R2, R8, R7, R2 ;
 IMAD.IADD R3, R2, 0x1, R9 ;
-BRA <+0x28b0> ;
+BRA <+0x2b70> ;
 S2R R15, SR_TID.X ;
 BSSY B1, <+0xb0> ;
 IMAD.MOV.U32 R18, RZ, RZ, RZ ;
@@ -78955,27 +78955,49 @@
 IADD3 R18, R4, R3, R18 ;
 IADD3 R18, R16, R7, R18 ;
 BSYNC B1 ;

cub.bench.find_bound.lower_bound_sorted_values.base - sm_80

Showing 40/2998 diff lines, 1856 changes. - ⬇️ Full diff

--- base/cub.bench.find_bound.lower_bound_sorted_values.base.sm_80
+++ test/cub.bench.find_bound.lower_bound_sorted_values.base.sm_80
@@ -81956,13 +81956,13 @@
 S2R R0, SR_CTAID.X ;
 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
 ULDC UR4, c[0x0][0x18c] ;
-BSSY B0, <+0x41d0> ;
+BSSY B0, <+0x4490> ;
 USHF.L.U32 UR4, UR4, 0xc, URZ ;
 LOP3.LUT P0, RZ, R2, 0xf, RZ, 0xc0, !PT ;
 ULDC.64 UR6, c[0x0][0x118] ;
 IMAD.SHL.U32 R17, R0, 0x1000, RZ ;
 IADD3 R28, -R17, c[0x0][0x188], RZ ;
-@!P0 BRA <+0x2630> ;
+@!P0 BRA <+0x2790> ;
 ISETP.GE.U32.AND P0, PT, R28, 0x1000, PT ;
 @!P0 BRA <+0x18a0> ;
 S2R R2, SR_TID.X ;
@@ -82349,7 +82349,7 @@
 @!P0 STS [R4.X4+0x8], R3 ;
 BAR.SYNC.DEFER_BLOCKING 0x0 ;
 ISETP.NE.AND P0, PT, R2, RZ, PT ;
-@P0 BRA <+0x2930> ;
+@P0 BRA <+0x2bf0> ;
 LDS R2, [0xc] ;
 LDS.128 R4, [0x10] ;
 LDS.64 R8, [0x20] ;
@@ -82357,7 +82357,7 @@
 IADD3 R2, R6, R5, R2 ;
 IADD3 R2, R8, R7, R2 ;
 IMAD.IADD R3, R2, 0x1, R9 ;
-BRA <+0x28b0> ;
+BRA <+0x2b70> ;
 S2R R15, SR_TID.X ;
 BSSY B1, <+0xb0> ;
 IMAD.MOV.U32 R18, RZ, RZ, RZ ;
@@ -82517,27 +82517,49 @@
 IADD3 R18, R4, R3, R18 ;
 IADD3 R18, R16, R7, R18 ;
 BSYNC B1 ;

cub.bench.find_bound.upper_bound.base - sm_80

Showing 40/2998 diff lines, 1856 changes. - ⬇️ Full diff

--- base/cub.bench.find_bound.upper_bound.base.sm_80
+++ test/cub.bench.find_bound.upper_bound.base.sm_80
@@ -78394,13 +78394,13 @@
 S2R R0, SR_CTAID.X ;
 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
 ULDC UR4, c[0x0][0x18c] ;
-BSSY B0, <+0x41d0> ;
+BSSY B0, <+0x4490> ;
 USHF.L.U32 UR4, UR4, 0xc, URZ ;
 LOP3.LUT P0, RZ, R2, 0xf, RZ, 0xc0, !PT ;
 ULDC.64 UR6, c[0x0][0x118] ;
 IMAD.SHL.U32 R17, R0, 0x1000, RZ ;
 IADD3 R28, -R17, c[0x0][0x188], RZ ;
-@!P0 BRA <+0x2630> ;
+@!P0 BRA <+0x2790> ;
 ISETP.GE.U32.AND P0, PT, R28, 0x1000, PT ;
 @!P0 BRA <+0x18a0> ;
 S2R R2, SR_TID.X ;
@@ -78787,7 +78787,7 @@
 @!P0 STS [R4.X4+0x8], R3 ;
 BAR.SYNC.DEFER_BLOCKING 0x0 ;
 ISETP.NE.AND P0, PT, R2, RZ, PT ;
-@P0 BRA <+0x2930> ;
+@P0 BRA <+0x2bf0> ;
 LDS R2, [0xc] ;
 LDS.128 R4, [0x10] ;
 LDS.64 R8, [0x20] ;
@@ -78795,7 +78795,7 @@
 IADD3 R2, R6, R5, R2 ;
 IADD3 R2, R8, R7, R2 ;
 IMAD.IADD R3, R2, 0x1, R9 ;
-BRA <+0x28b0> ;
+BRA <+0x2b70> ;
 S2R R15, SR_TID.X ;
 BSSY B1, <+0xb0> ;
 IMAD.MOV.U32 R18, RZ, RZ, RZ ;
@@ -78955,27 +78955,49 @@
 IADD3 R18, R4, R3, R18 ;
 IADD3 R18, R16, R7, R18 ;
 BSYNC B1 ;

cub.bench.find_bound.upper_bound_sorted_values.base - sm_80

Showing 40/2998 diff lines, 1856 changes. - ⬇️ Full diff

--- base/cub.bench.find_bound.upper_bound_sorted_values.base.sm_80
+++ test/cub.bench.find_bound.upper_bound_sorted_values.base.sm_80
@@ -81966,13 +81966,13 @@
 S2R R0, SR_CTAID.X ;
 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
 ULDC UR4, c[0x0][0x18c] ;
-BSSY B0, <+0x41d0> ;
+BSSY B0, <+0x4490> ;
 USHF.L.U32 UR4, UR4, 0xc, URZ ;
 LOP3.LUT P0, RZ, R2, 0xf, RZ, 0xc0, !PT ;
 ULDC.64 UR6, c[0x0][0x118] ;
 IMAD.SHL.U32 R17, R0, 0x1000, RZ ;
 IADD3 R28, -R17, c[0x0][0x188], RZ ;
-@!P0 BRA <+0x2630> ;
+@!P0 BRA <+0x2790> ;
 ISETP.GE.U32.AND P0, PT, R28, 0x1000, PT ;
 @!P0 BRA <+0x18a0> ;
 S2R R2, SR_TID.X ;
@@ -82359,7 +82359,7 @@
 @!P0 STS [R4.X4+0x8], R3 ;
 BAR.SYNC.DEFER_BLOCKING 0x0 ;
 ISETP.NE.AND P0, PT, R2, RZ, PT ;
-@P0 BRA <+0x2930> ;
+@P0 BRA <+0x2bf0> ;
 LDS R2, [0xc] ;
 LDS.128 R4, [0x10] ;
 LDS.64 R8, [0x20] ;
@@ -82367,7 +82367,7 @@
 IADD3 R2, R6, R5, R2 ;
 IADD3 R2, R8, R7, R2 ;
 IMAD.IADD R3, R2, 0x1, R9 ;
-BRA <+0x28b0> ;
+BRA <+0x2b70> ;
 S2R R15, SR_TID.X ;
 BSSY B1, <+0xb0> ;
 IMAD.MOV.U32 R18, RZ, RZ, RZ ;
@@ -82527,27 +82527,49 @@
 IADD3 R18, R4, R3, R18 ;
 IADD3 R18, R16, R7, R18 ;
 BSYNC B1 ;

cub.bench.find_if.base.base - sm_80

Showing 40/2998 diff lines, 1856 changes. - ⬇️ Full diff

--- base/cub.bench.find_if.base.base.sm_80
+++ test/cub.bench.find_if.base.base.sm_80
@@ -47678,13 +47678,13 @@
 S2R R0, SR_CTAID.X ;
 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
 ULDC UR4, c[0x0][0x18c] ;
-BSSY B0, <+0x41d0> ;
+BSSY B0, <+0x4490> ;
 USHF.L.U32 UR4, UR4, 0xc, URZ ;
 LOP3.LUT P0, RZ, R2, 0xf, RZ, 0xc0, !PT ;
 ULDC.64 UR6, c[0x0][0x118] ;
 IMAD.SHL.U32 R17, R0, 0x1000, RZ ;
 IADD3 R28, -R17, c[0x0][0x188], RZ ;
-@!P0 BRA <+0x2630> ;
+@!P0 BRA <+0x2790> ;
 ISETP.GE.U32.AND P0, PT, R28, 0x1000, PT ;
 @!P0 BRA <+0x18a0> ;
 S2R R2, SR_TID.X ;
@@ -48071,7 +48071,7 @@
 @!P0 STS [R4.X4+0x8], R3 ;
 BAR.SYNC.DEFER_BLOCKING 0x0 ;
 ISETP.NE.AND P0, PT, R2, RZ, PT ;
-@P0 BRA <+0x2930> ;
+@P0 BRA <+0x2bf0> ;
 LDS R2, [0xc] ;
 LDS.128 R4, [0x10] ;
 LDS.64 R8, [0x20] ;
@@ -48079,7 +48079,7 @@
 IADD3 R2, R6, R5, R2 ;
 IADD3 R2, R8, R7, R2 ;
 IMAD.IADD R3, R2, 0x1, R9 ;
-BRA <+0x28b0> ;
+BRA <+0x2b70> ;
 S2R R15, SR_TID.X ;
 BSSY B1, <+0xb0> ;
 IMAD.MOV.U32 R18, RZ, RZ, RZ ;
@@ -48239,27 +48239,49 @@
 IADD3 R18, R4, R3, R18 ;
 IADD3 R18, R16, R7, R18 ;
 BSYNC B1 ;

cub.bench.for_each.base.base - sm_80

Showing 40/2998 diff lines, 1856 changes. - ⬇️ Full diff

--- base/cub.bench.for_each.base.base.sm_80
+++ test/cub.bench.for_each.base.base.sm_80
@@ -43618,13 +43618,13 @@
 S2R R0, SR_CTAID.X ;
 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
 ULDC UR4, c[0x0][0x18c] ;
-BSSY B0, <+0x41d0> ;
+BSSY B0, <+0x4490> ;
 USHF.L.U32 UR4, UR4, 0xc, URZ ;
 LOP3.LUT P0, RZ, R2, 0xf, RZ, 0xc0, !PT ;
 ULDC.64 UR6, c[0x0][0x118] ;
 IMAD.SHL.U32 R17, R0, 0x1000, RZ ;
 IADD3 R28, -R17, c[0x0][0x188], RZ ;
-@!P0 BRA <+0x2630> ;
+@!P0 BRA <+0x2790> ;
 ISETP.GE.U32.AND P0, PT, R28, 0x1000, PT ;
 @!P0 BRA <+0x18a0> ;
 S2R R2, SR_TID.X ;
@@ -44011,7 +44011,7 @@
 @!P0 STS [R4.X4+0x8], R3 ;
 BAR.SYNC.DEFER_BLOCKING 0x0 ;
 ISETP.NE.AND P0, PT, R2, RZ, PT ;
-@P0 BRA <+0x2930> ;
+@P0 BRA <+0x2bf0> ;
 LDS R2, [0xc] ;
 LDS.128 R4, [0x10] ;
 LDS.64 R8, [0x20] ;
@@ -44019,7 +44019,7 @@
 IADD3 R2, R6, R5, R2 ;
 IADD3 R2, R8, R7, R2 ;
 IMAD.IADD R3, R2, 0x1, R9 ;
-BRA <+0x28b0> ;
+BRA <+0x2b70> ;
 S2R R15, SR_TID.X ;
 BSSY B1, <+0xb0> ;
 IMAD.MOV.U32 R18, RZ, RZ, RZ ;
@@ -44179,27 +44179,49 @@
 IADD3 R18, R4, R3, R18 ;
 IADD3 R18, R16, R7, R18 ;
 BSYNC B1 ;

github-actions · 2026-09-05T03:21:53Z

🥳 CI Workflow Results

🟩 Finished in 4h 53m: Pass: 100%/195 | Total: 4d 23h | Max: 4h 52m | Hits: 52%/1367847

See results here.

fbusato added 5 commits September 1, 2026 16:22

draft

70811f9

fix doc

0117697

update tests

ac2ee4b

add documentation

0db8158

move to a seperate file

73042cd

fbusato self-assigned this Sep 4, 2026

fbusato requested review from a team as code owners September 4, 2026 00:41

fbusato requested a review from gonidelis September 4, 2026 00:41

fbusato added this to CCCL Sep 4, 2026

fbusato requested a review from pciolkosz September 4, 2026 00:41

github-project-automation Bot moved this to Todo in CCCL Sep 4, 2026

cccl-authenticator-app Bot moved this from Todo to In Review in CCCL Sep 4, 2026

minor fix

70f958a

This comment has been minimized.

Sign in to view

davebayer reviewed Sep 4, 2026

View reviewed changes

Comment thread libcudacxx/include/cuda/std/__cccl/host_compiler.h

miscco reviewed Sep 4, 2026

View reviewed changes

This comment has been minimized.

Sign in to view

update documentation

4e04634

Navigation Menu

Uh oh!

Provide `CCCL_HOST_COMPILER` macro - #11195

Provide `CCCL_HOST_COMPILER` macro#11195
fbusato wants to merge 7 commits into
NVIDIA:mainfrom
fbusato:host-compiler-macro

fbusato commented Sep 4, 2026

Uh oh!

coderabbitai Bot commented Sep 4, 2026 •

edited

Loading

Summary by CodeRabbit

Walkthrough

Changes

Uh oh!

This comment has been minimized.

davebayer left a comment

Uh oh!

Uh oh!

Uh oh!

miscco Sep 4, 2026

Uh oh!

fbusato Sep 4, 2026

Uh oh!

miscco commented Sep 4, 2026

Uh oh!

This comment has been minimized.

fbusato commented Sep 4, 2026

Uh oh!

fbusato commented Sep 4, 2026

Uh oh!

github-actions Bot commented Sep 4, 2026

Uh oh!

github-actions Bot commented Sep 5, 2026

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

Uh oh!

Conversation

fbusato commented Sep 4, 2026

Description

Uh oh!

coderabbitai Bot commented Sep 4, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Summary by CodeRabbit

Walkthrough

Changes

Uh oh!

This comment has been minimized.

davebayer left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

miscco Sep 4, 2026

Choose a reason for hiding this comment

Uh oh!

fbusato Sep 4, 2026

Choose a reason for hiding this comment

Uh oh!

miscco commented Sep 4, 2026

Uh oh!

This comment has been minimized.

fbusato commented Sep 4, 2026

Uh oh!

fbusato commented Sep 4, 2026

Uh oh!

github-actions Bot commented Sep 4, 2026

🔬 CUB benchmark SASS comparison

‼️ Summary of Differences ‼️

Uh oh!

github-actions Bot commented Sep 5, 2026

🥳 CI Workflow Results

🟩 Finished in 4h 53m: Pass: 100%/195 | Total: 4d 23h | Max: 4h 52m | Hits: 52%/1367847

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

coderabbitai Bot commented Sep 4, 2026 •

edited

Loading