Add PRESTEP0 DDR pre-init step to boot protocol#44
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HiTool sends PRESTEP0 (a 64-byte DDR controller pre-init) before DDRSTEP0 for all SoCs. Without it, chips like hi3516av200/av300 fail during SPL transfer because DDR init doesn't complete properly. - Add optional PRESTEP0 field to SoCProfile schema - Send PRESTEP0 HEAD+DATA+TAIL before DDRSTEP0 when present - Add PRESTEP0 data to 66 chip profiles (extracted from HiTool 5.0.61) - Add hi3516av300 profile - Fix power-cycle timing: start handshake before power-on to catch fast-boot devices with <100ms bootrom windows - Add packet-level debug tracing to protocol (logger.debug) Tested on hi3516av300 hardware: full DDR→SPL→U-Boot transfer succeeds. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
logger.debug()calls throughout the protocol for diagnosing boot issues with-dflag.Changes
src/defib/profiles/schema.py— Add optionalPRESTEP0field toSoCProfilesrc/defib/protocol/hisilicon_standard.py— Send PRESTEP0 before DDRSTEP0 when present; add debug tracingsrc/defib/recovery/session.py— Split power cycle: off → start handshake → on (catches fast bootrom)src/defib/profiles/data/hi3516av300.json— New profiletests/test_protocol_robustness.py— Update ACK counts for PRESTEP0Test plan
uv run pytest tests/ -x -v --ignore=tests/fuzz— 326 passed🤖 Generated with Claude Code