Add PRESTEP1 DDR training step and fix boot timing

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Summary

• PRESTEP1: Add DDR training verification step (sent after DDRSTEP0). hi3516av200 requires this 128-byte bytecode to complete DDR initialization — without it, U-Boot crashes silently.
• Non-fatal TAIL: PRESTEP0/DDRSTEP0/PRESTEP1 TAIL frames are now non-fatal (av200 bootrom doesn't ACK them).
• Rehandshake after PRESTEP0: av200 bootrom goes silent after executing PRESTEP0 code, needs rehandshake before accepting DDRSTEP0.
• HEAD timeout: Increased from 30ms to 150ms — av200 needs ~100ms after handshake before accepting frames.
• Power-cycle timing: Flush serial buffer 1s after power-cycle API call to discard warm-reboot markers that cause false handshake triggers.

Test plan

• uv run pytest tests/ -x -v --ignore=tests/fuzz — 326 passed
• hi3516av200 hardware: full PRESTEP0→DDRSTEP0→PRESTEP1→SPL→U-Boot transfer, U-Boot boots
• hi3516av300 hardware: full install with --power-cycle (previous PR)

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