feat(runtime): integrate Verilog crawler and catalog

[HKU-LiBoyu]

Summary

This PR consolidates the Agentic Circuit Verilog runtime work and the pyCircuit RTL crawler into the pyCircuit repository.

• Adds 132 accepted runtime catalog entries under library/verilog/, with canonical wrappers, vendored dependency closures, manifests, provenance and license files. The package contains 449 closure files and 25 license files; existing PTO-ISA primitives remain intact.
• Adds the runtime discovery, candidate staging, dependency-closure, adapter, promotion, functional-oracle, Verilator/Yosys and vendoring tools under ools/runtime/.
• Adds the complete pyCircuit RTL crawler v0.14 and frozen 355-candidate inventory under ools/pycircuit_rtl_crawler_v0.14/.
• Restores and integrates the parameterized �c.var.priority_encode ACIR operation through verification, QueueGraph planning, gfsim C++/PYC generation, and PYC-to-Verilog code generation.
• Adds the priority encoder Python frontend example with both w8_lo_to_hi and w16_hi_to_lo configurations under �xamples/agentic-circuit/blocks/priority_encode_runtime/.
• Adds the runtime migration gate evidence under docs/gates/logs/runtime-verilog-migration-20260904/.

Validation

• Catalog verification: 132/132 accepted entries.
• Vendoring closure check: 132 passed, 0 failed.
• Representative packaged Verilator/Yosys gate: 6/6 passed using Verilator 5.051 and Yosys 0.68.
• Priority encoder functional oracle: passed.
• Python runtime tests: 85/85 passed.
• Priority encoder end-to-end flow: Python -> ACIR -> verified ACIR -> QueueGraph plan -> gfsim C++/PYC IR -> Verilog -> Verilator/Yosys, passed for both parameter configurations.
• WSL toolchain rebuilt with Ninja -j1.
• Catalog path audit found no absolute or legacy runtime paths.

Generated builds and test outputs remain under .pycircuit_out/ and are intentionally ignored. The full pre-commit bootstrap requires the first-time Node hook environment to finish installing; the local API-hygiene hook passed. Dynamic power is not claimed by this structural gate because no technology Liberty/activity trace is included.