GitHub - ProjetISIE/tp-codesign: TP CoDesign Verilog C

Name		Name	Last commit message	Last commit date
Latest commit History 34 Commits
soft		soft
.envrc		.envrc
.gitignore		.gitignore
DE2_115_pin_assignments.csv		DE2_115_pin_assignments.csv
flake.lock		flake.lock
flake.nix		flake.nix
modMultiPWM.v		modMultiPWM.v
modPWM.v		modPWM.v
pwmGen.qpf		pwmGen.qpf
pwmGen.qsf		pwmGen.qsf
pwmGen.qsys		pwmGen.qsys
pwmGenDe2_115.v		pwmGenDe2_115.v