n32 n32h760zil7-stb bsp修复完善，n32h497zgl7-evb和n32h487zgl7-evb bsp添加

.github/ALL_BSP_COMPILE.json

@@ -342,8 +342,9 @@
         "n32/n32gxx_lxx/n32l43xrl-stb",
         "n32/n32gxx_lxx/n32l436-evb",
         "n32/n32gxx_lxx/n32wb45xl-evb",
-        "n32g452xx/n32g452xx-mini-system",
-		"n32/n32hxxx/n32h760zil7-stb",
+        "n32/n32hxxx/n32h760zil7-stb",
+        "n32/n32hxxx/n32h487zgl7-evb",
+        "n32/n32hxxx/n32h497zgl7-evb",
         "apm32/apm32f103xe-minibroard",
         "apm32/apm32f407ig-minibroard",
         "apm32/apm32f407zg-evalboard",

bsp/README.md

@@ -317,21 +317,24 @@ This document is based on the RT-Thread mainline repository and categorizes the
 
 #### 🟡 N32
 
-| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT |
+| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT | PWM |ENCODER | LPTIM | NAND | ETH | ON-Chip FLASH |
 |----------|------|------|-----|-----|-----|---------|-----|-----|-----|-----|
-| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | - |
+| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
+| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
+| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
+| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
+
 
 #### 🟡 NRF5x
 
@@ -420,11 +423,6 @@ This document is based on the RT-Thread mainline repository and categorizes the
 | [swm320-mini](synwit/swm320-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
 | [swm341-mini](synwit/swm341-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
 
-#### ⚪ N32G452xx
-| BSP Name | GPIO | UART | ADC | CAN | DAC | Flash | HWTimer | I2C | PWM | RTC | SDIO | SPI | WDT |
-|----------|------|------|-----|-----|-----|-------|---------|-----|-----|-----|------|-----|-----|
-| [n32g452xx-mini-system](n32g452xx/n32g452xx-mini-system) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ |
-
 #### ⚪ W60x
 | BSP Name | GPIO | UART | ADC | Crypto | Flash | HWTimer | WDT | PWM | I2C | SPI |
 |----------|------|------|-----|--------|-------|---------|-----|-----|-----|-----|

bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_gcc.s

@@ -72,7 +72,7 @@ LoopFillZerobss:
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
-  bl  main
+  bl  entry
   bx  lr    
 .size  Reset_Handler, .-Reset_Handler
 

bsp/n32/n32hxxx/.clang-format-ignore

@@ -5,8 +5,5 @@
 
 # 从 .ignore_format.yml 迁移的规则
 /n32h760zil7-stb/board/Cube_Config/
-/n32h760zil7-stb/board/Cube_Config/data/
-/n32h760zil7-stb/board/Cube_Config/Driver/
-/n32h760zil7-stb/board/Cube_Config/MDK-ARM/
-/n32h760zil7-stb/board/Cube_Config/startup/
-/n32h760zil7-stb/board/Cube_Config/USER/
+/n32h487zgl7-evb/board/Cube_Config/
+/n32h497zgl7-evb/board/Cube_Config/

bsp/n32/n32hxxx/libraries/Kconfig

@@ -6,4 +6,14 @@ config SOC_SERIES_N32H7xx
     select ARCH_ARM_CORTEX_M7
     select SOC_FAMILY_N32
 
+config SOC_SERIES_N32H47x_48x
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_N32
+
+
+config SOC_SERIES_N32H49x
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_N32
 

bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/SConscript

@@ -12,24 +12,87 @@ if GetDepend(['RT_USING_PIN']):
     src += ['drv_gpio.c']
 
 if GetDepend(['RT_USING_SERIAL']):
-    src += ['drv_usart.c']
+    if GetDepend(['RT_USING_SERIAL_V2']):
+        src += ['drv_usart_v2.c']
+    else:
+        src += ['drv_usart.c']
+
+if GetDepend(['BSP_USING_CLOCK_TIMER']):
+    src += ['drv_tim.c']
+
+if GetDepend(['BSP_USING_PWM']):
+    src += ['drv_pwm.c', 'drv_tim.c']
 
 if GetDepend(['RT_USING_SPI']):
     src += ['drv_spi.c']
 
+if GetDepend(['RT_USING_QSPI']):
+    src += ['drv_qspi.c']
+
 if GetDepend(['RT_USING_I2C']):
     if GetDepend('BSP_USING_HARD_I2C1') or GetDepend('BSP_USING_HARD_I2C2') or GetDepend('BSP_USING_HARD_I2C3') or GetDepend('BSP_USING_HARD_I2C4') or GetDepend('BSP_USING_HARD_I2C5') or GetDepend('BSP_USING_HARD_I2C6') or GetDepend('BSP_USING_HARD_I2C7') or GetDepend('BSP_USING_HARD_I2C8') or GetDepend('BSP_USING_HARD_I2C9') or GetDepend('BSP_USING_HARD_I2C10'):
         src += ['drv_hard_i2c.c']
 
-if GetDepend('BSP_USING_ONCHIP_RTC'):
-    src += ['drv_rtc.c']
+if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
+    src += ['drv_eth.c']
 
 if GetDepend(['RT_USING_ADC']):
     src += ['drv_adc.c']
 
+if GetDepend(['RT_USING_DAC']):
+    src += ['drv_dac.c']
+
+if GetDepend(['RT_USING_CAN']):
+    if GetDepend(['SOC_SERIES_N32H7xx']) or GetDepend(['SOC_SERIES_N32H47x_48x']) or GetDepend(['SOC_SERIES_N32H49x']):
+        src += ['drv_fdcan.c']
+    else:
+        src += ['drv_can.c']
+
+if GetDepend(['RT_USING_PM']):
+    src += ['drv_pm.c']
+
+if GetDepend(['BSP_USING_LPTIM']):
+    src += ['drv_lptim.c']
+
+if GetDepend('BSP_USING_SDRAM'):
+    src += ['drv_sdram.c']
+
+if GetDepend(['BSP_USING_NAND']):
+    src += ['drv_nand.c']
+
+if GetDepend('BSP_USING_LCD'):
+    src += ['drv_lcd.c']
+
+if GetDepend('BSP_USING_ONCHIP_RTC'):
+    src += ['drv_rtc.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H49x']):
+    src += [os.path.join('drv_flash', 'drv_flash_h49x.c')]
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H47x_48x']):
+    src += [os.path.join('drv_flash', 'drv_flash_h47x_48x.c')]
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H7xx']):
+    src += [os.path.join('drv_flash', 'drv_flash_h7xx.c')]
+
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['BSP_USING_SDIO']):
+    if GetDepend('SOC_SERIES_N32H7xx'):
+        src += ['drv_sdmmc.c']
+    else:
+        src += ['drv_sdio.c']
+
+if GetDepend(['BSP_USING_PULSE_ENCODER']):
+    src += ['drv_pulse_encoder.c', 'drv_tim.c']
+
 
 path += [os.path.join(cwd, 'config')]
 
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    path += [os.path.join(cwd, 'drv_flash')]
+
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
 
 Return('group')

bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/dma_config.h

@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author           Notes
+ * 2026-04-07     ox-horse         first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* DMA1 channel1 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA)
+#define UART1_RX_DMA            DMA1
+#define UART1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
+#define UART1_RX_DMA_CHType     DMA1_CH1
+#define UART1_RX_DMA_IRQ        DMA1_Channel1_IRQn
+#define UART1_RX_DMA_RCC        RCC_AHB_PERIPHEN_DMA1
+#define UART1_RX_DMA_REQUEST    DMA_REMAP_USART1_RX
+#define UART1_RX_DMA_CHANNEL    1U
+#endif
+
+/* DMA1 channel2 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA)
+#define UART2_RX_DMA            DMA1
+#define UART2_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler
+#define UART2_RX_DMA_CHType     DMA1_CH2
+#define UART2_RX_DMA_IRQ        DMA1_Channel2_IRQn
+#define UART2_RX_DMA_RCC        RCC_AHB_PERIPHEN_DMA1
+#define UART2_RX_DMA_REQUEST    DMA_REMAP_USART2_RX
+#define UART2_RX_DMA_CHANNEL    2U
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA)
+#define UART3_RX_DMA            DMA1
+#define UART3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_CHType     DMA1_CH3
+#define UART3_RX_DMA_IRQ        DMA1_Channel3_IRQn
+#define UART3_RX_DMA_RCC        RCC_AHB_PERIPHEN_DMA1
+#define UART3_RX_DMA_REQUEST    DMA_REMAP_USART3_RX
+#define UART3_RX_DMA_CHANNEL    3U
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA)
+#define UART4_RX_DMA            DMA1
+#define UART4_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
+#define UART4_RX_DMA_CHType     DMA1_CH4
+#define UART4_RX_DMA_IRQ        DMA1_Channel4_IRQn
+#define UART4_RX_DMA_RCC        RCC_AHB_PERIPHEN_DMA1
+#define UART4_RX_DMA_REQUEST    DMA_REMAP_USART4_RX
+#define UART4_RX_DMA_CHANNEL    4U
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA)
+#define UART5_RX_DMA            DMA1
+#define UART5_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
+#define UART5_RX_DMA_CHType     DMA1_CH5
+#define UART5_RX_DMA_IRQ        DMA1_Channel5_IRQn
+#define UART5_RX_DMA_RCC        RCC_AHB_PERIPHEN_DMA1
+#define UART5_RX_DMA_REQUEST    DMA_REMAP_UART5_RX
+#define UART5_RX_DMA_CHANNEL    5U
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA)
+#define UART6_RX_DMA            DMA1
+#define UART6_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler
+#define UART6_RX_DMA_CHType     DMA1_CH6
+#define UART6_RX_DMA_IRQ        DMA1_Channel6_IRQn
+#define UART6_RX_DMA_RCC        RCC_AHB_PERIPHEN_DMA1
+#define UART6_RX_DMA_REQUEST    DMA_REMAP_UART6_RX
+#define UART6_RX_DMA_CHANNEL    6U
+#endif
+
+/* DMA1 channel7 */
+#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA)
+#define UART7_RX_DMA            DMA1
+#define UART7_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
+#define UART7_RX_DMA_CHType     DMA1_CH7
+#define UART7_RX_DMA_IRQ        DMA1_Channel7_IRQn
+#define UART7_RX_DMA_RCC        RCC_AHB_PERIPHEN_DMA1
+#define UART7_RX_DMA_REQUEST    DMA_REMAP_UART7_RX
+#define UART7_RX_DMA_CHANNEL    7U
+#endif
+
+/* DMA1 channel8 */
+#if defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA)
+#define UART8_RX_DMA            DMA1
+#define UART8_RX_DMA_IRQHandler DMA1_Channel8_IRQHandler
+#define UART8_RX_DMA_CHType     DMA1_CH8
+#define UART8_RX_DMA_IRQ        DMA1_Channel8_IRQn
+#define UART8_RX_DMA_RCC        RCC_AHB_PERIPHEN_DMA1
+#define UART8_RX_DMA_REQUEST    DMA_REMAP_UART8_RX
+#define UART8_RX_DMA_CHANNEL    8U
+#endif
+
+/* DMA2 channel1 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA)
+#define UART1_TX_DMA            DMA2
+#define UART1_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler
+#define UART1_TX_DMA_CHType     DMA2_CH1
+#define UART1_TX_DMA_IRQ        DMA2_Channel1_IRQn
+#define UART1_TX_DMA_RCC        RCC_AHB_PERIPHEN_DMA2
+#define UART1_TX_DMA_REQUEST    DMA_REMAP_USART1_TX
+#define UART1_TX_DMA_CHANNEL    1U
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA)
+#define UART2_TX_DMA            DMA2
+#define UART2_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler
+#define UART2_TX_DMA_CHType     DMA2_CH2
+#define UART2_TX_DMA_IRQ        DMA2_Channel2_IRQn
+#define UART2_TX_DMA_RCC        RCC_AHB_PERIPHEN_DMA2
+#define UART2_TX_DMA_REQUEST    DMA_REMAP_USART2_TX
+#define UART2_TX_DMA_CHANNEL    2U
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA)
+#define UART3_TX_DMA            DMA2
+#define I2C10_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler
+#define UART3_TX_DMA_CHType     DMA2_CH3
+#define UART3_TX_DMA_IRQ        DMA2_Channel3_IRQn
+#define UART3_TX_DMA_RCC        RCC_AHB_PERIPHEN_DMA2
+#define UART3_TX_DMA_REQUEST    DMA_REMAP_USART3_TX
+#define UART3_TX_DMA_CHANNEL    3U
+#endif
+
+/* DMA2 channel4 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA)
+#define UART4_TX_DMA            DMA2
+#define UART4_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler
+#define UART4_TX_DMA_CHType     DMA2_CH4
+#define UART4_TX_DMA_IRQ        DMA2_Channel4_IRQn
+#define UART4_TX_DMA_RCC        RCC_AHB_PERIPHEN_DMA2
+#define UART4_TX_DMA_REQUEST    DMA_REMAP_USART4_TX
+#define UART4_TX_DMA_CHANNEL    4U
+#endif
+
+/* DMA2 channel5 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA)
+#define UART5_TX_DMA            DMA2
+#define UART5_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
+#define UART5_TX_DMA_CHType     DMA2_CH5
+#define UART5_TX_DMA_IRQ        DMA2_Channel5_IRQn
+#define UART5_TX_DMA_RCC        RCC_AHB_PERIPHEN_DMA2
+#define UART5_TX_DMA_REQUEST    DMA_REMAP_UART5_TX
+#define UART5_TX_DMA_CHANNEL    5U
+#endif
+
+/* DMA2 channel6 */
+#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA)
+#define UART6_TX_DMA            DMA2
+#define UART6_TX_DMA_IRQHandler DMA2_Channel6_IRQHandler
+#define UART6_TX_DMA_CHType     DMA2_CH6
+#define UART6_TX_DMA_IRQ        DMA2_Channel6_IRQn
+#define UART6_TX_DMA_RCC        RCC_AHB_PERIPHEN_DMA2
+#define UART6_TX_DMA_REQUEST    DMA_REMAP_UART6_TX
+#define UART6_TX_DMA_CHANNEL    6U
+#endif
+
+/* DMA2 channel7 */
+#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA)
+#define UART7_TX_DMA            DMA2
+#define UART7_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
+#define UART7_TX_DMA_CHType     DMA2_CH7
+#define UART7_TX_DMA_IRQ        DMA2_Channel7_IRQn
+#define UART7_TX_DMA_RCC        RCC_AHB_PERIPHEN_DMA2
+#define UART7_TX_DMA_REQUEST    DMA_REMAP_UART7_TX
+#define UART7_TX_DMA_CHANNEL    7U
+#endif
+
+/* DMA2 channel8 */
+#if defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA)
+#define UART8_TX_DMA            DMA2
+#define UART8_TX_DMA_IRQHandler DMA2_Channel8_IRQHandler
+#define UART8_TX_DMA_CHType     DMA2_CH8
+#define UART8_TX_DMA_IRQ        DMA2_Channel8_IRQn
+#define UART8_TX_DMA_RCC        RCC_AHB_PERIPHEN_DMA2
+#define UART8_TX_DMA_REQUEST    DMA_REMAP_UART8_TX
+#define UART8_TX_DMA_CHANNEL    8U
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */
+