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1. Asynchronous_FIFO Asynchronous_FIFO Public

   Asynchronous FIFO design and verification in SystemVerilog based on Clifford Cummings’ “Simulation and Synthesis Techniques for Asynchronous FIFO Design,” using Gray code pointers that are synchron…

   SystemVerilog

2. Quantitative_Evaluation_of_Tomasulo_Based_Microarchitectures Quantitative_Evaluation_of_Tomasulo_Based_Microarchitectures Public

   A C++ simulator that models three versions of Tomasulo's Algorithm. Model A does Dynamic Scheduling, Model B has dynamic scheduling, RoB but no Speculation and Model C has both along with a single …

   C++

3. Weighted-Round-Robin-Arbiter_-Assertion-Based-Verification Weighted-Round-Robin-Arbiter_-Assertion-Based-Verification Public

   This project implements a weighted round-robin arbiter in SystemVerilog for sharing resources between multiple requesters. Each requester is given a weight, and grants are given based on weight and…

   SystemVerilog

4. MIPS-5-Stage-Pipeline-Simulator MIPS-5-Stage-Pipeline-Simulator Public

   MIPS Simulator with three following modes: ***A. Functional simulator *** B. No pipeline forwarding ***C. Pipeline forwarding

   SystemVerilog

5. Split-L1-Cache-with-MESI-coherence-and-LRU-Replacement Split-L1-Cache-with-MESI-coherence-and-LRU-Replacement Public

   Designed a split L1 cache (separate instruction and data) with MESI coherence protocol to maintain consistency across cores and LRU replacement to manage cache evictions and improve hit rate under …

   SystemVerilog

6. Parallelization_of_Artificial_Bee_Colony_Algorithm- Parallelization_of_Artificial_Bee_Colony_Algorithm- Public

   Work-in-progress C++ implementation of ABC algorithm with a focus on parallelization. The goal is to distribute bee agents and fitness evaluations across multiple threads to reduce runtime on expen…