Sync with upstream (2026-05-20): 5dfe1056b85f249e7b4ad454a59f2951c716191e #4550
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Sync with upstream (2026-05-20): 5dfe1056b85f249e7b4ad454a59f2951c716191e
#4550dkm wants to merge 454 commits into
dkm wants to merge 454 commits into
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…gned bitfield extractions
Some functional change as was already posted, this time with a testcase. Given
it's been in my tester and through the pre-commit CI system, I'm going forward
now.
--
So as the PR notes, this is an attempt to squeeze out some instructions from a
hot part of leela, the random number generator in particular.
typedef unsigned int uint32;
uint32 random(uint32 s1) {
const uint32 mask = 0xffffffff;
s1 = (((s1 & 0xFFFFFFFEU) << 12) & mask);
return s1;
}
Generates this RISC-V code:
slli a5,a0,44 # 25 [c=4 l=4] ashldi3
srai a0,a5,44 # 26 [c=4 l=4] ashrdi3
andi a0,a0,-2 # 21 [c=4 l=4] *anddi3/1
slli a0,a0,12 # 22 [c=4 l=4] ashldi3
But this is an equivalent sequence:
andi a0, a0, -2
slliw a0, a0, 12
The key is realizing that the the first two statements are just a sign extended
bitfield of length 20. That ultimately gets shifted left 12 bits. 20+12 = 32,
so we can at least conceptually use slliw (shift left sign extending result
from SI to DI). The andi just turns off the low bit.
Given a sign extracted bitfield starting at bit 0, of size N that is then left
shifted by M where N+M == 32 is a natural slliw instruction. However, when I
tried to recognize that and generate the slliw form I saw code quality
regressions that didn't look particularly reasonable to try and fix. So we
want to be more selective about recognizing that idiom. So we recognize it
when we subsequently mask off some bits and the mask can be encoded via andi.
This likely could be extended to other logical operations that don't ultimately
affect the SI sign bit.
PR target/124955
gcc/
* config/riscv/riscv.md (masked shifted bitfield extraction): New
splitter to utilize slliw to eliminate the need for sign extnesion.
gcc/testsuite/
* gcc.target/riscv/pr124955.c: New test
Bootstrapped and regression tested in x86. PR tree-optimization/119422 gcc/ChangeLog: * match.pd(`(bool >= A) >= A -> bool >= A`): New pattern. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/pr119422.c: New test. * gcc.dg/tree-ssa/pr119422-2.c: New test.
…[PR125087] The static analyser cppcheck reported a pointless assignment in function free_format_data. The intent of the assignment was to finally nullify the pointer to allocated format data after memory has been freed. Since C does not support references, add a level of indirection to the function argument so that the dereferenced argument can be nullified. PR libfortran/125087 libgfortran/ChangeLog: * io/format.c (free_format_data): Change argument from pointer to format_data to pointer to pointer of object. (free_format_hash_table): Adjust argument passed to free_format_data. (save_parsed_format): Likewise. * io/format.h (free_format_data): Adjust prototype. * io/transfer.c (st_read_done_worker): Adjust argument passed to free_format_data. (st_write_done_worker): Likewise.
…s on big-endian targets This patch resolves PR middle-end/124637, a wrong code regression when passing a struct as a register on big-endian targets. On big-endian targets, store_constructor fills fields from the most significant bits, so for structs narrower than word size, any padding is incorrectly placed in the least significant bytes. This issue is fixed (on affected targets) by using a (unsigned) right shift on the value determined by store_constructor to correctly align the structure in the least significant bytes, and place the padding in the high bits. Many thanks to Manjunath Matti for testing this patch on real hardware, and Drea Pinski for reviewing/approving it. The new test case may be a little fragile, but currently "works for me". Please feel free to tweak it for powerpc variants/environments I've not consider/encountered. 2026-05-08 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog PR middle-end/124637 * calls.cc (load_register_parameters): If using store_constructor to place a constant structure in a register, use a right shift to align the structure/padding if required on big-endian targets. gcc/testsuite/ChangeLog PR middle-end/124637 * gcc.target/powerpc/pr124637.c: New test case.
The patch that allowed DECL_NTTP_OBJECT_P in invalid_tparm_referent_p also added the assert checking for tinfos/__func__ (r14-8189). But in these tests we got to the assert with a temporary object coming from create_temporary_var: either a reference temporary or compound literal temporary. The former could be checked by seeing if the name starts with _ZGR but the latter don't have it. So perhaps we can just check DECL_IGNORED_P, always set for create_temporary_var objects. PR c++/115181 PR c++/125043 PR c++/124979 gcc/cp/ChangeLog: * pt.cc (invalid_tparm_referent_p): Allow DECL_IGNORED_P in an assert. gcc/testsuite/ChangeLog: * g++.dg/cpp1z/nontype-auto27.C: New test. * g++.dg/cpp1z/nontype-auto28.C: New test. * g++.dg/cpp2a/nontype-class75.C: New test. Reviewed-by: Jason Merrill <jason@redhat.com>
…25234] In r17-231-gc65691bc5a2873, I messed up the resulting constant for `(a != b) & ((a | b) == 0)` and `(a == b) | ((a | b) != 0)`. I had swapped which one was resulting in true/false. This fixes the issue and adds a testcase to make sure it does not regress again. Pushed as obvious after a bootstrap/test on x86_64-linux-gnu. PR tree-optimization/125234 gcc/ChangeLog: * match.pd (`(a !=/== b) &\| ((a|b) ==/!= 0)`): Fix resulting constant form. gcc/testsuite/ChangeLog: * gcc.dg/torture/pr125234-1.c: New test. Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
This patch makes cp_genericize_r unconditionally walk DECL_VALUE_EXPR as per the TODO from r16-7523. PR c++/121500 gcc/cp/ChangeLog: * cp-gimplify.cc (cp_genericize_r): Unconditionally walk DECL_VALUE_EXPR. Reviewed-by: Jason Merrill <jason@redhat.com>
For CONST_VECTOR source, check CONST0_RTX and CONSTM1_RTX with
X86_CSE_CONSTM1_VECTOR when placing
(insn 32 2 7 2 (set (reg:V2DI 114)
(const_vector:V2DI [
(const_int 0 [0]) repeated x2
])) -1
(nil))
after
(note 2 3 32 2 NOTE_INSN_FUNCTION_BEG)
for X86_CSE_VEC_DUP, not X86_CSE_CONST0_VECTOR or X86_CSE_CONSTM1_VECTOR,
after replacing redundant vector loads:
(insn 31 15 16 2 (set (reg/v/f:DI 99 [ d ])
(const_int 0 [0])) "x.c":5:16 -1
(nil))
...
(insn 18 17 19 2 (set (reg:V2DI 111 [ _22 ])
(vec_duplicate:V2DI (reg/v/f:DI 99 [ d ]))) "x.c":5:16 9345 {*vec_dupv2di}
(nil))
...
(insn 29 12 15 2 (set (reg/v/f:DI 98 [ c ])
(const_int 0 [0])) "x.c":5:16 -1
(nil))
...
(insn 20 19 21 2 (set (reg:V2DI 112 [ _20 ])
(vec_duplicate:V2DI (reg/v/f:DI 98 [ c ]))) "x.c":5:16 9345 {*vec_dupv2di}
(nil))
with
(insn 18 17 19 2 (set (reg:V2DI 111 [ _22 ])
(reg:V2DI 114)) "x.c":5:16 2454 {movv2di_internal}
(nil))
and
(insn 20 19 21 2 (set (reg:V2DI 112 [ _20 ])
(reg:V2DI 114)) "x.c":5:16 2454 {movv2di_internal}
(nil))
Adjust gcc.target/i386/pr124407-1.c for the expected x86_cse dump:
(insn 35 8 9 2 (set (reg:V16QI 125)
(const_vector:V16QI [
(const_int 0 [0]) repeated x16
])) -1
(nil))
instead of
(insn 36 8 35 2 (set (reg:SF 126)
(const_double:SF 0.0 [0x0.0p+0])) -1
(nil))
(insn 35 36 9 2 (set (reg:V4SF 125)
(vec_duplicate:V4SF (reg:SF 126))) -1
(nil))
gcc/
PR target/125239
* config/i386/i386-features.cc (ix86_place_single_vector_set):
For CONST_VECTOR source, check CONST0_RTX with
X86_CSE_CONST0_VECTOR and CONSTM1_RTX with X86_CSE_CONSTM1_VECTOR.
(ix86_broadcast_inner): Set x86_cse kind to X86_CSE_CONST0_VECTOR
for CONST0_RTX and X86_CSE_CONSTM1_VECTOR for CONSTM1_RTX.
gcc/testsuite/
PR target/125239
* gcc.target/i386/pr124407-1.c: Adjusted.
* gcc.target/i386/pr125239.c: New test.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
This is the first step in constification (and/or C++ification) of the cfghooks. Currently we compare variables to figure out what the current IR type is. Rather let's move the ir_type into the cfghooks. This will help with constification due to sel-sched overloading one of the hooks. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * cfghooks.cc (current_ir_type): Return cfghooks' ir field. * cfghooks.h (struct cfg_hooks): Add ir field. * cfgrtl.cc (rtl_cfg_hooks): Update for new ir field. (cfg_layout_rtl_cfg_hooks): Likewise. * tree-cfg.cc (gimple_cfg_hooks): Likewise. Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Now we have an IR field, we can remove the name field. The only time the name is used was for internal errors so having this field outside of the hooks is better anyways. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * cfghooks.cc (current_ir_name): New function. (dump_bb_for_graph): Use current_ir_name instead of accessing the name field. (dump_bb_as_sarif_properties): Likewise. (redirect_edge_and_branch): Likewise. (can_remove_branch_p): Likewise. (redirect_edge_and_branch_force): Likewise. (split_block_1): Likewise. (move_block_after): Likewise. (delete_basic_block): Likewise. (split_edge): Likewise. (create_basic_block_1): Likewise. (can_merge_blocks_p): Likewise. (predict_edge): Likewise. (predicted_by_p): Likewise. (merge_blocks): Likewise. (make_forwarder_block): Likewise. (force_nonfallthru): Likewise. (can_duplicate_block_p): Likewise. (duplicate_block): Likewise. (block_ends_with_call_p): Likewise. (block_ends_with_condjump_p): Likewise. (flow_call_edges_add): Likewise. * cfghooks.h (struct cfg_hooks): Remove the name field. * cfgrtl.cc (rtl_cfg_hooks): Update for the removal of the name field. (cfg_layout_rtl_cfg_hooks): Likewise. * tree-cfg.cc (struct cfg_hooks): Likewise. Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
This constifies the hooks so the structs can't be changed at runtime. The only odd place where we need to handle special is sel-sched. This is because we make a copy of the current cfghooks and then use its own. This changes things slightly there, there is still a copy used but instead of copying back into the current cfghooks, we just change the pointer back to the original one. This code is only enabled by ia64 backend by default so I doubt it will change. Boostrapped and tested on x86_64-linux-gnu. PR middle-end/117871 gcc/ChangeLog: * cfghooks.cc (cfg_hooks): Change the type to be a pointer to a const struct cfg_hooks. (get_cfg_hooks): Return the current pointer rather the struct. (set_cfg_hooks): Change the argument type and set the cfg_hooks directly to it. * cfghooks.h (gimple_cfg_hooks): Constify. (rtl_cfg_hooks): Likewise. (cfg_layout_rtl_cfg_hooks): Likewise. (get_cfg_hooks): Update declration. (set_cfg_hooks): Likewise. * cfgrtl.cc (rtl_cfg_hooks): Constify. (cfg_layout_rtl_cfg_hooks): Likewise. * sel-sched-ir.cc (orig_cfg_hooks): Change to a pointer. (sel_create_basic_block): Update for orig_cfg_hooks being a pointer. (sel_register_cfg_hooks): Update for the constification of cfg_hooks. * tree-cfg.cc (gimple_cfg_hooks): Constify. Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Add a test for https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125245 which has been fixed by commit 7d84a35 Author: H.J. Lu <hjl.tools@gmail.com> Date: Sat May 9 05:58:09 2026 +0800 x86_cse: Check CONST0_RTX and CONSTM1_RTX PR target/125245 * gcc.target/i386/pr125245.c: New test. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
…PR125217]
Currently when -fcf-protection=return and zcmp are enabled this code is
generated:
sspush ra
cm.push {ra, s0-s1}, -32
..
cm.popret {ra, s0-s1}, 32
riscv_expand_epilogue will skip emitting sspopchk when cm.popret is
emitted. After this patch we will no longer emit cm.popret and instead
use cm.pop + sspopchk + a regular return:
sspush ra
cm.push {ra, s0-s1}, -32
..
cm.pop {ra, s0-s1}, 32
sspopchk ra
jr ra
Regtested for rv32g & rv64g.
PR target/125217
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_gen_multi_pop_insn): Rename variable.
(riscv_expand_epilogue): Don't emit cm.popret with shadow stack.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/ssp-zcmp.c: New test.
The parts of this patch is fix the problem are chunks 2 and 3. Chunk3 prevents gfc_conv_intrinsic_caf_get from working in the module namespace, when the array symbol is in a module. Equally, though, gfc_current_ns is not necessarily in the referencing procedure namespace. The second chunk makes sure that this is the case. As an aside, it seems to us that it makes considerably more sense that gfc_current_ns be that of the current procedure. The first chunk makes sure that result symbol initialization does not occur outside the function. Passes regtesting with FC44/x86_64. 2026-05-10 Andre Vehreschild <vehre@gcc.gnu.org> Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/125051 * trans-decl.cc (gfc_get_symbol_decl): gfc_defer_symbol_init must not be called for PDT types, classes or types with PDT (gfc_generate_function_code): If gfc_current_ns is not the same as the function namespace, stash it,change it to the function namespace and restore after translation of the code. * trans-intrinsic.cc (gfc_conv_intrinsic_caf_get): If the array is in a module, use the symbol namespace. * trans-openmp.cc (gfc_trans_omp_array_reduction_or_udr): If the current namespace is not that of the procedure, change to the procedure namspace and revert on leaving this function. gcc/testsuite/ PR fortran/125051 * gfortran.dg/coarray/pr125051.f90: New test.
Convert vector load:
(insn 14 465 412 3 (set (reg:SI 507 [ j_lsm.26 ])
(const_int 2 [0x2])) "foo.c":10:12 discrim 2 100 {*movsi_internal}
(nil))
...
(insn 518 507 434 16 (set (reg:V2SI 493)
(reg:V2SI 517)) 2066 {*movv2si_internal}
(nil))
to constant integer load:
(insn 566 55 56 6 (set (subreg:DI (reg:V2SI 517) 0)
(const_int 8589934594 [0x200000002])) -1
(nil))
...
(insn 518 507 434 16 (set (reg:V2SI 493)
(reg:V2SI 517)) 2066 {*movv2si_internal}
(nil))
Tested on Linux/x86-64.
gcc/
PR target/125238
* config/i386/i386-features.cc (ix86_broadcast_inner): Set kind
to X86_CSE_CONST_VECTOR if the vector load can be converted to
constant integer load.
gcc/testsuite/
PR target/125238
* gcc.target/i386/pr125238.c: New test.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
The is_mappable_routine function has to identify all routines that are lengthety-mapped. This includes math functions like sin and cos. This patch removes the handling of several math routines that we are not implementing as compiler builtins: arccosdg cbrt curt gammaincgf arccotdg cosdg erf sindg arcsindg cospi erfc sinpi arctandg cot gamma tandg beta cotdg gammainc tanpi betainc cotpi gammaincg If these routines ever get added to the extended standard prelude, it will be as regular procedures rather than compiler builtins. Signed-off-by: Jose E. Marchesi <jemarch@gnu.org> Reported-by: "Nelson H. F. Beebe" <beebe@math.utah.edu> gcc/algol68/ChangeLog * a68-parser-taxes.cc (is_mappable_routine): Remove handling of non-implemented math functions.
This just aligns gnattools with both c++tools and gotools. gnattools/ PR ada/125232 * Makefile.in (ADA_FOR_BUILD): Delete. (ADA_FOR_TARGET): Likewise. (LDFLAGS): Set to @LDFLAGS@.
The problem is that Expand_Image_Attribute incorrectly fetches the root type for enumeration types, thus bypassing a clause present on the derived type. The fix is to change the two fields Lit_Indexes and Lit_Strings defined for enumeration types and subtypes to be formally present on root types only, as well as to make Expand_Image_Attribute stick to base types. gcc/ada/ PR ada/125240 * gen_il-gen-gen_entities.adb (Enumeration_Kind): Make Lit_Indexes and Lit_Strings be defined for root types only. * einfo.ads (Lit_Hash): Adjust description. (Lit_Indexes): Likewise. (Lit_Strings): Likewise. (E_Enumeration_Type): Likewise. * exp_imgv.adb (Expand_Image_Attribute): Do not fetch the root type for enumeration types, except for character types, and adjust. gcc/testsuite/ * gnat.dg/enum6.adb: New test.
It is quite dishonest to check the false_value and output "true", and we should strive to be honest. gcc/ChangeLog: * gcov.cc (json_set_prime_path_coverage): Read arc.true_value.
…down to xor
So this is the target independent work to finish resolving pr80770. It's a
combination of Shreya's efforts and my own.
To recap, the basic idea is we want to simplify RTL blobs which ultimately are
just flipping a bit. Consider:
> (set (reg:DI 153)
> (ior:DI (and:DI (reg:DI 140 [ *s_4(D) ])
> (const_int 254 [0xfe]))
> (and:DI (not:DI (reg:DI 140 [ *s_4(D) ]))
> (const_int 1 [0x1]))))
The first operand of the IOR clears the low bit of the source register leaving
everything else unchanged. The second operand of the IOR clears everything but
the low bit and flips the low bit. When we IOR those together we get the
original value with the lowest bit flipped. The key is to realize we have the
same pseudo in both arms and there are no bits in common for the constants. So
this works for an arbitrary bit(s) as long as the constants have the right
form.
That gets us good code on riscv and almost certainly helps other targets.
There is another form which shows up on the H8 and possibly other targets
sub-word arithmetic. op0 and op1 are respectively:
> (gdb) p debug_rtx (op0)
> (and:QI (reg:QI 24 [ *s_4(D) ])
> (const_int 127 [0x7f]))
> $1 = void
> (gdb) p debug_rtx (op1)
> (plus:QI (and:QI (reg:QI 24 [ *s_4(D) ])
> (const_int -128 [0xffffffffffffff80]))
> (const_int -128 [0xffffffffffffff80]))
> $2 = void
Note we're in QImode. op1 just flips the highest QImode bit. If there are
carry-outs, we don't really care about them. The net is we can capture that
case on the H8 by verifying this form flips the highest bit for the given mode.
Otherwise the carry-outs are relevant and our transformation is incorrect.
Plan is to commit Friday. While it has been tested with the usual bootstraps
as well as testing on various cross platforms, I'm more comfortable giving
folks time to take a looksie to see if Shreya or I missed anything critical.
For the testcase in question before/afters look like this:
x86:
movzbl (%rdi), %eax
movl %eax, %edx
andl $-2, %eax
andl $1, %edx
xorl $1, %edx
orl %edx, %eax
movb %al, (%rdi)
Turns into:
xorb $1, (%rdi)
RISC-V:
lbu a5,0(a0)
andi a4,a5,1
xori a4,a4,1
andi a5,a5,-2
or a5,a5,a4
sb a5,0(a0)
Turns into:
lbu a5,0(a0)
xori a5,a5,1
sb a5,0(a0)
PR rtl-optimization/80770
gcc/
* rtl.h (simplify_context::simplify_ior_with_common_term): Add
new method.
(simplify_context::simplify_binary_operation_1): Use new method.
* simplify-rtx.cc (simplify_context::simplify_ior_with_common_term):
New method.
gcc/testsuite/
* gcc.target/riscv/pr80770.c: New test.
* gcc.target/riscv/pr80770-2.c: New test.
* gcc.target/h8300/pr80770.c: New test.
* gcc.target/h8300/pr80770-2.c: New test.
Co-authored-by: Jeff Law <jeffrey.law@oss.qualcomm.com>
… [PR125209] In combine_simplify_rtx, CLOBBER can be returned, which is propagated to make_compound_operation. When make_compound_operation_int then calls simplify_subreg, it triggers a gcc_assert, because the mode is neither inner, nor void. This results in an ICE. We fix this by checking if we got CLOBBER before calling simplify_subreg from make_compound_operation and bail out; we return NULL_RTX. Testcase from the bug report by Zhendong Su. Bootstrapped and tested on x86_64-linux-gnu. PR rtl-optimization/125209 gcc/ * combine.cc (make_compound_operation_int): Return NULL_RTX if we got CLOBBER. gcc/testsuite/ * gcc.dg/pr125209.c: New test. Signed-off-by: Boudewijn van der Heide <boudewijn@delta-utec.com>
ChangeLog: * MAINTAINERS: Update my email and add myself to the DCO section. Signed-off-by: Naveen <naveen.siddegowda@oss.qualcomm.com>
Extend AdvSIMD constant materialization to recognize vectors where only the low element is a representable floating-point constant and all other elements are zero. Bootstrapped and tested on aarch64-linux-gnu. PR target/113856 gcc/ChangeLog: * config/aarch64/aarch64-protos.h (aarch64_output_simd_mov_imm_low): New. (aarch64_const_vec_fmov_p): New. * config/aarch64/aarch64-simd.md (mov<mode>): Do not expand constant vectors handled by aarch64_const_vec_fmov_p into VDUP. (*aarch64_simd_mov<VDMOV:mode>): Add Dc alternatives for FMOV based SIMD constant moves. (*aarch64_simd_mov<VQMOV:mode>): Likewise. * config/aarch64/aarch64.cc (aarch64_const_vec_fmov_p): New function. (aarch64_output_simd_mov_imm_low): New function. * config/aarch64/constraints.md (Dc): New constraint. gcc/testsuite/ChangeLog: * gcc.target/aarch64/pr113856.c: New test. Signed-off-by: Naveen <naveen.siddegowda@oss.qualcomm.com>
…426]
This fixes
t.c:6:1: error: unable to find a register to spill
6 | }
| ^
for target avr. In the PR we are given a patch which makes use of hard
register constraints in the machine description for divmodhi4. Prior
combine we have for the test from the PR
(insn 7 6 8 2 (parallel [
(set (reg:HI 46 [ _1 ])
(div:HI (reg/v:HI 44 [ k ])
(reg:HI 48)))
(set (reg:HI 47)
(mod:HI (reg/v:HI 44 [ k ])
(reg:HI 48)))
(clobber (scratch:HI))
(clobber (scratch:QI))
]) "t.c":5:5 602 {divmodhi4}
(expr_list:REG_DEAD (reg:HI 48)
(expr_list:REG_DEAD (reg/v:HI 44 [ k ])
(expr_list:REG_UNUSED (reg:HI 47)
(nil)))))
(insn 8 7 9 2 (set (reg:HI 22 r22)
(symbol_ref/f:HI ("*.LC0") [flags 0x2] <var_decl 0x3fff7950d10 *.LC0>)) "t.c":5:5 128 {*movhi_split}
(nil))
(insn 9 8 10 2 (set (reg:HI 24 r24)
(reg:HI 46 [ _1 ])) "t.c":5:5 128 {*movhi_split}
(expr_list:REG_DEAD (reg:HI 46 [ _1 ])
(nil)))
The patched instruction divmodhi4 constraints operand 2 (here pseudo
48) to hard register 22. Combine merges insn 7 into 9 by crossing a
hard register assignment of register 22.
(note 7 6 8 2 NOTE_INSN_DELETED)
(insn 8 7 9 2 (set (reg:HI 22 r22)
(symbol_ref/f:HI ("*.LC0") [flags 0x2] <var_decl 0x3fff7950d10 *.LC0>)) "t.c":5:5 128 {*movhi_split}
(nil))
(insn 9 8 10 2 (parallel [
(set (reg:HI 24 r24)
(div:HI (reg:HI 49 [ k ])
(reg:HI 48)))
(set (reg:HI 47)
(mod:HI (reg:HI 49 [ k ])
(reg:HI 48)))
(clobber (scratch:HI))
(clobber (scratch:QI))
]) "t.c":5:5 602 {divmodhi4}
(expr_list:REG_DEAD (reg:HI 48)
(expr_list:REG_DEAD (reg:HI 49 [ k ])
(nil))))
This leaves us with a conflict for pseudo 48 in the updated insn 9 since
register 22 is live here.
Fixed by pulling the sledge hammer and rejecting any resulting insn
which makes use of hard register constraints. Ideally we would skip
based on the fact whether a combination crosses a hard register
assignment and the corresponding hard register is also referred by a
single register constraint of the resulting insn.
PR rtl-optimization/121426
gcc/ChangeLog:
* combine.cc (recog_for_combine_1): Reject insns which make use
of hard register constraints.
The following adds special handling to OMP SIMD vector call costs which were not costed at all and for which a single simple vector stmt isn't appropriate. PR125174 shows that even when AVX imposes more overhead (from also slightly bogus costing) than SSE, when there's two OMP SIMD calls involved doing less of those should trump that. PR target/125174 * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): Cost calls as 10 times FMA.
…_range. If _M_format_range was called with prvalue of span S (or any contiguous_range), the previous chain of if-contexpr will call _M_format_range<S&>, then _M_format_range<const S&> and then format(string_view). By checking for contiguous_range first, it calls format(string_view) direclty, removing unnecessary instantiations and symbols. Similary, for all prvalues of type R, that meet __simply_formattable_range R, we were instantiating _M_format_range<R&> and then _M_format_range<const R&>. By moving the if for __simply_formattable_range before is_lvalue_reference_v, we call _M_format_range<const R&> direclty. libstdc++-v3/ChangeLog: * include/std/format (__formatter_str::_M_format_range): Reorder constexpr checks, to reduce number of instantiations. Reviewed-by: Jonathan Wakely <jwakely@redhat.com> Signed-off-by: Tomasz Kamiński <tkaminsk@redhat.com>
Previously, this code
extern int shl;
int get_shl(void) { return shl; }
gave errors like
$ x86_64-w64-mingw32-gcc -masm=intel test.c
ccUSyr0f.s: Assembler messages:
ccUSyr0f.s:24: Error: invalid use of operator "shl"
because it contained
.refptr.shl:
.quad shl
This `shl` should have referenced the symbol, but it appeared in an expression
context, where, in Intel syntax, it got interpreted as the shift-left operator.
This commit fixes the issue by emitting the target symbol with
`ASM_OUTPUT_LABELREF`, which will quote it properly with regard to the output
assembler syntax.
PR target/53929
gcc/ChangeLog:
* config/mingw/winnt.cc (mingw_pe_file_end): Use `ASM_OUTPUT_LABELREF`
to emit `name`.
Signed-off-by: LIU Hao <lh_mouse@126.com>
Signed-off-by: Jonathan Yong <10walls@gmail.com>
ChangeLog: * .github/ISSUE_TEMPLATE/bug_report.yml: New file. * .github/ISSUE_TEMPLATE/bug_report.md: Deleted old template. Signed-off-by: Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com>
ChangeLog: * README.md: Add fedora deps. Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@iki.fi>
Co-authored-by: Arthur Cohen <arthur.cohen@embecosm.com> Co-authored-by: Sam James <sam@gentoo.org> Co-authored-by: Owen Avery <powerboat9.gamer@gmail.com> Co-authored-by: Philip Herron <herron.philip@googlemail.com> Co-authored-by: Marc Poulhiès <dkm@kataplop.net> Signed-off-by: Philip Herron <herron.philip@googlemail.com> Signed-off-by: Owen Avery <powerboat9.gamer@gmail.com> Signed-off-by: Marc Poulhiès <dkm@kataplop.net>
Signed-off-by: Owen Avery <powerboat9.gamer@gmail.com> Signed-off-by: Marc Poulhiès <dkm@kataplop.net> Co-authored-by: Owen Avery <powerboat9.gamer@gmail.com> Co-authored-by: Marc Poulhiès <dkm@kataplop.net>
This new workflow is used to send emails to the gcc-patches@ mailing list
after every merged PR.
For each merged PR:
- remove commits touching files not to-be-upstreamed (e.g. github
workflow, README.md, ...)
- send a mail series
Each mail contains explanation + links to commits/PR on the github
project.
Authors of commits will be put in Cc: of emails.
Configure it by setting the following secrets in github:
- SMTP_PASSWORD
And the following variables:
- PATCH_TO: the "To:" field for the emails
- PATCH_CC: optional "Cc:"
- SMTP_FROM, SMTP_PASSWORD, SMTP_PORT, SMTP_SERVER, STMP_USERNAME: self explanatory
ChangeLog:
* .github/workflows/send-emails.yml: New file.
Co-authored-by: Andrew V. Teylu <andrew.teylu@vector.com>
Signed-off-by: Andrew V. Teylu <andrew.teylu@vector.com>
Signed-off-by: Marc Poulhiès <dkm@kataplop.net>
Since f1982cc, we are using clang-format-16 instead of clang-format-10. This commit updates the clang-format version documented in CONTRIBUTING.md so that new contributors don't get tripped. ChangeLog: * CONTRIBUTING.md: Update clang-format version Signed-off-by: Ryo Yoshida <low.ryoshida@gmail.com>
ChangeLog: * .github/workflows/commit-format.yml: adjust grep. Signed-off-by: Marc Poulhiès <dkm@kataplop.net>
Use dtolnay/rust-toolchain action to install rustc toolchain. Use a composite action for the various build/check on ubuntu. More cleanup possible (the 32/64bits builds could be simplified and only build 1 compiler and split the checks) ChangeLog: * .github/workflows/ccpp.yml: Refactor. * .github/actions/build-gcc/action.yml: New file. Signed-off-by: Marc Poulhiès <dkm@kataplop.net>
ChangeLog: * README.md: Add Fedora WSL deps. Signed-off-by: Osama Albahrani <osalbahr@gmail.com>
We've had at least one case of mails not being sent because the commit log was so big that the $GH_EVENT var couldn't be expanded by the shell. Using envsubst avoids having the shell do the expansion. ChangeLog: * .github/workflows/send-emails.yml: use envsubst. Signed-off-by: Marc Poulhiès <dkm@kataplop.net>
Fixes: #4503 gcc/rust/ChangeLog: * lang.opt (flag_name_resolution_2_0): Remove. * resolve/rust-name-resolver.cc: Remove include. Signed-off-by: Fisnik Hasani <opensource@fisnikhasani.com>
CompoundAssignmentExpr codegen was missing the final assignment statement when it was evaluated in a const context. gcc/rust/ChangeLog: * backend/rust-compile-expr.cc (CompileExpr::visit): Emit the missing assignment for CompoundAssignmentExpr. gcc/testsuite/ChangeLog: * rust/compile/const-compound-assignment.rs: New test. * rust/execute/const-compound-assignment.rs: New test. Signed-off-by: Islam-Imad <islamimad404@gmail.com>
the problem is cfg-strip emits an error for unstrippable expressions but doesn't mark the parent for strip, leaving a broken subtree for later passes to ICE on. gcc/rust/ChangeLog: * expand/rust-cfg-strip.cc (CfgStrip::visit): mark CallExpr for strip when function expression fails stripping. (CfgStrip::visit): mark ArrayIndexExpr for strip when array or index expression fails stripping. gcc/testsuite/ChangeLog: * rust/compile/issue-4167.rs: New test. Signed-off-by: Harishankar <harishankarpp7@gmail.com>
Look for Rust-GCC/gccrs#XXXXXX issue references (and only that) and expand them as github URLs in the email body. See #4529 ChangeLog: * .github/workflows/send-emails.yml: Expand github's issues references in sent emails.
gcc/rust/ChangeLog: * util/rust-attributes.cc (__definitions): Add entries for warn and deny attributes. Signed-off-by: Owen Avery <powerboat9.gamer@gmail.com>
Fixes #3972. Trait functions without an explicit return type can have a null `return_type` in `TraitFunctionDecl`. When such declarations are copied, the copy constructor and assignment operator currently try to clone the return type unconditionally, and this can lead to an ICE. Handle this case by keeping `nullptr` when there is no return type to clone. Also add a regression test for the example from #3972. gcc/rust/ChangeLog: * hir/tree/rust-hir-item.cc (TraitFunctionDecl::TraitFunctionDecl): Handle null return types in copy constructor. (TraitFunctionDecl::operator=): Likewise. gcc/testsuite/ChangeLog: * rust/compile/issue-3972.rs: New test. Signed-off-by: lishin <lishin1008@gmail.com>
Assert macro handler was missing, insert a basic handler that desugars to a condition and a call to panic. gcc/rust/ChangeLog: * expand/rust-macro-builtins-log-debug.cc (MacroBuiltin::assert_handler): Add basic assert builtin macro handler. gcc/testsuite/ChangeLog: * rust/compile/assert_missing_panic.rs: New test. Signed-off-by: Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com>
gcc/rust/ChangeLog: * resolve/rust-forever-stack.h: Move declarations from ForeverStack to NRCtx, make most of the ForeverStack members public as it helps the Ctx a lot. * resolve/rust-forever-stack.hxx: Move implementation of resolve_path methods to NRCtx. * resolve/rust-name-resolution-context.h: Declare resolve_path methods. * resolve/rust-name-resolution-context.hxx: New file with resolve_path impls.
gcc/rust/ChangeLog: * resolve/rust-name-resolution-context.hxx: Do segment resolution in types NS for more correctness and correct behavior when later resolving paths that use imports and/or modules.
Number literal evaluation and suffix validation should be done after macro expansion, so we defer these to the parser phase. This preserves source fidelity for macro token trees. gcc/rust/ChangeLog: * ast/rust-ast-collector.cc (TokenCollector::visit): Update Token::make_int and Token::make_float calls to include suffix_start and IntegerLiteralBase::Decimal. * expand/rust-macro-builtins-location.cc (MacroBuiltin::column_handler): Pass string length and base to Token::make_int. (MacroBuiltin::line_handler): Likewise. * lex/rust-lex.cc (Lexer::parse_in_type_suffix): Rename to parse_in_suffix and return string instead of PrimitiveCoreType. (Lexer::parse_in_suffix): Remove underscore stripping to preserve source fidelity for macros. (Lexer::parse_in_exponent_part): Preserve '+' and '-' characters in the raw string. (Lexer::parse_in_decimal): Remove underscore stripping. (Lexer::parse_non_decimal_int_literal): Track suffix start index and pass literal base. (Lexer::parse_non_decimal_int_literals): Use IntegerLiteralBase enum values instead of raw integers. (Lexer::parse_decimal_int_or_float): Track suffix string length and pass base parameters to token creation. * lex/rust-lex.h: Update method signatures for suffix parsing. * lex/rust-token.h (enum class IntegerLiteralBase): New enum to represent numeric bases. * parse/rust-parse-impl-expr.hxx: use LiteralResolve functions to evaluate raw token strings. * parse/rust-parse-impl-pattern.hxx: Use evaluated literal strings for INT and FLOAT tokens. * parse/rust-parse.cc (resolve_literal_suffix): Move suffix validation logic from lexer to parser. (evaluate_integer_literal): New function to strip underscores and convert to decimal via GMP. (evaluate_float_literal): New function to strip underscores from floats. * parse/rust-parse.h (evaluate_integer_literal): Declare in LiteralResolve namespace. (evaluate_float_literal): Likewise. (resolve_literal_suffix): Likewise. * util/rust-token-converter.cc (from_literal): Safely reconstruct raw text and suffix to dynamically determine base and suffix_start for ProcMacros. gcc/testsuite/ChangeLog: * rust/compile/deferred-suffix-validation.rs: New test. * rust/compile/evaluate-integer-or-float.rs: New test. * rust/compile/tuple-index.rs: New test. Signed-off-by: Enes Cevik <nsvke@proton.me>
Previously, the lexer evaluated empty non-decimal literals (like 0x, 0b, 0o) as 0. Now, it emits error E0768 when there are no valid digits. gcc/rust/ChangeLog: * lex/rust-lex.cc (Lexer::parse_non_decimal_int_literal): Emit E0768. gcc/testsuite/ChangeLog: * rust/compile/empty-non-decimal.rs: New test. Signed-off-by: Enes Cevik <nsvke@proton.me>
rustc_const_stable attributes are used within the core library but were not properly feature gated. The compiler now rejects their usage when the feature has not been explicitly enabled. gcc/rust/ChangeLog: * checks/errors/feature/rust-feature-gate.cc (FeatureGate::visit): Add a feature gate around rustc_const_stable attributes. gcc/testsuite/ChangeLog: * rust/compile/const-issue1440.rs: Enable staged_api feature. * rust/compile/for-loop1.rs: Likewise. * rust/compile/for-loop2.rs: Likewise. * rust/compile/issue-1031.rs: Likewise. * rust/compile/issue-1289.rs: Likewise. * rust/compile/iterators1.rs: Likewise. * rust/compile/rustc_const_stable.rs: Likewise. * rust/compile/torture/issue-1075.rs: Likewise. * rust/compile/torture/issue-1432.rs: Likewise. * rust/execute/torture/const-generics-7.rs: Likewise. * rust/execute/torture/for-loop1.rs: Likewise. * rust/execute/torture/for-loop2.rs: Likewise. * rust/execute/torture/issue-1120.rs: Likewise. * rust/execute/torture/issue-1133.rs: Likewise. * rust/execute/torture/issue-1232.rs: Likewise. * rust/execute/torture/issue-1436.rs: Likewise. * rust/execute/torture/iter1.rs: Likewise. * rust/execute/torture/slice-magic.rs: Likewise. * rust/execute/torture/slice-magic2.rs: Likewise. * rust/execute/torture/str-layout1.rs: Likewise. * rust/compile/missing_staged_api.rs: New test. Signed-off-by: Pierre-Emmanuel Patry <pierre-emmanuel.patry@embecosm.com>
Fixes #3537 gcc/testsuite/ChangeLog: * rust/compile/issue-3537.rs: New test. Signed-off-by: Harishankar <harishankarpp7@gmail.com>
gcc/rust/ChangeLog: * hir/tree/rust-hir-visibility.h: Switch Visibility::VisType to an enum class, adapt variants' case. * backend/rust-compile-base.cc (HIRCompileBase::setup_fndecl): Use the new enum API. * backend/rust-compile-implitem.cc (CompileTraitItem::visit): Likewise. * checks/errors/privacy/rust-visibility-resolver.cc (VisibilityResolver::resolve_visibility): Likewise. * hir/rust-ast-lower.cc (translate_visibility): Likewise. * hir/tree/rust-hir.cc (Visibility::to_string): Likewise. * metadata/rust-export-metadata.cc (PublicInterface::is_crate_public): Likewise. * util/rust-hir-map.cc (Mappings::Mappings): Likewise.
gcc/testsuite/ChangeLog: * rust/compile/issue-4158.rs: New test. Signed-off-by: Harishankar <harishankarpp7@gmail.com>
gcc/testsuite/ChangeLog: * rust/compile/issue-4159.rs: New test Signed-off-by: Harishankar <harishankarpp7@gmail.com>
…se/2026-05-20 This branch has a no-op merge as the last commit: - one arm is the "current" development branch from github - the other arm is a rebased version of the "current" master branch onto a recent GCC's master The merge is obtained with "git merge --strategy=ours" to only keep the changes from second arm.
Member
Author
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Wooop Looks like something changed upstream and broke gccrs. I'll have a look later. |
Member
Author
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More detailed error: |
Member
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I'm seeing conversation about this on the ML: https://gcc.gnu.org/pipermail/gcc-patches/2026-May/717273.html I don't know that there's anything we can do here other than wait for a bit |
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This is a sync with upstream GCC:
upstream GCC revision: 5dfe105
gccrs github: 833d880
-- gerris 🦀