Multi-Mode 4-Bit Digital Code Converter

VLSI Training Program project — a Universal 4-Bit Multi-Mode Code Converter that consolidates four distinct code-conversion algorithms (Binary↔Gray, BCD↔Excess-3) into a single hardware hub, selectable in real time via a 2-bit mode-select line.

Originally submitted as a VLSI Training Program report, Centre for Innovation — Semiconductor and VLSI Design Centre, St. Joseph's College of Engineering & St. Joseph's Institute of Technology (Batch 2024–2028).

Overview

Modern digital systems often need multiple numeric code formats — Gray code for error reduction, Excess-3 for decimal arithmetic — which conventionally requires separate hardware for each conversion. This project consolidates four converters into one module using a bank of four 4-to-1 multiplexers driven by a 2-bit select input (sel), instead of separate standalone circuits:

sel	Mode
00	Binary → Gray
01	BCD → Excess-3
10	Gray → Binary
11	Excess-3 → BCD

Design methodology

The 4-bit input is fed in parallel into four independent logic engines:

• Gray-code conversions use XOR-gate networks (bin_to_gray, gray_to_bin)
• Excess-3 conversions use carry-propagate arithmetic — add/subtract 0011 (bcd_to_ex3, ex3_to_bcd)

All four results are routed through a bank of four mux_4to1 multiplexers, one per output bit, so the 2-bit sel line acts as a digital switchboard picking which conversion reaches the shared 4-bit output — instead of rewiring for each format.

Repo structure

multi-mode-code-converter/
├── design/
│   └── all_in_one_converter.v   # mux_4to1, bin_to_gray, bcd_to_ex3,
│                                 # gray_to_bin, ex3_to_bcd, all_in_one_converter
├── sim/
│   └── all_in_one_converter_tb.v  # testbench (Verilog, timescale 1ns/1ps)
└── docs/
    └── Project_report_PPT.pdf   # full training program report (design
                                   # methodology, flowchart, netlist, timing
                                   # diagram, references)

Simulating

Any Verilog simulator works (Icarus Verilog shown here):

iverilog -o sim_out design/all_in_one_converter.v sim/all_in_one_converter_tb.v
vvp sim_out
# view all_in_one_converter.vcd in GTKWave or similar

Results

Verified via Verilog testbench and waveform analysis (Vivado synthesis + EDA Playground simulation — see the full report in docs/): for input 1010 (decimal 10), the converter correctly produced 1111 in Gray mode and 1101 in Excess-3 mode. All four modes (00–11) were validated with 100% logical accuracy against expected outputs, and the design synthesized cleanly to a Xilinx xc7vx485tffg1157-1 target (14 cells, 10 I/O ports, 20 nets).

Scalability

The modular per-bit multiplexer approach scales directly to 8-bit or 16-bit data widths for more complex data-encoding needs.

Authors

• P. Sanjai
• R. Sanjay
• U. Thulasirajan

Under the supervision of Dr. P. Latha, Associate Professor, Centre for Innovation — Semiconductor and VLSI Design Centre.

References

• N. Guleria, "Binary to gray code converter implementation using QCA," 2017 3rd International Conference on Advances in Computing, Communication & Automation (ICACCA), Dehradun, India, 2017, pp. 1-6.
• N. R. Kumar and M. Janardhan, "Design and Analysis of Multiplexer Based 4-Bit Flash ADC," International Conference on Recent Trends in Electrical, Electronics & Computer Engineering for Environmental Monitoring (ICRTEEECE), 2019.