docs(topic13): peephole optimizer docs and tests - #39
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| # Rule 5: mv a, b; ... (a not used) mv c, a -> mv c, b | ||
| # (redundant move through intermediate) | ||
| # Rule 4: mv a, b; mv c, a -> mv c, b (skip intermediate register a) | ||
| # Unsound if `a` is live after the pair; callers/tests must treat as |
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既然知道这里可能产生bug, 我觉得应该把rule 4列为TODO, 而不是直接写一个有问题的然后提交。并且这个bug貌似没有构造用例在ci中测试?
| machine_instrs = selector.run() | ||
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| # Linear-scan: skip greedy allocator, use liveness-driven allocator | ||
| alloc = RegisterAllocator(machine_instrs, mode=self.config.reg_alloc) |
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这里linear模式不一定会生效, 需要再check一下
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寄存器分配线性扫描的优化 pr 已经合入,可以确认一下文档
| assert pre["t2"] == post["t2"] == 9 | ||
| # …but live intermediate differs without liveness analysis. | ||
| assert pre["t0"] == 9 | ||
| assert post.get("t0", 0) != pre["t0"] |
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看上去测试的是优化前后的 t0 必须不同? 只是保证了这个优化生效了, 但没有保证这个优化是正确的
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| ## 代码与测试 |
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缺少优化前后经 assembler/simulator 执行的语义等价测试,后续应补充端到端正确性、寄存器压力 spill/reload、linear/greedy 配置矩阵及随机生成测试, 这部分可以考虑让小组其他同学来做
Summary
Test plan