[draft] minimax & kimi Amd/vllm disagg mvp dev#1141

Merged

Klaud-Cold merged 31 commits intoSemiAnalysisAI:amd/vllm_disagg_mvp_devfrom

ichbinblau:amd/vllm_disagg_mvp_dev

Apr 28, 2026

Commits on Apr 27, 2026

[AMD] Add vLLM disaggregated prefill-decode benchmark for MI355X

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Refactor vLLM disagg recipe: models.yaml, UCX cleanup, QoS support

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Update vLLM disagg recipe for v0.17.1 NixlConnector API

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Make vLLM disagg recipe CI-compatible (mia1 cluster)

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Co-locate vLLM disagg router with prefill on NODE_RANK=0

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Use public vLLM base image with runtime dependency install

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Enable Expert Parallelism with MoRI all-to-all on vLLM disagg decode

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Switch vLLM disagg KV transfer to MoRI-IO with protocol-aware proxy

chunfangamd
authored and
thshan@amd.com
committed
[AMD] BUG fix: RANDOM_RANGE_RATIO never reaches bench.sh

ichbinblau
authored and
thshan@amd.com
committed
Bug fix: 1. With DRY_RUN=1, node 0 skipped starting proxy/prefill but still ran the first barrier; 2. kill and kill run only when DRY_RUN=0

ichbinblau
authored and
thshan@amd.com
committed
[AMD] Fix vLLM disagg hang: READ mode support + safety timeouts

chunfangamd
authored and
thshan@amd.com
committed
Adapt vLLM disagg recipe for 9N mia1 cluster (mlx5 NICs)

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Fix vLLM disagg sweep hang: KV cache leak + benchmark client hardening

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Fix vLLM disagg Slurm job never terminating after benchmark completion

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Enable MoRI-IO READ mode by default for vLLM disagg

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Fix CI checkout failure caused by root-owned __pycache__ files

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Fix CI checkout EACCES by redirecting Python bytecache off NFS

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Fix KV reaper deadlock on high-ISL disagg workloads

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Enable reading PREFILL_TP,PREFILL_EP,PREFILL_DP_ATTN,DECODE_TP,DECODE_EP,DECODE_DP_ATTN from amd-master.yaml config.

ichbinblau
authored and
thshan@amd.com
committed
[AMD] Upgrade vLLM disagg image from v0.17.1 to v0.18.0

chunfangamd
authored and
thshan@amd.com
committed
[AMD] Add Kimi-K2.5-MXFP4 disagg inference config (1P2D)

chunfangamd
authored and
thshan@amd.com
committed
feat: add MiniMax M2.5 PD disaggregation recipe (1P2D, MoRI-EP + MoRI-IO)

authored and
thshan@amd.com
committed
feat: add Dockerfile and runtime patch for MiniMax M2.5 WideEP + MoRI

authored and
thshan@amd.com
committed
Fix: rename minimaxm25 to minimaxm2.5 for CI naming consistency

chunfangamd
authored and
thshan@amd.com
committed
Optimize: add --gpu-memory-utilization 0.95 and --block-size 32 to MiniMax M2.5 disagg

chunfangamd
authored and
thshan@amd.com
committed
Fix: MiniMax M2.5 disagg — require EP=8 for prefill, fix ROCm gate dtype

chunfangamd
authored and
thshan@amd.com
committed
Remove unused docker/minimax-m25-disagg/ directory

chunfangamd
authored and
thshan@amd.com
committed
remove vllm disagg for dpsr1 and dpv3

ichbinblau
authored and
thshan@amd.com
committed
consolidate amd_utils for sglang and vllm

ichbinblau
authored and
thshan@amd.com
committed
use vLLM router as default router for vllm disagg

ichbinblau
authored and
thshan@amd.com
committed
fix bugs

ichbinblau
authored and
thshan@amd.com
committed

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[draft] minimax & kimi Amd/vllm disagg mvp dev#1141

[draft] minimax & kimi Amd/vllm disagg mvp dev#1141
Klaud-Cold merged 31 commits intoSemiAnalysisAI:amd/vllm_disagg_mvp_devfrom
ichbinblau:amd/vllm_disagg_mvp_dev

Commits on Apr 27, 2026

[AMD] Add vLLM disaggregated prefill-decode benchmark for MI355X

[AMD] Refactor vLLM disagg recipe: models.yaml, UCX cleanup, QoS support

[AMD] Update vLLM disagg recipe for v0.17.1 NixlConnector API

[AMD] Make vLLM disagg recipe CI-compatible (mia1 cluster)

[AMD] Co-locate vLLM disagg router with prefill on NODE_RANK=0

[AMD] Use public vLLM base image with runtime dependency install

[AMD] Enable Expert Parallelism with MoRI all-to-all on vLLM disagg decode

[AMD] Switch vLLM disagg KV transfer to MoRI-IO with protocol-aware proxy

[AMD] BUG fix: RANDOM_RANGE_RATIO never reaches bench.sh

Bug fix: 1. With DRY_RUN=1, node 0 skipped starting proxy/prefill but still ran the first barrier; 2. kill and kill run only when DRY_RUN=0

[AMD] Fix vLLM disagg hang: READ mode support + safety timeouts

Adapt vLLM disagg recipe for 9N mia1 cluster (mlx5 NICs)

[AMD] Fix vLLM disagg sweep hang: KV cache leak + benchmark client hardening

[AMD] Fix vLLM disagg Slurm job never terminating after benchmark completion

[AMD] Enable MoRI-IO READ mode by default for vLLM disagg

[AMD] Fix CI checkout failure caused by root-owned pycache files

[AMD] Fix CI checkout EACCES by redirecting Python bytecache off NFS

[AMD] Fix KV reaper deadlock on high-ISL disagg workloads

[AMD] Enable reading PREFILL_TP,PREFILL_EP,PREFILL_DP_ATTN,DECODE_TP,DECODE_EP,DECODE_DP_ATTN from amd-master.yaml config.

[AMD] Upgrade vLLM disagg image from v0.17.1 to v0.18.0

[AMD] Add Kimi-K2.5-MXFP4 disagg inference config (1P2D)

feat: add MiniMax M2.5 PD disaggregation recipe (1P2D, MoRI-EP + MoRI-IO)

feat: add Dockerfile and runtime patch for MiniMax M2.5 WideEP + MoRI

Fix: rename minimaxm25 to minimaxm2.5 for CI naming consistency

Optimize: add --gpu-memory-utilization 0.95 and --block-size 32 to MiniMax M2.5 disagg

Fix: MiniMax M2.5 disagg — require EP=8 for prefill, fix ROCm gate dtype

Remove unused docker/minimax-m25-disagg/ directory

remove vllm disagg for dpsr1 and dpv3

consolidate amd_utils for sglang and vllm

use vLLM router as default router for vllm disagg

fix bugs