feat: add EFR32MG21 (xG21) CPU platform and BRD4180A board - #3
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Add the EFR32xG21 CPU platform description and BRD4180A radio board support, enabling emulation of EFR32MG21A020F1024IM32 (Series 2 Config 1, Cortex-M33) targets. The memory map and interrupt assignments follow the EFR32xG21 Reference Manual (Rev. 1.0). Peripheral IP-version models are reused from the architecturally-closest supported part (xG22 generation); crypto is provided by the Secure Engine mailbox (SEMAILBOX) as on xG24. The HFXO configuration includes releaseFsmLockOnDisableOnDemand since MG21 has no HFXO MANUALOVERRIDE command — without it, CMU_HFXOInit() spins forever polling FSMLOCK. Validated by booting stripped Zigbee application firmware through clock, power and radio init into a steady-state idle loop.
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Pull request overview
This PR adds Renode platform descriptions to emulate Silicon Labs EFR32xG21 (Series 2 Config 1, Cortex-M33) devices and the BRD4180A (EFR32MG21A020F1024IM32) radio board, aligning memory map/IRQ layout with the EFR32xG21 Reference Manual and reusing existing Series-2 peripheral models.
Changes:
- Added a new CPU/platform
.replfor EFR32xG21, including CMU/EMU/MSC, radio (LPW), TrustZone NVIC mappings, and Secure Engine mailbox crypto. - Added a new board
.replfor BRD4180A with LED/button GPIO wiring and flash/lockbits sizing.
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 3 comments.
| File | Description |
|---|---|
| platforms/cpus/silabs/efr32s2/efr32xG21.repl | Introduces the EFR32xG21 SoC platform definition (memory map, IRQ wiring, peripherals, radio/sequencer). |
| platforms/boards/silabs/brd4180a.repl | Adds the BRD4180A board wrapper with GPIO mappings and flash/lockbits layout. |
Comments suppressed due to low confidence (1)
platforms/cpus/silabs/efr32s2/efr32xG21.repl:236
prortcis currently assignedIRQ -> nvic@39, which conflicts with the radio's host mailbox interrupt assignment used on other EFR32S2 parts (and would also conflict with the addedHostMailboxIRQ -> nvic@39). Consider aligningprortctonvic@41like other platforms using the same PRORTC model to avoid sharing an NVIC line between unrelated peripherals.
IRQ -> nvic@39
SeqIRQ -> seqnvic@21
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| cpu0: cpu | ||
| SecureIRQ -> nvic@3 | ||
| SecurePriviledgedIRQ -> nvic@4 | ||
| NonSecurePriviledgedIRQ -> nvic@4 |
| } | ||
| sequencer: seqcpu | ||
| bufferController: lpwBufferController | ||
| prortc: prortc | ||
| // Main CPU interrupts |
| RadioControllerRadioStateMachineIRQ -> nvic@37 | ||
| RadioControllerSequencerIRQ -> nvic@38 | ||
| SynthesizerIRQ -> nvic@40 |
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Reviewed commit: 764ca77194
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| sequencer: seqcpu | ||
| bufferController: lpwBufferController | ||
| prortc: prortc |
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When firmware transmits or schedules protocol-timer events, this SiLabs_xG22_LPW instance has no clockFrequency configured in either the CPU or board description. The reused xG22 platform explicitly supplies 38.4 MHz, as do the other Series 2 radio platforms; leaving it unset makes radio timing use an uninitialized/default frequency, so initialization reaching idle does not validate actual packet timing or transmission.
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| } | ||
| -> nvic@21 |
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When a UART or radio request starts an LDMA transfer, this reused SiLabs_LDMA_0_1 instance has no context: cpu. Every existing Series 2 LDMA platform, including the xG22 configuration this file derives from, supplies that context so DMA bus accesses carry the Cortex-M33 security state; without it, descriptor and payload accesses can use the wrong access context or fail once DMA is exercised.
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- Add clockFrequency: 38400000 to the Wireless.SiLabs_xG22_LPW radio block, matching the xG22 platform and 802.15.4 timing requirements. - Add context: cpu to the LDMA block, matching xG22/xG24 platforms. Without it DMA transfers use wrong TrustZone access context. Both issues identified by PR review; verified against EFR32MG21 CMSIS header (efr32mg21a010f768im32.h IRQn_Type enum). Three other review comments about SMU/HostMailbox/PRORTC IRQ routing are not applicable — xG21 has different interrupt assignments from xG22 (verified at source).
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Reviewed commit: 0ca661aff2
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| cpu0: cpu | ||
| SecureIRQ -> nvic@3 | ||
| SecurePriviledgedIRQ -> nvic@4 | ||
| NonSecurePriviledgedIRQ -> nvic@4 |
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On xG21, the SMU nonsecure-privileged interrupt is IRQ 5, while IRQ 4 is the separate secure-privileged interrupt. With both outputs connected to IRQ 4 here, firmware enabling the IRQ 5 handler will never receive nonsecure SMU events, and those events can instead invoke the wrong secure handler.
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|
This PR depends on the following upstream changes. After each is merged, the corresponding submodule pointer needs to be bumped.
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Add the EFR32xG21 CPU platform description and BRD4180A radio board
support, enabling emulation of EFR32MG21A020F1024IM32 (Series 2 Config 1,
Cortex-M33) targets.
The memory map and interrupt assignments follow the EFR32xG21 Reference
Manual (Rev. 1.0). Peripheral IP-version models are reused from the
architecturally-closest supported part (xG22 generation); crypto is
provided by the Secure Engine mailbox (SEMAILBOX) as on xG24.
The HFXO configuration includes
releaseFsmLockOnDisableOnDemandsinceMG21 has no HFXO MANUALOVERRIDE command — without it, CMU_HFXOInit()
spins forever polling FSMLOCK.
Validated by booting stripped Zigbee application firmware through clock,
power and radio init into a steady-state idle loop.
Closes #2