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MT6589 MSDC support#26

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akku1139 wants to merge 38 commits intoblade/v6.16from
dev/v6.16/mt6589-sd
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MT6589 MSDC support#26
akku1139 wants to merge 38 commits intoblade/v6.16from
dev/v6.16/mt6589-sd

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@akku1139 akku1139 commented Mar 2, 2026

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akku1139 commented Mar 3, 2026

needs #25

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akku1139 commented Mar 7, 2026

https://github.com/bq/aquaris-5/blob/aquaris-5/mediatek/platform/mt6589/kernel/drivers/mmc-host/mt_sd.h

drive power play lol

/********************MSDC0*************************************************/
#define MSDC0_TDSEL_BASE		(GPIO_BASE+0x0700)
#define MSDC0_RDSEL_BASE		(GPIO_BASE+0x0700)
#define MSDC0_TDSEL				(0xF << 8)
#define MSDC0_RDSEL				(0x3FUL << 16)
#define MSDC0_DAT_DRVING_BASE	(GPIO_BASE+0x0500)
#define MSDC0_DAT_DRVING		(0x7 << 0)
#define MSDC0_CMD_DRVING_BASE	(GPIO_BASE+0x0500)
#define MSDC0_CMD_DRVING		(0x7 << 4)
#define MSDC0_CLK_DRVING_BASE	(GPIO_BASE+0x05C0)
#define MSDC0_CLK_DRVING		(0x7 << 12)
#define MSDC0_DAT_SR_BASE		(GPIO_BASE+0x0500)
#define MSDC0_DAT_SR			(0x1 << 3)
#define MSDC0_CMD_SR_BASE		(GPIO_BASE+0x0500)
#define MSDC0_CMD_SR			(0x1 << 7)
#define MSDC0_CLK_SR_BASE		(GPIO_BASE+0x05C0)
#define MSDC0_CLK_SR			(0x1 << 15)
#define MSDC0_IES_BASE			(GPIO_BASE+0x0100)
#define MSDC0_IES_DAT			(0x1 << 10)
#define MSDC0_IES_CMD			(0x1 << 5)
#define MSDC0_IES_CLK			(0x1 << 6)

#define MSDC0_SMT_BASE			(GPIO_BASE+0x0300)
#define MSDC0_SMT_DAT			((0xF << 7) | (0xF << 0))	//MASK:DAT0|DAT1|DAT2|DAT3|CLK|CMD|RSTB(Please use default value)|DAT4|DAT5|DAT6|DAT7
#define MSDC0_SMT_CMD			(0x1 << 5)	
#define MSDC0_SMT_CLK			(0x1 << 6)	

#define MSDC0_R0_BASE			(GPIO_BASE+0x04F0)//1.8v 10K resistor control
#define MSDC0_R0_DAT			((0xF << 6)|(0xF << 2))  //MASK:DAT7|DAT6|DAT5|DAT4|DAT3|DAT2|DAT1|DAT0|CMD|CLK
#define MSDC0_R0_CMD			(0x1 << 1)  
#define MSDC0_R0_CLK			(0x1 << 0)  

#define MSDC0_R1_BASE			(GPIO_BASE+0x0200)
#define MSDC0_R1_DAT			((0xF << 7)	| (0xF << 0))//MASK:DAT0|DAT1|DAT2|DAT3|CLK|CMD|RSTB(Please use default value)|DAT4|DAT5|DAT6|DAT7
#define MSDC0_R1_CMD			(0x1 << 5)	
#define MSDC0_R1_CLK			(0x1 << 6)	


#define MSDC0_PUPD_BASE			(GPIO_BASE+0x0400)// '1' = pull up '0' =pull down
#define MSDC0_PUPD_DAT			((0xF << 7) |(0xF << 0))	//MASK:DAT0|DAT1|DAT2|DAT3|CLK|CMD|RSTB(Please use default value)|DAT4|DAT5|DAT6|DAT7
#define MSDC0_PUPD_CMD			(0x1 << 5)	
#define MSDC0_PUPD_CLK			(0x1 << 6)	


/****************************MSDC1*************************************************/

#define MSDC1_TDSEL_BASE		(GPIO_BASE+0x0780)
#define MSDC1_RDSEL_BASE		(GPIO_BASE+0x0780)
#define MSDC1_TDSEL				(0xFUL  << 16)
#define MSDC1_RDSEL				(0x3FUL << 24)

#define MSDC1_DAT_DRVING_BASE	(GPIO_BASE+0x05A0)
#define MSDC1_DAT_DRVING		(0x7UL  << 20)

#define MSDC1_CMD_DRVING_BASE	(GPIO_BASE+0x05A0)
#define MSDC1_CMD_DRVING		(0x7UL  << 24)

#define MSDC1_CLK_DRVING_BASE	(GPIO_BASE+0x05C0)
#define MSDC1_CLK_DRVING		(0x7 << 16)

#define MSDC1_DAT_SR_BASE		(GPIO_BASE+0x05A0)
#define MSDC1_DAT_SR			(0x1 << 23)
#define MSDC1_CMD_SR_BASE		(GPIO_BASE+0x05A0)
#define MSDC1_CMD_SR			(0x1 << 27)
#define MSDC1_CLK_SR_BASE		(GPIO_BASE+0x05C0)
#define MSDC1_CLK_SR			(0x1 << 19)

#define MSDC1_IES_BASE			(GPIO_BASE+0x01B0)
#define MSDC1_IES_DAT			(0x1 << 4)
#define MSDC1_IES_CMD			(0x1 << 7)
#define MSDC1_IES_CLK			(0x1 << 8)

#define MSDC1_SMT_BASE			(GPIO_BASE+0x03B0)
															
#define MSDC1_SMT_DAT			((0x3 << 9) | (0x3 << 4))	//DATA3|DATA2...DATA1|DATA0
#define MSDC1_SMT_CMD			(0x1 << 7)				
#define MSDC1_SMT_CLK			(0x1 << 8)				


#define MSDC1_PUPD_ENABLE_BASE			(GPIO_BASE+0x02B0)// '1'= enable '0' = disable
#define MSDC1_PUPD_POLARITY_BASE		(GPIO_BASE+0x04B0)// '1' = pull up '0' =pull down

#define MSDC1_PUPD_DAT			((0x3 << 9) | (0x3 << 4))	//DATA3|DATA2...DATA1|DATA0
#define MSDC1_PUPD_CMD			(0x1 << 7)				
#define MSDC1_PUPD_CLK			(0x1 << 8)	

/****************************MSDC2*************************************************/

#define MSDC2_TDSEL_BASE		(GPIO_BASE+0x0780)
#define MSDC2_RDSEL_BASE		(GPIO_BASE+0x0780)
#define MSDC2_TDSEL				(0xFUL  << 0)
#define MSDC2_RDSEL				(0x3FUL << 8)

#define MSDC2_DAT_DRVING_BASE	(GPIO_BASE+0x05A0)
#define MSDC2_DAT_DRVING		(0x7	<< 8)

#define MSDC2_CMD_DRVING_BASE	(GPIO_BASE+0x05A0)
#define MSDC2_CMD_DRVING		(0x7	<< 12)

#define MSDC2_CLK_DRVING_BASE	(GPIO_BASE+0x05C0)
#define MSDC2_CLK_DRVING		(0x7UL 	<< 20)

#define MSDC2_DAT_SR_BASE		(GPIO_BASE+0x05A0)
#define MSDC2_DAT_SR			(0x1 << 11)
#define MSDC2_CMD_SR_BASE		(GPIO_BASE+0x05A0)
#define MSDC2_CMD_SR			(0x1 << 15)
#define MSDC2_CLK_SR_BASE		(GPIO_BASE+0x05C0)
#define MSDC2_CLK_SR			(0x1 << 23)

#define MSDC2_IES_BASE			(GPIO_BASE+0x01B0)
#define MSDC2_IES_DAT			(0x1 << 3)
#define MSDC2_IES_CMD			(0x1 << 0)
#define MSDC2_IES_CLK			(0x1 << 1)

#define MSDC2_SMT_BASE1			(GPIO_BASE+0x03B0)
#define MSDC2_SMT_DAT1_0		(0x3 << 2)	//...DAT1|DAT0...
#define MSDC2_SMT_CMD			(0x1 << 0)				
#define MSDC2_SMT_CLK			(0x1 << 1)				
#define MSDC2_SMT_BASE2			(GPIO_BASE+0x03A0)
#define MSDC2_SMT_DAT2_3		(0x3 << 14)	//...DAT2|DAT3...


#define MSDC2_PUPD_ENABLE_BASE1			(GPIO_BASE+0x02B0)// '1'= enable '0' = disable
#define MSDC2_PUPD_POLARITY_BASE1		(GPIO_BASE+0x04B0)// '1' = pull up '0' =pull down
#define MSDC2_PUPD_DAT1_0		(0x3 << 2) //...DAT1|DAT0...
#define MSDC2_PUPD_CMD			(0x1 << 0)				
#define MSDC2_PUPD_CLK			(0x1 << 1)	

#define MSDC2_PUPD_ENABLE_BASE2			(GPIO_BASE+0x02A0)// '1'= enable '0' = disable
#define MSDC2_PUPD_POLARITY_BASE2		(GPIO_BASE+0x04A0)// '1' = pull up '0' =pull down
#define MSDC2_PUPD_DAT2_3		(0x3 << 14) 
	
/****************************MSDC3*************************************************/

#define MSDC3_TDSEL_BASE		(GPIO_BASE+0x0790)
#define MSDC3_RDSEL_BASE		(GPIO_BASE+0x0790)
#define MSDC3_TDSEL				(0xFUL  << 16)
#define MSDC3_RDSEL				(0x3FUL << 24)

#define MSDC3_DAT_DRVING_BASE	(GPIO_BASE+0x05C0)
#define MSDC3_DAT_DRVING		(0x7	<< 4)

#define MSDC3_CMD_DRVING_BASE	(GPIO_BASE+0x05C0)
#define MSDC3_CMD_DRVING		(0x7    << 8)

#define MSDC3_CLK_DRVING_BASE	(GPIO_BASE+0x05C0)
#define MSDC3_CLK_DRVING		(0x7UL  << 24)

#define MSDC3_DAT_SR_BASE		(GPIO_BASE+0x05C0)
#define MSDC3_DAT_SR			(0x1 << 7)
#define MSDC3_CMD_SR_BASE		(GPIO_BASE+0x05C0)
#define MSDC3_CMD_SR			(0x1 << 11)
#define MSDC3_CLK_SR_BASE		(GPIO_BASE+0x05C0)
#define MSDC3_CLK_SR			(0x1 << 27)

#define MSDC3_IES_BASE			(GPIO_BASE+0x01E0)
#define MSDC3_IES_DAT			(0x1 << 7)
#define MSDC3_IES_CMD			(0x1 << 4)
#define MSDC3_IES_CLK			(0x1 << 5)

#define MSDC3_SMT_BASE			(GPIO_BASE+0x03E0)
															
#define MSDC3_SMT_DAT			((0x3 << 6) | (0x3 << 2))	//..DAT0|DAT1..DAT3|DAT2
#define MSDC3_SMT_CMD			(0x1 << 4)				
#define MSDC3_SMT_CLK			(0x1 << 5)				

#define MSDC3_R0_BASE			(GPIO_BASE+0x04F0)//1.8v 10K resistor control

#define MSDC3_R0_DAT			(0xF << 12)  //MASK:DAT3|DAT2|DAT1|DAT0
#define MSDC3_R0_CMD			(0x1 << 11)  
#define MSDC3_R0_CLK			(0x1 << 10)  


#define MSDC3_R1_BASE			(GPIO_BASE+0x02E0)
#define MSDC3_R1_DAT			((0x3 << 6) | (0x3 << 2))	//MASK:DAT0|DAT1...DAT3|DAT2
#define MSDC3_R1_CMD			(0x1 << 4)	
#define MSDC3_R1_CLK			(0x1 << 5)	


#define MSDC3_PUPD_BASE			(GPIO_BASE+0x04E0)// '1' = pull up '0' =pull down
#define MSDC3_PUPD_DAT			((0x3 << 6) | (0x3 << 2))	//MASK:DAT0|DAT1...DAT3|DAT2
#define MSDC3_PUPD_CMD			(0x1 << 4)	
#define MSDC3_PUPD_CLK			(0x1 << 5)	

/********************MSDC4*************************************************/
#define	GPIO_BASE2				(0xF020C000)
#define MSDC4_TDSEL_BASE		(GPIO_BASE2+0x0760)
#define MSDC4_RDSEL_BASE		(GPIO_BASE2+0x0770)
#define MSDC4_TDSEL				(0xFUL << 24)
#define MSDC4_RDSEL				(0x3F  << 0)
#define MSDC4_DAT_DRVING_BASE	(GPIO_BASE2+0x0580)
#define MSDC4_DAT_DRVING		(0x7 << 20)
#define MSDC4_CMD_DRVING_BASE	(GPIO_BASE2+0x0570)
#define MSDC4_CMD_DRVING		(0x7 << 16)
#define MSDC4_CLK_DRVING_BASE	(GPIO_BASE2+0x0580)
#define MSDC4_CLK_DRVING		(0x7 << 0)
#define MSDC4_DAT_SR_BASE		(GPIO_BASE2+0x0580)
#define MSDC4_DAT_SR			(0x1 << 23)
#define MSDC4_CMD_SR_BASE		(GPIO_BASE2+0x0570)
#define MSDC4_CMD_SR			(0x1 << 19)
#define MSDC4_CLK_SR_BASE		(GPIO_BASE2+0x0580)
#define MSDC4_CLK_SR			(0x1 << 3)
#define MSDC4_IES_BASE			(GPIO_BASE2+0x0180)
#define MSDC4_IES_DAT			(0x1 << 2)
#define MSDC4_IES_CMD			(0x1 << 13)
#define MSDC4_IES_CLK			(0x1 << 11)

#define MSDC4_SMT_BASE			(GPIO_BASE2+0x0380)
#define MSDC4_SMT_DAT			((0x1 << 12) | (0x1F << 6)|  (0x3 << 2))	//MASK:DAT3..DAT2|DAT4|DAT7|DAT6|DAT5|DAT1|DAT0...
#define MSDC4_SMT_CMD			(0x1 << 13)	
#define MSDC4_SMT_CLK			(0x1 << 11)	

#define MSDC4_R0_BASE			(GPIO_BASE+0x04F0)//1.8v 10K resistor control
#define MSDC4_R0_DAT			(0xFFUL << 18)  //MASK:DAT7|DAT6|DAT5|DAT4|DAT3|DAT2|DAT1|DAT0|CMD|CLK
#define MSDC4_R0_CMD			(0x1 << 17)  
#define MSDC4_R0_CLK			(0x1 << 16)  

#define MSDC4_R1_BASE			(GPIO_BASE2+0x0280)
#define MSDC4_R1_DAT			((0x1 << 12) | (0x1F << 6)|  (0x3 << 2))	//MASK:DAT3..DAT2|DAT4|DAT7|DAT6|DAT5|DAT1|DAT0...
#define MSDC4_R1_CMD			(0x1 << 13)	
#define MSDC4_R1_CLK			(0x1 << 11)	


#define MSDC4_PUPD_BASE			(GPIO_BASE2+0x0480)// '1' = pull up '0' =pull down
#define MSDC4_PUPD_DAT			((0x1 << 12) | (0x1F << 6)|  (0x3 << 2))	//MASK:DAT3..DAT2|DAT4|DAT7|DAT6|DAT5|DAT1|DAT0...
#define MSDC4_PUPD_CMD			(0x1 << 13)
#define MSDC4_PUPD_CLK			(0x1 << 11)


#define EN18IOKEY_BASE				(GPIO_BASE2+0x920)

#define MSDC_EN18IO_CMP_SEL_BASE	(GPIO_BASE2+0x910)
#define	MSDC1_EN18IO_CMP_EN			(0x1 << 3)
#define MSDC1_EN18IO_SEL1			(0x7 << 0)
#define	MSDC2_EN18IO_CMP_EN			(0x1 << 7)
#define MSDC2_EN18IO_SEL			(0x7 << 4)

#define MSDC_EN18IO_SW_BASE			(GPIO_BASE+0x900)
#define MSDC1_EN18IO_SW				(0x1 << 19)
#define MSDC2_EN18IO_SW				(0x1 << 25)
#define MSDC1_TUNE					(0xF << 20)
#define MSDC2_TUNE					(0xFUL << 26)

@akku1139
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akku1139 commented Mar 7, 2026

in blade/6.16

@akku1139 akku1139 closed this Mar 7, 2026
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