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Add column mux ratio for ratio = 1, 2, 4 #10018

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Add column mux ratio for ratio = 1, 2, 4 #10018

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5f95e8b
ram: add column_mux_ratio feature
tnguy19 Apr 1, 2026
39b47be
Fix word_sel placement order and inv column filling, update golden files
tnguy19 Apr 2, 2026
09dea70
Fix placement so word_sel cells are placed in buffer row, add golden …
tnguy19 Apr 3, 2026
2494777
add make_8x8_mux_4 to regression tests
tnguy19 Apr 3, 2026
0789d9d
add make_8x8_mux4 to regression tests and clang-format
tnguy19 Apr 3, 2026
e358284
modify so select_b net and select_inv gate is shared per row for colu…
tnguy19 Apr 4, 2026
ce72977
Increase power grid pitch to be at least 4 bits wide, add constraints…
tnguy19 Apr 7, 2026
cbff38f
Fix rebase conflicts, clang-format, update golden files for all configs
tnguy19 Apr 13, 2026
253a2a8
Fix rebase conflicts, clang-format, update golden files for all configs
tnguy19 Apr 13, 2026
0735c1a
update make_8x8.tcl
tnguy19 Apr 13, 2026
3832e85
Rename mux test files to sky130 convention, update golden files
tnguy19 Apr 13, 2026
f38d74c
Fix hardcoded port names to use PortRoleType, update golden files
tnguy19 Apr 13, 2026
1f8d1f4
Update golden files for sky130 and nangate45
tnguy19 Apr 13, 2026
280b17e
replace hardcoded sky130 expression for finding AOI22 with truth tabl…
tnguy19 Apr 14, 2026
0deefd4
add header providing uint16_t
tnguy19 Apr 14, 2026
0a8f159
update regression_tests.tcl, use smart pointer for port_iter in AOI22…
tnguy19 Apr 15, 2026
38c9cb2
fix smart pointer type for port_iter in AOI22 finder
tnguy19 Apr 15, 2026
863f7a6
fix DataOut port selection to select non-inverted output, update gold…
tnguy19 Apr 15, 2026
1a3928c
Add error checking for col_mux_ratio > 1, read_ports > 1
tnguy19 Apr 17, 2026
a5d3d16
fix fix buildPortMap to select Q not QN for sequential cells
tnguy19 Apr 18, 2026
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18 changes: 16 additions & 2 deletions src/ram/include/ram/ram.h
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Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,7 @@ class RamGen
void generate(int mask_size,
int word_size,
int num_words,
int column_mux_ratio,
int read_ports,
odb::dbMaster* storage_cell,
odb::dbMaster* tristate_cell,
Expand Down Expand Up @@ -139,22 +140,32 @@ class RamGen
void makeSlice(int slice_idx,
int mask_size,
int row_idx,
int word_idx,
int read_ports,
int column_mux_ratio,
odb::dbNet* clock,
odb::dbNet* write_enable,
odb::dbNet* word_select,
const std::vector<odb::dbNet*>& selects,
const std::vector<odb::dbNet*>& shared_select_b_nets,
bool create_select_inv,
const std::vector<odb::dbNet*>& data_input,
const std::vector<std::vector<odb::dbBTerm*>>& data_output);
const std::vector<std::vector<odb::dbNet*>>& data_output);

void makeWord(int slices_per_word,
int mask_size,
int row_idx,
int word_idx,
int read_ports,
int column_mux_ratio,
odb::dbNet* clock,
odb::dbNet* word_select,
std::vector<odb::dbBTerm*>& write_enable,
const std::vector<odb::dbNet*>& selects,
const std::vector<odb::dbNet*>& shared_select_b_nets,
bool create_select_inv,
const std::vector<odb::dbNet*>& data_input,
const std::vector<std::vector<odb::dbBTerm*>>& data_output);
const std::vector<std::vector<odb::dbNet*>>& data_output);

odb::dbBTerm* makeBTerm(const std::string& name, odb::dbIoType io_type);

Expand Down Expand Up @@ -185,6 +196,7 @@ class RamGen
odb::dbMaster* and2_cell_{nullptr};
odb::dbMaster* clock_gate_cell_{nullptr};
odb::dbMaster* buffer_cell_{nullptr};
odb::dbMaster* aoi22_cell_{nullptr};
odb::dbMaster* tapcell_{nullptr};

std::map<PortRole, std::string> storage_ports_;
Expand All @@ -198,6 +210,8 @@ class RamGen
std::vector<odb::dbBTerm*> data_inputs_;
std::vector<std::vector<odb::dbBTerm*>> q_outputs_;
std::string behavioral_verilog_filename_;
std::string aoi22_in_a1_, aoi22_in_a2_, aoi22_in_b1_, aoi22_in_b2_,
aoi22_out_;
Grid ram_grid_;
};

Expand Down
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