Drop chisel

[oharboe]

I asked claude to ditch chisel and use system verilog for test/orfs/mock-array....

Needs review...

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[gemini-code-assist]

Code Review

This pull request replaces the Chisel-based MockArray implementation with a SystemVerilog version, removing Scala and Chisel dependencies and updating the Bazel build and OpenROAD flow scripts. Feedback identifies a critical syntax error in MockArray.sv caused by duplicated generate block labels, which necessitates updates to hierarchical paths in the TCL scripts. Furthermore, the glob patterns for pin matching in the TCL scripts likely require adjustment to correctly match packed and unpacked array indices, and an unused reset input was found in the MockArray module.

[gemini-code-assist]

The generate block label ces is duplicated for the inner and outer loops. This is not valid SystemVerilog, as generate block labels must be unique within their scope. This will cause a synthesis error.

You should use unique labels for the generate blocks. For example:

  for (genvar r = 0; r < HEIGHT; r++) begin : ces_row
    for (genvar c = 0; c < WIDTH; c++) begin : ces_col
      Element ces(
        ...
      );
    end
  end

After fixing this, you will also need to update test/orfs/mock-array/load_mock_array.tcl to use the correct hierarchical path that results from this change (e.g., ces_row[${r}].ces_col[${c}].ces).

  for (genvar r = 0; r < HEIGHT; r++) begin : ces_row
    for (genvar c = 0; c < WIDTH; c++) begin : ces_col

[gemini-code-assist]

The hierarchical path ces\[${r}\].ces\[${c}\].ces is based on an invalid SystemVerilog structure in MockArray.sv where generate block labels are duplicated. Once the generate block labels in MockArray.sv are fixed to be unique, this path will need to be updated to match the new valid hierarchy.

[gemini-code-assist]

The glob patterns io_lsbIns.* and io_lsbOuts.* are likely incorrect for matching the pins of the io_lsbIns and io_lsbOuts ports. These ports are defined as packed vectors in MockArray.sv, and synthesis tools typically generate pin names like io_lsbIns[0], io_lsbIns[1], etc. The . character in a Tcl glob pattern matches a literal dot, not the brackets and index. This will likely cause I/O placement to fail.

Please use [*] to match the array indices.

    {*}[match_pins io_lsbIns[*] ]] \
    [concat \
      {*}[match_pins io_lsbOuts[*] ]]]

[gemini-code-assist]

The glob patterns using .* to match pins of unpacked array ports (e.g., io_ins_down.*) are likely incorrect. Synthesis tools typically flatten unpacked arrays into pins with names like port_name[0][0], port_name[0][1], etc. The . in the glob pattern matches a literal dot and will likely fail to match these pins, causing I/O placement to fail.

You should use [*] to match array indices. For the multi-dimensional array ports in this file, a pattern like io_ins_down[*][*] might be necessary. Please verify the exact naming convention produced by your synthesis tool and adjust the glob patterns accordingly.

[gemini-code-assist]

The reset input to MockArray is declared but never used within the module. The rst inputs to the underlying Multiplier instances are all tied to 1'b0. If a reset is not necessary for this design, this input should be removed from the module's port list to improve clarity and avoid confusion.

  input  logic                  clock,

[maliberty]

Looks like gemini has some thoughts to address before I look.

[oharboe]

out of sight, out of mind for now. I'm good with this change, but my focus is elsewhere right now, so I don't want to think about nursing it through.