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Feature/avalon #37
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Feature/avalon #37
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…names with VHDL-2019 bit types
…es with UpperCamelCase naming
… with UpperCamelCase naming
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I've rebuilt the feature/avalon branch to ensure it includes only Avalon-related changes, removing Wishbone files. I've also added the required final line breaks to the source files to comply with Linux text command standards. |
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@parhamsoltani thanks for splitting Avalon and Wishbone. Please see my detailed review. I created many code suggestions, which you can accept (as bulk operation on GitHub's Files changed tab).
Please also see some comments and questions in between suggestions.
Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>


Interface now uses std_ulogic/std_ulogic_vector, addresses are now unsigned and UpperCamelCase is used to increase readability. Contributions on feature/avalon are now splitted into a new PR.