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@parhamsoltani parhamsoltani commented Dec 11, 2025

Interface now uses std_ulogic/std_ulogic_vector, addresses are now unsigned and UpperCamelCase is used to increase readability. Contributions on feature/avalon are now splitted into a new PR.

@Paebbels
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Thanks for the PR split. GitHub shows me 10 modified files including Wishbone files:
image

Please have a look. I also see indications for missing line breaks at the last line in the source file:
image

A final line break is required by many text based Linux commands.

@Paebbels Paebbels added Enhancement New feature or request SoC Bus Architecture labels Dec 11, 2025
@Paebbels Paebbels added this to the v1.1 milestone Dec 11, 2025
This was linked to issues Dec 11, 2025
@Paebbels Paebbels added Internal Mainly internal interface between components. Streaming Memory-Mapped labels Dec 11, 2025
@parhamsoltani
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I've rebuilt the feature/avalon branch to ensure it includes only Avalon-related changes, removing Wishbone files. I've also added the required final line breaks to the source files to comply with Linux text command standards.

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@parhamsoltani thanks for splitting Avalon and Wishbone. Please see my detailed review. I created many code suggestions, which you can accept (as bulk operation on GitHub's Files changed tab).

Please also see some comments and questions in between suggestions.

@Paebbels Paebbels mentioned this pull request Dec 13, 2025
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Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
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