Feature/wishbone#38

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parhamsoltani wants to merge 8 commits intoVHDL:mainfrom

parhamsoltani:feature/wishbone

Commits on Dec 10, 2025

Refactor Wishbone and Avalon interfaces to use spec-compliant signal names with VHDL-2019 bit types
parhamsoltani
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minor change on compileorder
parhamsoltani
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Commits on Dec 14, 2025

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