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Detailed ddr bandwidth metric sets#86

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jvillarre merged 3 commits into
Xilinx:masterfrom
jyothees99:detailed-ddr-bandwidth-metric-sets
Jun 23, 2026
Merged

Detailed ddr bandwidth metric sets#86
jvillarre merged 3 commits into
Xilinx:masterfrom
jyothees99:detailed-ddr-bandwidth-metric-sets

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jyothees99 and others added 3 commits June 19, 2026 00:36
… metric sets for AIE dtrace

Add two VE2 aie_dtrace interface-tile metric sets that program 4 shim
performance counters with direct NoC0 DMA events for a single MM2S/S2MM
channel selected via the metric's ":<channel>" suffix:
  PC0 start_task -> finished_task, PC1 stalled_lock,
  PC2 starvation, PC3 backpressure.

- getInterfaceTiles: match the new metric names so interface tiles get configured
- aie_profile_metadata: accept the names in dtrace bandwidth mode
- CT writer: generate per-channel DMA-event counter config (no stream-switch
  port selection) and thread the channel through
- aie_dtrace_ve2: pass the configured channel to the CT writer

Co-authored-by: Cursor <cursoragent@cursor.com>
…andwidth

Performance counter 0 for detailed_ddr_read_bandwidth and
detailed_ddr_write_bandwidth now measures PORT_RUNNING_0 on the channel's
stream-switch port instead of start_task -> finished_task.

- getBandwidthCounterConfigs: counter 0 eventType "running" with the DMA
  stream-switch port index for the selected channel/direction
- generatePerfCounterConfig: PC0 start/stop = PORT_RUNNING_0_PL
- generateStreamSwitchPortConfig: route logical SS port 0 to the channel's
  DMA port (add channel param); no longer skipped for detailed sets

Co-authored-by: Cursor <cursoragent@cursor.com>
…tadata

For detailed_ddr_*_bandwidth, counter 2 and 3 event labels now encode the
memory- vs stream-side so the generated CT counter metadata "event" field is
unambiguous:
  detailed_ddr_read_bandwidth  (MM2S): memory_starvation, stream_backpressure
  detailed_ddr_write_bandwidth (S2MM): stream_starvation, memory_backpressure

Co-authored-by: Cursor <cursoragent@cursor.com>
@jvillarre jvillarre merged commit 58ff2bb into Xilinx:master Jun 23, 2026
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2 participants