Skip to content

Temporarily use empty value for clock_freq_MHz to avoid verification pipeline errors#88

Open
IshitaGhosh wants to merge 1 commit into
Xilinx:masterfrom
IshitaGhosh:clk
Open

Temporarily use empty value for clock_freq_MHz to avoid verification pipeline errors#88
IshitaGhosh wants to merge 1 commit into
Xilinx:masterfrom
IshitaGhosh:clk

Conversation

@IshitaGhosh

Copy link
Copy Markdown
Collaborator

No description provided.

…pipeline errors

Signed-off-by: Ishita Ghosh <ishitag@amd.com>
@IshitaGhosh IshitaGhosh requested a review from jvillarre July 1, 2026 23:54
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant