This repository contains selected academic assignments completed as part of VLSI-related courses.
The projects cover transistor-level analysis, CMOS logic design, layout verification, parasitic extraction, digital logic implementation, and quantum/CMOS-related theoretical analysis.
This assignment focuses on basic CMOS device characterization and transistor-level circuit design.
The work includes IV-curve simulations for several NMOS and PMOS devices, threshold-voltage extraction, leakage-current analysis, Ion/Ioff ratio calculation, and subthreshold-slope estimation.
The second part of the assignment covers CMOS inverter design, including transistor sizing, beta optimization, delay measurements, output-load analysis, layout creation, and DRC/LVS/PEX verification.
The final part presents buffer design using two different implementation approaches and compares the effect of parasitic extraction on propagation delay.
Main topics:
- NMOS / PMOS IV-curve analysis
- Threshold voltage extraction
- Leakage current and Ion/Ioff analysis
- CMOS inverter sizing and delay measurement
- Layout design, DRC, LVS and PEX
- Buffer implementation and parasitic-delay comparison
File: VLSI Assignment 1.pdf
This assignment focuses on the design, simulation, layout, and verification of CMOS-based digital blocks.
The first part presents the implementation of a 2-to-1 MUX, including schematic design, symbol creation, transient simulation, delay measurements, layout design, DRC/LVS verification, and PEX-based post-layout simulation.
The second part extends the design into an 8-bit Barrel Shifter built from MUX-based structures.
The work includes schematic implementation, testbench validation for different shift-control combinations, timing analysis, layout implementation, and comparison between pre-layout and post-layout parasitic results.
Main topics:
- 2-to-1 MUX design
- Transient simulation and delay extraction
- Layout implementation
- DRC, LVS and PEX verification
- 8-bit Barrel Shifter design
- Post-layout timing analysis with parasitics
File: VLSI Assignment 2.pdf
This lab focuses on RTL-based digital arithmetic design using Verilog.
The work begins with a Half Adder implementation, including Verilog coding, RTL schematic generation, testbench verification, and synthesis.
The assignment then extends the design to a Full Adder based on two Half Adders, followed by a 4-bit Ripple Carry Adder built from chained Full Adders.
The project demonstrates hierarchical digital design, simulation using testbenches, RTL visualization, synthesis, and implementation-level inspection.
Main topics:
- Verilog-based digital design
- Half Adder implementation
- Full Adder implementation
- 4-bit Ripple Carry Adder
- Testbench verification
- RTL schematic generation
- Synthesis and implementation inspection
File: VLSI Assignment 3.pdf
This assignment focuses on theoretical analysis of Beyond-CMOS systems, with emphasis on superconducting quantum circuits and quantum-system modeling.
The work analyzes a capacitively coupled two-transmon circuit using Josephson-junction relations, Kirchhoff equations, Lagrangian mechanics, conjugate momenta, and Hamiltonian formulation.
The assignment also discusses multi-level quantum systems, perturbation-based coupling, time-dependent Schrödinger-equation coefficients, state occupation probabilities, quantum superposition, entanglement, Bell states, and the Hadamard gate.
Main topics:
- Josephson junction and nonlinear inductance
- Capacitively coupled transmon circuits
- Equations of motion
- Lagrangian and Hamiltonian derivation
- Quantum state evolution
- Superposition and entanglement
- Hadamard gate and Bloch-sphere interpretation
File: Quantum Systems Assingment.pdf