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  1. SIWADO SIWADO Public

    16-bit RISC SoC with dedicated math accelerators (MAC/CLZ) and a memory-mapped I/O architecture.

    SystemVerilog

  2. Rice-MECE-Capstone-Projects/Hydra Rice-MECE-Capstone-Projects/Hydra Public

    Data movement hardware accelerator for autonomous data transformation in the Wally RISC-V SoC.

    TeX

  3. mon-CHERI-DMA mon-CHERI-DMA Public

    CHERIoT capability-enforcing DMA engine in SystemVerilog. Includes ASAP7 7nm PPA with Genus/Innovus.

    SystemVerilog