arch/arm/gd32f4: fix missing CTL selector bits in up_disableusartint.#19112
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lccosy wants to merge 2 commits into
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arch/arm/gd32f4: fix missing CTL selector bits in up_disableusartint.#19112lccosy wants to merge 2 commits into
lccosy wants to merge 2 commits into
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Add NULL check for g_uart_devs[i] before accessing ->priv in arm_earlyserialinit() loop. When a USART is not enabled in defconfig, g_uart_devs[i] is NULL, causing a HardFault crash during early boot. The bug occurs because the original code only checked g_uart_devs[i]->priv without first verifying g_uart_devs[i] is not NULL. On Cortex-M4, NULL pointer dereference reads from Flash vector table (0x00000000 maps to 0x08000000), returning a function pointer that causes BusFault when written to. This fix matches the existing NULL check pattern used in arm_serialinit() at line 2835 of the same file. Tested on mplant-gd32f450 board with only USART5 enabled in defconfig. Before fix: HardFault at boot (IPSR=3, PC=0x080003e0) After fix: System boots normally to NSH Shell Signed-off-by: lccosy <1191294205@qq.com>
up_disableusartint() saves USART interrupt state from hardware CTL0-CTL3 registers but omits the CTL selector bits (bits 24-27) in the encoded ie value. When up_restoreusartint() later restores interrupts, it uses ie >> 24 to determine which CTL register to write. Without selector bits this evaluates to 0, so no CTL register is updated and all interrupt enables (including RBNEIE) are permanently lost. This causes RX interrupts to never fire after any call to up_putc() (e.g. via syslog), making the serial console unable to receive input. Fix by adding the corresponding CTL selector bit (USART_CFG_CTLx_INT << USART_CFG_SHIFT) whenever a CTL register has active interrupt bits. Signed-off-by: lccosy <1191294205@qq.com>
xiaoxiang781216
approved these changes
Jun 10, 2026
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Summary
Fix a bug in
up_disableusartint()where USART interrupt state is saved without CTL selector bits (bits 24-27), causingup_restoreusartint()to never restore interrupt enables.Problem
up_disableusartint()saves interrupt state from hardware CTL0-CTL3 registers into an encodedievalue, but omits the CTL selector bits. Whenup_restoreusartint()later restores interrupts usingie >> 24to determine which CTL register to write, this evaluates to 0, so no CTL register is updated and all interrupt enables (including RBNEIE) are permanently lost.This causes RX interrupts to never fire after any call to
up_putc()(e.g. via syslog), making the serial console unable to receive input on GD32F4 platforms.Impact
up_putc()is usedFix
Add the corresponding CTL selector bit (
USART_CFG_CTLx_INT << USART_CFG_SHIFT) whenever a CTL register has active interrupt bits, so thatup_restoreusartint()can correctly identify and restore the interrupt state.Testing
Tested on mplant-gd32f450 custom board (GD32F450ZGT6) with USART5 as serial console:
sh>\ prompt , like this
sh>\ prompt appears, like this